Solar cells and solar modules

Abstract

This application provides a solar cell and a solar module, relating to the technical field of photovoltaic power. The solar cell includes a silicon substrate including opposing first and second surfaces, an N-type doped layer with a sheet resistance of 14 Ω / sq to 40 Ω / sq located in at least a portion of the first surface of the silicon substrate, and a plurality of spaced-apart and parallel N-type current collector grid lines located on the opposite side of the N-type doped layer from the silicon substrate, wherein the spacing between adjacent N-type current collector grid lines is less than 1.391 mm. In this application, the sheet resistance of the N-type doped layer is 14 Ω / sq to 40 Ω / sq, and the spacing between adjacent N-type current collector grid lines is less than 1.391 mm, thereby achieving a good balance of elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

Description

Technical Field

[0001] This application relates to the technical field of photovoltaic power generation, and particularly to solar cells and solar modules.

[0002] (Cross-reference to related applications) This application claims the priority of a Chinese patent application with the application number 202410752794.0 and the invention-creation title "Solar Cell and Solar Module", which was filed with the Chinese Patent Office on June 11, 2024, and all of its contents are incorporated herein by reference.

Background Art

[0003] Solar cells can convert solar energy into electrical energy and are widely applicable in the future for utilizing clean energy.

[0004] In solar cells, in order to well realize the function of converting solar energy into electrical energy, it is necessary to combine each element with each other. However, in conventional solar cells, the combination of each element is not appropriate, so the performance of the solar cell is improved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This application aims to solve the problem in conventional solar cells that the performance of the solar cell is improved because the combination of different elements is not appropriate, and provides a solar cell and a solar module.

Means for Solving the Problems

[0006] In the first aspect of this application, a silicon substrate including opposing first and second surfaces, [[ID=四十二]] an N-type doped layer with a sheet resistance of 14 Ω / sq or more and 40 Ω / sq or less located in at least a partial region of the first surface of the silicon substrate, Provided is a solar cell, comprising a plurality of N-type collector grid lines that are located on the side opposite to the silicon substrate of the N-type doped layer and are spaced apart and distributed in parallel, wherein the distance between adjacent N-type collector grid lines is less than 1.391 mm.

[0007] In an embodiment of the present application, the sheet resistance of the N-type doped layer is 14 Ω / sq or more and 40 Ω / sq or less, the distance between adjacent N-type collector grid lines is less than 1.391 mm, and because the sheet resistance of the N-type doped layer and the distance between adjacent N-type collector grid lines are respectively within the above ranges, a good balance is achieved among factors such as parasitic absorption, recombination current in the metal region, and lateral resistance, the performance of the solar cell is improved, and the photoelectric conversion efficiency becomes higher.

[0008] In some possible embodiments, the sheet resistance of the N-type doped layer is 14 Ω / sq or more and 20 Ω / sq or less, the distance between adjacent N-type collector grid lines is 1.019 mm or more and 1.296 mm or less, or the sheet resistance of the N-type doped layer is more than 20 Ω / sq and 40 Ω / sq or less, and the distance between adjacent N-type collector grid lines is 0.839 mm or more and 0.977 mm or less.

[0009] In some possible embodiments, the thickness of the N-type doped layer is 100 nm or more and 140 nm or less.

[0010] In some possible embodiments, the doping concentration of the N-type doped layer is 3E20 cm

[0011] or more and 7E20 cm -3 or less.

[0011] In some possible embodiments, the solar cell further comprises a P-type doped layer with a sheet resistance of 20 Ω / sq or more and 166 Ω / sq or less, and a plurality of P-type collector grid lines that are located on the side opposite to the silicon substrate of the P-type doped layer and are spaced apart and distributed in parallel.

[0012] In some possible embodiments, the N-type doped layer comprises an N-type doped polycrystalline silicon layer and / or an N-type doped microcrystalline silicon layer. The solar cell further includes a first tunnel oxide layer located between the N-type doped layer and the silicon substrate, The spacing between adjacent P-type current collection grid lines is less than or equal to the spacing between adjacent N-type current collection grid lines.

[0013] In some possible embodiments, the first surface includes a first conductive region and a second conductive region that are spaced apart from each other. The N-type doped layer is located in the first conductive region, The P-type doped layer is located in the second conductive region, The solar cell further includes a second tunnel oxide layer located between the P-type doped layer and the silicon substrate.

[0014] In some possible embodiments, the N-type doped layer is located on the first surface of the silicon substrate, and the P-type doped layer is located on the second surface of the silicon substrate.

[0015] In some possible embodiments, the P-type doped layer is a P-type polycrystalline silicon doped layer and / or a P-type doped microcrystalline silicon layer.

[0016] In the second aspect of this application, A silicon substrate including opposing light-receiving and non-light-receiving surfaces, An N-type doped layer with a thickness of 100 nm to 140 nm located on the non-light-receiving surface of the silicon substrate, A plurality of N-type current collection grid lines located on the opposite side of the N-type doped layer from the silicon substrate, distributed spaced apart and parallel to each other, wherein the spacing between adjacent N-type current collection grid lines is less than 1.391 mm, A P-type doped layer located on the light-receiving surface of the aforementioned silicon substrate, The present invention provides a solar cell comprising a plurality of spaced-apart and parallel P-type current collector grid lines located on the opposite side of the P-type doped layer from the silicon substrate, wherein the spacing between adjacent P-type current collector grid lines is less than or equal to the spacing between adjacent N-type current collector grid lines.

[0017] In this application, the N-type doped layer is located on the non-light-receiving surface of the silicon substrate, and the thickness of the N-type doped layer is 100 nm to 140 nm. This is advantageous for several factors such as the sheet resistance, parasitic absorption, recombination current in the passivation region, and recombination current in the metal region of the N-type doped layer, thereby improving the performance of the solar cell and increasing the photoelectric conversion efficiency. Furthermore, the spacing between adjacent N-type current collector grid lines is less than 1.391 mm, which provides a good balance of factors such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency. Moreover, the spacing between adjacent P-type current collector grid lines is less than or equal to the spacing between adjacent N-type current collector grid lines. Specifically, since it is difficult to obtain a high doping concentration in the P-type doped layer, the spacing between adjacent P-type current collector grid lines may be made even smaller, further improving the efficiency of the solar cell.

[0018] In the third aspect of this application, A silicon substrate including opposing light-receiving and non-light-receiving surfaces, A silicon substrate including a first conductive region and a second conductive region in which the non-light-receiving surfaces are distributed at a distance from each other, An N-type doped layer located in the first conductive region with a sheet resistance greater than 14Ω / sq and less than 40Ω / sq, A P-type doped layer located in the second conductive region with a sheet resistance of 20 Ω / sq to 166 Ω / sq, The present invention provides a solar cell comprising a plurality of N-type current collector grid lines located on the opposite side of the N-type doped layer from the silicon substrate, distributed spaced apart and parallel to each other, wherein the spacing between adjacent N-type current collector grid lines is less than 1.391 mm.

[0019] In this application, both the N-type doped layer and the P-type doped layer are located on the non-light-receiving surface of the silicon substrate, the sheet resistance of the N-type doped layer is between 14Ω / sq and 40Ω / sq, and the spacing between adjacent N-type current collector grid lines is less than 1.391 mm. By having the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collector grid lines within the above ranges, a good balance is achieved in elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency. If the sheet resistance of the P-type doped layer is within this range, it is advantageous for improving the efficiency of the solar cell.

[0020] A fourth aspect of this application provides a solar module comprising a plurality of battery strings, the battery strings comprising a plurality of solar cells and a plurality of connecting members, the connecting members being used to connect the plurality of solar cells in series, and the solar cells comprising a plurality of any one of the aforementioned solar cells.

[0021] The solar cells and solar modules mentioned above have the same or similar beneficial effects, and are therefore omitted here to avoid duplication.

[0022] The above description is merely an overview of the technical solution provided in this application. In order to more clearly understand the technical means of this application and to implement them based on the contents of the specification, and to make the above and other objectives, features, and benefits of this application easier to understand, specific embodiments of this application will be given below. [Brief explanation of the drawing]

[0023] To more clearly explain the embodiments of this application or the technical solutions in the prior art, the drawings necessary for describing the embodiments or the prior art will be briefly described below. Naturally, the drawings described below are only a part of the embodiments of this application, and those skilled in the art will be able to conceive of other drawings based on these drawings without requiring any creative effort. [Figure 1] A schematic diagram of a partial structure of a solar cell in an embodiment of this application is shown. [Figure 2]This graph shows the effect of the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collector grid lines on the efficiency of the solar cell in the embodiment of this application. [Figure 3] This figure shows a fitting graph of the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collection grid lines in an embodiment of this application. [Figure 4] This graph shows the effect of the thickness of the N-type dope layer and the spacing between adjacent N-type current collector grid lines on the efficiency of the solar cell in the embodiment of this application. [Figure 5] This graph shows the effect of the sheet resistance of the P-type doped layer and the spacing between adjacent P-type current collector grid lines on the efficiency of the solar cell in the embodiment of this application. [Figure 6-8] The following are schematic diagrams of the structures of several solar cells in the embodiments of this application. [Modes for carrying out the invention]

[0024] To further clarify the purpose, technical solutions, and advantages of the embodiments of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the drawings of the embodiments. Naturally, the embodiments described are only a part of the embodiments of this application, not all of them. All other embodiments that can be obtained by a person skilled in the art without creative effort based on the embodiments of this application are all within the scope of protection of this application.

[0025] As those skilled in the art will understand, in the disclosure of this application, terms such as "first," "second," "third," "fourth," and "fifth" are merely for distinguishing different structures and do not limit the number of specific structures, connection relationships, etc. Furthermore, directions or positional relationships indicated by terms such as "vertical," "horizontal," "up," "down," "front," "back," "left," "right," "perpendicular," "horizontal," "top," "bottom," "inside," and "outside" are based on the drawings and are merely for the purpose of easily explaining this application and simplifying the description. They do not indicate or suggest that the described devices or elements necessarily have a specific direction, are composed of a specific direction, or must operate in a specific direction, so the above terms should not be understood as limiting this application.

[0026] This application provides at least three types of solar cells, and below, several of these solar cells will be interpreted and described mainly from the perspectives of the first, second, and third embodiments. Of these, the solar cell according to the first embodiment corresponds to the solar cell according to the first embodiment in the aforementioned application, the solar cell according to the second embodiment corresponds to the solar cell according to the aforementioned application, and the solar cell according to the third embodiment corresponds to the solar cell according to the aforementioned application. Here, in the solar cell according to the first embodiment, the N-type doped layer may be located on the entire first surface of the silicon substrate, or on a part of the first surface of the silicon substrate. In the solar cell according to the second embodiment, the N-type doped layer may be located on the non-light-receiving surface of the silicon substrate, and the P-type doped layer may be located on the light-receiving surface of the silicon substrate, resulting in a double-sided cell. The specific type of solar cell according to the second embodiment is not limited; for example, the solar cell according to the second embodiment may be a double-sided TOPCON (Tunnel Oxide Passivated Contact) cell. In the solar cell according to the third embodiment, both the N-type doped layer and the P-type doped layer may be located on the non-light-receiving surface of the silicon substrate, resulting in a back-contact solar cell. The specific type of solar cell according to the third embodiment is not limited; for example, the solar cell according to the third embodiment may be a TBC (a combination of TOPCON and IBC) cell.

[0027] Before introducing the solar cell according to the first embodiment, we will first briefly introduce some related aspects of the solar cell according to the three embodiments. In solar cell design, recombination and series resistance are two core elements that affect efficiency, and performance improvement must be achieved by synergistic optimization of parameters. Therefore, in a solar cell, if series resistance is the main influencing factor, it is necessary to reduce the series resistance by adjusting to a low sheet resistance and improve conductivity. In a solar cell, if recombination is the main factor, it is necessary to consider reducing the doping concentration or depth and increasing the sheet resistance, thereby reducing carrier recombination. In the design of a particular doping layer in a solar cell, the thickness of the N-type doping layer and the P-type doping layer can usually be related to their corresponding sheet resistance, and the general relationship is as follows. If the thickness of the N-type doping layer or P-type doping layer is too thin, the sheet resistance becomes too high, reducing the lateral current transport capability and potentially affecting the efficiency of the solar cell. However, if the thickness of the N-type doping layer or P-type doping layer is too thick, light absorption loss may increase further. Therefore, the thickness of the N-type doping layer and P-type doping layer must be considered comprehensively, taking into account factors such as parasitic absorption, doping, and sheet resistance. In solar cells, the doping concentrations of the N-type doping layer and P-type doping layer are usually related to their corresponding sheet resistances, and the general relationship is as follows: The doping concentration of the N-type doping layer and the doping concentration of the P-type doping layer are roughly inversely proportional to the sheet resistance; that is, the higher the doping concentration, the lower the sheet resistance. However, if the doping concentration is too low, the passivation effect will be low and the contact resistance will be high, while if the doping concentration is too high, parasitic absorption will become severe and Auger recombination will increase. Therefore, the doping concentration of the N-type doped layer and the P-type doped layer must be considered comprehensively, taking into account factors such as sheet resistance, passivation effect, and parasitic absorption. In solar cells, current collection grid lines are used to collect current or carriers, and the spacing of the current collection grid lines is closely related to factors such as recombination during carrier transport and shading.This application aims to select the most optimal and balanced result possible by comprehensively considering related elements for different parameters, thereby ensuring that each element is appropriately combined in the solar cell of this application, and improving the performance of the solar cell.

[0028] To avoid duplication, the main point to be explained is that, in the solar cells of the second and third embodiments, only the differences from the solar cell of the first embodiment will be explained, and any parts that are the same as or related to the solar cell of the first embodiment can be referred to in the relevant description in the first embodiment.

[0029] The following describes a solar cell according to the first embodiment. The solar cell according to the first embodiment may include a silicon substrate, and the doping type, crystal type, etc. of the silicon substrate are not specifically limited; for example, the silicon substrate may be N-type doped single-crystal silicon. The silicon substrate includes a first surface and a second surface facing each other, where one of the first and second surfaces is a light-receiving surface and the other is a non-light-receiving surface. In the process of the solar cell's normal operation, the surface that is mainly exposed to light is the light-receiving surface, and the non-light-receiving surface faces the light-receiving surface.

[0030] The solar cell may further include an N-type doped layer, and the N-type doped layer and the silicon substrate can form a high-low junction or a PN junction, and are not specifically limited thereto. The N-type doped layer is located in at least a portion of the first surface of the silicon substrate, but is not specifically limited thereto; it may be located on the entire first surface or only in a portion of the first surface. The sheet resistance of the N-type doped layer is 14 Ω / sq (Ω / □) or more and 40 Ω / sq or less. The sheet resistance (unit: Ω / sq) of the N-type doped layer is defined as follows: Considering a portion of the N-type doped layer with length l, width w, and height d (i.e., the thickness of the N-type doped layer), in this case, L=l and S=w×d, therefore R sh =ρ×l / (w×d)=(ρ / d)×(l / w). When l=w, R sh = (ρ / d), where ρ is the resistivity of the N-type doped layer, and R at this timesh is the sheet resistance of the N-type doped layer. Here, "sheet" refers to a single region in the N-type doped layer that has equal length and width and variable thickness. When the length and width of the sheet are equal, the magnitude of the length and width has almost no effect on the magnitude of the sheet resistance. For example, when the length and width of the sheet are equal, the length and width can both be 1 cm or 1 m, and the corresponding sheet resistance is the same in both cases, but decreases as the thickness of the sheet increases.

[0031] The solar cell may further include a plurality of spaced-apart, parallel-distributed N-type current collector grid lines located on the opposite side of the N-type doped layer from the silicon substrate, the N-type current collector grid lines being used to collect carriers. As shown in Figure 1, 1 represents the N-type doped layer, 2 represents the N-type current collector grid lines, and the number of N-type current collector grid lines 2 in the solar cell is not specifically limited. In Figure 1, the silicon substrate is located above the N-type doped layer, the N-type current collector grid lines 2 are inserted into the N-type doped layer 1, the spacing between adjacent N-type current collector grid lines 2 is less than 1.391 mm, and the spacing between adjacent N-type current collector grid lines 2 refers to the spacing between two adjacent N-type current collector grid lines 2. In the embodiment of this application, the sheet resistance of the N-type doped layer is 14Ω / sq to 40Ω / sq, and the spacing between adjacent N-type current collector grid lines is less than 1.391 mm. Because the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collector grid lines are within the above ranges, a good balance is achieved in elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

[0032] For example, the sheet resistance of the N-type doped layer is 14Ω / sq, 14.7Ω / sq, 15Ω / sq, 16.8Ω / sq, 17.6Ω / sq, 18.5Ω / sq, 19.3Ω / sq, 20.4Ω / sq, 22Ω / sq, 25Ω / sq, 23.1Ω / sq, 29.5Ω / sq, 27Ω / sq, 30Ω / sq, 32.5Ω / sq, 38Ω / sq. The impedance may be Ω / sq, 39.1Ω / sq, or 40Ω / sq, and the spacing between adjacent N-type current collection grid wires may be 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 1mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, 0.839mm, or 0.8mm.

[0033] More specifically, Figure 2 is a graph showing the effect of the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collector grid lines on the efficiency of the solar cell. For example, referring to Figure 2 below, the horizontal axis in Figure 2 is the sheet resistance of the N-type doped layer, such as an N-type doped polycrystalline silicon layer or a phosphorus-doped polycrystalline silicon layer, and the vertical axis in Figure 2 is the efficiency of the solar cell. In Figure 2, each curve corresponds to the spacing between 15 adjacent N-type current collector grid lines, sequentially from bottom to top: 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, 1.391 mm, 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, and 0.839 mm. In Figure 2, solar cells with efficiencies of 26% or higher, for example, 26.0% to 26.5%, are selected as high-efficiency solar cells, i.e., the area enclosed by the dashed frame in Figure 2. The efficiencies of the solar cells corresponding to the lower part of the dashed frame are all less than 26%. As can be seen from Figure 2, among the 15 adjacent N-type current collector grid lines mentioned above, the efficiencies of the corresponding solar cells when the spacing between adjacent N-type current collector grid lines is 1.391 mm or more, i.e., the five spacings of 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, and 1.391 mm, and / or when the sheet resistance of the N-type doped layer is less than 14 Ω / sq or greater than 40 Ω / sq, are all less than 26%. This indicates that when the spacing between adjacent N-type current collector grid lines is 1.391 mm or more, and / or the sheet resistance of the N-type doped layer is less than 14 Ω / sq or greater than 40 Ω / sq, the solar cell cannot achieve good efficiency. Therefore, in this application, setting the spacing between adjacent N-type current collector grid lines to less than 1.391 mm and the sheet resistance of the N-type doped layer to 14 Ω / sq or more and 40 Ω / sq or less is advantageous for improving the efficiency of the solar cell. As shown in Figure 2, in this application, when the spacing between adjacent N-type current collector grid lines is less than 1.391 mm and the sheet resistance of the N-type doped layer is to 14 Ω / sq or more and 40 Ω / sq or less, the efficiency of the solar cell is 26% or more, and even reaches 26.5% or higher.

[0034] In some possible embodiments, the sheet resistance of the N-type doped layer is 14Ω / sq or more and 20Ω / sq or less, and the spacing between adjacent N-type current collection grid lines is 1.019 mm or more and 1.296 mm or less, or the sheet resistance of the N-type doped layer is greater than 20Ω / sq and 40Ω / sq or less, and the spacing between adjacent N-type current collection grid lines is 0.839 mm or more and 0.977 mm or less. Specifically, referring to Figure 2, the sheet resistance of the N-type doped layer at 20Ω / sq is approximately the sheet resistance of the N-type doped layer corresponding to the inflection point of efficiency in the portion where the efficiency is 26% or more. The sheet resistance of the N-type doped layer is 14Ω / sq or more and 20Ω / sq or less, and the spacing between adjacent N-type current collector grid lines is 1.019mm or more and 1.296mm or less. In all cases, the efficiency of the solar cells is 26.0% or more, and the rate of efficiency increase is the fastest. However, if the sheet resistance of the N-type doped layer is greater than 20Ω / sq and 40Ω / sq or less, and the spacing between adjacent N-type current collector grid lines is 0.839mm or more and 0.977mm or less, the efficiency of the solar cells is 26.0% or more, and the rate of efficiency decrease is the slowest. Therefore, in this application, the sheet resistance of the N-type doped layer is 14Ω / sq or more and 20Ω / sq or less, and the spacing between adjacent N-type current collector grid wires is 1.019 mm or more and 1.296 mm or less, or the sheet resistance of the N-type doped layer is greater than 20Ω / sq and 40Ω / sq or less, and the spacing between adjacent N-type current collector grid wires is 0.839 mm or more and 0.977 mm or less. The efficiency of the solar cell is further improved by optimizing the combination of the sheet resistance of the N-type doped layer and the spacing between adjacent N-type current collector grid wires. It should be noted that the material of the N-type current collector grid wires is not specifically limited; for example, the N-type current collector grid wires may be silver current collector grid wires.

[0035] For example, the sheet resistance of the N-type doped layer may be 14 Ω / sq, 14.7 Ω / sq, 15 Ω / sq, 15.3 Ω / sq, 16 Ω / sq, 16.5 Ω / sq, 17 Ω / sq, 17.7 Ω / sq, 18 Ω / sq, 18.5 Ω / sq, 19 Ω / sq, 19.5 Ω / sq, 20 Ω / sq, and the spacing between adjacent N-type current collecting grid lines may be 1.019 mm, 1.05 mm, 1.076 mm, 1.112 mm, 1.141 mm, 1.173 mm, 1.213 mm, 1.25 mm, 1.296 mm. Or, the sheet resistance of the N-type doped layer may be 20.3 Ω / sq, 20.7 Ω / sq, 21 Ω / sq, 21.3 Ω / sq, 22 Ω / sq, 22.5 Ω / sq, 23 Ω / sq, 23.5 Ω / sq, 24 Ω / sq, 24.5 Ω / sq, 25 Ω / sq, 25.6 Ω / sq, 27 Ω / sq, 28 Ω / sq, 29.6 Ω / sq, 30 Ω / sq, 31.6 Ω / sq, 36.2 Ω / sq, 38.56 Ω / sq, 40 Ω / sq, and the spacing between adjacent N-type current collecting grid lines may be 0.977 mm, 0.971 mm, 0.967 mm, 0.9 mm, 0.92 mm, 0.913 mm, 0.878 mm, 0.8 mm, 0.839 mm.

[0036] More specifically, fitting is performed based on the relevant data when the efficiency of the solar cell in FIG. 2 is 26.0% or more, for example, 26.0% or more and 26.5% or less. As shown in FIG. 3, a fitting curve between the spacing y between adjacent N-type current collecting grid lines and the sheet resistance x of the N-type doped layer in the back contact solar cell (BC) is obtained, that is, y = 0.004x 4 - 0.542x 3 + 24.53x 2 - 492.4x + 4687.3. The correlation degree R of the fitting curve 2= 0.998, and in the fitting curve or fitting formula, the unit of y is μm (micrometer) and the unit of x is Ω / sq. In Figure 3, each point includes data on the left and data on the right, the data on the left of each point is the sheet resistance of the N-type doped layer, and the data on the right is the spacing between adjacent N-type current collector grid lines corresponding to that sheet resistance. The combination of the spacing between adjacent N-type current collector grid lines and the sheet resistance of the N-type doped layer, as shown by this fitting curve, achieves a good balance of elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

[0037] In several possible embodiments, the thickness of the N-type doped layer is between 100 nm (nanometers) and 140 nm. An appropriate thickness of the N-type doped layer is advantageous for several factors, including the sheet resistance, parasitic absorption, recombination current of the passivation region, and recombination current of the metallic region, thereby improving the performance of the solar cell and increasing the photoelectric conversion efficiency. More specifically, referring to Figure 1, the sidewall of the N-type current collector grid wire 2 is in contact with the N-type doped layer 1. The larger the height h and base side length a of the N-type current collector grid wire 2, the larger the sidewall area of ​​the N-type current collector grid wire 2 becomes, and the larger the recombination current of the metallic region. Assuming that the recombination rate of the sidewall of the N-type current collector grid wire 2 is 107 cm / s, the recombination current of the metallic region and the recombination current of the passivation region are estimated and weighted averaged by area ratio to obtain the recombination current of the macro-metallic region. When the height h of the N-type current collector grid wire 2 is constant, the thickness of the N-type doped layer 1 is changed to t, and the recombination current of the metal region is estimated. Figure 4 is a graph showing the effect of the thickness of the N-type doped layer and the spacing between adjacent N-type current collector grid wires on the efficiency of the solar cell. In Figure 4, each curve corresponds to the spacing between 15 adjacent N-type current collector grid wires, sequentially from bottom to top: 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, 1.391 mm, 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, and 0.839 mm. In Figure 4, each point includes data on the left and data on the right, where the data on the left of the point is the thickness of the N-type doped layer, and the data on the right is the efficiency of the solar cell corresponding to that thickness.As can be seen from Figure 4, when the thickness of the N-type doped layer is 100 nm to 140 nm, particularly around 120 nm, the efficiency of the solar cell is almost always the greatest with respect to the spacing between the 15 adjacent N-type current collector grid lines. When the thickness of the N-type doped layer is less than 100 nm, the efficiency of the solar cell increases with increasing thickness. When the thickness of the N-type doped layer is greater than 140 nm, the efficiency of the solar cell remains stable or tends to decrease with increasing thickness. Furthermore, when the thickness of the N-type doped layer is 100 nm to 140 nm, the recombination current of the metal region, which was estimated as described above, is also small. Therefore, in this application, when the thickness of the N-type doped layer is 100 nm to 140 nm, it is advantageous for several factors such as the sheet resistance of the N-type doped layer, parasitic absorption, recombination current of the passivation region, and recombination current of the metal region, resulting in improved solar cell performance and higher photoelectric conversion efficiency. For example, if the thickness of the N-type doped layer is 120 nm,

number

[0038] For example, the thickness of the N-type doped layer may be 100nm, 103.2nm, 105nm, 109nm, 110nm, 115nm, 118.3nm, 120nm, 125nm, 128nm, 130nm, 132.3nm, 135nm, 137.9nm, or 140nm.

[0039] In some possible embodiments, the doping concentration of the N-type dope layer is 3E20cm². -3 More than 7E20cm -3 Specifically, the doping concentration of the N-type doped layer is an important factor that affects the sheet resistance of the N-type doped layer. In this application, by limiting the doping concentration of the N-type doped layer to an appropriate range, the sheet resistance of the N-type doped layer can be kept within the required range.

[0040] For example, the doping concentration in the N-type doping layer is 3E20cm². -3 , 3.2E20cm -3 , 3.5E20cm -3 , 4E20cm -3 , 4.3E20cm -3 , 4.7E20cm -3 , 4.21E20cm -3 , 5E20cm -3 , 5.2E20cm -3 , 5.5E20cm -3 , 6E20cm -3 , 6.3E20cm -3 , 7E20cm -3 That's fine.

[0041] In some possible embodiments, the solar cell further includes a p-type doped layer, and a PN junction or high-low junction is formed between the p-type doped layer and the silicon substrate, and the sheet resistance of the p-type doped layer is 20 Ω / sq to 166 Ω / sq. The sheet resistance of the p-type doped layer is defined as follows: Considering a portion of the p-type doped layer with length l, width w, and height d (i.e., the thickness of the p-type doped layer), in this case, L=l and S=w×d, therefore R sh =ρ×l / (w×d)=(ρ / d)×(l / w). When l=w, R sh = (ρ / d), where ρ is the resistivity of the P-type doped layer, and R at this time shis the sheet resistance of the P-type doped layer. When the sheet resistance of the P-type doped layer is within this range, it is advantageous for improving the efficiency of the solar cell, for example, the efficiency of the solar cell becomes 25.99% or higher. The solar cell further includes a plurality of spaced-apart and parallel-distributed P-type current collector grid lines located on the opposite side of the P-type doped layer from the silicon substrate, the P-type current collector grid lines being used to collect carriers.

[0042] More specifically, refer to Figure 5 below, a graph showing the effect of the sheet resistance of a P-type doped layer, such as a boron-doped polycrystalline silicon layer, and the spacing between adjacent P-type current collector grid lines on the efficiency of a solar cell. In Figure 5, the horizontal axis represents the sheet resistance of the P-type doped layer, such as a P-type doped polycrystalline silicon layer or a boron-doped polycrystalline silicon layer, and the vertical axis represents the efficiency of the solar cell. In Figure 5, each curve corresponds to the spacing between 15 adjacent P-type current collector grid lines, sequentially from bottom to top: 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, 1.391 mm, 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, and 0.839 mm. In Figure 5, the efficiency of the solar cell corresponding to the area enclosed by the dashed frame is 25.99% or higher, while the efficiency of the solar cells corresponding to the area outside the frame is all less than 25.99%. As can be seen from Figure 5, when the sheet resistance of the P-type doped layer is between 20Ω / sq and 166Ω / sq, the performance of each aspect of the solar cell is good, and the efficiency of the solar cell is high, reaching 25.99% or higher. In Figure 5, the data for both points includes the data on the left and the data on the right. The data on the left is the sheet resistance of the P-type doped layer, and the data on the right is the efficiency of the solar cell corresponding to that sheet resistance. In this application, by limiting the combination of elements such as the sheet resistance of the N-type doped layer and the sheet resistance of the P-type doped layer, the solar cell may appropriately select a relatively large grid line spacing, and further reduce the consumption per unit of grid lines.

[0043] For example, the sheet resistance of the P-type doped layer may be 20Ω / sq, 20.5Ω / sq, 36Ω / sq, 40Ω / sq, 50Ω / sq, 60Ω / sq, 70Ω / sq, 80Ω / sq, 90Ω / sq, 93Ω / sq, 100Ω / sq, 120Ω / sq, 130Ω / sq, 140Ω / sq, 150Ω / sq, 160Ω / sq, or 166Ω / sq.

[0044] In some possible embodiments, the N-type doped layer comprises an N-type doped polycrystalline silicon layer and / or an N-type doped microcrystalline silicon layer, and the solar cell further comprises a first tunnel oxide layer located between the N-type doped layer and the silicon substrate, and the first tunnel oxide layer and the N-type doped layer can form a passivation contact structure, further improving the efficiency of the solar cell. The spacing between adjacent P-type current collector grid lines is less than or equal to the spacing between adjacent N-type current collector grid lines. Specifically, since it is difficult to obtain a high doping concentration in the P-type doped layer, the spacing between adjacent P-type current collector grid lines may be made smaller, further improving the efficiency of the solar cell. When the spacing between adjacent P-type current collector grid lines is smaller than the spacing between adjacent N-type current collector grid lines, the magnitude of the difference between the two is not specifically limited. It should be noted that the material of the P-type current collector grid lines is not specifically limited, nor is it specifically limited whether the material of the P-type current collector grid lines is the same as the material of the N-type current collector grid lines. For example, the P-type current collector grid lines may be silver current collector grid lines, etc.

[0045] In several possible embodiments, the first surface of the silicon substrate includes a first conductive region and a second conductive region distributed at intervals, wherein leakage current is avoided by the spacing between the first and second conductive regions, and the relative sizes of the first and second conductive regions are not limited. The N-type doped layer is located in the first conductive region, and the P-type doped layer is located in the second conductive region. The solar cell may further include a second tunnel oxide layer located between the P-type doped layer and the silicon substrate, and the second tunnel oxide layer and the first tunnel oxide layer may be formed by the same process or by different processes, and are not specifically limited herein. If the second tunnel oxide layer and the first tunnel oxide layer are formed by different processes, it is not specifically limited whether the first tunnel oxide layer or the second tunnel oxide layer is formed first. For example, the first tunnel oxide layer may be formed first, and then the second tunnel oxide layer may be formed. The first surface here may be the non-light-receiving surface of the silicon substrate. In this case, the solar cell is a back-contact solar cell, and the solar cell has higher efficiency because the light-receiving surface of the silicon substrate is not shielded by the electrodes.

[0046] In some possible embodiments, the N-type doped layer may be located on a first surface of the silicon substrate, or the N-type doped layer may cover the entire first surface of the silicon substrate, and the P-type doped layer may be located on a second surface of the silicon substrate, or the P-type doped layer may cover the entire second surface of the silicon substrate, the solar cell becoming a double-sided cell, the type of solar cell being flexible and diverse, where one of the first and second surfaces is a light-receiving surface and the other is a non-light-receiving surface. For example, the silicon substrate may be N-type doped single-crystal silicon, the N-type doped layer may be an N-type doped polycrystalline silicon layer located on the non-light-receiving surface of the silicon substrate, the P-type doped layer may be a P-type doped polycrystalline silicon layer located on the light-receiving surface of the silicon substrate, and a first tunnel oxide layer is further provided between the N-type doped layer and the silicon substrate. The solar cell may further include film layers such as an anti-reflective layer, and the other film layers included are not specifically limited.

[0047] In some possible embodiments, the P-type doped layer is a P-type polycrystalline silicon doped layer and / or a P-type doped microcrystalline silicon layer, a P-type diffusion layer, and the P-type doped layer is flexible and diverse.

[0048] The solar cell according to the first aspect of this application will be further interpreted below with reference to specific examples.

[0049] The solar cell is a back-contact solar cell. The silicon substrate is N-type doped single-crystal silicon, and the first surface of the silicon substrate is a non-light-receiving surface. The first surface includes a first conductive region and a second conductive region that are spaced apart, and leakage current is avoided by the spacing between the first and second conductive regions. The N-type doped layer is an N-type doped polycrystalline silicon layer, and the P-type doped layer is a P-type doped polycrystalline silicon layer. The N-type doped polycrystalline silicon layer is located in the first conductive region, and the P-type doped polycrystalline silicon layer is located in the second conductive region. The doping element in the N-type doped polycrystalline silicon layer is phosphorus, and the doping element in the P-type doped layer is boron. A second tunnel oxide layer is provided between the P-type doped polycrystalline silicon layer and the silicon substrate, and a first tunnel oxide layer is provided between the N-type doped polycrystalline silicon layer and the silicon substrate. The sheet resistance of the N-type doped polycrystalline silicon layer is 24 Ω / sq, and the sheet resistance of the P-type doped polycrystalline silicon layer is 59 Ω / sq. The spacing between adjacent N-type current collector grid lines is 0.9 mm, and the spacing between adjacent P-type current collector grid lines is also 0.9 mm. The battery performance parameters of the back contact solar cell were measured, and the measurement results and the above parameters of the back contact are shown in the table below.

[0050] [Table 1]

[0051] In the table above, Eta is the efficiency of the back-contact solar cell, Voc is the open-circuit voltage of the back-contact solar cell, Jsc is the short-circuit current density of the back-contact solar cell, and FF is the curve factor of the back-contact solar cell. The efficiency of the back-contact solar cell is already high at 26.5%, mainly because, in the back-contact solar cell, by combining these parameters—the sheet resistance of the N-type doped polycrystalline silicon layer, the sheet resistance of the P-type doped polycrystalline silicon layer, the spacing between adjacent N-type current collector grid lines, and the spacing between adjacent P-type current collector grid lines—a good balance is achieved in elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

[0052] Before introducing the solar cell according to the second and third embodiments, we will first outline two important features common to the structures of the solar cell according to the second and third embodiments. First, the sheet resistance of the P-type doped layer 5 is greater than that of the N-type doped layer 1, and second, the doping concentration of the P-type doped layer 5 is less than that of the N-type doped layer 1. Such a setting can optimize the process rhythm and improve process efficiency, etc. Furthermore, when the silicon substrate is an N-type silicon substrate, the P-type doped layer 5 forms a PN junction or emitter junction with the N-type silicon substrate, separating electrons and holes. However, the N-type doped layer 1 forms a high-low junction with the N-type silicon substrate, accelerating electron collection. Also, if the sheet resistance of the P-type doped layer 5 is greater than that of the N-type doped layer 1, contact recombination of the PN junction or emitter junction can be reduced. If the doping concentration of the P-type doped layer 5 is lower than that of the N-type doped layer 1, parasitic absorption and Auger recombination in the emitter are reduced, which helps in carrier generation. Regarding high-low junctions, if the sheet resistance of the N-type doped layer 1 is lower, the transport and collection of many carriers can be increased. If the doping concentration of the N-type doped layer 1 is higher, the contact resistance between the doped layer that has collected many carriers and the electrode becomes lower. Therefore, in this application, both the PN junction and the high-low junction are optimized and balanced to further improve the conversion efficiency of the solar cell.

[0053] Referring to Figures 6 and 7, the solar cell according to the second embodiment will be introduced below. For all relevant parts of the solar cell according to the second embodiment, please refer to the relevant descriptions in the solar cell according to the first embodiment described above. To avoid duplication, only the differences from the solar cell according to the first embodiment will be introduced. The solar cell according to the second embodiment may also be a double-sided TOPCON cell.

[0054] The solar cell according to the second embodiment includes a silicon substrate 3, an N-type doped layer 1, an N-type current collector grid line 2, a P-type doped layer 5, and a P-type current collector grid line 6. The doping type and crystal type of the silicon substrate are not specifically limited; for example, the silicon substrate may be N-type doped single-crystal silicon. In Figures 6 and 7, the lower surface of the silicon substrate 3 is a non-light-receiving surface, and the upper surface is a light-receiving surface.

[0055] The N-type doped layer 1 is located on the non-light-receiving surface of the silicon substrate 3, and the N-type doped layer 1 and the silicon substrate 3 can form a high-low junction or a PN junction, and are not specifically limited here. Referring to Figure 6, the N-type doped layer 1 may be located on the entire non-light-receiving surface of the silicon substrate 3, and in some embodiments, referring to Figure 7, the N-type doped layer 1 may be located only on a portion of the non-light-receiving surface of the silicon substrate 3, for example, the N-type doped layer 1 may be located on only a portion of the non-light-receiving surface of the silicon substrate 3 in the form of a finger-like structure. The thickness of the N-type doped layer 1 is 100 nm (nanometers) or more and 140 nm or less. An appropriate thickness of the N-type doped layer 1 is advantageous for several factors such as the sheet resistance of the N-type doped layer 1, parasitic absorption, recombination current of the passivation region, and recombination current of the metal region, thereby improving the performance of the solar cell and increasing the photoelectric conversion efficiency. More specifically, referring to Figure 1, the sidewalls of the N-type current collector grid wire 2 are in contact with the N-type doped layer 1. The larger the height h and base side length a of the N-type current collector grid wire 2, the larger the sidewall area of ​​the N-type current collector grid wire 2 becomes, and the larger the recombination current in the metal region. Assuming that the recombination speed of the sidewalls of the N-type current collector grid wire 2 is 107 cm / s, the recombination current in the metal region and the recombination current in the passivation region are estimated and weighted averaged by area ratio to obtain the recombination current in the macro-metal region. When the height h of the N-type current collector grid wire 2 is constant, the thickness of the N-type doped layer 1 is changed to t, and the recombination current in the metal region is estimated. For a detailed explanation of the reasons, please refer to Figure 4 and the related descriptions above, and a detailed explanation is omitted here.

[0056] The solar cell may further include a plurality of spaced-apart and parallel-distributed N-type current collector grid lines located on the opposite side of the N-type doped layer 1 from the silicon substrate 3, the N-type current collector grid lines being used to collect carriers. A detailed explanation is omitted here to avoid duplication, as the relevant descriptions above can be referenced. The spacing between adjacent N-type current collector grid lines 2 is less than 1.391 mm, and this refers to the spacing between two adjacent N-type current collector grid lines 2. The spacing between adjacent N-type current collector grid lines being within this range allows for a good balance of elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency. For specific reasons and related descriptions, please refer to Figure 2 and the related descriptions above; a detailed explanation is omitted here.

[0057] For example, the spacing between adjacent N-type current collection grid lines may be 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 1 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, 0.839 mm, 0.8 mm, or 0.65 mm.

[0058] The P-type doped layer 5 is located on the light-receiving surface of the silicon substrate 3, that is, the N-type doped layer 1 of the solar cell according to the second embodiment is located on the non-light-receiving surface of the silicon substrate 3, and the P-type doped layer 5 is located on the light-receiving surface of the silicon substrate 3, and the solar cell is a double-sided cell, and the other structure of the solar cell is not limited. Here, a PN junction or a high-low junction is formed between the P-type doped layer 5 and the silicon substrate 3. The P-type doped layer 5 may cover the entire light-receiving surface of the silicon substrate 3 or a part of the light-receiving surface, and is not limited thereto. For example, the silicon substrate 3 may be N-type doped single-crystal silicon, the N-type doped layer 1 is an N-type doped polycrystalline silicon layer, the N-type doped polycrystalline silicon layer is located on the non-light-receiving surface of the silicon substrate 3, and the P-type doped layer 5 is a boron diffusion layer or a P-type doped polycrystalline silicon layer, and the P-type doped layer is located on the light-receiving surface of the silicon substrate 3. A first tunnel oxide layer 4 is further provided between the N-type doped layer 1 and the silicon substrate 3. The solar cell may further include a first passivation and anti-reflective layer 7 located on the opposite side of the P-type doped layer 5 from the silicon substrate, and a second passivation and anti-reflective layer 8 located on the opposite side of the N-type doped layer 1 from the silicon substrate, and the other film layers included are not specifically limited. The specific materials of the first passivation and anti-reflective layer 7 and the second passivation and anti-reflective layer 8 are not limited, nor is it specifically limited whether the materials of the two are the same. For example, both the first passivation and anti-reflective layer 7 and the second passivation and anti-reflective layer 8 may be a mixture of aluminum oxide and silicon nitride, or one of them may be a silicon nitride layer.

[0059] The solar cell may further include a plurality of spaced-apart and parallel P-type current collector grid lines 6 located on the opposite side of the P-type doped layer 5 from the silicon substrate 3, and the P-type current collector grid lines 6 are used to collect carriers. The spacing between adjacent P-type current collector grid lines 6 is less than or equal to the spacing between adjacent N-type current collector grid lines. Specifically, in a solar cell, recombination and series connection resistance are two relatively major influencing factors, and for a double-sided TOPCON battery, recombination has a more serious impact on the battery, mainly for the following reasons. First, the P-type doped layer 5 of the TOPCON battery is located on the light-receiving side of the silicon substrate 3 and is formed by boron diffusion in the silicon substrate. Compared to the recombination of the N-type doped layer 1 into the silicon substrate via the first tunnel oxide layer 4, the recombination of the P-type doped layer 5 by diffusion into the silicon substrate is more serious. Furthermore, the higher the doping concentration of the P-type doped layer 5, the deeper the doping, the greater the degree of diffusion of the P-type doped layer 5 into the silicon substrate, and the more serious the recombination. Therefore, in order to reduce the degree of diffusion of the P-type doped layer 5 into the silicon substrate or to reduce the degree of recombination, this application appropriately controls the doping concentration and junction depth of the P-type doped layer 5. By lowering the doping concentration and making the junction depth shallower, the sheet resistance of the P-type doped layer 5 increases, reducing the lateral transport capability of carriers. To improve the lateral transport capability of carriers, this application appropriately reduces the spacing between adjacent P-type current collector grid lines 6. This shortens the lateral transport distance of carriers, effectively offsetting the adverse effects of the high sheet resistance of the P-type doped layer 5 and further improving the efficiency of the solar cell. Secondly, the P-type doped layer 5 is manufactured by a boron diffusion process. Compared to the phosphorus diffusion process for the N-type doped layer 1, the boron diffusion process is more difficult, requiring a long high-temperature process to obtain a high doping concentration, which can adversely affect the performance of the battery cell. Therefore, by lowering the doping concentration in the P-type doped layer 5, the negative effects of the long-duration high-temperature process are mitigated.A decrease in the doping concentration of the P-type dope layer 5 slightly increases its sheet resistance, but based on the above discussion, the spacing between adjacent P-type current collector grid lines 6 can be made smaller, further improving the efficiency of the solar cell. When the spacing between adjacent P-type current collector grid lines 6 is smaller than the spacing between adjacent N-type current collector grid lines, there is no specific limit to the magnitude of the difference between the two. It should be explained that there is no specific limit to the material of the P-type current collector grid line 6, nor is there a specific limit to whether the material of the P-type current collector grid line 6 is the same as the material of the N-type current collector grid line; for example, the P-type current collector grid line 6 may be a silver current collector grid line, etc.

[0060] What needs to be explained is that when the spacing between adjacent P-type current collector grid lines 6 is smaller than the spacing between adjacent N-type current collector grid lines, the width of the P-type current collector grid lines 6 may be appropriately reduced, thereby achieving approximately the same level of shading by the P-type current collector grid lines 6 as when the spacing between adjacent P-type current collector grid lines 6 is equal to the spacing between adjacent N-type current collector grid lines. For example, in this application, when the spacing between adjacent P-type current collector grid lines 6 is equal to the spacing between adjacent N-type current collector grid lines, the width of the P-type current collector grid lines 6 may be 30 μm or more and 35 μm or less. Furthermore, for example, in this application, when the spacing between adjacent P-type current collector grid lines 6 is smaller than the spacing between adjacent N-type current collector grid lines, the width of the P-type current collector grid lines 6 may be 25 μm or more and 30 μm or less. In some embodiments, as can be seen from Figure 5, when the spacing between adjacent P-type current collector grid lines 6 is less than 1.391 mm, the performance of each aspect of the solar cell is excellent, the efficiency of the solar cell is high, and it reaches 26% or more. For example, the spacing between adjacent P-type current collection grid lines 6 may be 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.99 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, or 0.839 mm.

[0061] In some embodiments, the P-type doped layer 5 is a P-type polycrystalline silicon doped layer and / or a P-type doped microcrystalline silicon layer, or a P-type diffusion layer, and the P-type doped layer 5 is flexible and versatile.

[0062] In some embodiments, the N-type doped layer 1 includes an N-type doped polycrystalline silicon layer and / or an N-type doped microcrystalline silicon layer.

[0063] In some embodiments, the spacing between adjacent N-type current collection grid wires is between 0.839 mm and 0.977 mm.

[0064] In several embodiments, the spacing between adjacent N-type current collector grid wires is between 0.839 mm and 0.977 mm. Specifically, when the spacing between adjacent N-type current collector grid wires is between 1.019 mm and 1.296 mm, the efficiency of the solar cells is always 26.0% or higher, and the rate of efficiency increase is the fastest. When the spacing between adjacent N-type current collector grid wires is between 0.839 mm and 0.977 mm, the efficiency of the solar cells is always 26.0% or higher, and the rate of efficiency decrease is the slowest. Therefore, in this application, the spacing between adjacent N-type current collector grid wires is between 0.839 mm and 0.977 mm, and further optimization of the spacing between adjacent N-type current collector grid wires will further improve the efficiency of the solar cells. It should be noted that the material of the N-type current collector grid wires is not specifically limited; for example, the N-type current collector grid wires may be made of silver.

[0065] For example, the spacing between adjacent N-type current collection grid lines may be 0.977 mm, 0.971 mm, 0.967 mm, 0.9 mm, 0.92 mm, 0.913 mm, 0.878 mm, 0.8 mm, or 0.839 mm.

[0066] In some examples, the doping concentration of the N-type dope layer 1 was 3E20cm². -3 More than 7E20cm -3Specifically, the doping concentration of the N-type doped layer 1 is an important factor that affects the sheet resistance of the N-type doped layer 1. In this application, by limiting the doping concentration of the N-type doped layer 1 to the appropriate range described above, the sheet resistance of the N-type doped layer 1 is within an appropriate range, a good balance is achieved in elements such as parasitic absorption, recombination current in the metal region and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

[0067] For example, the doping concentration of N-type dope layer 1 is 3E20cm². -3 , 3.2E20cm -3 , 3.5E20cm -3 , 4E20cm -3 , 4.3E20cm -3 , 4.7E20cm -3 , 4.21E20cm -3 , 5E20cm -3 , 5.2E20cm -3 , 5.5E20cm -3 , 6E20cm -3 , 6.3E20cm -3 , 7E20cm -3 That's fine.

[0068] In some embodiments, the sheet resistance of the N-type doped layer 1 is greater than 20Ω / sq and less than or equal to 40Ω / sq. For the definition of the sheet resistance of the N-type doped layer 1, please refer to the above description, and a detailed explanation will be omitted here to avoid repetition. For specific reasons, etc., please refer to Figure 2 above, and a detailed explanation will be omitted here to avoid repetition.

[0069] For example, the sheet resistance of the N-type doped layer 1 may be 20.3Ω / sq, 20.7Ω / sq, 21Ω / sq, 21.3Ω / sq, 22Ω / sq, 22.5Ω / sq, 23Ω / sq, 23.5Ω / sq, 24Ω / sq, 24.5Ω / sq, 25Ω / sq, 25.6Ω / sq, 27Ω / sq, 28Ω / sq, 29.6Ω / sq, 30Ω / sq, 31.6Ω / sq, 36.2Ω / sq, 38.56Ω / sq, or 40Ω / sq, and the spacing between adjacent N-type current collection grid lines may be 0.977mm, 0.971mm, 0.967mm, 0.9mm, 0.92mm, 0.913mm, 0.878mm, 0.8mm, or 0.839mm.

[0070] In some embodiments, the sheet resistance of the N-type doped layer 1 is between 14Ω / sq and 20Ω / sq, and the spacing between adjacent N-type current collection grid lines is between 1.019mm and 1.296mm. For specific reasons and other details, please refer to Figure 2 above; a detailed explanation is omitted here to avoid repetition.

[0071] For example, the sheet resistance of the N-type doped layer 1 may be 14Ω / sq, 14.7Ω / sq, 15Ω / sq, 15.3Ω / sq, 16Ω / sq, 16.5Ω / sq, 17Ω / sq, 17.7Ω / sq, 18Ω / sq, 18.5Ω / sq, 19Ω / sq, 19.5Ω / sq, or 20Ω / sq, and the spacing between adjacent N-type current collection grid lines may be 1.019mm, 1.05mm, 1.076mm, 1.112mm, 1.141mm, 1.173mm, 1.213mm, 1.25mm, or 1.296mm.

[0072] Furthermore, for example, the sheet resistance of the N-type doped layer 1 may be 14Ω / sq, 14.7Ω / sq, 15Ω / sq, 16.8Ω / sq, 17.6Ω / sq, 18.5Ω / sq, 19.3Ω / sq, 20.4Ω / sq, 22Ω / sq, 25Ω / sq, 23.1Ω / sq, 29.5Ω / sq, 27Ω / sq, 30Ω / sq, 32.5Ω / sq, 38Ω / sq, 39.1Ω / sq, or 40Ω / sq.

[0073] In some embodiments, the sheet resistance of the P-type doped layer 5 is between 20 Ω / sq and 166 Ω / sq. For the definition of the sheet resistance of the P-type doped layer 5, please refer to the related description above, and a detailed explanation is omitted here to avoid duplication. When the sheet resistance of the P-type doped layer 5 is within this range, it is advantageous for improving the efficiency of the solar cell, for example, the efficiency of the solar cell becomes 25.99% or higher. For details, please refer to Figure 5 and the corresponding related description, and a detailed explanation is omitted here to avoid duplication.

[0074] For example, the sheet resistance of the P-type doped layer 5 may be 20Ω / sq, 20.5Ω / sq, 36Ω / sq, 40Ω / sq, 50Ω / sq, 60Ω / sq, 70Ω / sq, 80Ω / sq, 90Ω / sq, 93Ω / sq, 100Ω / sq, 120Ω / sq, 130Ω / sq, 140Ω / sq, 150Ω / sq, 160Ω / sq, 165Ω / sq, or 166Ω / sq.

[0075] In some embodiments, the solar cell further includes a first tunnel oxide layer 4 located between the N-type doped layer 1 and the silicon substrate 3, and a passivation contact structure can be formed between the first tunnel oxide layer 4 and the N-type doped layer 1, further improving the efficiency of the solar cell. In Figure 7, both the first tunnel oxide layer 4 and the N-type doped layer 1 are provided only in a portion of the non-light-receiving surface of the silicon substrate, and electrodes are provided above them. In a double-sided TOPCON cell, it is necessary not only to reduce Auger recombination and parasitic absorption in the non-electrode contact region, but also to improve the doping amount in the electrode contact region to reduce contact resistance and reduce metal-semiconductor recombination. Therefore, in the solar cell of Figure 7, only the electrode contact region is provided to have a localized passivation contact structure. In contrast to the solar cell shown in Figure 6, the solar cell in Figure 7 is provided with only the second passivation / anti-reflective layer 8 in the non-electrode contact region. By reducing the coverage area of ​​the doped layer, parasitic absorption by the N-type doped layer 1 is reduced, and a localized passivation contact structure is provided in the electrode contact region, thereby ensuring the electrode contact effect and improving the conversion efficiency of the solar cell. Furthermore, the non-electrode contact region in Figure 7 may also be a textured structure, which increases light absorption and improves the bifacial ratio.

[0076] In some embodiments, when the P-type doped layer 5 is a P-type doped polycrystalline silicon layer, the solar cell may further include a second tunnel oxide layer located between the P-type doped layer 5 and the silicon substrate 3. The second tunnel oxide layer and the first tunnel oxide layer 4 may be formed by the same process or by different processes, and are not specifically limited herein. When the second tunnel oxide layer and the first tunnel oxide layer are formed by different processes, it is not specifically limited whether the first tunnel oxide layer 4 or the second tunnel oxide layer is formed first. For example, the first tunnel oxide layer may be formed first, and then the second tunnel oxide layer may be formed.

[0077] The solar cell according to the second embodiment will be further interpreted and explained below with reference to specific examples.

[0078] Referring to the double-sided TOPCON battery shown in Figures 6 and 7, the N-type doped layer 1 is an N-type doped polycrystalline silicon layer, the thickness of the N-type doped layer 1 is approximately 135 nm, and the spacing between adjacent N-type current collector grid lines 2 is between 0.839 mm and 0.977 mm, for example, it may be around 0.92 mm. The spacing between adjacent P-type current collector grid lines 6 is also within the range of 0.839 mm and 0.977 mm, but is smaller than the spacing between adjacent N-type current collector grid lines 2, for example, the spacing between adjacent P-type current collector grid lines 6 may be around 0.89 mm. The sheet resistance of the N-type doped layer 1 is between 14 Ω / sq and 45 Ω / sq, and may be between 40 Ω / sq and 45 Ω / sq. For example, it may be 42 Ω / sq. The sheet resistance of the P-type doped layer is 200 Ω / sq to 500 Ω / sq, and may also be 200 Ω / sq to 300 Ω / sq, for example, 220 Ω / sq. The doping concentration of the N-type doped layer is 2E20 cm -3 More than 5E21cm -3 The following applies: The doping concentration in the high-concentration doped portion of the P-type doped layer is 3E18cm². -3 The above is 5E19cm -3 The following applies: The doping concentration in the low-concentration doped portion of the P-type doped layer is 2E18cm². -3 More than 3E18cm -3The following applies: When the silicon substrate is an N-type silicon substrate and the P-type doped layer is a P-type diffusion layer obtained by boron diffusion in the silicon substrate, the P-type diffusion layer and the N-type silicon substrate form a PN junction, and the junction depth of this PN junction is approximately 0.5 μm to 2 μm. It should be explained that the non-photosensitive surface of the silicon substrate further has an internal diffusion layer, and the depth of this internal diffusion layer is approximately 20 nm to 100 nm. With respect to the non-photosensitive surface of the silicon substrate, the first tunnel oxide layer 4 has a predetermined blocking effect against the internal diffusion of the N-type doped layer 1 into the silicon substrate, and slight internal diffusion of the N-type doped layer 1 into the silicon substrate can further play a role in field passivation, improvement of tunneling effect, and reduction of series resistance. In this application, internal diffusion refers to the phenomenon in which the doped elements diffuse to the silicon substrate when the doped layer undergoes a diffusion process. In addition, the doping concentration distribution of the N-type doped layer 1 is more uniform than the doping concentration distribution of the P-type diffusion layer.

[0079] What needs to be explained is that, compared to the prior art, in order to improve current collection efficiency and match the sheet resistance of the P-type doped layer and the N-type doped layer, the spacing between the N-type and P-type current collection grid lines of the battery may be further reduced, thereby reducing recombination during carrier transport. At the same time, the number of grid lines increases, so the width of the N-type and P-type current collection grid lines can be appropriately reduced, for example, the width of the N-type and P-type current collection grid lines may be 20 μm or more and 30 μm or less. Even if the number of grid lines increases, the light shielding area by the N-type and P-type current collection grid lines remains substantially the same as in the conventional method. For example, in this application, the width of the N-type and P-type current collection grid lines may be 25 μm, the spacing between adjacent N-type current collection grid lines 2 is 0.92 mm, and the spacing between adjacent P-type current collection grid lines 6 is 0.89 mm.

[0080] In some embodiments, there is a ratio between the grid line width and the spacing between adjacent grid lines of the same polarity. When the ratio of the spacing between adjacent grid lines of the same polarity to the grid line width is between 20 and 49, and may be between 20 and 37, the grid line installation not only satisfies transportation requirements but also ensures that the light-shielding area is as small as possible, thereby improving current collection efficiency. For example, in this application, the grid line width is 28 μm, the distance between adjacent N-type grid lines is 0.92 mm, and the ratio of the distance between adjacent N-type grid lines to the grid line width is 32.85, improving the collection efficiency of the battery. Furthermore, for example, the ratio of the spacing between adjacent grid lines of the same polarity to the grid line width may be 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, or 37.

[0081] The following describes a solar cell according to the third embodiment. For all relevant parts of the solar cell according to the third embodiment, please refer to the relevant descriptions in the solar cells according to the first and second embodiments described above. To avoid duplication, only the differences from the solar cells according to the first and second embodiments will be described.

[0082] Referring to Figure 8, the solar cell according to the third embodiment includes a silicon substrate 3, an N-type doped layer 1, a P-type doped layer 5, and an N-type current collector grid line. The silicon substrate 3 includes opposing light-receiving and non-light-receiving surfaces, and the non-light-receiving surface includes a first conductive region and a second conductive region distributed at a distance from each other. Leakage current is avoided by the spacing between the first and second conductive regions, and the relative size of the first and second conductive regions is not limited. The N-type doped layer 1 is located in the first conductive region, and the P-type doped layer 5 is located in the second conductive region. In this case, the solar cell becomes a back-contact solar cell, and in this solar cell, the light-receiving surface of the silicon substrate 3 is not shielded by electrodes, resulting in higher efficiency. When the sheet resistance of the P-type doped layer 5 is between 20Ω / sq and 166Ω / sq, it is advantageous for improving the efficiency of the solar cell. The sheet resistance of the N-type doped layer 1 is between 14Ω / sq and 40Ω / sq. Multiple N-type current collector grid lines, which are spaced apart and distributed parallel to each other, are located on the opposite side of the silicon substrate 3 of the N-type doped layer 1. The spacing between adjacent N-type current collector grid lines is less than 1.391 mm. Because the sheet resistance of the N-type doped layer 1 and the spacing between adjacent N-type current collector grid lines are within the above ranges, a good balance is achieved in elements such as parasitic absorption, recombination current in the metal region, and lateral resistance, improving the performance of the solar cell and increasing the photoelectric conversion efficiency.

[0083] For example, the sheet resistance of N-type doped layer 1 is 14Ω / sq, 14.7Ω / sq, 15Ω / sq, 16.8Ω / sq, 17.6Ω / sq, 18.5Ω / sq, 19.3Ω / sq, 20.4Ω / sq, 22Ω / sq, 25Ω / sq, 23.1Ω / sq, 29.5Ω / sq, 27Ω / sq, 30Ω / sq, 32.5Ω / sq, 38Ω / sq. The impedance may be Ω / sq, 39.1Ω / sq, or 40Ω / sq, and the spacing between adjacent N-type current collection grid lines may be 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 1mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, 0.839mm, or 0.8mm.

[0084] More specifically, Figure 2 is a graph showing the effect of the sheet resistance of the N-type doped layer 1 and the spacing between adjacent N-type current collector grid lines on the efficiency of the solar cell. For example, referring to Figure 2 below, the horizontal axis in Figure 2 is the sheet resistance of the N-type doped layer 1, such as an N-type doped polycrystalline silicon layer or a phosphorus-doped polycrystalline silicon layer, and the vertical axis in Figure 2 is the efficiency of the solar cell. In Figure 2, each curve corresponds to the spacing between 15 adjacent N-type current collector grid lines, sequentially from bottom to top: 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, 1.391 mm, 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, and 0.839 mm. In Figure 2, solar cells with an efficiency of 26% or higher, for example, 26.0% to 26.5%, are selected as high-efficiency solar cells, i.e., the area enclosed by the dashed frame in Figure 2. The efficiency of the solar cells corresponding to the lower part of the dashed frame is all less than 26%. As can be seen from Figure 2, among the 15 adjacent N-type current collector grid lines mentioned above, the efficiency of the corresponding solar cells when the spacing between adjacent N-type current collector grid lines is 1.391 mm or more, i.e., the five spacings of 1.964 mm, 1.78 mm, 1.628 mm, 1.5 mm, and 1.391 mm, and / or when the sheet resistance of the N-type doped layer 1 is less than 14 Ω / sq or greater than 40 Ω / sq, is all less than 26%. This indicates that when the spacing between adjacent N-type current collector grid lines is 1.391 mm or more, and / or the sheet resistance of the N-type doped layer 1 is less than 14 Ω / sq or greater than 40 Ω / sq, the solar cell cannot achieve good efficiency. Therefore, in this application, setting the spacing between adjacent N-type current collector grid lines to less than 1.391 mm and the sheet resistance of the N-type doped layer 1 to 14 Ω / sq or more and 40 Ω / sq or less is advantageous for improving the efficiency of the solar cell. As shown in Figure 2, in this application, when the spacing between adjacent N-type current collector grid lines is less than 1.391 mm and the sheet resistance of the N-type doped layer 1 to 14 Ω / sq or more and 40 Ω / sq or less, the efficiency of the solar cell is 26% or more, and even reaches 26.5% or higher.

[0085] Referring to Figure 2, the sheet resistance of the N-type doped layer 1 at 20 Ω / sq is approximately the sheet resistance of the N-type doped layer 1 corresponding to the inflection point of efficiency in the portion where the efficiency is 26% or higher. More specifically, when the sheet resistance of the N-type doped layer 1 is between 14 Ω / sq and 20 Ω / sq, and the spacing between adjacent N-type current collector grid lines is between 1.019 mm and 1.296 mm, the efficiency of the solar cells is always 26.0% or higher, and the rate of efficiency increase is the fastest. In some examples, when the sheet resistance of the N-type doped layer 1 is between 20 Ω / sq and 40 Ω / sq, and the spacing between adjacent N-type current collector grid lines is between 0.839 mm and 0.977 mm, the efficiency of the solar cells is always 26.0% or higher, and the rate of efficiency decrease is the slowest. Therefore, in this application, the sheet resistance of the N-type doped layer 1 is 14Ω / sq or more and 20Ω / sq or less, and the spacing between adjacent N-type current collector grid lines is 1.019 mm or more and 1.296 mm or less, or the sheet resistance of the N-type doped layer 1 is greater than 20Ω / sq and 40Ω / sq or less, and the spacing between adjacent N-type current collector grid lines is 0.839 mm or more and 0.977 mm or less. The efficiency of the solar cell is further improved by optimizing the combination of the sheet resistance of the N-type doped layer 1 and the spacing between adjacent N-type current collector grid lines.

[0086] For example, the sheet resistance of the N-type doped layer 1 may be 14Ω / sq, 14.7Ω / sq, 15Ω / sq, 15.3Ω / sq, 16Ω / sq, 16.5Ω / sq, 17Ω / sq, 17.7Ω / sq, 18Ω / sq, 18.5Ω / sq, 19Ω / sq, 19.5Ω / sq, or 20Ω / sq, and the spacing between adjacent N-type current collection grid lines may be 1.019mm, 1.05mm, 1.076mm, 1.112mm, 1.141mm, 1.173mm, 1.213mm, 1.25mm, or 1.296mm. Alternatively, the sheet resistance of the N-type doped layer 1 is 20.3Ω / sq, 20.7Ω / sq, 21Ω / sq, 21.3Ω / sq, 22Ω / sq, 22.5Ω / sq, 23Ω / sq, 23.5Ω / sq, 24Ω / sq, 24.5Ω / sq, 25Ω / sq, 25.6Ω / sq, 27Ω / sq, 28Ω / sq, 29.6Ω / sq, 30 The impedance may be Ω / sq, 31.6Ω / sq, 36.2Ω / sq, 38.56Ω / sq, or 40Ω / sq, and the spacing between adjacent N-type current collection grid lines may be 0.977mm, 0.971mm, 0.967mm, 0.9mm, 0.92mm, 0.913mm, 0.878mm, 0.8mm, or 0.839mm.

[0087] In some examples, the doping concentration of the N-type dope layer 1 was 3E20 cm⁻¹. -3 More than 7E20 cm -3 Specifically, the doping concentration of the N-type doped layer 1 is an important factor affecting the sheet resistance of the N-type doped layer 1. In this application, by limiting the doping concentration of the N-type doped layer 1 to an appropriate range, the sheet resistance of the N-type doped layer 1 can be kept within the required range.

[0088] For example, the doping concentration of N-type dope layer 1 is 3E20cm². -3 , 3.2E20cm -3 , 3.5E20cm -3 , 4E20cm -3 , 4.3E20cm -3 , 4.7E20cm -3 , 4.21E20cm -3 , 5E20cm -3 , 5.2E20cm -3, 5.5E20cm -3 , 6E20cm -3 , 6.3E20cm -3 , 7E20cm -3 That's fine.

[0089] The solar cell further includes a plurality of spaced-apart and parallel-distributed P-type current collector grid lines 6 located on the opposite side of the P-type doped layer 5 from the silicon substrate 3, and the efficiency of the solar cell can be further improved if the spacing between adjacent P-type current collector grid lines 6 is less than or equal to the spacing between adjacent N-type current collector grid lines. For example, the spacing between adjacent P-type current collector grid lines 6 is equal to the spacing between adjacent N-type current collector grid lines, or the spacing between adjacent P-type current collector grid lines 6 is less than the spacing between adjacent N-type current collector grid lines.

[0090] In some embodiments, as can be seen from Figure 5, when the spacing between adjacent P-type current collector grid lines 6 is less than 1.391 mm, the performance of each solar cell is excellent, and the efficiency of the solar cell is high, reaching 26% or more. For example, the spacing between adjacent P-type current collector grid lines 6 may be 1.296 mm, 1.213 mm, 1.141 mm, 1.076 mm, 1.019 mm, 0.99 mm, 0.977 mm, 0.967 mm, 0.92 mm, 0.878 mm, or 0.839 mm.

[0091] In some embodiments, the solar cell further includes a first tunnel oxide layer 4 located between an N-type doped layer 1 and a silicon substrate 3, and a second tunnel oxide layer 9 located between a P-type doped layer 5 and the silicon substrate 3. The second tunnel oxide layer 9 and the first tunnel oxide layer 4 may be formed by the same process or by different processes, and are not specifically limited herein. If the second tunnel oxide layer 9 and the first tunnel oxide layer 4 are formed by different processes, it is not specifically limited whether the first tunnel oxide layer 4 or the second tunnel oxide layer 9 is formed first. For example, the first tunnel oxide layer 4 may be formed first, and then the second tunnel oxide layer 9 may be formed.

[0092] In some embodiments, leakage current is avoided by the spacing between the first conductive region and the second conductive region, and the relative size of the first conductive region and the second conductive region is not limited.

[0093] In some embodiments, the N-type doped layer 1 is an N-type doped polycrystalline silicon layer, the P-type doped layer is a P-type doped polycrystalline silicon layer, and the thickness of the P-type doped layer 5 is greater than or equal to the thickness of the N-type doped layer 1. Specifically, since it can be difficult to obtain a high doping concentration in the P-type doped layer 5, the sheet resistance becomes higher. To reduce the sheet resistance, the thickness of the P-type doped layer 5 is appropriately increased, further improving the efficiency of the solar cell. For example, the thickness of the P-type doped layer 5 may be 100 nm to 500 nm, or more precisely, 200 nm to 400 nm, for example, 300 nm. Furthermore, for example, the thickness of the N-type doped layer 1 may be 80 nm to 400 nm, or more precisely, 150 nm to 300 nm, for example, 200 nm.

[0094] The solar cell according to the third embodiment will be further interpreted and explained below with reference to specific examples.

[0095] Referring to the TBC (TopCon-Back Contact) battery shown in Figure 8, the N-type doped layer 1 is an N-type doped polycrystalline silicon layer, and the thickness of the N-type doped layer 1 is 100 nm to 400 nm, for example, it may be around 200 nm. The P-type doped layer 5 is a P-type doped polycrystalline silicon layer, and the thickness of the P-type doped layer 5 is 100 nm to 500 nm, for example, it may be around 300 nm. The spacing between adjacent N-type current collector grid lines 2 and the spacing between adjacent P-type current collector grid lines 6 are both 0.839 mm to 0.977 mm, for example, it may be around 0.92 mm. The sheet resistance of the N-type doped layer 1 is 14 Ω / sq to 50 Ω / sq, and may be further 20 Ω / sq to 40 Ω / sq. For example, it may be 24 Ω / sq. The sheet resistance of the P-type doped layer is 50 Ω / sq to 200 Ω / sq, or 50 Ω / sq to 120 Ω / sq. For example, it may be 90 Ω / sq. The doping concentration of the N-type doped layer is 2E20 cm⁻¹.-3 More than 7E21cm -3 For example, 6E20cm -3 The doping concentration in the P-type doped layer at high doping levels is 2E19cm³. -3 More than 5E20cm -3 For example, 6E19cm -3 Therefore, the doping concentration at low doping levels in the P-type dope layer is 2E18cm³. -3 The above is 5E19cm -3 For example, 6E18cm -3 The silicon substrate is an N-type silicon substrate. The degree of internal diffusion of the N-type doped layer 1 into the silicon substrate is stronger than the degree of internal diffusion of the P-type doped layer into the silicon substrate. For example, the internal diffusion of the N-type doped layer 1 into the silicon substrate is approximately E17cm. -3 More than 8E20cm -3 The following is observed: Internal diffusion of the P-type doped layer into the silicon substrate is approximately E16cm. -3 The above is 5E19cm -3 The following applies:

[0096] Other film layers in the solar cell according to the third embodiment are not limited, and for example, the description of other film layers in the solar cell according to the first embodiment may be referred to. The specific parameter range of the remaining layers or structures in the solar cell according to the second embodiment is not limited, and for example, the relevant description in the solar cell according to the first embodiment may be referred to further.

[0097] In some embodiments, there is a ratio between the grid line width of a solar cell and the width of the N-type doped layer or P-type doped layer. When the ratio of the width of the N-type doped layer or P-type doped layer to the grid line width is in the range of 10 to 35, it is possible to satisfy the requirements for carrier transport, reduce the manufacturing cost of the grid lines, and improve the contact performance between the doped layer and the electrodes. For TBC batteries, if the N-type substrate is a silicon substrate, an emitter is formed between the P-type doped layer and the N-type substrate. To ensure carrier generation, the width of the P-type doped layer is larger than the width of the N-type doped layer, and therefore the ratio of the width of the P-type doped layer to the grid line width is slightly larger than the ratio of the width of the N-type doped layer to the grid line span. For example, the ratio of the width of the N-type doped layer or P-type doped layer to the grid line width may be 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35.

[0098] What needs to be explained is that the solar cells according to the first, second, and third embodiments described above all aim to improve the performance of the solar cell and increase the photoelectric conversion efficiency by balancing elements such as parasitic absorption, recombination current in the metal region, and lateral resistance in the solar cell, and therefore belong to the same patent application concept.

[0099] This application further provides a solar module including a plurality of battery strings, the battery strings comprising a plurality of solar cells and a plurality of connecting members, the connecting members being used to connect the plurality of solar cells in series. The solar cells comprise a plurality of any one of the aforementioned solar cells, and the solar module may further include other structures, for example, the solar module may further include package adhesive films located on opposite sides of the solar cells, and the other structures of the solar module are not specifically limited, and the solar module has the same or similar beneficial effects as any one of the aforementioned solar cells, and a detailed description is omitted here to avoid duplication. The connecting members may include ribbons and conductive connecting members, etc., and the connecting members are electrically connected to the positive electrode of one of two adjacent solar cells and the negative electrode of the latter solar cell in order to connect two adjacent solar cells in series.

[0100] It should be noted that while the embodiments of the method are presented as a combination of a series of actions for the sake of simplicity, those skilled in the art should understand that, according to the embodiments of this application, some steps can be performed in a different order or simultaneously, and therefore the embodiments of this application are not limited by the described sequence of actions. Furthermore, those skilled in the art should understand that all embodiments described in the specification are preferred embodiments, and such actions are not necessarily required for the embodiments of this application. [Explanation of Symbols]

[0101] 1. N-type doped layer 2 N-type current collection grid line 3. Silicon substrate 4. First Tunnel Oxidation Layer 5. P-type doped layer 6 P-type current collection grid line 7. First Passivation / Anti-Reflection Layer 8. Second Passivation / Anti-Reflection Layer 9. Second tunnel oxidation layer

Claims

1. A silicon substrate including opposing first and second surfaces, An N-type doped layer with a sheet resistance of 14 Ω / sq to 40 Ω / sq located in at least a portion of the first surface of the silicon substrate, A solar cell comprising a plurality of spaced-apart and parallel-distributed N-type current collector grid lines located on the opposite side of the N-type doped layer from the silicon substrate, wherein the spacing between adjacent N-type current collector grid lines is less than 1.391 mm.

2. The sheet resistance of the N-type doped layer is 14 Ω / sq or more and 20 Ω / sq or less, and the spacing between adjacent N-type current collection grid lines is 1.019 mm or more and 1.296 mm or less, or The solar cell according to claim 1, wherein the sheet resistance of the N-type doped layer is greater than 20 Ω / sq and less than or equal to 40 Ω / sq, and the spacing between adjacent N-type current collector grid lines is 0.839 mm or more and less than or equal to 0.977 mm.

3. The solar cell according to claim 1, wherein the thickness of the N-type doped layer is 100 nm or more and 140 nm or less.

4. The doping concentration of the aforementioned N-type doped layer is 3E20cm². －３ More than 7E20cm －３ The solar cell according to claim 1, which is as follows:

5. A P-type doped layer with a sheet resistance of 20 Ω / sq to 166 Ω / sq, The solar cell according to any one of claims 1 to 4, further comprising a plurality of spaced-apart and parallel-distributed P-type current collector grid lines located on the opposite side of the P-type doped layer from the silicon substrate.

6. The N-type doped layer includes an N-type doped polycrystalline silicon layer and / or an N-type doped microcrystalline silicon layer. The solar cell further includes a first tunnel oxide layer located between the N-type doped layer and the silicon substrate, The solar cell according to claim 5, wherein the spacing between adjacent P-type current collection grid lines is less than or equal to the spacing between adjacent N-type current collection grid lines.

7. The first surface includes a first conductive region and a second conductive region that are distributed at a distance from each other. The N-type doped layer is located in the first conductive region, The P-type doped layer is located in the second conductive region, The solar cell according to claim 6, further comprising a second tunnel oxide layer located between the P-type doped layer and the silicon substrate.

8. The solar cell according to claim 6, wherein the N-type doped layer is located on the first surface of the silicon substrate, and the P-type doped layer is located on the second surface of the silicon substrate.

9. The solar cell according to claim 5, wherein the P-type doped layer is a P-type polycrystalline silicon doped layer and / or a P-type doped microcrystalline silicon layer.

10. A silicon substrate including opposing light-receiving and non-light-receiving surfaces, An N-type doped layer with a thickness of 100 nm to 140 nm located on the non-light-receiving surface of the silicon substrate, A plurality of N-type current collection grid lines located on the opposite side of the N-type doped layer from the silicon substrate, distributed spaced apart and parallel to each other, wherein the spacing between adjacent N-type current collection grid lines is less than 1.391 mm, A P-type doped layer located on the light-receiving surface of the aforementioned silicon substrate, A solar cell comprising a plurality of spaced-apart and parallel P-type current collector grid lines located on the opposite side of the P-type doped layer from the silicon substrate, wherein the spacing between adjacent P-type current collector grid lines is less than or equal to the spacing between adjacent N-type current collector grid lines.

11. The solar cell according to claim 10, wherein the spacing between adjacent N-type current collection grid lines is 0.839 mm or more and 0.977 mm or less.

12. The solar cell according to claim 10, wherein the N-type doped layer is located in a portion of the non-light-receiving surface of the silicon substrate.

13. The doping concentration of the aforementioned N-type doped layer is 3E20cm². －３ More than 7E20cm －３ The solar cell according to claim 10, which is as follows:

14. The sheet resistance of the aforementioned N-type doped layer is greater than 20 Ω / sq and less than or equal to 40 Ω / sq, and / or The solar cell according to any one of claims 10 to 13, wherein the sheet resistance of the P-type doped layer is 20 Ω / sq or more and 166 Ω / sq or less, and / or the spacing between adjacent P-type current collector grid lines is less than 1.391 mm.

15. A silicon substrate including opposing light-receiving and non-light-receiving surfaces, A silicon substrate including a first conductive region and a second conductive region in which the non-light-receiving surfaces are distributed at a distance from each other, An N-type doped layer located in the first conductive region with a sheet resistance greater than 14 Ω / sq and less than or equal to 40 Ω / sq, A P-type doped layer with a sheet resistance of 20 Ω / sq to 166 Ω / sq located in the second conductive region, A solar cell comprising a plurality of N-type current collector grid lines located on the opposite side of the N-type doped layer from the silicon substrate, distributed spaced apart and parallel to each other, wherein the spacing between adjacent N-type current collector grid lines is less than 1.391 mm.

16. The sheet resistance of the aforementioned N-type doped layer is greater than 20 Ω / sq and less than or equal to 40 Ω / sq. The solar cell according to claim 15, wherein the spacing between adjacent N-type current collection grid lines is 0.839 mm or more and 0.977 mm or less.

17. The doping concentration of the aforementioned N-type doped layer is 3E20cm². －３ More than 7E20cm －３ The solar cell according to claim 15, which is as follows:

18. The solar cell according to claim 15, further comprising a plurality of spaced-apart and parallel-distributed P-type current collector grid lines located on the opposite side of the P-type doped layer from the silicon substrate, wherein the spacing between adjacent P-type current collector grid lines is less than or equal to the spacing between adjacent N-type current collector grid lines, and / or the spacing between adjacent P-type current collector grid lines is less than 1.391 mm.

19. A first tunnel oxide layer located between the N-type doped layer and the silicon substrate, A solar cell according to any one of claims 15 to 18, further comprising a second tunnel oxide layer located between the P-type doped layer and the silicon substrate.

20. A solar module comprising a plurality of battery strings, the battery strings comprising a plurality of solar cells and a plurality of connecting members, the connecting members being used to connect the plurality of solar cells in series, and the solar cells being the solar cells described in any one of claims 1 to 19.

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