Data processing systems, storage, data reading / writing methods, and devices

Abstract

A data processing system, storage, data read / write method, and device are provided. In this application, the processor sends a read / write request to the storage. The read / write request is used to request that the storage perform a data read / write, and the read / write request holds the logical address of the data. After receiving the read / write request, the storage maps the logical address to a target location in a bank of N storage chips in the storage, and performs a data read / write at the target location in the bank of N storage chips. The target locations in the bank of N storage chips are distributed in different areas. The N target locations are not in the same area, thereby ensuring that in a single read / write process in the storage, the error rate of the storage does not fluctuate significantly due to different logical addresses, and that the error rate of the storage remains stable within a small range.

Description

Technical Field

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[0003] , , ,

[0001] [Cross - reference to Related Applications] This application was filed with the China National Intellectual Property Administration on June 29, 2023, and claims priority to Chinese Patent Application No. 202310794233.2 titled "STORAGE APPARATUS", and Chinese Patent Application No. 202311199956.4 titled "DATA PROCESSING SYSTEM, STORAGE, DATA READING / WRITING METHOD, AND DEVICE" filed with the China National Intellectual Property Administration on September 15, 2023. These Chinese patent applications are hereby incorporated by reference in their entirety into this specification.

[0002] This application relates to the field of communication technologies, and in particular, to data processing systems, storage, data reading / writing methods, and devices.

Background Art

[0003] Memory address assignment generally refers to identifying the position in a bank of storage chips in memory based on a logical address sent by a processor. In some storage, the data in the logical address is usually distributed across storage chips, and the storage chips share the logical address. That is, in the memory address assignment process, the position in each bank of storage chips needs to be determined. In other words, multiple positions need to be identified.

[0004] In practice, due to the design of the storage's internal circuitry, a storage chip's bank may contain multiple areas with different error rate ranges. During memory addressing, if multiple locations in a bank all fall within an area with the highest error rate range, the probability of errors in data read / write at a logical address doubles. Conversely, during memory addressing, if multiple locations in a bank all fall within an area with the lowest error rate range, the probability of errors in data read / write at a logical address is significantly reduced.

[0005] Based on existing memory addressing schemes, it can be seen that the overall error rate of storage changes with changes in logical addresses. The overall error rate of storage is unstable, which increases the difficulty of later designing the storage as an error-correcting storage. [Overview of the Initiative]

[0006] Embodiments of the present invention provide a data processing system, storage, a data reading / writing method, and a device for stabilizing the error rate of storage.

[0007] According to a first aspect, one embodiment of the present application provides a data processing system. The data processing system comprises a processor and storage.

[0008] The processor sends read / write requests to storage. Read / write requests are used to request that data be read / written to storage, and they hold the logical address of the data.

[0009] After receiving a read / write request, the storage maps the logical address to a target location in a bank of N storage chips within the storage, and then performs the data read / write at the target location in the bank of N storage chips. The target locations in the bank of N storage chips are distributed across different areas, where N is a positive integer. The areas in the bank are formed by partitioning based on error rates, and the error rates differ between different areas.

[0010] In the aforementioned system, for the same logical address, the storage maps the logical address to a target location in a bank of N storage chips. The N target locations are distributed in different areas. The N target locations are not in the same area, and this ensures that the storage error rate does not fluctuate significantly due to different logical addresses during a single read / write process in the storage, and that the storage error rate remains stable within a small range.

[0011] In possible implementations, the storage has an address remapping function, and the storage provides an external option to enable this function. For example, before sending a read / write request, the processor sends an address remapping instruction to the storage. The address remapping instruction is used to enable the storage's address remapping function. In this way, the processor can enable the storage's address remapping function based on actual requirements.

[0012] In a possible implementation, the storage has N first address remapping modules, and each storage chip corresponds to one first address remapping module. After receiving an address remapping instruction, the control circuit controls M first address remapping modules to be activated according to the instruction. M is a positive integer and is not greater than N.

[0013] Any active first address remapping module corrects the physical address converted from the logical address. The corrected physical address points to the target location in the storage chip bank corresponding to the first address remapping module.

[0014] In the aforementioned system, the first address remapping module, while in operation, can modify the physical address. Since the first address remapping modules corresponding to M of the N storage chips can modify the physical address, the physical addresses obtained by the M storage chips are not exactly the same, further ensuring that the logical addresses can ultimately be mapped to target locations in different areas of the N storage chips.

[0015] In possible implementations, when modifying a physical address, the active first address remapping module may modify fields within the physical address that point to rows and / or columns in the bank.

[0016] In the aforementioned system, the first address remapping module, while operational, only needs to modify a portion of the fields in the physical address to ensure that the logical address can ultimately be mapped to a target location in a different area of ​​the N storage chips. The implementation is simple.

[0017] In possible implementations, a first address remapping module that is not operational does not modify the physical address, but rather maintains the immutability of each field in the physical address. The physical address points to the target location in the bank of the storage chip corresponding to the first address remapping module.

[0018] In the aforementioned system, the first address remapping module that is operational and the first address remapping module that is not operational process physical addresses in different ways, thereby ultimately ensuring that the N physical addresses obtained by the N storage chips are different, and that the target addresses mapped to the N different physical addresses in the bank of the N storage chips belong to different areas.

[0019] In possible implementations, any storage chip determines a target location in the storage chip's bank based on a physical address obtained from a corresponding first address remapping module, and performs data read / write operations at the target location. A physical address obtained by the storage chip from an active second address remapping module is a modified physical address, while a physical address obtained by the storage chip from an inactive second address remapping module is the original physical address.

[0020] In the aforementioned system, the physical addresses obtained by the N storage chips from the corresponding first address remapping module are not exactly the same, and the final determined target locations in the storage chip bank are different.

[0021] In possible implementations, as described above, the storage address remapping function is implemented by directly modifying the physical address converted from the logical address. Alternatively, the storage address remapping function may be implemented by modifying the logical address. The following description illustrates this implementation. The control circuit includes N second address remapping modules, with each storage chip corresponding to one second address remapping module.

[0022] The control circuit controls to activate M second address remapping modules according to an address remapping instruction. M is not greater than N.

[0023] Any second address remapping module in the active state modifies the logical address. The modified logical address is mapped to a target position in the bank of the storage chip corresponding to the second address remapping module.

[0024] In the above system, the second address remapping module in the active state can modify the logical address. Since the second address remapping modules corresponding to M of the N storage chips can modify the logical address, the physical addresses converted from the logical address and obtained by the M storage chips are not exactly the same, and it is further ensured that the logical address can be finally mapped to target positions in different areas of the N storage chips.

[0025] In a possible implementation, the second address remapping module in the active state modifies a field within the logical address that indicates a row and / or column in the bank.

[0026] In the above system, the second address remapping module in the active state only needs to change some of the fields in the logical address to ensure that the logical address can be finally mapped to target positions in different areas of the N storage chips. The implementation is simple.

[0027] In a possible implementation, the second address remapping module not in the active state maintains each field in the logical address unchanged. The logical address indicates the target position in the bank of the storage chip corresponding to the first address remapping module.

[0028] In the aforementioned system, the second address remapping module in the operating state and the second address remapping module not in the operating state process logical addresses in different ways, so that the N physical addresses obtained by the N storage chips are different, and finally it can be ensured that the N different physical addresses belong to different areas where the target positions mapped in the banks of the N storage chips are different.

[0029] In a possible implementation, the control circuit includes an address conversion module. The address conversion module converts the logical address obtained from the second address remapping module into a physical address and sends the physical address to the storage chip corresponding to the second address remapping module. The logical address obtained by the address conversion module from the second address remapping module in the operating state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module not in the operating state is the original logical address.

[0030] In the aforementioned system, the address conversion module can implement the conversion from a logical address to a physical address, and different logical addresses are converted into different physical addresses, so that it is ensured that the logical addresses received by the storage can be mapped to the target positions distributed in different areas in the banks of the N storage chips.

[0031] According to a second aspect, the present application further provides a storage. The storage has the functions of the storage in the first aspect and any possible implementation. For some of the beneficial effects, refer to the description of the first aspect. Details will not be described again in this specification. The storage includes a control circuit and N storage chips. n is a positive integer.

[0032] In storage, the control circuit receives read / write requests sent by the processor. A read request is used to request that data be read / written to the storage, and the read / write request holds the logical address of the data. After receiving the read / write request, the control circuit translates the logical address to a physical address and sends the physical address converted from the logical address to N storage chips in the storage. The physical address points to a target location in a bank of N storage chips, and the target locations in the bank of N storage chips are distributed in different areas, where N is a positive integer. The different areas are formed by partitioning based on the error rate in the bank, and the error rate ranges of the different areas are different.

[0033] After receiving a physical address, any storage chip performs data read / write operations at the target location in the storage chip's bank.

[0034] In the aforementioned storage, for the same logical address, the logical address may be mapped to a target location in a bank of N storage chips in the storage, and the N target locations are distributed in different areas, thereby ensuring that the error rate of the storage does not fluctuate significantly with different logical addresses received by the storage.

[0035] In possible implementations, the control circuit receives an address remapping instruction sent by the processor. The address remapping instruction is used to enable the address remapping function of the storage.

[0036] In a possible implementation, the storage comprises N first address remapping modules, each storage chip containing one first address remapping module, and the control circuit controls the activation of M first address remapping modules according to address remapping instructions, where M is a positive integer and is not greater than N.

[0037] Any active first address remapping module corrects the physical address converted from the logical address. The corrected physical address points to the target location in the storage chip bank corresponding to the first address remapping module.

[0038] In a possible implementation, the first address remapping module, while in operation, modifies fields that are within the physical address and point to rows and / or columns in the bank.

[0039] In possible implementations, a first address remapping module that is not operational maintains the immutability of each field in the physical address. The physical address points to the target location in the storage chip bank corresponding to the first address remapping module.

[0040] In possible implementations, any storage chip determines a target location in the storage chip's bank based on a physical address obtained from a corresponding first address remapping module, and performs data read / write operations at the target location. A physical address obtained by the storage chip from an active first address remapping module is a modified physical address, while a physical address obtained by the storage chip from an inactive first address remapping module is the original physical address.

[0041] In a possible implementation, the control circuit has N second address remapping modules, each storage chip corresponds to one second address remapping module, and the control circuit controls M second address remapping modules to be activated according to address remapping instructions, where M is a positive integer and is not greater than N.

[0042] Any second address remapping module that is in operation modifies the logical address. The modified logical address points to the target location in the storage chip bank corresponding to the second address remapping module.

[0043] In a possible implementation, a second address remapping module in operation modifies fields that are within a logical address and point to rows and / or columns in a bank.

[0044] In possible implementations, a second address remapping module that is not operational maintains the immutability of each field in the logical address. The logical address is mapped to a target location in the storage chip bank corresponding to the second address remapping module.

[0045] In possible implementations, the control circuit includes an address translation module. The address translation module translates the logical address obtained from the second address remapping module into a physical address and transmits the physical address to the storage chip corresponding to the second address remapping module. A logical address obtained by the address translation module from an active second address remapping module is a modified logical address, while a logical address obtained by the address translation module from an inactive second address remapping module is the original logical address.

[0046] According to a third aspect, the present invention further provides a data read / write method, in which the storage has the functions of the storage in the first aspect and any possible implementation. For beneficial effects, please refer to the description of the first aspect. Further details are not described again herein.

[0047] The control circuit receives read / write requests sent by the processor, where a read request is used to request that data be read / written to the storage, and the read / write request holds the logical address of the data; the control circuit translates the logical address to a physical address, and sends the physical address converted from the logical address to N storage chips, where the physical address points to a target location in a bank of N storage chips, and the target locations in the bank of N storage chips are distributed in different areas.

[0048] Any storage chip performs data read / write operations at a target location within the storage chip's bank.

[0049] In possible implementations, the control circuit may further receive address remapping instructions sent by the processor. Address remapping instructions are used to enable the address remapping function of the method.

[0050] In a possible implementation, the storage has N first address remapping modules, each storage chip corresponds to one first address remapping module, and the control circuit controls M first address remapping modules to be activated according to address remapping instructions, where M is not greater than N.

[0051] Any active first address remapping module corrects the physical address converted from the logical address. The corrected physical address points to the target location in the storage chip bank corresponding to the first address remapping module.

[0052] In a possible implementation, if an active first address remapping module modifies a physical address converted from a logical address, the active first address remapping module modifies fields within the physical address that point to rows and / or columns in a bank.

[0053] In possible implementations, a first address remapping module that is not operational maintains the immutability of each field in the physical address. The physical address points to the target location in the storage chip bank corresponding to the first address remapping module.

[0054] In a possible implementation, when any storage chip performs a data read / write operation at a target location in the storage chip's bank, the storage chip determines the target location in the storage chip's bank based on a physical address obtained from a corresponding first address remapping module, and then performs the data read / write operation at the target location.

[0055] In a possible implementation, the control circuit includes N second address remapping modules, each storage chip corresponds to one second address remapping module, and when the control circuit translates logical addresses to physical addresses, it controls the activation of M second address remapping modules according to address remapping instructions, where M is not greater than N.

[0056] Any second address remapping module that is in operation modifies the logical address. The modified logical address points to the target location in the storage chip bank corresponding to the second address remapping module.

[0057] In possible implementations, a second address remapping module that is not operational maintains the immutability of each field in the logical address. The logical address points to the target location in the storage chip bank corresponding to the second address remapping module.

[0058] In possible implementations, the control circuit includes an address translation module. The address translation module translates the logical address obtained from the second address remapping module into a physical address and transmits the physical address to the storage chip corresponding to the second address remapping module. A logical address obtained by the address translation module from an active second address remapping module is a modified logical address, while a logical address obtained by the address translation module from an inactive second address remapping module is the original logical address.

[0059] According to a fourth aspect, the present invention further provides a computing device, which includes the storage and possible implementations of the second aspect as described in the second aspect, and optionally further includes a processor.

[0060] According to a fifth aspect, the present invention further provides a computer-readable storage medium that stores instructions. When the instructions are executed on a computer, the computer is enabled to perform the methods of the third aspect and possible implementations thereof.

[0061] According to a sixth aspect, the present invention further provides a computer program product comprising instructions. When the computer program product is executed on a computer, the computer is enabled to perform the methods of the third aspect and possible implementations thereof.

[0062] According to a seventh aspect, the present invention further provides a computer chip connected to storage, which is configured to read and execute software programs stored in the storage to perform the methods of the third aspect and possible implementations thereof. [Brief explanation of the drawing]

[0063] [Figure 1] This is a diagram illustrating memory addressing in storage.

[0064] [Figure 2] This is a diagram showing the structure of a data processing system according to one embodiment of the present invention.

[0065] [Figure 3] This is a diagram showing the structure of a storage according to one embodiment of the present invention.

[0066] [Figure 4] This is a diagram showing the structure of a storage chip according to one embodiment of the present invention.

[0067] [Figure 5-1] Figure 5A is a diagram showing the area distribution in a bank of a storage chip according to one embodiment of the present invention.

[0068] [Figure 5-2] Figures 5B to 5D show the mapping of physical addresses in a bank of a storage chip according to one embodiment of the present invention.

[0069] [Figure 6]Figures 6A and 6B show the distribution of storage chip banks according to one embodiment of the present invention.

[0070] [Figure 7] This is a diagram of a data reading / writing method according to one embodiment of the present invention.

[0071] [Figure 8] This is a diagram showing the structure of a storage according to one embodiment of the present invention.

[0072] [Figure 9] This is a diagram of a data reading / writing method according to one embodiment of the present invention. [Modes for carrying out the invention]

[0073] Before describing the data processing systems, storage, data reading / writing methods, and devices mentioned in the embodiments of this application, a memory addressing scheme related to the embodiments of this application will be described first.

[0074] Memory addressing scheme:

[0075] Generally, storage used as memory may include multiple storage chips. The storage may be phase-change memory (PCM), dynamic random access memory (DRAM), or another type of storage.

[0076] From a hardware architecture perspective, a storage chip is the smallest physical unit for storing data in storage. The internal storage space of any storage chip may be further divided. Each storage chip contains multiple banks. Each bank may be considered a storage matrix, which resembles a grid matrix. This "grid matrix" has many columns and many rows. When data in the storage space needs to be retrieved, only the bank and the rows and columns within that bank need to be specified. The size of each bank, the number of rows, and the number of columns are fixed; that is, the range of logical addresses covered by each bank is fixed.

[0077] In storage systems such as PCM or DRAM, multiple storage chips within the storage system share the same logical address. That is, after a storage system receives a read / write request that holds a logical address, its internal control circuit converts the logical address to a physical address and sends the physical address to each storage chip. The address decoding circuit deployed in each storage chip parses the physical address to obtain address information that points to the bank, column, and row, and then performs data read / write operations in the bank, column, and row pointed to by the address information.

[0078] Figure 1 is a diagram of memory addressing in storage. Figure 1 shows an example of the addressing scheme of a single storage chip in storage. An address register is located on the storage chip. The address register is configured to receive a physical address transmitted from the storage's control circuit. After receiving the physical address, the address register transmits the received physical address to the address decoding circuit on the storage chip. The address decoding circuit determines address information pointing to the bank, column, and row from the received physical address, and can then locate the bank and the row or column within that bank on the storage chip.

[0079] Specifically, the address decoding circuit includes bank control logic, column address decoding logic, and row address decoding logic. After receiving a physical address, the address register may send the portion of the physical address that represents the bank (e.g., 4 bits) to the bank control logic, the portion of the logical address that represents the column (e.g., 15 bits) to the column address decoding logic, and the portion of the logical address that represents the row (e.g., 11 bits) to the row address decoding logic. The bank control logic parses and retrieves address information that points to the bank based on the received portion of the physical address, the column address decoding logic parses and retrieves address information that points to the column based on the received portion of the physical address, and the row address decoding logic parses and retrieves address information that points to the row based on the received portion of the physical address.

[0080] If the storage system includes eight storage chips, each storage chip may contribute a portion of the data. For example, each storage chip contributes 8 bytes of data. In this way, the amount of data read / written in each data read / write operation is the sum of the amounts of data contributed by all storage chips. For example, the amount of data read / written in a single data read / write operation is 64 bytes of data. The data at logical addresses is distributed across the storage chips of the storage system in terms of physical location.

[0081] Since the physical addresses parsed by the address decoding circuits of all storage chips are translated from the same logical addresses, the address information that is ultimately parsed and retrieved, and which points to banks, columns, and rows, is generally the same. In other words, it can be understood that logical addresses map to the same location on all storage chips, or the same physical addresses map to the same location on all storage chips.

[0082] The error rates of different areas within a storage chip's bank differ due to the influence of factors such as the routing method of the storage's internal circuitry and the design method of the drive voltage inside the storage. That is, each bank may be further divided into multiple areas based on the error rate, and the error rates in each area are within the same range, while the error rates in different areas are within different ranges. In other words, each bank of a storage chip includes areas with high error rates, areas with low error rates, and areas with moderate error rates. If the location to which a logical address is mapped in the bank is in an area with a high error rate, the probability of an error during data read / write at that location is high, meaning that the read or written data is prone to errors. If the location to which a logical address is mapped in the bank is in an area with a low error rate, the probability of an error during data read / write at that location is low, meaning that the read or written data is not prone to errors. The error rate indicates the probability of a data error during data read / write at that location or area. In the embodiments of this application, the specific method for calculating the error rate is not limited. The error rate at a given location or area may be equal to the ratio of the number of erroneous bits in a given number of data read / write operations to the total number of bits read / written in a given number of data read / write operations, or it may be equal to the ratio of the number of erroneous bits in multiple data read / write operations performed within a unit of time to the total number of bits read / written in a given number of data read / write operations.

[0083] It can be seen that the same logical address (or the physical address converted from a logical address) ultimately maps to the same location in each storage chip's bank. Since the locations are the same, the error rate range of the area to which those locations belong is also the same. If the error rate of the area to which the location belongs is high, the error rate of data read / write at the logical address doubles.

[0084] In other words, with this memory addressing scheme, the overall error rate of the storage changes along with the area where the data is located during data reading / writing, making it unstable. In addition, error correction circuits are added to the storage to reduce the overall error rate, but the unstable error rate increases the difficulty of setting up the error correction circuits.

[0085] Therefore, the storage referred to in this application has an address remapping function. When storage having this function maps logical addresses, the logical addresses may be mapped to different locations in the storage chip's bank. That is, the locations to which logical addresses are mapped in the bank do not belong to areas having the same error rate range, and the locations to which logical addresses are mapped in the bank may be distributed across multiple areas. In this way, the error rates of the locations to which logical addresses are mapped in the bank are not exactly the same. The storage's address remapping function has two implementations. One implementation involves processing the physical addresses converted from logical addresses received by each storage chip in the storage. The storage's address remapping function is implemented using a first address remapping module (the first address remapping module is configured to modify the physical addresses) within the storage chip. In the other implementation, a control circuit in the storage converts logical addresses to physical addresses that are not exactly the same and transmits these non-existent physical addresses to the respective storage chips. The storage address remapping function is implemented within the control circuit using a second address remapping module (configured to modify logical addresses). Regardless of which implementation is used, the final effect of the implementation is that the same logical address is ultimately mapped to different locations in the storage chip's bank. In this way, during data read / write operations in the storage, the overall error rate of the storage does not fluctuate significantly with the area where the data is located, resulting in a stable overall error rate for the storage.

[0086] First implementation: The storage address remapping function is implemented by using a first address remapping module within the storage chip.

[0087] The following description will explain a data processing system provided in embodiments of the present application with reference to the accompanying drawings. Figure 2 is a diagram showing the structure of a data processing system according to one embodiment of the present application. The data processing system 10 includes a processor 100 and storage 200.

[0088] Processor 100 is the computing core of the system. Processor 100 can complete the main data calculation operation. In the process of performing the data calculation operation, processor 100 may access storage 200 and read data from or write data to storage 200. For example, processor 100 may read data from storage 200 and perform data calculations on the read data; processor 100 may further store the data generated by the data calculations in storage 200.

[0089] When accessing storage 200, processor 100 sends a read / write request to storage 200. The read / write request holds the logical address of the data to indicate to storage 200 that it will perform a data read / write at that logical address.

[0090] In this embodiment of the present application, the processor 100 can access the storage 200, and the processor 100 can further enable the address remapping function of the storage 200. For example, the processor 100 may send an address remapping instruction to the storage 200. The address remapping instruction is used to enable the address remapping function of the storage 200.

[0091] The processor 100 may be a central processing unit (CPU) or another specific integrated circuit. Alternatively, the processor 100 may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or similar.

[0092] The storage 200 has a data storage function. The storage 200 may store data requested by the processor 100 for data calculations, and may further store data generated by the data calculations of the processor 100. For example, the storage 200 receives and processes read / write requests from the processor 100, and performs data read / write at logical addresses: writes data obtained by the data calculations of the processor 100 to logical addresses, or reads data requested by the processor 100 for data calculations from logical addresses and feeds the read data back to the processor 100.

[0093] In this embodiment of the present application, the storage 200 further has an address remapping function. The storage 200 can map logical addresses to target locations in multiple banks. The target locations in the multiple banks are distributed across multiple areas, and different areas correspond to different error rate ranges.

[0094] Storage 200 may provide an external option to enable the address remapping function, that is, it may allow devices other than Storage 200 to enable the address remapping function. When the address remapping function is enabled, Storage 200 may map the received logical address to a target location in multiple banks, where the target location in multiple banks is distributed across multiple areas. When the address remapping function is not enabled, Storage 200 may map the received logical address to the same location in multiple banks.

[0095] The manner in which the storage 200 provides an option to enable the address remapping function is not limited to this embodiment of the present application. For example, the storage 200 device may be configured to include an address remapping function enable switch, and the user may switch the address remapping function enable switch on or off based on actual requirements. As another example, the storage 200 may be configured to include an address remapping instruction parsing function. Devices other than the storage 200 may send address remapping instructions to the storage 200. The storage 200 enables the address remapping function by parsing the received address remapping instructions.

[0096] In addition, if the address remapping feature is enabled, storage 200 may provide several different address remapping policies externally. Any address remapping policy describes some or all of the following information: The number of first address remapping modules 222 in operation; and A method by which any first address remapping module 222 in operation corrects the physical address converted from a logical address.

[0097] The number of active first address remapping modules 222 and / or the method by which any active first address remapping module 222 modifies the physical address converted from the logical address may differ as described in different address remapping policies.

[0098] Correspondingly, the method by which the storage 200 provides multiple different address remapping policies is not limited to this embodiment of the present application. For example, a selection button for multiple different address remapping policies may be configured on the storage 200, and the user may use this selection button to select an address remapping policy based on their actual requirements. As another example, the storage 200 is configured to include an address remapping command parsing function. In addition to commanding the activation of the address remapping function, an address remapping command sent to the storage 200 by a device other than the storage 200 may further indicate an address remapping policy. The storage 200 parses the received address remapping command, activates the address remapping function, and performs address remapping by using the address remapping policy indicated in the address remapping command.

[0099] Of course, in actual applications, the address remapping function may, alternatively, be enabled before the storage 200 leaves the factory; that is, the address remapping function is enabled after the storage 200 leaves the factory and no further action is required.

[0100] The following description will explain the structure of the storage 200 with reference to Figure 3. Figure 3 shows the storage 200 according to one embodiment of the present application. The storage 200 includes a control circuit 210 and a plurality of storage chips 220. For a specific description of the storage chips 220, please refer to the description above. Details will not be described again in this specification.

[0101] In the storage 200, the storage chip 220 is primarily configured to store data, and the control circuit 210 is the control center for the storage 200. The control circuit 210 can process read / write requests received by the storage 200. Specifically, the control circuit 210 parses the logical address held in the read / write request and can perform data read / write operations on each storage chip 220 based on the logical address.

[0102] In this embodiment of the present invention, the control circuit 210 can convert logical addresses to physical addresses and transmit the physical addresses to each storage chip 220. In any storage chip 220, the physical address points to a target location in the bank of the storage chip 220.

[0103] When Storage 200 enables address remapping, target locations across multiple banks are distributed in different areas, and these different areas correspond to different error rate ranges.

[0104] If Storage 200 does not enable address remapping, target locations across multiple banks will be distributed within the same area.

[0105] If the storage 200 optionally provides an external option to enable the address remapping function, the control circuit 210 can detect the status of the address remapping function's activation, i.e., decide whether or not to enable the address remapping function. For example, if an address remapping function activation switch is configured on the storage 200 device, the control circuit 210 may detect the address remapping function activation switch and decide whether or not to enable the address remapping function. As another example, if the storage 200 is configured to include an address remapping instruction parsing function, the parsing function may be implemented by the control circuit 210, which may parse the received address remapping instruction and enable the address remapping function.

[0106] The following explanation only describes the case where storage 200 enables the address remapping function. If storage 200 does not enable the address remapping function, please refer to the method shown in Figure 1 for how storage 200 internally performs data read / write operations at logical addresses. Further details are not provided in this specification.

[0107] From the memory addressing scheme shown in Figure 1, it can be seen that when a logical address is mapped to each storage chip 220, the control circuit 210 needs to translate the logical address to obtain the corresponding physical address, and then the physical address is sent to each storage chip 220. Each storage chip 220 parses the physical address to determine address information that points to the bank, row, and column, and then locates its position within the bank based on the address information that points to the bank, row, and column.

[0108] In this embodiment of the present application, different storage chips 220 may parse physical addresses using different parsing schemes, and the address information ultimately obtained using different parsing schemes and pointing to banks, rows, and columns may not be exactly the same. By "not exactly the same," I mean, in this specification, that the address information obtained using different parsing schemes and pointing to banks, rows, and columns may be completely different or partially different.

[0109] It is assumed that when the same physical address is parsed in two different ways, two groups of address information may be generated. Each group of address information includes address information pointing to banks, rows, and columns. If two groups of address information exist and the address information pointing to banks is the same, and if two groups of address information exist and the address information pointing to rows and columns is completely different, then the two groups of address information correspond to two different locations in the bank, and the areas in which these two locations are located may be different. If two groups of address information exist and the address information pointing to banks and rows is the same, and if two groups of address information exist and the address information pointing to columns is different, then the two groups of address information correspond to two different locations in the bank, and the areas in which these two locations are located may be different.

[0110] When storage 200 enables the address remapping function, storage chip 220 may parse physical addresses in completely different ways to obtain multiple groups of address information that are not exactly the same, in order to ensure that the target locations to which logical addresses are mapped are distributed in different areas across multiple banks. In other words, multiple storage chips 220 may convert physical addresses into multiple groups of address information that are not exactly the same, and these multiple groups of address information that are not exactly the same correspond to different target locations in multiple banks. In this way, the target locations in multiple banks do not belong to the same area.

[0111] In this embodiment of the present application, "not exactly the same" refers to two cases: one is that they are partially the same and partially different; the other is that they are completely different.

[0112] The storage chip 220 may parse physical addresses in partially different ways to obtain multiple groups of address information that are not exactly the same. That is, for some of the storage chips 220 in a plurality of storage chips 220, the physical addresses are parsed in one parsing method to obtain multiple groups of the same address information; and for other parts of the storage chips 220 in a plurality of storage chips 220, the physical addresses are parsed in a different parsing method for logical addresses to obtain multiple groups of the same address information. In this way, of the multiple groups of address information that are not exactly the same, some of the multiple groups of address information correspond to the same target location in multiple banks, and other parts of the multiple groups of address information correspond to other same target locations in multiple banks.

[0113] For example, storage chip 220 uses two different parsing methods for physical addresses. Storage chips 220-1, 220-2, 220-3, and 220-4 use one parsing method, while storage chips 220-5, 220-6, 220-7, and 220-8 use another. In this case, the four groups of address information obtained by parsing in storage chips 220-1, 220-2, 220-3, and 220-4 are the same, each pointing to target location A in the bank of storage chips 220-1, 220-2, 220-3, and 220-4, respectively. The location of target location A is the same in the bank to which it belongs. In other words, the target location is the same across multiple banks. The four groups of address information obtained by parsing in storage chips 220-5, 220-6, 220-7, and 220-8 are the same, and each points to target location B in the bank of storage chips 220-5, 220-6, 220-7, and 220-8, respectively. The location of target location B is the same in the bank to which it belongs. In other words, the target location is the same across multiple banks.

[0114] The specific method by which the storage chip 220 parses physical addresses is not limited to this embodiment of the present application. Any method by which a physical address can be parsed into address information pointing to banks, rows, and columns is applicable to this embodiment of the present application. For example, in the process of parsing a physical address, the storage chip 220 may modify a portion of the fields of the physical address and then, based on a first mapping relationship, analyze the modified physical address to generate address information pointing to banks, rows, and columns. The first mapping relationship records the correspondence between each field in the physical address and the banks, rows, and columns.

[0115] The following description explains the structure and specific functions of the storage 200. Figure 4 is a diagram of the structure of the storage 200 according to one embodiment of the present application. The storage 200 includes a control circuit 210 and a plurality of storage chips 220. Each storage chip 220 includes an address register 221, a first address remapping module 222, and an address decoding circuit 223.

[0116] The address register 221 is a register with memory functionality. The first address remapping module 222 and the address decoding circuit 223 may be logic circuits. The specific internal structure of the first address remapping module 222 and the address decoding circuit 223 is not limited to this embodiment of the present application. Any logic circuit capable of implementing the corresponding functions may be used as the first address remapping module 222 and the address decoding circuit 223.

[0117] In each storage chip 220, the first address remapping module 222 is positioned between the address register 221 and the address decoding circuit 223. That is, the physical address transmitted to the address decoding circuit 223 by the address register 221 first passes through the first address remapping module 222. After performing an operation on the physical address, the first address remapping module 222 may transmit the processed physical address to the address decoding circuit 223. The first address remapping module 222 may perform one of two operations on the physical address. One is to modify the physical address, and the other is to keep each field of the physical address immutable. The first address remapping module 222 in an operational state may modify the physical address, while the first address remapping module 222 in an inactive state keeps each field of the physical address immutable.

[0118] For any storage chip 220, the address register 221 is configured to store the physical address transmitted by the control circuit 210. Generally, when transmitting a physical address, the control circuit 210 requires multiple clock cycles to transmit the entire physical address to the storage chip 220. That is, the amount of data transferred by the control circuit 210 in one clock cycle is limited, and the control circuit 210 may transmit fields of the physical address to the storage chip 220 at multiple points in time. The address register 221 may receive and buffer the fields of the physical address transmitted by the control circuit 210. For example, the control circuit 210 may transmit a 6-bit address in each clock cycle, the total length of the physical address is 48 bits, and the control circuit 210 may transmit the 48-bit physical address to the storage chip 220 over 8 clock cycles. Each time the address register 221 receives 6 bits, the address register 221 buffers those 6 bits until the amount of buffered data reaches 48 bits.

[0119] After address register 221 has received all addresses included in the physical address, address register 221 may send the physical address to the first address remapping module 222.

[0120] After receiving the physical address transmitted by the address register 221, the first address remapping module 222 may perform a processing operation on the physical address and transmit the processed physical address to the address decoding circuit 223. The method by which the first address remapping module 222 modifies the physical address is not limited to this embodiment of the present application. For example, the first address remapping module 222 may perform an inversion on a portion of the fields in the physical address. As another example, the first address remapping module 222 may perform a subtraction on a portion of the fields in the physical address and a preset value to obtain the difference, and replace the portion of the fields in the physical address with the difference.

[0121] After obtaining a physical address from the first address remapping module 222, the address decoding circuit 223 may analyze the physical address based on the first mapping relationship to obtain address information indicating the bank, row, and column. Subsequently, the target location in the bank of the storage chip 220 is determined, and data reading / writing is performed at the target address. The specific implementation of how the address decoding circuit 223 obtains address information indicating the bank, row, and column based on the physical address is not limited to this embodiment of the present application. Any method of analyzing a physical address to obtain address information indicating the bank, row, and column is applicable to this embodiment of the present application.

[0122] Specifically, the address decoding circuit 223 includes bank control logic, column address decoding logic, and row address decoding logic. After modifying the physical address, the first address remapping module 222 may send the portion of the modified physical address that represents the bank (e.g., 4 bits) to the bank control logic, the portion of the physical address that represents the column (e.g., 15 bits) to the column address decoding logic, and the portion of the physical address that represents the row (e.g., 11 bits) to the row address decoding logic. The bank control logic obtains address information pointing to the bank based on the received portion of the physical address, the column address decoding logic obtains address information pointing to the column based on the received portion of the physical address, and the row address decoding logic obtains address information pointing to the column based on the received portion of the physical address.

[0123] After the address decoding circuit 223 obtains address information pointing to banks, rows, and columns, the target location in the bank may be located, and data reading / writing is implemented by changing the operating voltage of the component at the target location.

[0124] Figure 1 shows that the address register 221 can transmit a physical address to the address decoding circuit 223, which can parse the received physical address to obtain address information indicating the bank, row, and column. In this embodiment of the present invention, a first address remapping module 222 is added before the address decoding circuit 223. The first address remapping module 222 added before the address decoding circuit 223 can modify the physical address received by the address decoding circuit 223, thereby allowing the address decoding circuit 223 to parse the modified physical address. This modification method requires only a portion of the circuit logic to be added to the original design of the storage 200. This modification method is simple and low cost.

[0125] The following description lists several specific methods by which the storage 200 implements the address remapping function, based on the control circuit 210 shown in Figure 4.

[0126] Before describing some specific implementations, it is first assumed that, by testing storage 200, it is determined that the banks of storage 200 contain three areas, each corresponding to a different error rate range. For ease of explanation, the three areas will be referred to as Area 1, Area 2, and Area 3. The distribution of physical addresses in the three areas may be shown in Table 1. Table 1 [Table 1]

[0127] ADDR[M] represents the Mth bit of the physical address, and ADDR[M:N] represents the Mth to Nth bits of the physical address. For example, ADDR[1]=0 means that the first bit of the physical address is 0. ADDR[2:8]+ADDR[9:31]≧40 means that the sum of twice the values ​​of the 2nd to 8th bits of the physical address and the 9th to 31st bits of the physical address is greater than or equal to 40.

[0128] Figure 5A shows the distribution of areas AREA1, AREA2, and AREA3 in the bank. Area AREA1 is located in the lower part of the bank, area AREA3 is located in the upper part of the bank, and area AREA2 is located in the center of the bank. According to the test, of the three areas, area AREA1 has the highest error rate, area AREA2 has a moderate error rate, and area AREA3 has the lowest error rate.

[0129] It should be noted that the division of a bank into areas with different error rate ranges is related to several factors, including the routing of the control circuit 210 inside the storage 200 and the design of the drive voltage in the storage 200. The number of areas included in the bank and the error rate range of each area are related to the specific design of the storage 200. In addition, during specific testing, the number of areas with different error rate ranges in the bank and the error rate range of each area will change due to the setting of test parameters. For example, during specific testing, if a higher accuracy is selected or if there are more level options for the error rate, the bank may include more areas. Table 1 merely lists the types of possible distributions.

[0130] For any storage chip 220, the storage 200 may implement address remapping in the following two ways:

[0131] Method 1: The physical address indicating the location of the storage chip 220 in area AREA1 within the bank is mapped to the target location in area AREA3.

[0132] The locations in Area 1 and Area 3 are on different rows. Therefore, during the mapping from Area 1 to Area 3, the fields that are within the physical address and represent the row need to be changed.

[0133] The first address remapping module 222 modifies fields in the physical address that represent rows and columns, thereby changing the address information that points to banks, rows, and columns and is obtained based on the modified physical address, compared to the address information that points to banks, rows, and columns and is obtained based on the original physical address.

[0134] For example, the field ADDR'[15:12], which is included in the modified physical address and represents a row, satisfies the following: ADDR'[15:12]=40-ADDR[15:12].

[0135] As shown in Figure 5B, the address register 221 sends the physical address to the first address remapping module 222, which then modifies the fields in the physical address that are present and represent rows, and the physical address pointing to the location in area AREA1 within the bank of the storage chip 220 is mapped to the target location in area AREA3.

[0136] Method 2: The physical address indicating the location of the storage chip 220 in area AREA1 within the bank is mapped to the target location in area AREA2.

[0137] The simplest way to map from Area 1 to Area 2 is to modify a field that is within the physical address and represents a row, or a field that is within the physical address and represents both a row and a column.

[0138] (1) Modify a field that is located within a physical address and represents a row.

[0139] The first address remapping module 222 may modify fields in the physical address that represent rows, thereby changing the address information that points to banks, rows, and columns and is obtained based on the modified physical address, relative to the address information that points to rows in the address information that points to banks, rows, and columns and is obtained based on the original physical address.

[0140] In other words, the first address remapping module 222 only needs to modify fields that are in the physical address and represent rows. For example, the first address remapping module 222 may invert one or more bits in the fields that are in the physical address and represent rows, for example, it may invert bit ADDR

[16] in the fields that are in the physical address and represent rows, i.e., the modified bit ADDR'

[16] in the physical address and representing rows satisfies: ADDR'

[13] =invADDR

[16] .

[0141] As shown in Figure 5C, the address register 221 in the control circuit 210 sends the row field in the physical address to the first address remapping module 222, and after the first address remapping module 222 modifies the row field in the physical address, the physical address pointing to the location in area AREA1 within the bank of the storage chip 220 is mapped to the target location in area AREA2.

[0142] (2) Modify the fields that are located within the physical address and represent rows and columns.

[0143] The first address remapping module 222 may modify fields in the physical address that represent rows and columns, thereby changing the address information that points to banks, rows, and columns and is obtained based on the modified physical address, relative to the address information that points to banks, rows, and columns and is obtained based on the original physical address, which points to columns.

[0144] In other words, the first address remapping module 222 needs to modify fields that are in the physical address and represent rows and columns. For example, the first address remapping module 222 may perform an inversion on one or more bits in the field that is in the physical address and represents a column, for example, on bit ADDR

[23] in the field that is in the physical address and represents a column, i.e., the modified bit ADDR'

[23] in the physical address and representing a column satisfies: ADDR'

[23] =invADDR

[23] . The first address remapping module 222 may perform an inversion on one or more bits in the field that is in the physical address and represents a row, for example, on bit ADDR

[16] in the field that is in the physical address and represents a row, i.e., the modified bit ADDR'

[16] in the physical address and representing a row satisfies: ADDR'

[13] =invADDR

[16] .

[0145] As shown in Figure 5D, the address register 221 in the control circuit 210 sends the column field in the physical address to the first address remapping module 222, and after the first address remapping module 222 modifies the column field in the physical address, the physical address pointing to the location in area AREA1 within the bank of the storage chip 220 is mapped to the target location in area AREA2.

[0146] The specific method described above by the first address remapping module 222 to modify the physical address is merely an example. In actual applications, the method by which the first address remapping module 222 modifies the physical address may be designed based on the location of fields representing rows and columns within the physical address, and the distribution of areas having different error rate ranges.

[0147] In addition, in actual applications, considering different design methods for the storage chip 220, the banks inside the storage chip 220 may be arranged in a planar manner, that is, the banks included in the storage chip 220 may be on the same plane, or the banks inside the storage chip 220 may be arranged in a three-dimensional manner, that is, the banks in the storage chip 220 may include multiple stacked layers.

[0148] Figure 6A shows the arrangement of banks within the storage chip 220 in a planar configuration, where the banks within the storage chip 220 are on the same plane. In this configuration, all areas within the banks of the storage chip 220 are on the same plane, meaning that during address remapping, only the fields that are within the physical address and represent rows / columns need to be changed.

[0149] Figure 6B shows the arrangement of banks within the storage chip 220 in a three-dimensional manner, where each bank within the storage chip 220 includes an upper layer and a lower layer. In this specification, only an example in which a bank includes two layers is used. In practice, a bank may alternatively include three or more layers.

[0150] Each layer of the bank may contain multiple different areas, each corresponding to a different error rate range. In addition, due to factors such as the internal design of the storage 200, the error rate ranges of opposing areas in the upper and lower layers of the bank may differ. Opposing areas are two areas located opposite each other within the same bank.

[0151] In this configuration, the physical address typically includes a field representing the layer in the bank, and address remapping may be implemented by changing the field representing the layer in the bank, in addition to changing the field representing the row / column within the physical address.

[0152] In the preceding description, only a few possible specific methods for implementing address remapping are illustrated by example. In this embodiment of the present application, the method by which the control circuit 210 modifies each field in the physical address when implementing address remapping is not limited. Any method of modifying the physical address to implement a mapping from a physical address pointing to a location in one area to a location in another area is applicable to this embodiment of the present application.

[0153] In addition, in some scenarios, the error rates at the same row and column positions within different banks may differ, i.e., the error rates at the same position in different banks may differ. In this scenario, when correcting the physical address, the first address remapping module 222 may further correct bits that are in the physical address and represent the bank. The method of correcting the bits is similar to the method by which the first address remapping module 222 corrects bits that are in the physical address and represent the row or column, and the details are not described again herein.

[0154] When the storage 200 enables the address remapping function based on the control circuit 210 shown in Figure 4, it is not necessary for all first address remapping modules 222 inside the storage 200 to be operational. That is, when the storage 200 enables the address remapping function, it is only necessary to ensure that some of the first address remapping modules 222 in the multiple first address remapping modules 222 can modify the received physical address. Another first address remapping module 222 does not need to modify the received physical address and may send the physical address directly to the address decoding circuit 223 after receiving it.

[0155] For example, if storage 200 includes N storage chips, then storage 200 includes N first address remapping modules 222. In storage 200, M first address remapping modules 222 may be enabled, thereby making M first address remapping modules 222 operational. M is a positive integer less than N.

[0156] Whether or not the first address remapping module 222 in the storage 200 is operational can be set by the control circuit 210. For example, after the control circuit 210 receives an address remapping command, the control circuit 210 may control the first address remapping module 222 to be operational if its quantity is equal to a specified value in a plurality of first address remapping modules 222.

[0157] Alternatively, whether or not the first address remapping module 222 in the storage 200 is operational, and which of the first address remapping modules 222 is operational, may be set before the storage 200 leaves the factory; that is, some of the first address remapping modules 222 in a plurality of first address remapping modules 222 are set to operational before the storage 200 leaves the factory.

[0158] Alternatively, the processor 100 may indicate whether the first address remapping modules 222 in the storage 200 are operational, and which first address remapping modules 222 are operational. For example, in addition to commanding the activation of the address remapping function, the address remapping command sent by the processor 100 further holds an address remapping policy. The address remapping policy indicates the number (e.g., M) of the first address remapping modules 222 that are operational. The control circuit 210 may control the operational status of a subset of the first address remapping modules 222 in a plurality of first address remapping modules 222. The number of such subsets of the first address remapping modules 222 is as indicated by the address remapping command. As another example, in addition to commanding the activation of the address remapping function, the address remapping command sent by the processor 100 further indicates which first address remapping modules 222 are operational, i.e., which first address remapping modules 222 need to be operational. The control circuit 210 may control a portion of the first address remapping modules 222 in a plurality of first address remapping modules 222 to be activated. The portion of the first address remapping module 222 is the first address remapping module 222 indicated by the address remapping instruction.

[0159] In addition, if the address remapping policy further indicates a method by which the operational first address remapping module 222 modifies the physical address, the control circuit 210 may further control the operational first address remapping module 222 to modify the received physical address in the modification method indicated by the address remapping policy.

[0160] Naturally, in actual applications, if each of the first address remapping modules 222 in operation modifies the physical address in a different manner, all of the first address remapping modules 222 inside the storage 200 may be controlled to be in operation. Due to the manner in which each of the first address remapping modules 222 in operation modifies the physical address, the physical addresses obtained by the processing of the first address remapping modules 222 in the storage chip 220 (i.e., the modified physical addresses) are not exactly the same, and these multiple physical addresses, which are not exactly the same, point to the target location in the bank of the storage chip 220.

[0161] In the control circuit 210 shown in Figure 4, a corresponding first address remapping module 222 is provided for each storage chip 220. In actual applications, the storage 200 may alternatively have first address remapping modules 222 provided for only some of the storage chips 220. The first address remapping modules 222 may be set to an operational state before being shipped from the factory, or when the processor 100 sends an address remapping command instructing the processor to enable the address remapping function, the control circuit 210 controls the included first address remapping modules 222 to be set to an operational state.

[0162] The following description illustrates the data reading / writing method provided in this application with reference to Figure 7. In this specification, an example is used in which the storage 200 provides an external option to enable address remapping functionality. If the storage 200 does not provide an external option to enable address remapping functionality, steps 700-701 may be omitted.

[0163] Stage 700: The processor 100 sends an address remapping instruction to the storage 200. The address remapping instruction is used to instruct the storage to enable the address remapping function, and the address remapping instruction further indicates a first address remapping module 222 that must be in an operational state.

[0164] Stage 701: The storage 200 receives an address remapping instruction and controls the first address remapping module 222, indicated by the address remapping instruction, to be activated according to the instruction.

[0165] Stage 702: Processor 100 sends a read / write request to storage 200. The read / write request holds the logical address of the data.

[0166] Stage 703: The storage 200 receives a read / write request and maps the logical address to the target location in the bank of the storage chip 220 in the storage 200.

[0167] In storage 200, after converting logical addresses to physical addresses, control circuit 210 transmits the physical addresses to each storage chip 220. The address register 221 in each storage chip 220 receives the physical address transmitted by control circuit 210 and transmits the physical address to the first address remapping module 222 of each storage chip 220. For the first address remapping module 222 that is operational, the first address remapping module 222 modifies the physical address and transmits the modified physical address to the address decoding circuit 223 of the storage chip 220. The address decoding circuit 223 analyzes the modified physical address to obtain address information indicating the bank, row, and column, and then locates the target position in the bank based on the address information.

[0168] For the first address remapping module 222 that is not in operation, the first address remapping module 222 transmits the received physical address to the address decoding circuit 223 of the storage chip 220. The address decoding circuit 223 analyzes the acquired physical address to obtain address information that points to the bank, row, and column, and then locates the target position in the bank based on the address information.

[0169] Stage 704: Storage 200 performs data read / write operations at target locations in the bank of each storage chip 220.

[0170] If the read / write request is a read request to request that data be read, the storage 200 reads the data from the target location in the bank of each storage chip 220, summarizes the data read from the storage chip 220, and feeds the data back to the processor 100.

[0171] If a read / write request is a write request to request the writing of data, the storage 200 writes the data held in the write request to the target location in the bank of each storage chip 220. The data written at each target location is a portion of the data held in the write request, and the data written at all target locations is the data held in the write request.

[0172] Second implementation: The address remapping function for storage 200 is implemented by using a second address remapping module 211 inside the control circuit 210.

[0173] In this implementation, the structure of the data processing system 10 provided in this embodiment of the present application, and the functions of the processor 100 and storage 200 included in the data processing system, are similar to those of the data processing system shown in Figure 2. For further details, please refer to the above description. Further details are not described again herein.

[0174] In this implementation, if the address remapping feature is enabled, storage 200 may further provide multiple different address remapping policies externally. Any address remapping policy describes some or all of the following information: The number of second address remapping modules 211 in operation; and A method in which any second address remapping module 211 that is in operation modifies the logical address.

[0175] The number of active second address remapping modules 211 and / or the method by which any active second address remapping module 211 modifies logical addresses may differ as described in different address remapping policies.

[0176] Correspondingly, the method by which the storage 200 provides multiple different address remapping policies is not limited to this embodiment of the present application. For example, a selection button for multiple different address remapping policies may be configured on the storage 200, and the user may use this selection button to select an address remapping policy based on their actual requirements. As another example, the storage 200 is configured to include an address remapping command parsing function. In addition to commanding the activation of the address remapping function, an address remapping command sent to the storage 200 by a device other than the storage 200 may further indicate an address remapping policy. The storage 200 parses the received address remapping command, activates the address remapping function, and performs address remapping by using the address remapping policy indicated in the address remapping command.

[0177] The following description explains the structure of storage 200. Similar to the structure of storage 200 shown in Figure 3, in this implementation, storage 200 includes a control circuit 210 and a plurality of storage chips 220. However, in this implementation, the structure of the control circuit 210 and storage chips 220 differs from the structure of storage 200 shown in Figure 3. The structure of storage chips 220 is similar to the structure of storage chips 220 in the embodiment shown in Figure 1. For details, please refer to the above description. Details are not described again in this specification.

[0178] In the storage 200, the storage chip 220 is primarily configured to store data, and the control circuit 210 is the control center for the storage 200. The control circuit 210 can process read / write requests received by the storage 200. Specifically, the control circuit 210 parses the logical address held in the read / write request and can perform data read / write operations on each storage chip 220 based on the logical address.

[0179] In this embodiment of the present application, the control circuit 210 can map logical addresses to each storage chip 220. In any storage chip 220, the logical address may be mapped to a target location in the bank of the storage chip 220. In other words, the control circuit 210 may map logical addresses to target locations in multiple banks.

[0180] When Storage 200 enables address remapping, target locations across multiple banks are distributed in different areas, and these different areas correspond to different error rate ranges.

[0181] If Storage 200 does not enable address remapping, target locations across multiple banks will be distributed within the same area.

[0182] If the storage 200 optionally provides an external option to enable the address remapping function, the control circuit 210 can detect the status of the address remapping function's activation, i.e., decide whether or not to enable the address remapping function. For example, if an address remapping function activation switch is configured on the storage 200 device, the control circuit 210 may detect the address remapping function activation switch and decide whether or not to enable the address remapping function. As another example, if the storage 200 is configured to include an address remapping instruction parsing function, the parsing function may be implemented by the control circuit 210, which may parse the received address remapping instruction and enable the address remapping function.

[0183] The following explanation will only describe the case where the storage 200 enables the address remapping function. If the storage 200 does not enable the address remapping function, please refer to the method shown in Figure 1 for how the control circuit 210 performs address read / write operations at logical addresses. Further details will not be explained again in this specification.

[0184] From the memory addressing scheme shown in Figure 1, it can be seen that when logical addresses are mapped to each storage chip 220, the control circuit 210 needs to convert the logical addresses to obtain the corresponding physical addresses, and then transmit the physical addresses to each storage chip 220.

[0185] In this embodiment of the present application, when the control circuit 210 translates a logical address, different translation schemes may be used for different storage chips 220, and different physical addresses are ultimately obtained in the different translation schemes.

[0186] The control circuit 210 may translate logical addresses for the storage chip 220 in ways that are not exactly the same, thereby obtaining multiple physical addresses that are not exactly the same. For example, for some of the storage chips 220 in multiple storage chips 220, the control circuit 210 may translate logical addresses in one translation scheme to ultimately obtain multiple identical physical addresses; for other parts of the storage chips 220 in multiple storage chips 220, the control circuit 210 may translate logical addresses in another translation scheme to ultimately obtain multiple identical physical addresses. In this way, for multiple ultimately obtained physical addresses that are not exactly the same, some of the multiple physical addresses correspond to the same target location in multiple banks, and other parts of the multiple physical addresses correspond to other identical target locations in multiple banks. As another example, the control circuit 210 may translate logical addresses for the storage chip 220 in completely different ways to obtain multiple groups of completely different address information. That is, for different storage chips 220, the control circuit 210 may use different translation schemes for logical addresses to translate logical addresses, ultimately obtaining multiple completely different physical addresses. In this way, multiple physical addresses correspond to different target locations in multiple banks, and target locations in multiple banks do not belong to the same area.

[0187] For example, the control circuit 210 translates the logical addresses of the storage chips 220 in two different ways. One translation method is used for storage chips 220-1, 220-2, 220-3, and 220-4, while the other translation method is used for storage chips 220-5, 220-6, 220-7, and 220-8. In this case, the physical addresses obtained by storage chips 220-1, 220-2, 220-3, and 220-4 are the same, pointing to target location A in the bank of storage chips 220-1, 220-2, 220-3, and 220-4, respectively. The location of target location A in the bank to which target location A belongs is the same. In other words, the target location is the same across multiple banks. The physical addresses obtained by storage chips 220-5, 220-6, 220-7, and 220-8 are the same, and each points to target location B in its respective bank. The location of target location B is the same in the bank to which it belongs. In other words, the target location is the same across multiple banks.

[0188] The specific method by which the control circuit 210 translates a logical address is not limited to this embodiment of the present application. Any method by which a logical address can be translated into a physical address is applicable to this embodiment of the present application. For example, in the process of translating a logical address, the control circuit 210 may modify some or all of the fields in the logical address, and then analyze the modified logical address based on a preset mapping relationship to generate a physical address.

[0189] The following description explains the structure and specific functions of the storage 200. Figure 8 is a diagram of the structure of the storage 200 according to one embodiment of the present application. The control circuit 210 includes a plurality of second address remapping modules 211 and a plurality of address translation modules 212. The second address remapping modules 211 and the plurality of address translation modules 212 may be logic circuits. The specific internal structure of the second address remapping modules 211 and the plurality of address translation modules 212 is not limited to this embodiment of the present application. Any logic circuit capable of implementing the corresponding functions is applicable to this embodiment of the present application.

[0190] Each storage chip 220 corresponds to one second address remapping module 211 and one address translation module 212. The second address remapping module 211 is positioned between the storage chip 220 and the address translation module 212. That is, logical addresses first pass through the second address remapping module 211. After performing an operation on the logical address, the second address remapping module 211 may send the logical address on which the operation was performed to the address translation module 212. The address translation module 212 is configured to translate the logical address on which the operation was performed to a physical address based on a second mapping relationship. The second mapping relationship is a mapping relationship between a physical address and a logical address.

[0191] The second address remapping module 211 may perform one of two processing operations on a logical address. One is to modify the logical address. The method by which the second address remapping module 211 modifies the logical address is not limited to this embodiment of the present application. For example, the second address remapping module 211 may perform an inversion on a portion of the fields in the logical address. Another example is that the second address remapping module 211 may perform a subtraction on a portion of the fields and a preset value in the logical address to obtain the difference, and replace the portion of the fields in the logical address with the difference. The other is to keep each field in the logical address immutable. The activated second address remapping module 211 may modify the logical address, while the deactivated second address remapping module 211 keeps each field in the logical address immutable.

[0192] After receiving the logical address transmitted by the second address remapping module 211, the address translation module 212 may translate the acquired logical address to the corresponding physical address based on the second mapping relationship and transfer the physical address to the storage chip 220. For the process of parsing the physical address inside the storage chip 220, please refer to the relevant description in the embodiment shown in Figure 1. Details are not described again herein.

[0193] Figure 8 is merely a diagram of possible structures of the control circuit 210. The module division method in the control circuit 210 is not limited to this embodiment of the present application.

[0194] The method by which the second address remapping module 211 modifies logical addresses is similar to the method by which the first address remapping module 222 modifies physical addresses. See above for details. Details will not be described again in this specification. The difference is that the second address remapping module 211 may use different specific values ​​for fields that are within the logical address and represent banks, rows, and columns, and may perform different specific actions for each field.

[0195] Based on the storage 200 shown in Figure 8, when the storage 200 enables the address remapping function, it is not necessary for all second address remapping modules 211 in the control circuit 210 to be operational. That is, when the storage 200 enables the address remapping function, it is only necessary to ensure that some of the second address remapping modules 211 in the multiple second address remapping modules 211 can modify the received logical address. Another second address remapping module 211 does not need to modify the received logical address and may send the logical address directly to the address decoding circuit 223 after receiving it.

[0196] The method for setting the second address remapping module 211 to an active state is similar to the method for setting the first address remapping module 222 to an active state. For details, please refer to the above description. Details will not be described again in this specification.

[0197] The following description illustrates the data reading / writing method provided in this application with reference to Figure 9. In this specification, an example is used in which the storage 200 provides an external option to enable address remapping functionality. If the storage 200 does not provide an external option to enable address remapping functionality, steps 900-901 may be omitted.

[0198] Stage 900: The processor 100 sends an address remapping instruction to the storage 200. The address remapping instruction is used to instruct the storage to enable the address remapping function, and the address remapping instruction further indicates a second address remapping module 211 that must be in an operational state.

[0199] Stage 901: The storage 200 receives an address remapping instruction and controls the second address remapping module 211, indicated by the address remapping instruction, to be activated according to the instruction.

[0200] Stage 902: Processor 100 sends a read / write request to storage 200. The read / write request holds a logical address.

[0201] Stage 903: Storage 200 receives a read / write request and maps the logical address to the target location in the bank of each storage chip 220 of storage 200.

[0202] In the storage 200, the second address remapping module 211 corresponding to each storage chip 220 obtains the transmitted logical address. For the second address remapping module 211 that is in operation, the second address remapping module 211 modifies the fields in the logical address and sends the modified logical address to the address translation module 212 corresponding to the storage chip 220. The address translation module 212 translates the modified logical address to obtain the physical address and sends the physical address to the corresponding storage chip 220.

[0203] For the second address remapping module 211, which is not in operation, the second address remapping module 211 transmits the received logical address to the address translation module 212 corresponding to the storage chip 220. The address translation module 212 translates the logical address to obtain the physical address and transmits the physical address to the corresponding storage chip 220.

[0204] Stage 904: Storage 200 performs data read / write operations at target locations in the bank of each storage chip 220.

[0205] If the read / write request is a read request to request that data be read, the storage 200 reads the data from the target location in the bank of each storage chip 220, summarizes the data read from the storage chip 220, and feeds the data back to the processor 100.

[0206] If a read / write request is a write request to request the writing of data, the storage 200 writes the data held in the write request to the target location in the bank of each storage chip 220. The data written at each target location is a portion of the data held in the write request, and the data written at all target locations is the data held in the write request.

[0207] It should be noted that in the second implementation, an example in which the second address remapping module 211 directly modifies the logical address is used for illustrative purposes. In possible implementations, the second address remapping module 211 may not directly modify the logical address, but rather modify the physical address obtained by the translation of the address translation module 212, and then send the modified physical address to the corresponding storage chip 220.

[0208] It should be noted that the module division in the embodiments of this application is merely an example and represents only a logical functional division. In actual implementations, other division methods may be used. The functional modules in the embodiments of this application may be integrated into a single processing module, or each module may exist physically independently, or two or more modules may be integrated into a single module. The integrated module may be implemented in hardware form or in the form of a software functional module.

[0209] The embodiments described above may be implemented in whole or in part by using software, hardware, firmware, or any combination thereof. When software is used for implementation, the embodiments described above may be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, optical fiber, or digital subscriber line (DSL)) or wireless (e.g., infrared, radio, or microwave) method. Computer-readable storage media may be any usable media accessible by a computer, or a data storage device such as a server or data center that integrates one or more usable media. Usable media may be magnetic media (e.g., floppy disks, hard disk drives, or magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media may be solid-state drives (SSDs).

[0210] Those skilled in the art will understand that embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may be implemented in the form of hardware-only embodiments, software-only embodiments, or embodiments of a combination of software and hardware. In addition, the present application may be implemented in the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, CD-ROM, optical storage, and similar) containing computer-usable program code.

[0211] This application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products relating to this application. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and combinations of processes and / or blocks in the flowcharts and / or block diagrams, may be implemented by using computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, an embedded processor, or another programmable data processing device, which may generate a machine in which the instructions executed by the processor of the computer or another programmable data processing device generate a device for implementing one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0212] These computer program instructions may, alternatively, be stored in computer-readable storage capable of guiding a computer or another programmable data processing device to operate in a particular manner, thereby generating a product including an instruction unit, the instruction unit implementing a function specified in one or more processes of a flowchart and / or one or more blocks of a block diagram.

[0213] These computer program instructions may, alternatively, be loaded onto a computer or another programmable data processing device, thereby executing a series of operational steps on the computer or another programmable device to generate computer implementation processing, and thus the instructions executed on the computer or another programmable device provide steps to implement the functions specified in one or more processes of a flowchart and / or one or more blocks of a block diagram.

[0214] It will be apparent to those skilled in the art that various modifications and variations can be made to this application without departing from its scope. In this case, if these modifications and variations made to this application fall within the scope of the claims of this application and the equivalent art, this application is intended to encompass these modifications and variations.

Claims

1. A data processing system, wherein the data processing system is: A processor configured to send read / write requests to storage, wherein the read / write requests hold the logical address of the data; and The storage is configured to receive the read / write request, map the logical address to a target location in a bank of N storage chips in the storage, and perform data read / write operations at the target location in the bank of the N storage chips. A data processing system comprising the following, wherein the target positions in the bank of the N storage chips are distributed in different areas, and N is a positive integer.

2. The data processing system according to claim 1, wherein the processor is further configured to send an address remapping instruction to the storage before sending the read / write request, the address remapping instruction being used to enable the address remapping function of the storage.

3. The storage comprises a control circuit and N first address remapping modules, each storage chip corresponding to one first address remapping module, and the control circuit: It is configured to control M first address remapping modules to be activated in accordance with the address remapping instruction, where M is not greater than N; The data processing system according to claim 2, wherein any first address remapping module in operation is configured to modify a physical address converted from the logical address, and the modified physical address points to a target location in a bank of storage chips corresponding to the first address remapping module.

4. The first address remapping module in the operating state is: The data processing system according to claim 3, configured to modify fields located within the aforementioned physical address and indicating rows and / or columns in a bank.

5. The first address remapping module is located within the corresponding storage chip; The data processing system according to any one of claims 2 to 4, wherein the control circuit is further configured to: receive the read / write request, convert the logical address to the physical address, and transmit the physical address to each storage chip.

6. The first address remapping module that is not in the operating state: The data processing system according to claim 3, wherein each field in the physical address is configured to remain immutable, and the physical address points to a target location in a bank of storage chips corresponding to the first address remapping module.

7. A data processing system according to any one of claims 2 to 4, wherein any storage chip is configured to determine a target location in a bank of the storage chip based on a physical address obtained from a corresponding first address remapping module, and to perform data read / write operations at the target location.

8. The control circuit includes N second address remapping modules, each storage chip corresponds to one second address remapping module, and the control circuit is: It is configured to control M first address remapping modules to be activated in accordance with the address remapping instruction, where M is not greater than N; The data processing system according to claim 2, wherein any second address remapping module in the operating state is configured to modify the logical address, and the modified logical address is mapped to a target location in a bank of storage chips corresponding to the second address remapping module.

9. The second address remapping module in the aforementioned operating state is: The data processing system according to claim 8, configured to modify fields located within the aforementioned logical address and indicating rows and / or columns in a bank.

10. The second address remapping module, which is not in the aforementioned operating state, is: The data processing system according to claim 8, configured to maintain each field in the logical address immutably.

11. The control circuit includes an address translation module; The data processing system according to any one of claims 2 and 8 to 10, wherein the address translation module is configured to: obtain a logical address from the second address remapping module, convert the logical address obtained from the second address remapping module into a physical address, and transmit the physical address to a storage chip corresponding to the second address remapping module.

12. A storage device comprising a control circuit and N storage chips; The control circuit receives read / write requests transmitted by the processor, the read request is used to request that data be read / written in the storage, the read / write request is configured to hold the logical address of the data, convert the logical address to a physical address, and transmit the physical address converted from the logical address to the N storage chips, the physical address points to a target location in the bank of the N storage chips of the storage, the target locations in the bank of the N storage chips are distributed in different areas, and A storage system in which any storage chip is configured to perform data read / write operations at a target location in the bank of the storage chip.

13. The storage according to claim 12, wherein the control circuit is further configured to receive an address remapping instruction transmitted by the processor, the address remapping instruction being used to enable the address remapping function of the storage.

14. The storage comprises N first address remapping modules, each storage chip corresponds to one first address remapping module, and the control circuit comprises: It is configured to control M first address remapping modules to be activated in accordance with the address remapping instruction, where M is not greater than N; The storage according to claim 13, wherein any first address remapping module in the operating state is configured to modify the physical address converted from the logical address, and the modified physical address points to a target location in a bank of storage chips corresponding to the first address remapping module.

15. The first address remapping module in the operating state is: The storage according to claim 13, which is located within the aforementioned physical address and is configured to modify fields that point to rows and / or columns in a bank.

16. The first address remapping module that is not in the operating state: The storage according to claim 15, configured to maintain each field in the physical address immutably, wherein the physical address points to a target location in a bank of storage chips corresponding to the first address remapping module.

17. The storage according to any one of claims 14 to 16, wherein any storage chip is configured to: determine a target location in the bank of the storage chip based on a physical address obtained from a corresponding first address remapping module, and to perform data read / write operations at the target location.

18. The control circuit has N second address remapping modules, each storage chip corresponds to one second address remapping module, and the control circuit: It is configured to control the activation of M second address remapping modules in accordance with the address remapping instruction, where M is not greater than N; The storage according to claim 13, wherein any second address remapping module in the operating state is configured to modify the logical address, and the modified logical address is mapped to a target location in a bank of storage chips corresponding to the second address remapping module.

19. The second address remapping module in the aforementioned operating state is: The storage according to claim 18, which is located within the aforementioned logical address and is configured to modify fields that point to rows and / or columns in a bank.

20. The second address remapping module, which is not in the aforementioned operating state, is: The storage according to claim 18, wherein each field in the logical address is configured to remain immutable, and the logical address is mapped to a target location in a bank of storage chips corresponding to the second address remapping module.

21. The control circuit includes an address translation module; The storage according to any one of claims 13 and 18 to 20, wherein the address translation module is configured to: translate a logical address obtained from the second address remapping module into a physical address, and transmit the physical address to a storage chip corresponding to the second address remapping module.

22. A data read / write method, wherein the method is applied to a storage, the storage comprising a control circuit and N storage chips, where N is a positive integer, and the method is: The control circuit receives a read / write request transmitted by the processor, the read request is used to request that data be read / written in the storage, the read / write request performs the steps of holding the logical address of the data, converting the logical address to a physical address, and transmitting the physical address converted from the logical address to the N storage chips, the physical address points to a target location in the bank of the N storage chips of the storage, the target locations in the bank of the N storage chips are distributed in different areas; and A step in which any storage chip performs data read / write operations at a target location in the bank of the storage chip. A method that includes [a certain feature].

23. The aforementioned method is: The method according to claim 22, further comprising the step of the control circuit receiving an address remapping instruction transmitted by the processor, wherein the address remapping instruction is used to activate the address remapping function of the method.

24. The storage comprises N first address remapping modules, each storage chip corresponds to one first address remapping module, and the method is: The control circuit controls M first address remapping modules to be activated in accordance with the address remapping command, where M is not greater than N; and The step of correcting the physical address converted from the logical address by any first address remapping module in the operating state. The method according to claim 23, further comprising the modified physical address which points to a target location in the bank of storage chips corresponding to the first address remapping module.

25. The step of correcting the physical address converted from the logical address by the first address remapping module in the operating state is as follows: The first address remapping module, in the operating state, modifies fields within the physical address that point to rows and / or columns in the bank. The method according to claim 24, having the following characteristics.

26. The aforementioned method is: The first address remapping module, which is not in operation, maintains the integrity of each field in the physical address. The method according to claim 24, further comprising, wherein the physical address points to a target location in a bank of storage chips corresponding to the first address remapping module.

27. The step of performing data read / write operations at the target location in the bank of the storage chip by the arbitrary storage chip is: The method according to any one of claims 24 to 26, comprising the steps of: determining the target location in the bank of the storage chip based on a physical address obtained from a corresponding first address remapping module using the arbitrary storage chip; and performing data read / write at the target location.

28. The control circuit has N second address remapping modules, each storage chip corresponds to one second address remapping module, and the method is: The control circuit controls M second address remapping modules to be activated in accordance with the address remapping command, where M is not greater than N; and The step of modifying the logical address by any second address remapping module in the aforementioned operating state. The method according to claim 23, further comprising the modified logical address which points to a target location in the bank of storage chips corresponding to the second address remapping module.

29. The step of modifying the logical address by the second address remapping module in the operating state is as follows: The second address remapping module, in the operating state, modifies a portion of the fields within the logical address that point to rows and / or columns in the bank. The method according to claim 28, wherein the method is characterized by having the following:

30. The aforementioned method is: The second address remapping module, which is not in the aforementioned operating state, maintains the integrity of each field in the logical address. The method according to claim 28, further comprising the logical address indicating a target location in a bank of storage chips corresponding to the second address remapping module.

31. The control circuit includes an address translation module, and the steps of the control circuit translating the logical address to the physical address and transmitting the physical address translated from the logical address to the N storage chips of the storage are as follows: The address translation module converts the logical address obtained from the second address remapping module into a physical address, and transmits the physical address to the storage chip corresponding to the second address remapping module. The method according to any one of claims 23 and 28 to 30, comprising:

32. A computing device comprising the storage described in any one of claims 12 to 21.

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