Multi-point reference distribution loop

Abstract

The circuit includes an amplifier, a pre-driver circuit, and an output circuit (206). The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit (206) includes a first transistor (228) and a second transistor (230). The first transistor (228) has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor (230) has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor (228), and a second terminal coupled to a reference terminal.

Description

Background Art

[0001] Various types of analog-to-digital converters (ADCs), such as successive approximation register (SAR) ADCs, sigma-delta ADCs, and pipeline ADCs, include a capacitive digital-to-analog converter (DAC) as a circuit element. For example, in a SAR ADC, during the conversion process, the capacitive DAC is periodically switched during the conversion process to generate an analog voltage level for comparison with the sampled input signal. The input of the capacitive DAC is continuously switched either to a reference voltage or to ground, thereby drawing current from the reference voltage source. The current drawn by the capacitive DAC can vary with the input signal. The variation in the current drawn by the capacitive DAC can induce non-linearity in the reference voltage.

Summary of the Invention

[0002] In one example, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The amplifier has first and second inputs and an output. The first transistor has a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal. The second transistor has a first terminal, a second terminal coupled to the first terminal of the first transistor, and a control terminal. The third transistor has a first terminal, a second terminal coupled to the second input of the amplifier, and a control terminal coupled to the second terminal of the second transistor. The fourth transistor has a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal. The fifth transistor has a control terminal, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to a reference terminal. The sixth transistor has a control terminal coupled to the first terminal of the fifth transistor, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal.

[0003] In another example, the circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.

[0004] In a further example, the analog-to-digital converter (ADC) includes a first capacitive digital-to-analog converter (CDAC), a second CDAC, and a reference buffer. The first CDAC has an input. The second CDAC has an input. The reference buffer is coupled to the first CDAC and the second CDAC. The reference buffer includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the first CDAC. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the reference terminal. The third transistor has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the second CDA. The fourth transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of an analog-to-digital converter that includes a multi-point reference distribution circuit.

[0006] [Figure 2A] Figure 1 is a schematic diagram of a first multi-point reference distribution circuit suitable for use with an analog-to-digital converter. [Figure 2B] Figure 1 is a schematic diagram of a first multi-point reference distribution circuit suitable for use with an analog-to-digital converter.

[0007] [Figure 3A] Figure 1 shows a schematic diagram of a second multi-point reference distribution circuit suitable for use with the analog-to-digital converter. [Figure 3B] Figure 1 shows a schematic diagram of a second multi-point reference distribution circuit suitable for use with the analog-to-digital converter.

[0008] [Figure 4A] This signal diagram compares the output of a single-point reference distribution circuit with the output of a multi-point reference distribution circuit shown in Figure 2A / Figure 2B or Figure 3A / Figure 3B. [Figure 4B] This signal diagram compares the output of a single-point reference distribution circuit with the output of a multi-point reference distribution circuit shown in Figure 2A / Figure 2B or Figure 3A / Figure 3B.

[0009] [Figure 5] Figure 1 is a block diagram of a digital beamforming system including an analog-to-digital converter. [Modes for carrying out the invention]

[0010] Analog-to-digital converters (ADCs) and other circuits include a reference voltage circuit that provides a stable voltage for comparison with other voltages in the circuit. For example, a bandgap circuit may be implemented to provide a reference voltage. A buffer circuit may be coupled to the output of the reference voltage circuit to drive the reference voltage to a load circuit. In circuits with variable load current, such as an ADC where the reference buffer is driving a capacitive digital-to-analog converter (CDAC), the reference voltage provided to the load by the reference buffer may be subject to nonlinearity caused by changes in current flowing through parasitic circuit inductances. Settling time may be introduced into the circuit timing adjustment to allow the reference voltage to settle to a desired value after changes in current draw. Settling time may reduce circuit performance by increasing the time required to perform operations such as analog-to-digital conversion cycles.

[0011] The multi-point reference distribution circuit described herein can reduce the reference voltage settling time by providing reference buffer outputs distributed across various load circuit inputs. The distributed outputs reduce the parasitic inductance driven by each output, thereby reducing the nonlinearity caused by changes in current flow through the parasitic inductance.

[0012] Figure 1 is a block diagram of an exemplary analog-to-digital converter (ADC) 100. The ADC 100 may be a successive approximation register (SAR) or a pipelined ADC. The ADC 100 includes ADC stages 102 and 104, a reference buffer circuit 110, a voltage reference circuit 112, and a combinational logic 114. The ADC stage 102 receives an input signal (VIN) for digitization. The ADC stage 102 digitizes VIN to a predetermined resolution and provides a digital value 120 representing Vin to the combinational logic 114. The ADC stage 102 provides a residual signal 124 to a subsequent ADC stage for digitization. Although two ADC stages (ADC stages 102 and 104) are shown in Figure 1, the ADC 100 may include three or more ADC stages. The ADC stage 104 receives a residual signal from the previous ADC stage and digitizes the residual signal to a predetermined resolution. The ADC stage 104 provides a digital value 122 representing the residual signal to the combinational logic 114. The combinational logic 114 combines the digital values ​​received from the ADC stage to generate a digital output value (DOUT) representing DIN.

[0013] ADC stage 102 includes CDAC 106, and ADC stage 104 includes CDAC 108. CDACs 106 and 108 include switched capacitors coupled in parallel. The switched capacitors may form a bank of binary weighted capacitors.

[0014] The voltage reference circuit 112 provides a reference voltage (V) for use by the ADC stage. REFThe voltage reference circuit 112 generates a reference voltage 118. The voltage reference circuit 112 is coupled to the reference buffer circuit 110. The reference buffer circuit 110 buffers the reference voltage and provides the buffered reference voltage 118 for use by the ADC stage (e.g., by the CDACs 106 and 108). The reference buffer circuit 110 provides the buffered reference voltage 118 to multiple inputs of each CDAC, for example, each switched capacitor bank of each CDAC. The reference buffer circuit 110 includes output circuit elements distributed to provide drive for the buffered reference voltage 118, relatively close to the different switched capacitor circuits of the CDAC. In this way, the nonlinearity of the buffered reference voltage 118 due to the path inductance and capacitance is reduced. Also, the settling time provided by the ADC stage to adapt to the CDAC switching is reduced, which can reduce the overall conversion time of the ADC stage.

[0015] Figures 2A and 2B are schematic diagrams of the first exemplary multi-point reference distribution circuit 200. The multi-point reference distribution circuit 200 is an example of a reference buffer circuit 110. The multi-point reference distribution circuit 200 includes an amplifier 202, a pre-driver circuit 204, and an output circuit 206. For reference, CDAC 106 and CDAC 108 are shown coupled to the multi-point reference distribution circuit 200. The first input of the amplifier 202 is a reference voltage (V REF The second input of amplifier 202 is coupled to the output of pre-driver circuit 204 to receive the reference feedback. The output of amplifier 202 is coupled to the input of pre-driver circuit 204. Capacitor 208 may be coupled between the output of amplifier 202 and a reference terminal (e.g., ground) to filter the amplifier output signal (REFINT).

[0016] The pre-driver circuit 204 isolates the output of the amplifier 202 (output signal REFINT) from the current changes drawn by the load circuit (e.g., CDAC 106 and 108). The pre-driver circuit 204 includes transistors 210, 212, 214, 216, 218, and 220, and snubber circuits 222, 223, and 224. Transistors 210, 212, and 214 control the current supplied to the REFOUT output of the pre-driver circuit 204. Transistors 216, 218, and 220 control the current drawn from the REFOUT output of the pre-driver circuit 204. Transistors 210, 212, and 220 may be p-type field-effect transistors (PFETs) as shown. Transistors 214, 216, and 218 may be n-type field-effect transistors (NFETs) as shown.

[0017] Transistor 210 includes a first terminal, also called a "current terminal" (e.g., source), which is coupled to a first power supply terminal (VDD1). A second terminal of transistor 210, also called a "current terminal" (e.g., drain), is coupled to the first current terminal (e.g., source) of transistor 212 and the control terminal (e.g., gate) of transistor 214. The control terminal (e.g., gate) of transistor 210 is coupled to a bias voltage circuit (PBIAS). The second current terminal (e.g., drain) of transistor 212 is coupled to a reference voltage terminal (e.g., ground). The control terminal (e.g., gate) of transistor 212 is coupled to the output of amplifier 202. The first current terminal (e.g., drain) of transistor 214 is coupled to a second power supply terminal (VDD2). The power supply voltage provided at VDD2 may be different from the power supply voltage provided at VDD1. The second current terminal (e.g., source) of transistor 214 provides the REFOUT output of pre-driver circuit 204. The snubber circuit 223 includes a resistor and a capacitor connected in series between the second current terminal of transistor 214 and the reference voltage terminal (e.g., ground). The snubber circuit 224 includes a resistor and a capacitor connected in series between the control terminal of transistor 214 and the reference voltage terminal.

[0018] Transistor 216 includes a first current terminal (e.g., drain) coupled to a second power supply terminal. The second current terminal (e.g., source) of transistor 216 is coupled to the first current terminal (e.g., drain) of transistor 218 and the control terminal (e.g., gate) of transistor 220. The control terminal (e.g., gate) of transistor 216 is coupled to the output of amplifier 202. The second current terminal (e.g., source) of transistor 218 is coupled to a reference voltage terminal (e.g., ground). The control terminal (e.g., gate) of transistor 218 is coupled to a bias voltage circuit (NBIAS). The first current terminal (e.g., source) of transistor 220 is coupled to the second current terminal of transistor 214. The second current terminal (e.g., drain) of transistor 220 is coupled to a reference voltage terminal (e.g., ground). The snubber circuit 222 includes a resistor and a capacitor coupled in series between the control terminal of transistor 220 and the reference voltage terminal (e.g., ground).

[0019] The output circuit 206 is coupled to the REFOUT output of the pre-driver circuit 204, the output taken from the second current terminal of transistor 210 (labeled node 238 in Figures 2A and 2B), and the output taken from the second current terminal of transistor 216 (labeled node 240 in Figures 2A and 2B). The output circuit 206 includes transistor pairs 226 distributed so that each pair is positioned close to the reference voltage input of CDA 106 or CDA 108. Although four transistor pairs 226 are shown in Figure 2B, the example of the multi-point reference distribution circuit 200 may include any number of transistor pairs 226 (e.g., more than four transistor pairs 226). Each transistor pair 226 includes transistors 228 and 230 and snubber circuits 232, 234, and 236. As shown, transistor 228 may be an NFET and transistor 230 may be a PFET. The current drawn by the reference voltage inputs of CDACs 106 and 108 flows primarily from the local power supply terminals, rather than from the pre-driver circuit 204 or amplifier 202. By positioning transistor pair 226 close to the reference voltage input (e.g., less than 50 micrometers from the reference voltage input), the parasitic inductance and capacitance between the output of transistor pair 226 and the reference voltage input are reduced, thereby reducing the nonlinearity of the reference voltage provided at the reference voltage input.

[0020] The first current terminal of transistor 228 is coupled to the second power supply terminal. The second current terminal (e.g., source) of transistor 228 provides the output of transistor pair 226 and is coupled to the CDAC reference voltage input. The snubber circuit 234 is coupled between the second current terminal of transistor 228 and the reference voltage terminal (e.g., ground). The snubber circuit 234 includes a resistor and a capacitor coupled in series. The snubber circuit 234 can be implemented using relatively small resistance and capacitance values. For example, the resistor of the snubber circuit 234 can have a resistance of a few ohms, and the capacitor of the snubber circuit 234 can have a capacitance of less than a picofarad. The control terminal (e.g., gate) of transistor 228 is coupled to the second current terminal of transistor 210. The snubber circuit 232 is coupled between the control terminal of transistor 228 and the reference voltage terminal (e.g., ground). The snubber circuit 232 includes a resistor and a capacitor coupled in series. [[ID=!]]

[0021] The first current terminal (e.g., source) of transistor 230 is coupled to the second current terminal of transistor 228. The second current terminal (e.g., drain) of transistor 230 is coupled to the reference voltage terminal (e.g., ground). The control terminal (e.g., gate) of transistor 230 is coupled to the second current terminal of transistor 216. The snubber circuit 236 is coupled between the control terminal of transistor 230 and the reference voltage terminal (e.g., ground). The snubber circuit 236 includes a resistor and a capacitor coupled in series.

[0022] Figures 3A and 3B are schematic diagrams of a second exemplary multi-point reference distribution circuit 300. The multi-point reference distribution circuit 300 is an example of a reference buffer circuit 110. The multi-point reference distribution circuit 300 includes an amplifier 202 and a pre-driver circuit 204, as described with respect to the multi-point reference distribution circuit 200. The multi-point reference distribution circuit 300 also includes an output circuit 306 coupled to the pre-driver circuit 204. The output circuit 306 is similar to the output circuit 206 and includes transistors 228 and 230, as well as snubber circuits 232, 234, and 236 (shown as transistor pair 326). The output circuit 306 also includes a drive circuit at the control terminals of transistors 228 and 230. The drive circuit can be considered an extension and distribution of the pre-driver circuit 204. The addition of the drive circuit reduces inductance in the signal path controlling transistors 228 and 230, and associated signal degradation. Although Figure 3B shows four transistor pairs 326, an example of the multi-point reference distribution circuit 300 may include any number of transistor pairs 326 (e.g., more than four transistor pairs 226), each transistor pair 326 being coupled to a drive circuit as shown in Figure 3B.

[0023] The drive circuit includes transistors 302, 304, 308, and 310. Transistors 302 and 304 may be PFETs as shown in the figure. Transistors 308 and 310 may be NFETs as shown in the figure. Transistors 302 and 304 are coupled to the control terminal of transistor 228. The first current terminal (e.g., source) of transistor 302 is coupled to the second power supply terminal, and the second current terminal (e.g., drain) of transistor 302 is coupled to the control terminal of transistor 228. The control terminal of transistor 302 is coupled to the control terminal of transistor 210. The first current terminal (e.g., source) of transistor 304 is coupled to the second current terminal of transistor 302, and the second current terminal (e.g., drain) of transistor 304 is coupled to the reference voltage terminal (e.g., ground). The control terminal (e.g., gate) of transistor 304 is coupled to the control terminal of transistor 212.

[0024] The first current terminal (e.g., drain) of transistor 308 is coupled to the second power supply terminal, and the second current terminal (e.g., source) of transistor 308 is coupled to the control terminal of transistor 230. The control terminal of transistor 308 is coupled to the control terminal of transistor 304. The first current terminal (e.g., drain) of transistor 310 is coupled to the second current terminal of transistor 308, and the second current terminal of transistor 310 is coupled to a reference voltage terminal (e.g., ground). The control terminal of transistor 310 is coupled to the control terminal of transistor 218.

[0025] The multi-point reference distribution circuit 200 can reduce the calibration error in the CDAC by, for example, eight times compared to the case of using a single-output reference buffer. The multi-point reference distribution circuit 300 can further improve the calibration time. For example, the multi-point reference distribution circuit 300 enables the calibration error in the CDAC to be reduced by ten times compared to the case of using a single-output reference buffer.

[0026] FIGS. 4A and 4B are signal diagrams comparing the output of the single-point reference distribution circuit and the output of the multi-point reference distribution circuit 200. FIG. 4A shows the buffered reference voltage 400 provided by the output of the multi-point reference distribution circuit 300 (provided at the second current terminal of transistor 228) and the buffered reference voltage 402 provided by the output of the single-output buffer circuit. The buffered reference voltage 400 behaves well and settles to the final value as a primary resistance-capacitor charging function. In contrast, the buffered reference voltage 402 vibrates (rings) and takes time to settle to the final value. FIG. 4B shows an expansion of the last 20 picoseconds of FIG. 4A.

[0027] Figure 4B shows that, in the last 20 picoseconds of the graph, the buffered reference voltage 400 has an error of approximately 140 microvolts, while the buffered reference voltage 402 has an error of approximately 1.23 millivolts. Therefore, the error of the buffered reference voltage 402 is approximately 10 times that of the buffered reference voltage 400. Furthermore, the settling time when using the buffered reference voltage 402 is also increased compared to the settling time required when using reference voltage 400 to allow ringing on the buffered reference voltage 402 to subside.

[0028] Figure 5 is a block diagram of the digital beamforming system 500. The digital beamforming system 500 includes multiple instances of an ADC 100 coupled to a beamforming circuit 502. Each instance of the ADC 100 is coupled to a receiver circuit (not shown) that provides a signal (R1-RN) to the ADC to be digitized. Each ADC 100 includes a reference buffer circuit 110, which may be implemented as a multi-point reference distribution circuit 200 or a multi-point reference distribution circuit 300. The ADC digitizes the received signal and provides the beamforming circuit 502 with digital values ​​representing the received signal. The beamforming circuit 502 weights the digital values ​​received from the ADC and sums the weighted values ​​to generate a beam signal representing the signal received from a selected direction.

[0029] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (A) in the first example, device A is connected to device B by a direct connection, or (B) in the second example, if the intervening component C does not alter the functional relationship between device A and device B, device A is connected to device B via the intervening component C so that device B is controlled by device A via the control signal generated by device A.

[0030] Furthermore, in this document, the phrase "based on ~" means "based at least partially on ~". Therefore, if X is based on Y, X can be a function of Y and any number of other factors.

[0031] A device "configured" to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform that function (e.g., programmed and / or wired), and / or may be configured (or reconfigurable) by the user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the configuration and / or layout of hardware components and / or the interconnection of the devices, or a combination thereof.

[0032] In this specification, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean the interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0033] Circuits or devices described herein as including specific components may instead be adapted to be coupled with those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current sources) may instead include only semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be adapted, at or after manufacturing, for example by an end user and / or a third party, to be coupled with at least some of the passive elements and / or power sources to form the described structure.

[0034] While this specification describes the use of specific transistors, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, field-effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in conjunction with the devices described herein. Transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0035] In the claims, there may be references to the control input and current terminals or terminals of a transistor. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0036] In this specification, an FET is "on" or "enabled" to mean that a conduction channel exists in the FET and drain current can flow through the FET. In this specification, an FET is "off" or "disabled" to mean that a conduction channel does not exist and drain current does not flow through the FET. However, an "off" FET may still have current flowing through the transistor's body diode.

[0037] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available before component replacement. Components indicated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the indicated resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0038] While certain elements of the examples described are included in the integrated circuit and other elements are outside the integrated circuit, additional or fewer features may be incorporated into the integrated circuit in other examples. Also, some or all of the features illustrated as being outside the integrated circuit may be included in the integrated circuit, and / or some of the features illustrated as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0039] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise stated herein, "about," "approximately," or "substantially" preceding a parameter means a reasonable range of values ​​within + / - 10% of that parameter, or, if the parameter is zero, near zero.

[0040] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a circuit, An amplifier having first and second inputs and outputs, A first transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal, A second transistor having a first terminal, a second terminal coupled to the first terminal of the first transistor, and a control terminal, A third transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and a control terminal coupled to the second terminal of the second transistor, A fourth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal, A fifth transistor having a control terminal, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to a reference terminal, A sixth transistor having a control terminal connected to the first terminal of the fifth transistor, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the reference terminal, A circuit that includes this.

2. The circuit according to claim 1, A circuit further comprising a seventh transistor having a control terminal coupled to the first terminal of the first transistor, a first terminal, and a second terminal coupled to the second terminal of the third transistor.

3. The circuit according to claim 2, An eighth transistor having a first terminal connected to the first terminal of the third transistor, a second terminal connected to the control terminal of the seventh transistor, and a control terminal connected to the control terminal of the second transistor, A ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output of the amplifier, A circuit that further includes the following.

4. The circuit according to claim 2, A circuit further comprising an eighth transistor having a control terminal coupled to the first terminal of the sixth transistor, a first terminal coupled to the second terminal of the seventh transistor, and a second terminal coupled to the reference terminal.

5. The circuit according to claim 4, A ninth transistor having a first terminal connected to the first terminal of the third transistor, a second terminal connected to the control terminal of the eighth transistor, and a control terminal connected to the output of the amplifier, A tenth transistor having a first terminal connected to the second terminal of the ninth transistor, a second terminal connected to the reference terminal, and a control terminal connected to the control terminal of the fifth transistor, A circuit that further includes the following.

6. The circuit according to claim 4, A first resistor and a first capacitor are connected in series between the control terminal and the reference terminal of the seventh transistor, A second resistor and a second capacitor are connected in series between the control terminal and the reference terminal of the eighth transistor, A circuit that further includes the following.

7. The circuit according to claim 1, A first resistor and a first capacitor are connected in series between the control terminal and the reference terminal of the third transistor, A second resistor and a second capacitor are connected in series between the control terminal and the reference terminal of the sixth transistor, A circuit that further includes the following.

8. It is a circuit, An amplifier having a first input, a second input and an output, A pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier, Output circuit and, Includes, The output circuit described above, A first transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit, A second transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the reference terminal, including, circuit.

9. The circuit according to claim 8, wherein the pre-driver circuit is A third transistor having a control terminal coupled to the output of the amplifier, a first terminal configured as the first output of the pre-driver circuit, and a second terminal coupled to the reference terminal, A fourth transistor having a first terminal, a second terminal coupled to the first terminal of the third transistor, and a control terminal, A fifth transistor having a first terminal, a second terminal coupled to the second input of the amplifier and configured as the third output of the pre-driver circuit, and a control terminal coupled to the second terminal of the fourth transistor, A sixth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal configured as the second output of the pre-driver circuit, A seventh transistor having a control terminal, a first terminal connected to the second terminal of the sixth transistor, and a second terminal connected to the reference terminal, An eighth transistor having a control terminal connected to the first terminal of the seventh transistor, a first terminal connected to the second terminal of the fifth transistor, and a second terminal connected to the reference terminal, A circuit that includes this.

10. The circuit according to claim 9, wherein the pre-driver circuit is A first snubber circuit coupled to the control terminal of the fifth transistor, A second snubber circuit coupled to the control terminal of the eighth transistor, A circuit that includes this.

11. The circuit according to claim 8, wherein the output circuit is A third transistor having a first terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal coupled to the first bias voltage circuit, A fourth transistor having a first terminal connected to the second terminal of the third transistor, a second terminal connected to the reference terminal, and a control terminal connected to the output of the amplifier, A circuit that includes this.

12. The circuit according to claim 8, wherein the output circuit is A third transistor having a first terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the output of the amplifier, A fourth transistor having a first terminal connected to the second terminal of the third transistor, a second terminal connected to the reference terminal, and a control terminal connected to the second bias voltage circuit, A circuit that includes this.

13. The circuit according to claim 8, A first snubber circuit coupled to the control terminal of the first transistor, A second snubber circuit coupled to the control terminal of the second transistor, A circuit that further includes the following.

14. An analog-to-digital converter (ADC), A first capacitive digital-to-analog converter (CDAC) having an input, A second CDAC having an input, A reference buffer coupled to the first CDAC and the second CDAC, Includes, The aforementioned reference buffer, An amplifier having a first input, a second input and an output, A pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier, Output circuit and, Includes, The output circuit described above, A first transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the first CDAC, A second transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the reference terminal, A third transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the second CDAC, A fourth transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal, including, circuit.

15. The ADC according to claim 14, wherein the pre-driver circuit is A fifth transistor having a control terminal coupled to the output of the amplifier, a first terminal configured as the first output of the pre-driver circuit, and a second terminal coupled to the reference terminal, A sixth transistor having a first terminal, a second terminal coupled to the first terminal of the fifth transistor, and a control terminal, A seventh transistor having a first terminal, a second terminal coupled to the second input of the amplifier and configured as the third output of the pre-driver circuit, and a control terminal coupled to the second terminal of the sixth transistor, An eighth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal configured as the second output of the pre-driver circuit, A ninth transistor having a control terminal, a first terminal coupled to the second terminal of the eighth transistor, and a second terminal coupled to the reference terminal, A tenth transistor having a control terminal connected to the first terminal of the ninth transistor, a first terminal connected to the second terminal of the seventh transistor, and a second terminal connected to the reference terminal, A first snubber circuit coupled to the control terminal of the seventh transistor, A second snubber circuit coupled to the control terminal of the tenth transistor, A circuit that includes this.

16. The ADC according to claim 14, wherein the output circuit is A fifth transistor having a first terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal coupled to the first bias voltage circuit, A sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the third output of the pre-driver circuit, A circuit that includes this.

17. The ADC according to claim 14, wherein the output circuit is A fifth transistor having a first terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the third output of the pre-driver circuit, A sixth transistor having a first terminal connected to the second terminal of the fifth transistor, a second terminal connected to the reference terminal, and a control terminal connected to the second bias voltage circuit, A circuit that includes this.

18. The ADC according to claim 14, wherein the output circuit is A fifth transistor having a first terminal, a second terminal coupled to the control terminal of the third transistor, and a control terminal coupled to the first bias voltage circuit, A sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the third output of the pre-driver circuit, A circuit that includes this.

19. The ADC according to claim 14, wherein the output circuit is A fifth transistor having a first terminal, a second terminal coupled to the control terminal of the fourth transistor, and a control terminal coupled to the third output of the pre-driver circuit, A sixth transistor having a first terminal connected to the second terminal of the fifth transistor, a second terminal connected to the reference terminal, and a control terminal connected to the second bias voltage circuit, A circuit that includes this.

20. ADC according to claim 14, A first snubber circuit coupled to the control terminal of the first transistor, A second snubber circuit coupled to the control terminal of the second transistor, A third snubber circuit coupled to the control terminal of the third transistor, A fourth snubber circuit coupled to the control terminal of the fourth transistor, A circuit that further includes the following.

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