Double-sided polishing of semiconductor wafers using dynamic control

Abstract

Disclosed is a polishing apparatus and method for double-sided polishing of semiconductor wafers, comprising a first platen, a second platen, a wafer carrier, and a controller. The controller is operable to perform operations including determining whether a batch of semiconductor wafers is loaded onto the wafer carrier for double-sided polishing and obtaining specifications for the batch of semiconductor wafers. The operations include determining the required adjustment amounts for one or more flatness control parameters and identifying or generating a recipe for performing double-sided polishing on the batch of semiconductor wafers based on the required adjustment amounts for one or more flatness control parameters. The operations may include storing statistical process control (SPC) feedback data in a database and performing one or more additional iterations of double-sided polishing on the batch of semiconductor wafers.

Description

Cross - reference to related applications

[0001] This application claims the priority of U.S. Patent Application No. 18 / 342,172, filed on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

[0002] This disclosure relates to the polishing of semiconductor wafers, and more particularly, to systems and methods for double - side polishing semiconductor wafers using dynamic control.

Background Art

[0003] Semiconductor wafers are generally used in the manufacture of integrated circuit (IC) chips on which circuits are printed. The circuits are first printed in a miniaturized form on the surface of the wafer. Thereafter, the wafer is diced into circuit chips. This mini - circuit requires that the front and back surfaces of the wafer be extremely flat and parallel to ensure that the circuits can be properly printed across the entire surface of the wafer. The flatness of the wafer surface on which the circuits are printed is extremely important to maintain a resolution of lines that can be as fine as 0.13 microns (5.1 microinches) or less. The need for a flat wafer surface, particularly the local flatness in individual regions on the surface, becomes more pronounced when stepper lithography processes such as electron beam lithography or photolithography processes (hereinafter, "lithography") are employed. To achieve this, grinding and polishing processes are commonly used to improve the flatness and parallelism of the front and back surfaces of the wafer after the wafer is cut from an ingot.

[0004] When polishing a wafer in preparation for printing a mini - circuit on the wafer by lithography, a particularly good finish is required. The wafer surface on which the mini - circuit is printed must be flat. Typically, when a new polishing pad is used for the wafer, the flatness of the surface of the wafer to be polished remains within the acceptable range, but as the polishing pad wears during the process of polishing many wafers, the flatness reaches an unacceptable level.

[0005] Conventional polishing machine configurations and operations can cause flatness parameters to become unacceptable. Polishing machines typically include a circular or annular polishing pad mounted on a turntable or platen to rotate around a vertical axis passing through the center of the pad. For greater polishing interaction between the polishing pad and the wafer surface, a polishing slurry typically containing chemical abrasives and polishing particles is applied to the pad. This type of polishing operation is commonly referred to as chemical mechanical polishing, or simply CMP.

[0006] During operation, the pad rotates, bringing the wafer into contact with the pad. As the pad wears down, for example after several hundred wafers, the pad is no longer flat and has worn annular bands that form depressions along the polishing surface of the pad, thus reducing the wafer's flatness parameter. Such pad wear affects the wafer's flatness and can cause "dishing" or "doming."

[0007] As shown in Figure 1, “doming” results in a wafer 50 having a roughly convex polished surface 52. The convex surface 52 can occur because the worn pad removes less material from the center of the wafer 50 surface than from the area closer to the wafer edge 54. This is because the removal rate of the worn pad is the opposite of wear. In other words, the less worn portion of the worn pad removes more material than the more worn portion of the worn pad. The portion of the pad corresponding to the worn annular band removes the minimum amount of material from the wafer 50. As a result, the polished surface 52 of the wafer is made to have a generally “domed” shape.

[0008] As shown in Figure 2, due to “dishing,” the wafer 60 has a roughly concave polished surface 62. One potential reason this occurs is that abrasive material (e.g., colloidal material from the slurry, debris from previously polished wafers, and debris from the retaining ring) is embedded in the polishing pad, increasing the removal rate of the worn area. The parts of the pad with more wear remove more material from the wafer during the polishing process than the parts of the pad with less wear. As a result, more material is removed from the center of the wafer 60 than from its edges 64, and consequently, the polished surface 62 of the wafer has a generally “dished” shape.

[0009] Furthermore, due to the non-uniform distribution of mechanical and / or chemical forces near the wafer edges, the thickness profile at the wafer periphery may be reduced, a phenomenon known as edge roll-off. Edge roll-off reduces the usable portion of the wafer available for device manufacturing. Edge roll-off is generally controlled by adjusting the amount and / or type of slurry applied to the pad.

[0010] When wafer flatness reaches an unacceptable level (e.g., excessive "doming" or "dishing"), worn polishing pads must be replaced with new ones, or pad dressing or conditioning operations must be performed to restore the pads to a usable state. These operations add considerable cost to the operation of the polishing machine due to the number of pads that need to be purchased, stored, and disposed of, as well as the significant downtime required to perform polishing pad replacement or pad dressing / conditioning.

[0011] Semiconductor wafers used in the manufacture of advanced semiconductor devices, such as 5-nanometer (nm) technology node or silicon-on-insulator (SOI) wafers, require excellent surface quality on both sides of the semiconductor wafer. Therefore, a double-sided polishing machine is used to achieve the required flatness and finish on both sides of the semiconductor wafer. A double-sided polishing machine includes first and second platens spaced apart from each other to form a gap. A wafer carrier is placed in the gap formed between the first and second platens. The first platen has a reaction plate, a polishing plate, and a bladder. The wafer placed on the wafer carrier is polished by the polishing plate while the polishing plate rotates at a constant rotational speed to obtain the desired surface flatness. The internal pressure in the bladder is adjusted to deflect the polishing plate relative to the wafer carrier in order to improve the flatness of the surface being polished.

[0012] Wafer flatness depends on many different conditions, including the quality of the wafer being accepted, the dynamics settings (e.g., the rotation speed of the upper platen, the rotation speed of the lower platen, the rotation speed of the wafer carrier, and / or the number of gears to drive the wafer carrier at the determined rotation speed), the aging of the polishing pads, the degradation of the polishing slurry, and the wear condition of the wafer carrier. In addition, temperature, platen deformation, platen shape, polishing endpoint, and polishing time also affect the wafer flatness quality in a double-sided polishing process.

[0013] During the double-sided polishing process, statistical process control (SPC) feedback data is generated regarding wafer flatness control parameters. This SPC feedback data is generated as a chart. The process support engineer reviews the SPC feedback data chart to determine whether all wafer flatness control parameters are within the specified range provided by the customer and / or specific application. If one or more flatness control parameters are determined to be outside the specified range, the process support engineer modifies the platen profile of the double-sided polishing process (e.g., applying different rotation speeds to the upper and / or lower platen, and / or applying different pressure values ​​to deflect the polishing plates of the upper and / or lower platen) and / or changes the step time. Because the platen profile and / or step time are updated based on the process support engineer's personal knowledge or experience, there can be significant variations in wafer flatness or other critical parameters between one process support engineer and another. Furthermore, double-sided polishing of semiconductor wafers currently in use can also increase manufacturing costs and / or manufacturing time.

[0014] Therefore, there is a need for a double-sided polishing method that addresses the aforementioned problems associated with known methods for polishing both sides of semiconductor wafers.

[0015] This background technology section is intended to introduce to the reader various aspects of technology that may be relevant to the various aspects of the disclosure described and / or claimed below. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of the disclosure. Therefore, it should be understood that these descriptions should be read in this context and not as an admission of prior art. [Overview of the project]

[0016] In one embodiment, a polishing apparatus for double-sided polishing a semiconductor wafer is disclosed. The polishing apparatus includes a first platen, a second platen, a wafer carrier disposed in a gap formed between the first and second platens, and a controller. The controller is configured to perform operations including determining whether a batch of semiconductor wafers is loaded onto the wafer carrier for double-sided polishing, and, in accordance with the determination that a batch of semiconductor wafers is loaded, obtaining specifications for the batch of semiconductor wafers. The operations include determining the required adjustments for one or more flatness control parameters based on the obtained specifications for the batch of semiconductor wafers, and identifying or generating a recipe for performing double-sided polishing on the batch of semiconductor wafers based on the required adjustments for one or more flatness control parameters. The operations include performing one or more additional iterations of double-sided polishing on the batch of semiconductor wafers, storing statistical process control (SPC) feedback data in a database, and performing double-sided polishing on the batch of semiconductor wafers according to the identified recipe.

[0017] In another embodiment, the control system is operably connected to a polishing apparatus for double-sided polishing of semiconductor wafers. The control system includes at least one memory configured to store instructions, and at least one processor configured to execute the stored instructions, which, when executed, causes the at least one processor to perform an operation including determining whether a batch of semiconductor wafers is loaded onto the wafer carrier of the polishing apparatus, and, in accordance with the determination that a batch of semiconductor wafers is loaded, obtaining specifications for the batch of semiconductor wafers. The operation includes determining the required adjustments for one or more flatness control parameters based on the obtained specifications for the batch of semiconductor wafers, and identifying or generating a recipe for performing double-sided polishing on the batch of semiconductor wafers based on the required adjustments for one or more flatness control parameters. The operation includes causing the polishing apparatus to perform double-sided polishing on the batch of semiconductor wafers using the recipe, receiving statistical process control (SPC) feedback data and storing it in a database, and performing one or more additional iterations of double-sided polishing on the batch of semiconductor wafers.

[0018] In yet another embodiment, the method includes determining whether a batch of semiconductor wafers is loaded onto a wafer carrier of a double-sided polishing apparatus, and obtaining specifications for the batch of semiconductor wafers in accordance with the determination that a batch of semiconductor wafers is loaded. The method includes determining the required adjustments for one or more flatness control parameters based on the specifications obtained for the batch of semiconductor wafers, and identifying a recipe for performing double-sided polishing on the batch of semiconductor wafers based on the required adjustments for one or more flatness control parameters, the recipe being identified based on analysis of historical statistical process control (SPC) feedback data. The method includes storing SPC feedback data corresponding to the performed iterations in a database when performing double-sided polishing iterations on the batch of semiconductor wafers according to the recipe. [Brief explanation of the drawing]

[0019] [Figure 1] It is a side view of a dome-shaped wafer. [Figure 2] It is a side view of a dish-shaped wafer. [Figure 3] It is an exploded view of a wafer double-sided polishing machine according to some embodiments. [Figure 4] It is an exemplary system block diagram for performing double-sided polishing of a semiconductor wafer using a dynamic control closed-loop mechanism according to some embodiments. [Figure 5] It is an exemplary flowchart of the operation of an algorithm for selecting a new recipe for performing double-sided polishing of a semiconductor wafer according to some embodiments. [Figure 6] It is an exemplary flowchart of operations for performing double-sided polishing of a semiconductor wafer using dynamic control according to some examples. [Figure 7] It is an exemplary block diagram of a distributed computing system including a double-sided polishing machine and a control system according to some embodiments. [[ID=2�]]

[0020] Like reference numerals in the various drawings indicate like elements.

Best Mode for Carrying Out the Invention

[0021] FIG. 3 is an exploded view of an exemplary double-sided polishing machine according to some embodiments. A schematic view of a part of the double-sided polishing machine 300 is shown in FIG. 3. The double-sided polishing machine 300 is used to polish the front and back of a semiconductor wafer W sliced from one or more single-crystalline silicon ingots. It is contemplated that other types of double-sided polishing machines can also be used. The double-sided polishing machine 300 includes a plurality of substantially annular wafer carriers 302 disposed between a substantially annular first platen 320a and a substantially annular second platen 320b.

[0022] Each wafer carrier 302 has at least one circular opening for receiving a wafer W to be polished. In FIG. 3, each wafer carrier 302 is shown as having three openings for receiving three wafers. However, the wafer carrier can have openings for receiving any number and / or any shape of wafers. The periphery of each wafer carrier 302 has a ring gear (not shown) that is engaged by the "sun" or inner gear and outer gear (not shown) of the double-sided polishing machine 300. The inner and outer gears are driven by a suitable drive mechanism to rotate the carrier at a selected speed.

[0023] The first platen 320a and the second platen 320b are rotated at a selected rotational speed by a suitable drive mechanism (not shown) as known in the art. In some embodiments, the double-sided polishing machine 300 includes a controller (such as the controller described later) that allows an operator to select a rotational speed of the first platen 320a that is different from the rotational speed of the second platen 320b. In some embodiments, the first platen 320a and the second platen 320b can rotate in the same direction or in opposite directions.

[0024] As shown in FIG. 3, the first platen 320a has a reaction plate 330a and a first polishing plate 350a. The first polishing plate 350a is mounted spaced apart from the bottom surface 332a of the reaction plate 330a. The second platen 320b has a second reaction plate 330b and a second polishing plate 350b. The second polishing plate 350b is mounted spaced apart from the surface 332b of the second reaction plate 330b.

[0025] The double-sided polishing machine 300 is shown here as an example only. However, according to this embodiment or other embodiments, any double-sided polishing machine, such as that described in U.S. Patent No. 9,180,569, may be used. The contents of U.S. Patent No. 9,180,569 are incorporated herein by reference in their entirety for all purposes.

[0026] The double-sided polishing machine 300 has a wafer carrier mounted between a first polishing plate of a first platen and a second polishing plate of a second platen. At least one wafer is placed in the wafer carrier. One side of the wafer faces the first polishing plate, and the other side of the wafer faces the second polishing plate.

[0027] During operation, the first platen is lowered toward the second platen, bringing the first polishing plate into contact with one side of the wafer and the second polishing plate into contact with the other side of the wafer. Polishing slurry is applied to at least one of the polishing plates. The wafer carrier, the first polishing plate, and the second polishing plate are rotated. The first platen is pressed down during polishing with a selected "pressure" such that the sides of the wafer are polished simultaneously by each polishing plate. The movement of the polishing plates toward the wafer polishes a portion of the wafer to form the polished surface.

[0028] During the polishing of a semiconductor wafer, the flatness of the surface to be polished is determined, for example, using a thickness endpoint detection unit (not shown in Figure 3) of a double-sided polishing machine 300. The thickness endpoint detection unit may be connected to a controller in a communicative or operational manner. The controller may be the controller of the double-sided polishing machine 300, or it may be a controller associated with a control system that operates / controls the double-sided polishing machine 300.

[0029] A thickness endpoint detection unit can continuously (or in real time) measure the thickness of a semiconductor wafer during double-sided polishing of the semiconductor wafer. As a non-limiting example, a thickness endpoint detection unit may include a non-contact wafer thickness gauge for measuring the thickness of the semiconductor wafer at multiple points on the surface of the semiconductor wafer. For example, a non-contact wafer thickness gauge may include a capacitance-based sensor, an ultrasonic sensor, a light amplification (laser) sensor using stimulated emission of radiation, or an X-ray sensor.

[0030] If it is determined that the surface flatness of a semiconductor wafer after performing double-sided polishing iterations does not meet the required specifications for the target wafer, a process support engineer can generate a new recipe using one or more ML algorithms. The new recipe can set one or more adjustable double-sided polishing parameters to different values ​​than those used in the iterations prior to the next double-sided polishing iteration. One or more adjustable double-sided polishing parameters may include, for example, upper platen profile control pressure, lower platen profile control pressure, upper and / or lower platen rotation speed, wafer carrier rotation speed, and / or step time related to roll-off control, to ensure that the semiconductor wafer has flatness that meets the specification requirements corresponding to, for example, thickness, flatness, doming, edge roll-off (ERO), as specified in the customer order.

[0031] Based on real-time measurements of the thickness at multiple points on a semiconductor wafer during double-sided polishing, the final thickness corresponding to various points on the surface of the semiconductor wafer (also referred to herein as target endpoints) can be predicted or estimated for the current recipe. If the predicted or estimated final thickness corresponding to the target endpoint is not within the required specifications, a warning or notification can be generated.

[0032] Warnings or notifications may include (or indicate) the thickness corresponding to the target endpoint measured over time, a predicted or estimated value of the thickness corresponding to the target endpoint, and whether the process support engineer wishes to interrupt the current iteration and / or generate and apply a new recipe for double-sided polishing of the semiconductor wafer, depending on the required specifications of the target wafer.

[0033] When it is determined that the predicted or estimated thickness corresponding to the target endpoint no longer meets the specification requirements, a new recipe can be automatically generated using one or more ML algorithms and applied to perform the next iteration of double-sided polishing of the semiconductor wafer. Notifications or alerts can be generated to inform process support engineers of the new recipe and the values ​​of the adjustable parameters within the new recipe.

[0034] Additionally or alternatively, once the iterations of double-sided polishing for a batch of semiconductor wafers are complete, a new recipe can be automatically generated using one or more ML algorithms and applied to perform the next iteration of double-sided polishing for the semiconductor wafers.

[0035] Figure 4 is an exemplary system block diagram 400 for performing double-sided polishing of semiconductor wafers using a dynamically controlled closed-loop mechanism, according to several embodiments. The various blocks shown in system block diagram 400 may be implemented as separate modules, libraries, and / or executable processes. Additionally or alternatively, one or more blocks may be combined into a single module, library, and / or executable process operating on a controller for a double-sided polishing machine, or on a controller for a control system that operates the double-sided polishing machine, as shown in Figure 7.

[0036] As shown in Figure 4, the kernel module 402 may be configured to select or determine a recipe from the recipe database 404 to perform double-sided polishing of semiconductor wafers as a batch run, which is shown as 406 in Figure 4. During the batch run 406, one or more semiconductor wafers (also referred to herein as a batch of semiconductor wafers) can be processed simultaneously for double-sided polishing using the double-sided polishing machine 300.

[0037] Initially, or while performing the first iteration of double-sided polishing on a batch of semiconductor wafers, a recipe can be selected based on information corresponding to the batch of semiconductor wafers. As a non-limiting example, the information corresponding to a batch of semiconductor wafers may include wafer identification information (ID), the lot number of the batch of semiconductor wafers loaded into the double-sided polishing machine 300, and / or details about the customer (or customer order). The information corresponding to the batch of semiconductor wafers and / or details about the customer (or customer order) can be received (or obtained) from the Manufacturing Execution System (MES) 408.

[0038] The MES408 may include a database for storing information corresponding to a batch of semiconductor wafers and / or details about the customer (or customer order). Thus, the MES408 provides identification information for each semiconductor wafer loaded into the double-sided polishing machine 300, and details about the customer on which the double-sided polishing is being performed. Using wafer IDs such as those provided by the MES408, the kernel 402 can receive additional details about the semiconductor wafer specifications, such as the resistivity of the batch of semiconductor wafers, from the Engineering Data Center (EDC) database 410.

[0039] Based on details from the customer (or customer order), the desired target specifications for a batch of semiconductor wafers, such as the thickness and / or flatness of the semiconductor wafers, can be obtained from the MES408. The kernel 402 can then determine or select a recipe that sets specific values ​​for each of the dynamic setting parameters (e.g., profile pressure values ​​for the upper and / or lower platen, and / or gears), the step time for edge roll-off control, etc. The selected recipe may then be sent or communicated to the recipe uploader 412.

[0040] Next, the recipe uploader 412 can transmit or communicate the received recipe for loading to the double-sided polishing machine 300. While the double-sided polishing machine 300 performs double-sided polishing of a batch of semiconductor wafers according to the received recipe, the wafer control setting module 414 can provide (or control) values ​​for wafer flatness parameters such as edge roll-off, dishing, and / or doming. The values ​​for the wafer flatness parameters can be provided according to the epitaxy (EPI) process being performed on the double-sided polished semiconductor wafers. As a non-limiting example, the values ​​for the wafer flatness parameters may or may not differ from the target specifications of the batch of semiconductor wafers.

[0041] Since double-sided polishing of a batch of semiconductor wafers is performed in one or more iterations, in some embodiments, the wafer control setting module 414 can provide different ranges of wafer flatness parameter values ​​for each iteration to gradually achieve the target specifications. Corresponding to the wafer flatness parameter for each iteration, the double-sided polishing (DSP) parameter setting module 416 can apply or adjust the correspondingly adjustable DSP parameters. The DSP parameter setting module 416 can specify the step time (minutes / second) for edge roll-off control, one or more inline thickness sensor endpoints where thickness is measured during double-sided polishing, one or more target endpoints on the surface of the semiconductor wafer being polished, upper platen profile control pressure and / or lower platen profile control pressure, upper platen rotation speed, lower platen rotation speed, wafer carrier rotation speed, the number of inner and / or outer gears controlling the wafer carrier rotation speed, and so on.

[0042] For example, the upper platen profile control pressure may be between 3 and 50 bar, and the lower platen profile control pressure may be between 0.5 and 1.05 bar. Similarly, the step time may be selected between 0 and 30 minutes, and the target endpoint thickness may be between 770 and 778 micrometers during each iteration of the batch run. The DSP parameters and / or values ​​specified for the DSP parameters described herein are examples only.

[0043] During batch run 406, the thickness corresponding to the target endpoint can be measured continuously (or in real time). Therefore, the measurement data corresponding to the thickness at the target endpoint corresponds to statistical process control (SPC) feedback data. The SPC feedback data can be sent to database 418 for storage. The SPC feedback data may be associated with a batch run number (or batch run ID) and then stored in database 418. In some embodiments, as a non-limiting example, the SPC feedback data may also be sent to MES 408. MES 408 may associate the SPC feedback data with the customer, the semiconductor wafer lot, and the batch run number (or batch run ID).

[0044] As a non-limiting example, SPC feedback data can be used to train one or more ML algorithms to predict wafer thickness and / or flatness values ​​based on current thickness and / or flatness measurements, specific wafer control settings, and / or DSP parameter settings. The one or more ML algorithms may be supervised and / or unsupervised ML algorithms. The SPC feedback data may be divided into two segments. SPC feedback data in one segment may be used to train an ML algorithm, while the other segment may be used to validate a trained ML algorithm before it is deployed to production.

[0045] SPC feedback data may include DSP parameter settings applied during each iteration of a batch run, thickness and / or flatness measurements at the start of the iteration, and specific wafer control settings corresponding to the target wafer specifications at the end of the iteration. Therefore, one or more ML algorithms trained using SPC feedback data can recommend a recipe to apply in the next iteration of the batch run. One or more ML algorithms, such as those described herein, are assumed to be part of kernel 402. However, one or more ML algorithms may be separate from kernel 402.

[0046] Next, kernel module 402 can determine the DSP parameter settings to be applied during the next iteration of the batch run, based on the recipe proposed by one or more ML algorithms. System block diagram 400 illustrates a closed-loop control system for double-sided polishing of semiconductor wafers, while Figure 5 illustrates an exemplary flowchart of double-sided polishing of semiconductor wafers for the closed-loop control system described using Figure 4.

[0047] Figure 5 is an illustrative flowchart of a method for double-sided polishing semiconductor wafers, particularly a method for selecting a recipe based on which double-sided polishing parameters to adjust during a particular iteration of double-sided polishing. The method is performed by kernel 402 (or one or more ML algorithms) and can select a recipe based on the current thickness and / or flatness measurements of a batch of semiconductor wafers, as well as a set of adjustable DSP parameters to adjust during the iteration.

[0048] As shown in flowchart 500, at 502, kernel 402 can periodically check the status of a new batch of semiconductor wafers loaded into the double-sided polishing machine 300. Kernel 402 can use a timer, and when the timer expires, kernel 402 can query MES 408 to obtain information corresponding to the customer (or customer order) and / or wafer ID. Once it is determined that a new batch of semiconductor wafers is waiting to undergo double-sided polishing and / or has been loaded into the double-sided polishing machine 300, kernel can also obtain data corresponding to the specifications of the semiconductor wafer batch from the EDC database 410.

[0049] The specifications for a batch of semiconductor wafers may include the initial flatness, thickness, and / or resistivity of each semiconductor wafer in the batch, based on each wafer ID. Furthermore, kernel 402 may also obtain target specifications corresponding to the desired thickness and / or flatness of the batch of semiconductor wafers based on customer (or customer order) information. As a non-limiting example, customer (or customer order) information may also include one or more wafer flatness control parameters. Thus, a recipe corresponding to the current and target specifications of the batch of semiconductor wafers can be selected from recipe database 404, and one or more wafer flatness control parameters in this recipe are adjusted to produce wafers having the flatness and thickness specified in the customer order information and / or customer order information.

[0050] As described above, the recipe database 404 stores the recipes selected during previously executed batch runs, along with the specifications of the semiconductor wafer at the start and / or end of each double-sided polishing iteration, as well as the DSP parameters applied during each double-sided polishing iteration and their respective values. Thus, based on predictions from one or more ML algorithms, the kernel 402 can identify a specific recipe for loading and executing double-sided polishing of a batch of semiconductor wafers.

[0051] If at least one iteration of double-sided polishing has previously been performed on a batch of semiconductor wafers, upon timer expiration, kernel 402 can check whether new SPC feedback data is available in database 418 based on the batch run number (or batch run ID). Then, kernel 402 can further adjust one or more wafer flatness control parameters by selecting a recipe from recipe database 404 that corresponds to the current specifications of the batch of semiconductor wafers at the end of the last iteration of double-sided polishing, and the target specifications of the batch of semiconductor wafers.

[0052] In 504, a decision is made as to whether the new SPC feedback data is within the flatness control parameters specified in the customer order. If it is determined that the new SPC feedback data is within the limits of the flatness control parameters specified in the customer order, the next iteration of the selected recipe can be performed, as shown as 520 in Figure 5, and the new SPC feedback data generated at the end of the iteration can be stored in the database 418, and the operations described above can be repeated by referring to 502.

[0053] In 504, if it is determined that the new SPC feedback data is not within the limits of the flatness control parameters specified in the customer order or the target range of the expected flatness control parameters, in 506, a decision or calculation is made regarding the amount of further adjustment required for one or more flatness control parameters. The one or more flatness control parameters considered for adjustment include doming, dishing, and / or edge roll-off. Based on the calculated further adjustment of one or more flatness control parameters, one or more ML algorithms may predict or recommend a new recipe containing a different set of values ​​for one or more flatness control parameters. In some embodiments, a new recipe containing a different set of values ​​for one or more flatness control parameters may be a recipe selected from the recipe database 404 if one exists in the recipe database 404. Otherwise, a new recipe may be created and added to the recipe database 404.

[0054] In 508, a decision is made as to whether endpoint control and / or step time control are available for adjustment. One or more adjustable DSP parameters may have minimum and maximum values ​​for effective flatness control. In one example, if it is determined that doming exceeds the maximum allowable value, the thickness corresponding to the endpoint can be reduced to achieve the desired flatness. However, the thickness may be reduced so that it remains within the range of the minimum and maximum allowable values ​​for the thickness.

[0055] During the double-sided polishing of a batch of semiconductor wafers, different pressure values ​​for the upper and / or lower platen profiles, rotational speeds for the upper and / or lower platens, and / or slurry settings can be applied during different polishing step times. As a non-limiting example, polishing step times may include L1 (ramp-up), L2 (warm-up), L3 (stock removal), L4 (edge ​​roll-off control), L5 (semi-final slurry control), etc. Polishing step times may be measured in minutes or seconds, for example, from 0 to 30 minutes.

[0056] Therefore, if further thickness adjustments and / or step times for further adjustments are available, the next iteration of the selected recipe can be performed, as shown as 520 in Figure 5. The next iteration of the selected recipe may be performed based on the new endpoint thickness and / or polishing step time determined in 510 for the calculated adjustments of doming and / or edge roll-off, as determined in 506. The new endpoint thickness and / or polishing step time may be as recommended by one or more ML algorithms, as described herein. At the end of the iteration, new SPC feedback data can be generated and stored in the database 518, and the operations described above can be repeated by referring to 502.

[0057] If further thickness adjustment is not possible and / or step time for further adjustment is unavailable, in 512 a decision is made as to whether the upper platen profile and / or lower platen profile are available to modify the flatness and / or doming of a batch of semiconductor wafers by applying different pressure values ​​to the semiconductor wafer. If the pads of the upper platen and / or lower platen are not worn, different upper platen profiles and / or lower platen profiles with different pressure values ​​can be applied, as shown as 514 in Figure 5, and the next iteration of the selected recipe can be performed, as shown as 520 in Figure 5. At the end of the iteration, new SPC feedback data can be generated and stored in the database 418, and the operations described above can be repeated with reference to 502. The pressure values ​​of the upper platen profile and / or lower platen profile may be as recommended by one or more ML algorithms, as described herein.

[0058] If the pads of the upper platen and / or lower platen are worn, and / or the flatness of the semiconductor wafers in a batch of semiconductor wafers is significantly outside the range that can be corrected, in 516, it may be determined whether to change the rotational speed values ​​of the upper platen and / or lower platen, and / or the number of inner gears and / or outer gears corresponding to the rotational speed of the wafer carrier. If it is determined that different rotational speed values ​​of the upper platen and / or lower platen, and / or different numbers of inner gears and / or outer gears for changing the rotational speed of the wafer carrier are available to change the wafer thickness and / or doming, the next iteration of the selected recipe can be performed according to the rotational speed values ​​and / or the number of inner gears and / or outer gears as suggested in the recipe selected from the recipe database 404, as shown as 520 in Figure 5. At the end of the iteration, new SPC feedback data can be generated and stored in the database 418, and the operation described above can be repeated by referring to 502. The rotational speeds of the upper and / or lower platen, the rotational speed of the wafer carrier, and / or the number of inner and / or outer gears may be as recommended by one or more ML algorithms.

[0059] However, if it is determined that different rotational speed values ​​for the upper and / or lower platen, different rotational speed values ​​for the wafer carrier, and / or different numbers of inner and / or outer gears are not effective in changing the wafer thickness and / or doming, a warning or notification may be generated. The warning or notification may indicate, for the intervention of a process support engineer, the current flatness control measurement, batch run number, lot number of the semiconductor wafer batch, customer and / or customer order details, and / or DSP parameters of the last batch run, etc.

[0060] To perform different iterations corresponding to a batch of semiconductor wafers, the same or different recipes can be selected from the recipe database 404. Furthermore, as described herein, the respective values ​​of each tunable DSP parameter in the recipe and / or set of tunable DSP parameters may be recommended by one or more ML algorithms.

[0061] Figure 6 is an exemplary flowchart 600 of performing operations for double-sided polishing of semiconductor wafers using dynamic control, in several examples. As shown in flowchart 600, at 602, a decision is made regarding whether a batch of semiconductor wafers is loaded into the wafer carrier of the double-sided polishing machine. This decision may be made in response to the receipt of a new order for double-sided polishing, and / or in response to a new batch of semiconductor wafers placed in the opening of the wafer carrier of the double-sided polishing machine, for example, using a robot that operates in response to a received new order. In some examples, sensors such as laser sensors and photoelectric sensors can be used to detect the presence of semiconductor wafers.

[0062] In 604, when a new batch of semiconductor wafers is loaded onto a wafer carrier, the specifications of the batch of semiconductor wafers loaded into the double-sided polisher can be obtained, as illustrated herein with reference to Figure 4. As described herein, the specifications of the batch of semiconductor wafers loaded into the double-sided polisher can be obtained using customer order details and / or wafer lot IDs. The specifications may include the current / initial flatness, thickness, and / or size of the semiconductor wafers. The specifications may also include details of the semiconductor wafer material composition and / or resistivity. Thus, the obtained specifications may include the acceptance specifications or current specifications of the batch of semiconductor wafers. The specifications may also include target specifications that describe the desired thickness and / or flatness according to customer orders, specific applications, etc.

[0063] In 606, based on the specifications of the semiconductor wafer batch obtained in 604, the adjustment amount of the loaded semiconductor wafer batch can be determined. The required adjustment amount can be determined to produce wafers according to the thickness and / or flatness specified by the customer in the customer order. Based on the required adjustment amount, in 608, a recipe for performing double-sided polishing of the loaded semiconductor wafer batch can be identified or generated. In some examples, the recipes described herein may include details such as the rotation speed of the upper platen, the rotation speed of the lower platen, the pressure value applied to the upper platen to deflect the upper platen, the rotation speed of the wafer carrier, the number of inner and / or outer gears corresponding to the rotation speed of the wafer carrier, and / or step times for various stages of the double-sided polishing process. The recipe may also include the amount and / or type of slurry used during double-sided polishing to control edge roll-off.

[0064] The recipe is appropriately selected from recipes stored in the database, and each recipe stored in the database can also identify the initial specifications of the semiconductor wafer before the recipe is applied to perform the double-sided polishing process, and the specifications of the semiconductor wafer at the end of the double-sided polishing process by the applied recipe. Thus, the recipe has the initial specifications or specifications of the semiconductor wafer prior to the recipe that match the acceptance specifications or current specifications of the batch of semiconductor wafers loaded into the double-sided polishing machine, and / or the specifications of the semiconductor wafer at the end of the double-sided polishing process that match the target specifications obtained in 604. In some examples, the recipe can be combined with another recipe that can also be applied to perform the double-sided polishing process to produce a semiconductor wafer with final specifications as the target specifications obtained in 604.

[0065] If no recipe exists in the database that matches the acceptance specifications and / or target specifications of a batch of semiconductor wafers loaded into a double-sided polishing machine, a new recipe can be generated using one or more ML algorithms trained with historical SPC feedback data, as described herein. Using the trained ML algorithms, the new recipe can specify, based on which parameter values ​​to change / adjust, the pressure and / or rotational speed of the upper platen and / or lower platen, the rotational speed of the wafer carrier, the number of inner and / or outer gears corresponding to the wafer carrier rotational speed, the type and / or amount of slurry, the step times corresponding to various stages of the double-sided polishing process, and so on.

[0066] In 610, after the recipe is uploaded to the double-sided polishing machine and the double-sided polishing process is performed, SPC feedback data is collected and stored in a database. As described herein, the SPC feedback data may be used to generate or identify another recipe for double-sided polishing of semiconductor wafers.

[0067] Figure 7 is an exemplary block diagram of a distributed computing system 700, which includes a double-sided polishing machine 702 and a double-sided polishing machine control system (or control system) 704. In some examples, the system 700 is used to perform double-sided polishing of semiconductor wafers using the double-sided polishing machine 702 and to control the double-sided polishing machine 702 using the control system 704. The control system 704 is a real-time data analysis and classification computer system configured to measure the thickness and / or flatness of the semiconductor wafer, select a recipe to achieve a desired target specification of the semiconductor wafer, and control the double-sided polishing machine, as described herein. In some examples, the control system 704 may implement one or more modules or blocks as described herein with reference to Figure 4.

[0068] The double-sided polishing machine 702 may include a controller 708 (also referred to herein as a double-sided polishing (DSP) controller 708), a memory 710, an assembly 712 for performing double-sided polishing of semiconductor wafers, one or more sensors 714, a communication interface 716, and / or an input / output device 718, etc. The control system 704 may include a controller 720, a memory 722, one or more sensors 724, a communication interface 726, and / or an input / output device 728, etc.

[0069] The DSP controller 708 can execute instructions stored in memory 710. The DSP controller 708 may include one or more processing units such as a central processing unit, a microprocessor, a microcontroller, a field-programmable gate array (FPGA), and / or an application-specific integrated circuit (ASIC). The controller 720 can execute instructions stored in memory 722. The controller 720 may include one or more processing units such as a central processing unit, a microprocessor, a microcontroller, a field-programmable gate array (FPGA), and / or an application-specific integrated circuit (ASIC).

[0070] Memory 710 and / or memory 722 may be random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), hard disk, solid state drive, flash drive, etc. One or more sensors 714 and / or 724 may include capacitance-based sensors, ultrasonic sensors, stimulated emission (laser) sensors, X-rays, etc., for measuring the thickness and / or flatness of the semiconductor wafer. As described herein, one or more sensors 714 and / or 724 may be included in measuring devices such as non-contact wafer thickness gauges for measuring the thickness of the semiconductor wafer at multiple points on the surface of the semiconductor wafer.

[0071] Communication interfaces 716 and 726 provide data communication and exchange between the double-sided polishing machine 702 and the control system 704. Communication interfaces 716 and 726 may include, for example, a local area network (LAN) or wide area network (WAN) interface, a dial-in connection, a cable modem, an internet connection, wireless, and a dedicated high-speed integrated digital network (ISDN) line.

[0072] Input / output devices 718 and / or 728 may include one or more displays for outputting information to the user and a keyboard, mouse, touchpad screen, etc., for receiving user input.

[0073] In some examples, system 700 may also include a measuring device 706 configured to generate a profile of its wafer corresponding to its thickness and / or flatness. More specifically, the measuring device 706 measures the thickness and / or flatness of the wafer using, for example, an optical wafer thickness gauge. The measuring device 706 can communicate with the control system 704 via a variety of wired or wireless interfaces, including but not limited to networks such as a local area network (LAN) or wide area network (WAN), dial-in connection, cable modem, internet connection, wireless, and dedicated high-speed integrated digital communication network (ISDN) line. The measuring device 706 performs the measurement corresponding to the thickness and / or flatness of the wafer and reports the measurement data to the control system 704.

[0074] The described embodiments improve methods for double-sided polishing of semiconductor wafers. For example, double-sided polishing parameters are adjusted based on one or more ML algorithms trained using historical SPC feedback data collected during previously performed batch runs. Thus, previous negative consequences associated with performing double-sided polishing depending on the personal knowledge or experience of the process support engineer are reduced or eliminated.

[0075] When introducing elements of the present invention or its embodiments, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more elements. The terms “comprising,” “including,” and “having” are intended to mean comprehensive and that additional elements other than those listed may exist. The use of terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” “down,” “up,” etc.) is for explanatory convenience and does not require a specific orientation of the items described.

[0076] Since various modifications can be made to the above configuration and method without departing from the scope of the present invention, all matters included in the above description and shown in the accompanying drawings are intended to be interpreted as illustrative rather than restrictive.

Claims

1. A polishing apparatus for polishing both sides of a semiconductor wafer, The first platen, The second platen, A wafer carrier disposed in the gap formed between the first platen and the second platen, It is a controller, Determining whether the batch of semiconductor wafers is loaded onto the wafer carrier for double-sided polishing, In accordance with the determination that the batch of semiconductor wafers has been loaded, the specifications of the batch of semiconductor wafers are obtained, Based on the acquired specifications for the batch of semiconductor wafers, the adjustment amount required for one or more flatness control parameters is determined. Identifying or generating a recipe for performing the double-sided polishing on the batch of semiconductor wafers based on the adjustment amount required for one or more flatness control parameters, When performing the double-sided polishing on the batch of semiconductor wafers according to the identified recipe, statistical process control (SPC) feedback data is stored in a database in order to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers. A polishing apparatus for double-sided polishing a semiconductor wafer, including a controller configured to perform operations including the following.

2. The polishing apparatus according to claim 1, wherein obtaining the specifications of the batch of semiconductor wafers includes obtaining at least one of the acceptance specifications of the batch of semiconductor wafers, the current specifications of the batch of semiconductor wafers, or the target specifications of the batch of semiconductor wafers.

3. The polishing apparatus according to claim 1, wherein the one or more flatness control parameters include at least one of edge roll-off or doming.

4. Identifying or generating the aforementioned recipe is Based on the acquired specifications for the batch of semiconductor wafers, identify a set of double-sided polishing parameters for adjustment and the respective values ​​of each parameter in the set of double-sided polishing parameters for performing the double-sided polishing iteration on the batch of semiconductor wafers, Based on an identified set of double-sided polishing parameters for adjustment and the respective values ​​of each parameter in the set of double-sided polishing parameters, the values ​​of each of the one or more flatness control parameters are predicted. Based on the prediction of the respective values ​​of each of the one or more flatness control parameters, identify or generate the identified set of double-sided polishing parameters for adjustment and the recipe corresponding to the respective values ​​of each parameter. The polishing apparatus according to claim 1, including the following:

5. The polishing apparatus according to claim 4, wherein identifying or generating the recipe further comprises determining whether the set of double-sided polishing parameters for adjustment and the respective values ​​of each parameter in the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of semiconductor wafers.

6. The polishing apparatus according to claim 4, wherein the set of double-sided polishing parameters for adjustment includes at least one of thickness or step time.

7. The polishing apparatus according to claim 4, wherein the set of double-sided polishing parameters for adjustment includes at least one of an upper platen profile or a lower platen profile.

8. The polishing apparatus according to claim 4, wherein the set of double-sided polishing parameters for adjustment includes at least one of the rotational speed of the upper platen, the rotational speed of the lower platen, the number of inner pin gears, or the number of outer pin gears.

9. The polishing apparatus according to claim 4, wherein predicting the respective values ​​of each of the one or more flatness control parameters includes making predictions using one or more algorithms configured to predict the respective values ​​of each of the one or more flatness control parameters based on historical SPC feedback data.

10. The polishing apparatus according to claim 1, wherein the SPC feedback data includes the acceptance specification of the batch of semiconductor wafers, the current specification of the batch of semiconductor wafers, or the target specification of the batch of semiconductor wafers, a batch run number, customer information, customer order information, or the batch ID of the semiconductor wafers.

11. A control system operably connected to a polishing apparatus for polishing both sides of a semiconductor wafer, At least one memory configured to execute stored instructions, At least one processor configured to execute the stored instructions, wherein when an instruction is executed, the at least one processor, Determining whether the batch of semiconductor wafers is loaded onto the wafer carrier of the polishing apparatus, In accordance with the determination that the batch of semiconductor wafers has been loaded, the specifications of the batch of semiconductor wafers are obtained, Based on the acquired specifications for the batch of semiconductor wafers, the adjustment amount required for one or more flatness control parameters is determined. Identifying or generating a recipe for performing the double-sided polishing on the batch of semiconductor wafers based on the adjustment amount required for one or more of the flatness control parameters, The polishing apparatus is made to perform double-sided polishing on the batch of semiconductor wafers using the recipe, In order to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers, statistical process control (SPC) feedback data is received and stored in a database. A control system including a processor that performs the following actions.

12. The control system according to claim 11, wherein obtaining the specifications of the batch of semiconductor wafers includes obtaining at least one of the acceptance specifications of the batch of semiconductor wafers, the current specifications of the batch of semiconductor wafers, or the target specifications of the batch of semiconductor wafers.

13. The control system according to claim 11, wherein the one or more flatness control parameters include at least one of edge roll-off or doming.

14. Identifying or generating the aforementioned recipe is Based on the acquired specifications for the batch of semiconductor wafers, identify a set of double-sided polishing parameters for adjustment and the respective values ​​of each parameter in the set of double-sided polishing parameters for performing the double-sided polishing iteration on the batch of semiconductor wafers, Based on an identified set of double-sided polishing parameters for adjustment and the respective values ​​of each of the one or more flatness control parameters in the set of double-sided polishing parameters, Based on the prediction of the respective values ​​of each of the one or more flatness control parameters, identify or generate the identified set of double-sided polishing parameters for adjustment and the recipe corresponding to the respective values ​​of each parameter. The control system according to claim 11, including the following:

15. The control system according to claim 14, wherein identifying or generating the recipe further includes determining whether the set of double-sided polishing parameters for adjustment and the respective values ​​of each parameter in the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of semiconductor wafers.

16. The control system according to claim 14, wherein the set of double-sided polishing parameters for adjustment includes at least one of thickness, step time, upper platen profile, lower platen profile, upper platen rotation speed, lower platen rotation speed, number of inner pin gears, or number of outer pin gears.

17. The control system according to claim 14, wherein predicting the respective values ​​of each of the one or more flatness control parameters includes making predictions using one or more algorithms configured to predict the respective values ​​of each of the one or more flatness control parameters based on historical SPC feedback data.

18. The control system according to claim 17, wherein the one or more algorithms are machine learning algorithms trained using the historical SPC feedback data.

19. The control system according to claim 11, wherein the SPC feedback data includes the acceptance specification of the batch of semiconductor wafers, the current specification of the batch of semiconductor wafers, or the target specification of the batch of semiconductor wafers, a batch run number, customer information, customer order information, or the batch ID of the semiconductor wafers.

20. It is a method, To determine whether a batch of semiconductor wafers is loaded onto the wafer carrier of a double-sided polishing machine, In accordance with the determination of whether the batch of semiconductor wafers has been loaded, the specifications of the batch of semiconductor wafers are obtained, Based on the acquired specifications for the batch of semiconductor wafers, the adjustment amount required for one or more flatness control parameters is determined. Identifying a recipe for performing double-sided polishing on the batch of semiconductor wafers based on the adjustment amount required for one or more flatness control parameters, wherein the recipe is identified based on analysis of historical statistical process control (SPC) feedback data. A method comprising storing SPC feedback data corresponding to the performed iterations in a database when performing the double-sided polishing iterations on the batch of semiconductor wafers according to the recipe described above.

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