Interface preparation for erosion and corrosion-resistant coatings for semiconductor components

Abstract

An exemplary processing method may include providing a component for semiconductor processing to a processing area in a processing chamber. The method may include providing one or more interface deposition precursors to the processing area. The method may include depositing a layer of interface material on the component for semiconductor processing within the processing area. The method may include providing one or more coating deposition precursors to the processing area. The method may include depositing a layer of coating material on the component for semiconductor processing within the processing area.

Description

[Technical Field]

[0001]

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 343,351, filed on 28 June 2023, entitled "INTERFACE TUNING FOR EROSION AND CORROSION RESISTANT COATINGS FOR SEMICONDUCTOR COMPONENTS," which is incorporated herein by reference in its entirety.

[0002]

[0002] This technology relates to a coating process and semiconductor chamber components. In particular, this technology relates to improved components and component materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by a process that generates intricately patterned material layers on the surface of a substrate. To generate patterned material on a substrate, a controlled method for forming and removing exposed material is required. The deposition and removal process may include, for example, generating a remote or local plasma within a processing area of ​​a semiconductor processing chamber between a showerhead or gas distributor and a substrate support. Multiple components of the semiconductor processing chamber may be exposed to plasma species during processing. Repeated exposure of components to corrosive species can lead to degradation of the components and contamination of the substrate being processed. Therefore, a top coating may be provided to protect the underlying components from corrosion and / or erosion. However, differences between the top coating material and the underlying component material can degrade the performance of the top coating.

[0004]

[0004] Therefore, there is a need for improved systems and system components that can be used in the manufacture of high-quality devices and structures. This technology addresses these and other needs. [Overview of the project]

[0005]

[0005] An exemplary processing method may include providing a component for semiconductor processing to a processing area of ​​a processing chamber. The method may include providing one or more interface deposition precursors to the processing area. The method may include depositing a layer of interface material on the component for semiconductor processing in the processing area. The layer of interface material may be an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-and-oxygen-containing material, a metal-and-fluorine-containing material, a metal-and-nitrogen-containing material, a metal-oxygen-and-nitrogen-containing material, or a metal-oxygen-fluorine-and-nitrogen-containing material. The method may include providing one or more coating deposition precursors to the processing area. The method may include depositing a layer of coating material on the component for semiconductor processing in the processing area.

[0006]

[0006] In some embodiments, the component for semiconductor processing may include a metal-containing material or a metallic-containing material. The component for semiconductor processing may include a ceramic-containing material. The ceramic-containing material may include one or more metals and one or more of oxygen, fluorine, and nitrogen. The ceramic-containing material may include aluminum oxide (Al2O3), aluminum oxyfluoride (AlO2O3), and x F y ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x Fy ) Titanium oxide (TiO2), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4), or silicon oxynitride (SiO x N y ), or may contain them. The layer of the interface material can be characterized by a coefficient of thermal expansion (CTE) that is higher than that of the parts for semiconductor processing and lower than that of the layer of the coating material. The metal-containing precursor can include aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium. One or more coating deposition precursors include a fluorine-containing precursor. The fluorine-containing precursor can be hydrogen fluoride (HF), ammonium fluoride (NH4F), ammonium bifluoride ([NH4]F·HF), HF-pyridine complex, nitrogen trifluoride (NF3), hexafluoroisopropanol (HFIP), tetrafluoropropanol (TFP), hexafluoroacetylacetonate (HHFAC), titanium tetrafluoride (TiF4), tantalum pentafluoride (TaF5), or tungsten hexafluoride (WF6), or a fluorine-containing plasma, or may contain them. The layer of the coating material is aluminum fluoride (AlF3), aluminum oxyfluoride (AlO x F y ), calcium fluoride (CaF2), calcium oxyfluoride (CaO x F y ), magnesium fluoride (MgF2), yttrium fluoride (YF3), yttrium oxyfluoride (YO x F y ), zirconium fluoride (ZrF4), zirconium oxyfluoride (ZrO x F y ), scandium fluoride (ScF3), or scandium oxyfluoride (ScO x F y), or a combination thereof, or may include these. One or more coating deposition precursors may further include oxygen-containing precursors. The oxygen-containing precursors may be or may include water vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, alcohol-based compounds, or alcohol-based plasmas. One or more coating deposition precursors may further include nitrogen-containing precursors. The method may include generating plasma emissions of one or more coating deposition precursors. The temperature in the processing area may be maintained at about 2000°C or less. Components for semiconductor processing may be or may include lids, nozzles, faceplates, gas distribution plates, heaters, screws, substrate supports, support platens, liners, edge rings, process kit rings, or lift pins.

[0007]

[0007] Some embodiments of the present technology may encompass a processing method. The method may include providing a component for semiconductor processing to a processing area in a processing chamber. The method may include depositing a layer of interface material on the component for semiconductor processing in the processing area. The layer of interface material may be an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-nitrogen-containing material, a material containing one or more metals and one or more of oxygen, fluorine, and nitrogen, or a combination thereof. The method may include depositing a layer of coating material on the layer of interface material in the processing area. Depositing the layer of coating material may include exposing the component for semiconductor processing to a first coating precursor, purging the processing area, and exposing the component for semiconductor processing to a second coating precursor. The layer of coating material may include the reaction product of the first coating precursor and the second coating precursor. The temperature inside the processing chamber can be maintained at approximately 400°C or higher.

[0008]

[0008] In some embodiments, components for semiconductor processing may be aluminum oxide (Al2O3), aluminum oxyfluoride (AlO x F y ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium oxide (TiO2), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4), or silicon oxynitride (SiO x N y ), or may include them. The layer of coating material may be a metal-fluorine-oxygen-containing material or may include them. The method may include generating a plasma emission of a first coating precursor, a second coating precursor, or both of them.

[0009]

[0009] Some embodiments of the present technology may include components for semiconductor processing. The components may include ceramic, metal, or non-metal components for semiconductor processing. The components may include a layer of interface material on the components for semiconductor processing. The layer of interface material may be an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-containing material, a metal-oxygen-nitrogen-containing material, a metal-oxygen-fluorine-nitrogen-containing material, a material including one or more metals and one or more of oxygen, fluorine, and nitrogen, or a combination thereof, or may include these. The components may include a layer of coating material on the layer of interface material.

[0010]

[0010] In some embodiments, components for semiconductor processing may be a lid, a nozzle, a faceplate, a gas distribution plate, a heater, a screw, a substrate support, a support platen, a liner, an edge ring, a process kit ring, or a lift pin, or may include them.

[0011]

[0011] Such a technique can provide more advantages than the prior art. For example, the method can provide a coated semiconductor processing component with improved compatibility with plasma processing applications. For example, the component can be chemically reduced to remove a passivation layer on the particles of the component. In this way, an interface layer can be formed on the component, and a layer of coating material can be coated on the interface layer, for example, by atomic layer deposition. The interface coating can adjust the coefficient of thermal expansion (CTE) between the component and the coating material, improve adhesion, act as a diffusion barrier, control nucleation, control or remove contamination, or control porosity. Therefore, the coated semiconductor processing component can exhibit improved thermal, mechanical, and / or chemical properties, including within a halogen plasma environment where semiconductor processing steps are performed. These embodiments and other embodiments are described in more detail below with their many advantages and features, along with the accompanying drawings.

[0012]

[0012] By referring to the following description and the drawings below, the nature and advantages of the technology of the present disclosure can be further understood.

Brief Description of the Drawings

[0013] [Figure 1]

[0013] A schematic diagram of an exemplary processing chamber according to some embodiments of the present technology is shown. [Figure 2]

[0014] An exemplary process in a deposition method according to some embodiments of the present technology is shown. [Figure 3]

[0015] A schematic diagram of a component during a process in a deposition method according to some embodiments of the present technology is shown. [Figure 4]

[0016] A schematic diagram of an exemplary processing chamber component formed by the method according to some embodiments of the present technology is shown.

Modes for Carrying Out the Invention

[0014]

[0017] Some of the drawings are included as schematics. Drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish similar components from each other. Where only a first reference numeral is used herein, its description may apply to any similar component having the same first reference numeral, regardless of the letters mentioned above.

[0016]

[0019] As part of semiconductor processing technology, deposition and removal processes may include, for example, generating a remote or local plasma within a processing area of ​​a semiconductor processing chamber between a showerhead or gas distributor and a substrate support. Multiple components of the semiconductor processing chamber may be or include metallic materials, metallic materials, and / or ceramic materials. To protect the metallic materials, metallic materials, and / or ceramic materials during the plasma-using process, a protective coating material may be provided for the underlying materials. The coating material may be a combination of materials such as oxides, nitrides, fluorides, metal oxides, metal nitrides, and / or metal fluorides, as well as mixed metallic materials. However, these coating materials have conventionally been formed directly on the components, which have sometimes been less effective or less effective than desired.

[0017]

[0020] Conventional techniques that form a coating material directly on the component to be protected have sometimes suffered from adhesion problems and differences in CTE (Critical Temperature Exposure) that can cause cracking and delamination of the coating material. This technique overcomes these limitations by forming an interface material on the component before forming the coating material. The interface material may have better adhesion to both the component and the coating material. Furthermore, the interface layer may have a CTE between the CTE of the component and the CTE of the coating material. This can mitigate the difference in CTE between the component and the coating material. In addition, the interface material can control diffusion, nucleation, contamination, and / or porosity. The interface material may be formed using specific elements to form stable phases such as spinel or garnet phases. This can enhance the effectiveness of the coating material. By depositing the coating material on the interface material, the lifespan and effectiveness of the coating can be improved. This makes it possible to prepare coated semiconductor processing components for applications such as plasma processing chamber components with thermal, mechanical, and chemical properties tuned for the conditions used in semiconductor processing. As a result, coated semiconductor processing components can be mounted in a semiconductor processing chamber exposed to a plasma process.

[0018]

[0021] After describing general aspects of chambers according to several embodiments of this technology in which plasma processing can be performed, specific methodologies and component configurations may be described. It should be understood that this technology is not intended to be limited to the specific films and processes described, as it can be used to improve several film formation processes and is applicable to various processing chambers and processes.

[0019]

[0022] Figure 1 shows a schematic diagram of an exemplary processing chamber 100 according to several embodiments of the present technology. The figure may show an overview of a system that incorporates one or more aspects of the present technology and / or can perform one or more steps according to multiple embodiments of the present technology. Further details of the chamber 100 or the method performed may be described further below. The chamber 100 may be used to form coated semiconductor processing components according to several embodiments of the present technology, but it should be understood that the method may be similarly performed in any chamber in which film formation may be performed. The processing chamber 100 may include a chamber body 102, a plasma system 104 inside the chamber body 102, a temperature control system 106, and a remote plasma system 108 coupled to the chamber body 102 and configured to provide plasma emissions to the processing area 120 of the chamber body 102.

[0020]

[0023] Components for semiconductor processing may be supplied to the processing area 120 through material feedthroughs such as ports or conduits that can be sealed for processing using slit valves, gate valves, or doors. As described below, precursors may be supplied to the chamber 100 through a gas supply system 110. Figure 1 shows a single inlet for the gas supply system 110, but the chamber 100 may include multiple gas inlets coupled to the chamber body 102 at one or more locations. For example, a plasma precursor may be introduced into the chamber body through a remote plasma system 108, while a second gas inlet may provide gases whose plasma dissociation could adversely affect the deposition process. The gases may be removed from the chamber body 102 by a gas removal system 112. The gas removal system 112 may include a vacuum system. This vacuum system is configured to facilitate the reduced-pressure process during the deposition process and to evacuate the chamber to remove process emissions and unreacted process gases. A measurement and control system may be coupled to the chamber to measure the operating pressure at one or more locations, such as the gas supply system 110, the gas removal system 112, or the processing area 120. In another embodiment, a temperature control system 106 may include a temperature sensor and a heating element configured to supply heat to or remove heat from the processing area 120. In this way, the chamber 100 can perform controlled deposition and removal processes, such as plasma etching and removal, and atomic layer deposition.

[0021]

[0024] As part of performing plasma processing of semiconductor components in chamber 100 according to the method described below, the plasma system 104 may be configured to form a plasma in a processing area 120. The plasma system 104 may be or include an indirect plasma system, such as an RF capacitively coupled plasma system, configured to form a plasma in the processing area 120 by generating a sufficiently strong electric field inside the chamber body 102. In some embodiments, the plasma system 104 may be or include a direct plasma system, thereby having one or more electrode surfaces positioned inside the chamber body. In this way, the processing area 120 may be defined between the active electrode of the plasma system 104 and a reference ground electrode. The plasma system 104 may also include control and power supply systems, such as impedance matching circuits and a 13.56 MHz RF power supply.

[0022]

[0025] Similarly, the remote plasma system 108 may be, or include, a direct plasma system or an indirect plasma system, such as an inductively coupled RF plasma system or a capacitively coupled RF plasma system. These may be configured to decompose a precursor into plasma emitters that can be provided to the processing area 120. For example, the gas supply system 110 may include a quartz inlet tube coupled to a feedthrough to the chamber body 102. In such a configuration, the remote plasma system 108 may be, or include, an ICP or CCP system located outside the quartz inlet tube and configured to form plasma within the quartz inlet tube. As further illustrated with reference to Figure 2, the precursor may include an inert carrier gas and a reaction precursor that may be, or include, a vapor or gas. In this way, the remote plasma system 108 may form an indirect plasma in the precursor and decompose it. The decomposed precursor may be, or include, plasma emitters. The plasma emitters may be, or include, a carrier gas, an unreacted precursor, and plasma-generating species. Plasma-generated species can, without limitation, act as reactants in chemical reaction-mediated deposition processes, including conformal deposition processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), and without limitation, direct line deposition processes such as physical vapor deposition (PVD), ion beam (IB) deposition, electron beam (EB) deposition, or electron beam-ion-assisted deposition (EB-IAD). Similar to plasma system 104, remote plasma system 108 may also include control systems and power supply systems, such as impedance matching circuits and a 13.56 MHz RF power supply.

[0023]

[0026] The temperature control system 106 may be configured to maintain the internal temperature within the processing area according to the processing method. For example, as part of atomic layer deposition, a deposition substrate, such as a component for semiconductor processing, may be heated to a reaction temperature in which specific reaction products are preferentially produced. In one exemplary embodiment, a surface reaction that forms a layer of material on the deposition substrate may be thermodynamically favorable at high temperatures. Therefore, the temperature control system 106 may provide heat to the processing area. In some embodiments, the temperature control system may be at least partially integrated into the plasma system 104. For example, the electrodes of the plasma system 104 may incorporate heating and / or cooling elements, allowing the plasma system to operate within an operating temperature range.

[0024]

[0027] In some embodiments, the chamber 100 may be configured to prepare coated semiconductor processing components. Multiple components are coated with one or more layers of material for semiconductor processing. As will be described below with reference to methods and systems, the chamber 100 may enable the preparation of improved coated semiconductor processing components. The improved coated components may be incorporated into a semiconductor processing system. Such components may exhibit improved thermal, mechanical, and / or chemical properties under processing conditions characteristic of plasma deposition and removal steps as part of semiconductor processing.

[0025]

[0028] Figure 2 shows exemplary steps in Method 200 according to several embodiments of the present technology. The method may be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps that may or may not be specifically associated with certain embodiments of the method according to the present technology. For example, many of the steps described are provided to offer a broader range of structure formation, but are not critically important to the technology or may be carried out by alternative methods that are easily understood.

[0026]

[0029] Method 200 describes the process schematically shown in Figure 3, but this description will be explained in conjunction with the process of Method 200. Figure 4 shows an exemplary semiconductor processing system incorporating materials produced according to several embodiments of Method 200. Figures 3 and 4 are schematic diagrams of only parts, and it should be understood that the processing system may include subsystems as shown, as well as alternative subsystems, and may be of any size or configuration from which multiple aspects of this technology can still be benefited.

[0027]

[0030] Figure 3 shows a schematic diagram of a semiconductor processing component 300 in the process of Method 200 according to several embodiments of the present technology. In some embodiments, Method 200 may include one or more steps preceding the steps shown in Figure 2. For example, one or more processes may be carried out to form the semiconductor processing component 300 from feedstock material. For example, the semiconductor processing component 300 may be formed by chemically converting an oxide to a nitride and may be cleaned by, for example, baking, etching, or degreasing. Several examples of nitride synthesis may, non-limitingly, include carbon thermal nitriding and / or direct nitriding. Furthermore, the semiconductor processing component 300 may be introduced into a processing chamber, such as a chamber 100 having a passivation layer 305. For example, the semiconductor processing component 300 may be or include aluminum nitride. Aluminum nitride may develop an oxide passivation layer through exposure to oxygen during cleaning or through exposure to air under ambient conditions.

[0028]

[0031] Method 200 may include further steps before commencing the enumerated steps. For example, as shown in Figure 3, Method 200 may include removing a passivation layer 305, such as a native oxide or surface oxide, before coating the part. Removal of the passivation layer may include providing hydrogen to the processing area of ​​the chamber. Hydrogen may allow a hydrogen plasma, hydrogen-rich plasma, or trace hydrogen plasma to form within the processing area as an approach to chemically reduce the passivation layer 305. Hydrogen may be provided to the processing area of ​​the chamber together with an inert carrier gas. In plasma systems, the inert carrier gas, also called the “forming gas,” facilitates plasma ignition and control of plasma conditions. For example, by providing hydrogen with a given inert gas fraction, the plasma may be allowed to operate under controlled plasma conditions, such as ionization fraction, ion temperature, or electron temperature. After introducing hydrogen to the processing area, Method 200 may include generating a plasma within the processing area. The plasma may be or include a hydrogen plasma. Therefore, the plasma may contain high-energy plasma species such as hydrogen ions, hydrogen radicals, or metastable diatomic hydrogen. Hydrogen plasma can be formed within a processing area while components 300 for semiconductor processing are placed within the processing area. Plasma processing can be performed based on hydrogen supplied with a carrier gas such as argon or helium to generate the plasma. Hydrogen may constitute a certain proportion of the material in the gas mixture.

[0029]

[0032] During method 200, the semiconductor processing component 300 may be placed within the processing area. In step 205, method 200 may include supplying the semiconductor processing component 300 to the processing area of ​​a processing chamber, such as the processing chamber 100 described above or other chambers that may contain multiple components as described above. The semiconductor processing component 300 may include multiple individual particles. In some embodiments, the particles constituting the semiconductor processing component 300 may be any type of material, and may be a metal-containing material, a metallic-containing material, or a ceramic-containing material. For example, the semiconductor processing component 300 may include one or more metals and one or more of oxygen, fluorine, and nitrogen (for example, a material containing one or more metals and one or more of oxygen, fluorine, and nitrogen), and not limited to aluminum, yttrium, magnesium, titanium, stainless steel, Hastelloy, aluminum oxide (Al2O3), aluminum oxyfluoride (AlO3), etc. x F y ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium dioxide (TiO2), titanium oxyfluoride (TiO2) x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4), or silicon oxynitride (SiO2 x N y ), or a combination thereof, or may include these.

[0030]

[0033] In some embodiments, method 200 may optionally include, in an optional step 210, oxidizing the semiconductor processing component 300. Optional step 210 may include introducing oxygen into the processing area of ​​the chamber. Introducing oxygen into the processing area as part of plasma-enhanced deposition may enable the formation of a controlled oxide layer on the semiconductor processing component 300. In contrast to the passivation layer 305, the controlled oxide layer may be formed under controlled conditions, such as within an oxygen plasma in the processing area. Thereafter, the oxide layer may be formed on the semiconductor processing component 300 with a characteristic and uniform thickness. Further or alternatively, optional step 210 may include thermal oxidation of the semiconductor processing component 300 after removal of the passivation film 305. The surface oxide layer may provide improved control over the thermal, mechanical, and / or chemical properties of the semiconductor processing component 300, for example, by acting as a diffusion barrier. In this method, it may be advantageous to reduce the semiconductor processing component 300 to remove the passivation layer 305, and then oxidize the semiconductor processing component 300 under controlled conditions to reform the oxide layer.

[0031]

[0034] In an optional step 210, after oxidizing the semiconductor processing component 300, method 200 may include forming a layer 310 of interface material on the semiconductor processing component 300 in step 310. Forming a layer 310 of interface material on the semiconductor processing component 300 may include performing the steps of an ALD process, thereby allowing the semiconductor processing component 300 to be uniformly coated. However, as previously stated, forming the layer 310 of interface material can be carried out using various deposition methods. For example, step 215 may include providing one or more interface deposition precursors, or introducing plasma emitters of one or more interface deposition precursors into the processing area. The plasma emitters may be or include plasma generated species formed by a remote plasma system, such as the remote plasma system 108 in Figure 1, which is in communication with the processing area. However, it has also been considered that the plasma emitters may be formed locally on the semiconductor processing component 300. Introducing the plasma emitters may also include introducing a carrier gas containing the plasma emitters. Introducing plasma emitters into the processing area in this manner allows the semiconductor processing component 300 to be exposed to plasma emitters of one or more interface deposition precursors that have undergone plasma decomposition. Therefore, the plasma emitters may be or contain ions, activated radicals, metastable species, and other decomposition products, and may be characterized by a lower average energy distribution than that of a direct plasma system. Exposure of the semiconductor processing component 300 to the plasma emitters allows for the formation of an adsorbed monolayer of the plasma emitters on the surface of the semiconductor processing component 300, which then acts as a precursor for the formation of a layer 310 of interface material. It has also been considered that the semiconductor processing component 300 may be exposed to thermal and / or chemical emitters of a first precursor, in addition to or instead of the plasma emitters.

[0032]

[0035] In the second step of atomic layer deposition, if formed, plasma emitters of the first precursor can be removed from the processing area by purging the gas from the processing area. Meanwhile, the semiconductor processing component 300 remains with the adsorbed monolayer. Purging the processing area can be carried out using a gas removal system such as the gas removal system 112 in Figure 1. After purging, the second precursor can be decomposed into second plasma emitters. Thus, the semiconductor processing component 300 is exposed to the second plasma emitters if formed. However, it has also been considered that the semiconductor processing component 300 may be exposed to thermal and / or chemical emitters of the second precursor in addition to or instead of the plasma emitters. The second precursor may be selected to decompose into plasma-generated species that react with the monolayer adsorbed on the semiconductor processing component 300 to form a layer of interface material 310. After the interface material layer 310 is formed, unreacted plasma emitters and reaction by-products can be removed by the gas removal system.

[0033]

[0036] In some embodiments, as further described below, the first and second precursors may be selected such that the interfacial material layer 310 can provide one or more benefits to the subsequently formed topcoat. For example, the interfacial material layer 310 can regulate the CTE between the part and the topcoat, improve adhesion, act as a diffusion barrier, control nucleation, control or remove contamination, or control porosity. In some embodiments, the interfacial material layer 310 may be an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-containing material, or a metal-oxygen-fluorine-nitrogen-containing material.

[0034]

[0037] In several embodiments, the one or more interface deposition precursors used may depend on the layer 310 of the interface material to be formed. For example, the one or more interface deposition precursors that can be used may include oxygen-containing precursors, nitrogen-containing precursors, fluorine-containing precursors, silicon-containing precursors, or metal-containing precursors. The oxygen-containing precursor may be any oxygen-containing material used or useful in semiconductor processing. For example, the oxygen-containing precursor may be or include water vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, alcohol-based compounds, or alcohol-based plasma. The nitrogen-containing precursor may be any nitrogen-containing material used or useful in semiconductor processing. For example, the nitrogen-containing precursor may be or include nitrous oxide (N2O), molecular nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or nitrogen-based plasma. The fluorine-containing precursor may be any fluorine-containing material used or useful in semiconductor processing. For example, fluorine-containing precursors may be or may include hydrogen fluoride (HF), ammonium fluoride (NH4F), ammonium difluoride ([NH4]F·HF), HF-pyridine complexes, nitrogen trifluoride (NF3), hexafluoroisopropanol (HFIP), tetrafluoropropanol (TFP), hexafluoroacetylacetonate (HHFAC), titanium tetrafluoride (TiF4), tantalum pentafluoride (TaF5), or tungsten hexafluoride (WF6), or fluorine-containing plasma. Silicon-containing precursors may be any silicon-containing material used or useful in semiconductor processing. For example, silicon-containing precursors may be or may include silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), or tetraethyl orthosilicate (TEOS). The metal in the metal-containing precursor may be, for example, a rare earth element or a transition metal, or may contain them. For example, the metal-containing precursor may contain aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium.In several embodiments, the metal-containing precursor may include a hexafluoroacetylacetone compound. For example, the metal may be in solution with hexafluoroacetylacetone (hfac). For example, the metal-containing precursor may be, without limitation, Mg(hfac)2, or Mg(hfac)(dmg)H2O, Al(hfac)3, Y(hfac)3, or may include these.

[0035]

[0038] In several embodiments, the interface material layer 310 may be a multilayer stack, nanolaminate stack, or microlaminate stack of one or more of the materials described above. Furthermore, the interface material layer 310 may be formed of a phase with enhanced stability. Improved stability may contribute to adjusting the CTE between the component and the coating material, improving adhesion, diffusion, contamination, and / or control of porosity. In several embodiments, the interface material layer 310 may be a variety of crystalline phases, including spinel, garnet, and any other phase.

[0036]

[0039] As described above, depending on the precursor used during deposition, the interfacial material layer 310 may be, for example, an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-containing material, or a metal-oxygen-fluorine-nitrogen-containing material. In some embodiments, the interfacial material layer 310 may contain multiple metals. For example, the interfacial material layer 310 may be an aluminum-magnesium-oxygen-containing material (Al x Mg y These may be magnesium-containing materials such as O), yttrium-aluminum-containing materials such as yttrium aluminum garnet (YAG), or erbium-aluminum-containing materials such as erbium aluminum garnet (EAG).

[0037]

[0040] After depositing the interface material layer 310 in step 215, method 200 may include, in step 220, forming a coating material layer 315 on the semiconductor processing component 300. Similar to forming the interface material layer 310, forming the coating material layer 315 on the semiconductor processing component 300 may include performing the steps of an ALD process, thereby uniformly coating the semiconductor processing component 300. However, as previously stated, forming the coating material layer 315 can be carried out using various deposition methods. For example, step 220 may include providing one or more coating deposition precursors, or introducing plasma emitters of one or more coating deposition precursors into the processing area. The plasma emitters may be, or include, plasma-generated species formed by a remote plasma system, such as the remote plasma system 108 in Figure 1, which is in communication with the processing area. However, it is also considered that the plasma emitters may be formed locally on the semiconductor processing component 300. Introducing the plasma emitters may also include introducing a carrier gas containing the plasma emitters. Introducing plasma emitters into the processing area in this manner allows the semiconductor processing component 300 to be exposed to plasma emitters of one or more plasma-decomposed precursors. Therefore, the plasma emitters may be or contain ions, activated radicals, metastable species, and other decomposition products, and may be characterized by a lower average energy distribution than that of a direct plasma system. Exposure of the semiconductor processing component 300 to the plasma emitters allows for the formation of an adsorbed monolayer of the plasma emitters on the surface of the semiconductor processing component 300, which then acts as a precursor for the formation of the coating material layer 315.

[0038]

[0041] In the second step of atomic layer deposition, plasma emitters of the first precursor can be removed from the processing area by purging the gas from the processing area. Meanwhile, the semiconductor processing component 300 remains with the adsorbed monolayer. Purging the processing area can be performed using a gas removal system such as the gas removal system 112 shown in Figure 1. After purging, the second precursor can be decomposed into second plasma emitters. Thereafter, the semiconductor processing component 300 is exposed to the second plasma emitters. The second precursor may be selected to decompose into plasma-generated species that react with the monolayer adsorbed on the semiconductor processing component 300 to form a layer 315 of coating material. After the layer 315 of coating material is formed, unreacted plasma emitters and reaction byproducts can be removed by the gas removal system.

[0039]

[0042] In some embodiments, the first and second precursors may be selected such that the coating material layer 315 may be or may contain a corrosion-resistant and / or erosion-resistant adhesive to improve the mechanical properties of the semiconductor processing component 300. For example, the coating material layer 315 may be an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-containing material, or a metal-oxygen-fluorine-nitrogen-containing material. The oxygen-containing material may be, for example, a silicon-oxygen-containing material or may contain one. The nitrogen-containing material may be, for example, a silicon-nitrogen-containing material or may contain one. The fluorine-containing material may be, for example, a fluorine-doped silicon-containing material or may contain one.

[0040]

[0043] In several embodiments, the one or more coating deposition precursors used may depend on the layer 315 of the coating material to be formed. For example, one or more of oxygen-containing precursors, nitrogen-containing precursors, fluorine-containing precursors, silicon-containing precursors, or metal-containing precursors may be used. The oxygen-containing precursor may be any oxygen-containing material used or useful in semiconductor processing. For example, the oxygen-containing precursor may be or include water vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, alcohol-based compounds, or alcohol-based plasma. The nitrogen-containing precursor may be any nitrogen-containing material used or useful in semiconductor processing. For example, the nitrogen-containing precursor may be or include nitrous oxide (N2O), molecular nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or nitrogen-based plasma. The fluorine-containing precursor may be any fluorine-containing material used or useful in semiconductor processing. For example, fluorine-containing precursors may be or may include hydrogen fluoride (HF), ammonium fluoride (NH4F), ammonium difluoride ([NH4]F·HF), HF-pyridine complexes, nitrogen trifluoride (NF3), hexafluoroisopropanol (HFIP), tetrafluoropropanol (TFP), hexafluoroacetylacetonate (HHFAC), titanium tetrafluoride (TiF4), tantalum pentafluoride (TaF5), or tungsten hexafluoride (WF6), or fluorine-containing plasma. Silicon-containing precursors may be any silicon-containing material used or useful in semiconductor processing. For example, silicon-containing precursors may be or may include silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), or tetraethyl orthosilicate (TEOS). The metal in the metal-containing precursor may be, for example, a rare earth element or a transition metal, or may contain them. For example, the metal-containing precursor may contain aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium.In several embodiments, the metal-containing precursor may include a hexafluoroacetylacetone compound. For example, the metal may be in solution with hexafluoroacetylacetone (hfac). For example, the metal-containing precursor may be, without limitation, Mg(hfac)2, or Mg(hfac)(dmg)H2O, Al(hfac)3, Y(hfac)3, or may include these.

[0041]

[0044] Depending on the precursor used during deposition, the coating material layer 315 may be, for example, aluminum fluoride (AlF3), aluminum oxyfluoride (AlO3), etc. x F y ), calcium fluoride (CaF2), calcium oxyfluoride (CaO x F y ), magnesium fluoride (MgF2), yttrium fluoride (YF3), yttrium oxyfluoride (YO x F y ), yttrium oxyfluoride (YO x F y ), zirconium fluoride (ZrF4), zirconium oxyfluoride (ZrO x F y ), scandium fluoride (ScF3), scandium oxyfluoride (ScO x F y Any other layer of the aforementioned materials is considered, including a layer 315 of coating material containing multiple metals, which may include, or a combination thereof. In one exemplary embodiment, the layer 315 of coating material may be a fluorine-containing material.

[0042]

[0045] In several embodiments, a further layer of material may be formed on the semiconductor processing component 300, or the coating material layer 315 may contain further elements. The further layer of material or the coating material layer 315 may contain several different materials, including oxides, nitrides, or fluoride materials in addition to the metal-containing material. Depending on the precursor used, the further layer of material may be an oxide, nitride, or oxynitride. For example, the further layer of material may be, or contain, aluminum oxide (Al2O3), yttrium oxide (Y2O3), magnesium oxide (MgO), titanium oxide (TiO2), erbium oxide (Er2O3), lanthanum oxide (La2O3), scandium oxide (Sc2O3), zirconium oxide (ZrO2), aluminum nitride (AlN), silicon nitride (SiN), tantalum nitride (TaN), titanium nitride (TiN), or zirconium nitride (ZrN).

[0043]

[0046] In some embodiments, the steps constituting step 220 may be repeated to deposit multiple monolayers. Thereafter, a layer 315 of the coating material may be formed monolayer by monolayer, and the thickness of the coating material layer 315 may be an integer multiple (number of repetitions of step 220) of the thickness of the monolayer. Furthermore, after step 220, a second layer 320 of the coating material may be formed on top of the layer 315 of the coating material by repeating the process using either the same set of first and second precursors or different sets of first and second precursors. For example, if the layer 315 of the coating material may be or contain aluminum fluoride, the second material 320 may be or contain a different fluoride such as yttrium aluminum fluoride, or another oxide, nitride, or fluoride. Therefore, the semiconductor processing component 300 coated by method 200 may include one or more layers of different materials, such as a controlled oxide layer, an interface material layer 310, a coating material layer 315, and a second layer 320 of the coating material.

[0044]

[0047] The flow rate of the coating precursor or deposition precursor introduced into the chamber may depend at least in part on one or more parameters of the chamber, the semiconductor processing component 300, or the method 200. For example, the flow rate may be adjusted so that a plasma with sufficient energy density or species density, such as ions, free electrons, or an activation precursor, can be formed to facilitate the reduction of the passivation layer 305 or the deposition of the coating material layer 315.

[0045]

[0048] In relation to the flow rate of the coating precursor or deposition precursor, the pulse size of the first or second precursor may be about 75 minutes or less. At times exceeding 75 minutes, the semiconductor processing component 300 may become completely saturated and can no longer accept the precursor to form a monolayer of the material. Therefore, the pulse size of the first or second precursor may be about 70 minutes or less, about 65 minutes or less, about 60 minutes or less, about 55 minutes or less, about 50 minutes or less, about 45 minutes or less, about 40 minutes or less, about 35 minutes or less, about 30 minutes or less, about 25 minutes or less, about 20 minutes or less, about 15 minutes or less, about 10 minutes or less, about 5 minutes or less, about 2 minutes or less, about 1 minute or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, about 20 seconds or less, about 10 seconds or less, or less.

[0046]

[0049] Similarly, the pulse size of the purge gas for purging the first precursor may be approximately 120 minutes or less, approximately 110 minutes or less, approximately 100 minutes or less, approximately 90 minutes or less, approximately 80 minutes or less, approximately 70 minutes or less, approximately 65 minutes or less, approximately 60 minutes or less, approximately 55 minutes or less, approximately 50 minutes or less, approximately 45 minutes or less, approximately 40 minutes or less, approximately 35 minutes or less, approximately 30 minutes or less, approximately 25 minutes or less, approximately 20 minutes or less, approximately 15 minutes or less, approximately 10 minutes or less, approximately 5 minutes or less, approximately 2 minutes or less, approximately 1 minute or less, or less. The purge may have a longer duration than the precursor to ensure that the precursor is completely removed from the processing area.

[0047]

[0050] In method 200, such as in step 210 and / or 215, the temperature in the processing chamber can be maintained at approximately 2000°C or lower. While higher temperatures may be employed, deposition in this technology can be performed at approximately 1750°C or lower, for example, approximately 1500°C or lower, approximately 1250°C or lower, approximately 1000°C or lower, approximately 900°C or lower, approximately 800°C or lower, approximately 750°C or lower, approximately 725°C or lower, approximately 700°C or lower, approximately 675°C or lower, approximately 650°C or lower, approximately 625°C or lower, approximately 600°C or lower, approximately 575°C or lower, approximately 550°C or lower, approximately 525°C or lower, approximately 500°C or lower, approximately 480°C or lower, approximately 460°C or lower, approximately 44 It can operate at temperatures below 0°C, below approximately 420°C, below approximately 400°C, below approximately 380°C, below approximately 360°C, below approximately 340°C, below approximately 320°C, below approximately 300°C, below approximately 280°C, below approximately 260°C, below approximately 240°C, below approximately 220°C, below approximately 200°C, below approximately 180°C, below approximately 160°C, below approximately 140°C, below approximately 120°C, below approximately 100°C, below approximately 80°C, below approximately 60°C, below approximately 40°C, below approximately 20°C, or below. However, higher temperatures can increase material deposition and improve throughput. In several embodiments, ALD deposition performed at higher temperatures may allow deposition to proceed in a manner closer to CVD deposition. Therefore, the temperature inside the processing chamber can be maintained at approximately 300°C or higher, for example, approximately 350°C or higher, approximately 400°C or higher, approximately 450°C or higher, approximately 500°C or higher, or even higher.

[0048]

[0051] Furthermore, during method 200, such as in process 210 and / or 215, the pressure in the processing chamber may be maintained at about 50 mTorr or less. Again, higher pressures may be employed, however, deposition in this technology may operate at about 50 mTorr or less, for example, about 45 mTorr or less, about 40 mTorr or less, about 35 mTorr or less, about 30 mTorr or less, about 25 mTorr or less, about 20 mTorr or less, about 15 mTorr or less, about 10 mTorr or less, about 7 mTorr or less, about 5 mTorr or less, about 3 mTorr or less, about 1 mTorr or less, or even lower.

[0049]

[0052] The interface material layer 310 and / or the coating material layer 315 may be formed to a thickness of about 3000 nm or less, for example, about 2750 nm or less, about 2500 nm or less, about 2250 nm or less, about 2000 nm or less, about 1750 nm or less, about 1500 nm or less, about 1250 nm or less, about 1000 nm or less, about 750 nm or less, about 500 nm or less, about 250 nm or less, about 100 nm or less, or less. In some embodiments, depending on the application, the interface material layer 310 and / or the coating material layer 315 may be formed to a considerably smaller thickness, for example, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, about 5 nm or less, about 2 nm or less, about 1 nm or less, or less.

[0050]

[0053] Method 200 and its constituent steps may provide one or more improvements to plasma-enhanced deposition processes for depositing materials onto semiconductor processing components, for example, by ALD. For example, Method 200 may provide coated semiconductor processing components characterized by a core-shell structure. In this case, the core may be, or may contain, a ceramic material of the component, such as aluminum nitride or any other ceramic material, accompanied by one or more shells, such as transition metal fluorides or rare earth fluorides. The shells may be precisely deposited by layered deposition using atomic layer deposition. Thereafter, the relative composition of the coated semiconductor processing component may be specified by repeating step 215 a predetermined number of times. Furthermore, by including an interface between the core and the shell, one or more desired properties may be obtained. For example, the interface may regulate the CTE between the core and the shell, improve adhesion between the core and the shell, act as a diffusion barrier layer, control nucleation, control or remove contamination, or control porosity. Furthermore, plasma removal of the native passivation layer 305 improves the control of surface chemistry and thus can improve the thermal, mechanical, and / or chemical properties of the coated semiconductor processing components.

[0051]

[0054] In several embodiments, components for semiconductor processing may be characterized by a first CTE. A layer 315 of coating material may be characterized by a second CTE. To adjust the difference between the first and second CTEs, a layer 310 of interface material may be characterized by a third CTE that is higher than the first CTE and lower than the second CTE.

[0052]

[0055] In addition to regulating the larger CTE difference between the part and the coating material layer, the interface material layer 310 may offer further or alternative advantages. The interface material layer may improve adhesion compared to conventional techniques in which the coating material layer can be formed directly on the part. Furthermore, the interface material layer can control diffusion, nucleation, contamination, and / or porosity. For example, during processing, material from the part, such as a metallic material, may begin to diffuse from the part. However, the interface material layer can reduce or prevent this diffusion. This also allows for control of contamination. The interface material layer can also reduce or prevent any nucleation that may occur between the part and the coating material layer. Finally, as previously mentioned, the interface material layer can be characterized by various crystalline structures, including spinel and garnet, to control porosity.

[0053]

[0056] As will be further explained with reference to Figure 4, components for semiconductor processing may, in no particular way, be lids, nozzles, faceplates, gas distribution plates, heaters, screws, substrate supports, support platens, liners, edge rings, process kit rings, or lift pins. These components are generally exposed to corrosive plasma conditions and may require corrosion-resistant and / or erosion-resistant coatings. By using the aforementioned coated components for semiconductor processing, corrosion-resistant and / or erosion-resistant materials can be effectively formed on the components to provide the desired corrosion and / or erosion resistance.

[0054]

[0057] Figure 4 shows a schematic diagram of an exemplary plasma processing system including one or more components formed by a method according to several embodiments of the present technology. Figure 4 further shows details relating to a semiconductor processing system 400 and one or more components that may be incorporated into the system 400, which may be or include coated semiconductor processing components. The coated semiconductor processing components may be formed by coating semiconductor processing components, such as coated semiconductor processing components prepared by method 200. The system 400 is understood to include any feature or embodiment of a semiconductor processing chamber and may be used to perform semiconductor processing steps including deposition, removal, and cleaning steps. The system 400 may show a partial view of a chamber component described, which may be incorporated into a typical semiconductor processing system, and may show a view across the center of the pedestal and gas distributor (which may be of any other size). Any embodiment of the system 400 may also be incorporated into other processing chambers or systems, as will be readily understood by those skilled in the art.

[0055]

[0058] The system 400 may include a semiconductor processing chamber 450 including a showerhead 405. A precursor 407 is supplied for processing through the showerhead 405 and may be configured to form a plasma 410 within a processing area between the showerhead 405 and a pedestal or substrate support 415. The showerhead 405 may be understood to be at least partially inside the chamber 450 and electrically isolated from the chamber 450. In this manner, the showerhead 405 may act as a live electrode or reference ground electrode of the plasma system to expose a substrate held on the substrate support 415 to plasma-generated species. The substrate support 415 may extend through the base of the chamber 450. The substrate support 415 may include a support platen 420. The support platen 420 may hold the semiconductor substrate 430 during a deposition or removal process used to form a patterned structure on the semiconductor substrate 430.

[0056]

[0059] The support platen 420 may be, or include, a component for processing coated semiconductors prepared according to multiple embodiments of Method 200. The support platen 420 may incorporate embedded electrodes for providing an electric field employed to hold the semiconductor substrate, and may also include, non-limitingly, a thermal control system that can facilitate processing steps, including deposition, etching, annealing, or desorption. In some embodiments, the support platen 420 may incorporate plates, perforated plates, meshes, wire screens, or any other dispersed arrangement of conductive elements. The embedded electrodes may be, or include, tuning electrodes for providing further control over the plasma 410 by adjusting the electric field near the surface of the support platen. Similarly, bias electrodes and / or electrostatic chuck electrodes may be coupled to the support platen 420. The bias electrodes may be coupled to a power source such as DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In this manner, the substrate support 415 and support platen 420 may be used during the plasma processing step not only to hold the semiconductor substrate 430 but also to adjust the state of the plasma 410. Adjusting the state of the plasma may include performing automatic impedance matching to maintain plasma conditions during the plasma processing step, for example, while the composition of the plasma 410 changes, or when the surface of the semiconductor substrate 430 changes, for example, due to the deposition of a dielectric film on the electrode surface. In this manner, precise control of the plasma 410 may depend on the material properties of the substrate support 415 and support platen 420.

[0057]

[0060] In some cases, the support platen 420 and other chamber components may be formed by coating the semiconductor processing component with a layer 434 of interface material and a layer 435 of coating material. For example, the semiconductor processing component may be processed to form a layer 434 of interface material, and then processed to deposit a layer 435 of coating material, such as a corrosion-resistant and / or erosion-resistant material, on the interface material layer 434. Pre- and / or post-processes, such as annealing, machining, and assembly of electrical components, may be applied to finish the component, providing an operating component that can be incorporated into a plasma system. For example, the advantages of using a coated semiconductor processing component may include the fact that a component finished with one or more layers 435 of coating material can act as a high-temperature resistant conductor with good electrical conductivity, as well as good thermal deformation properties and chemical resistance to plasma etching. Furthermore, the interface material layer 434 may help to enhance the advantages of the coating material layer 435.

[0058]

[0061] The preceding description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0059]

[0062] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the descriptions in the prior specification should not be considered to limit the scope of the Art. In addition, while methods or processes may be described as sequential or stepwise, it should be understood that these steps may be performed simultaneously or in a different order than described.

[0060]

[0063] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is specifically disclosed down to the smallest unit of the lower limit. This includes any smaller range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each of these narrower ranges, whether containing one, neither, or both of the limit values, is also included in the Art, although there may be limit values ​​specifically excluded within the stated range. Where a stated range contains one or both of the limit values, it also includes ranges that exclude one or both of these included limit values.

[0061]

[0064] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, a reference to “a precursor” includes multiple such precursors, a reference to “the layer” includes one or more layers and their equivalents known to those skilled in the art, and the same applies to the other forms.

[0062]

[0065] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or processes, but not to exclude the presence or addition of one or more other features, integers, components, processes, actions, or groups.

Claims

1. A processing method, To provide semiconductor processing components to the processing area of ​​a processing chamber. To provide one or more interface deposition precursors to the processing area, A layer of interface material is deposited on the semiconductor processing component within the processing region, wherein the layer of interface material includes an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-containing material, or a metal-oxygen-fluorine-nitrogen-containing material. Providing one or more coating deposition precursors to the processing area, A processing method comprising depositing a layer of coating material on the layer of interface material within the processing region.

2. The processing method according to claim 1, wherein the semiconductor processing component includes a metal-containing material or a metallic material.

3. The processing method according to claim 1, wherein the semiconductor processing component includes a ceramic-containing material, and the ceramic-containing material includes one or more metals and one or more of oxygen, fluorine, and nitrogen.

4. The ceramic-containing material is aluminum oxide (Al 2 O 3 ), aluminum oxyfluoride (AlO x F y ), yttrium oxide (Y 2 O 3 ), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium oxide (TiO 2 ), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiO x N y ), the processing method according to claim 3.

5. The processing method according to claim 1, wherein the layer of the interface material is characterized by a coefficient of thermal expansion (CTE) that is higher than that of the semiconductor processing component and lower than that of the coating material layer.

6. The treatment method according to claim 1, wherein the metal-containing precursor comprises aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium.

7. The one or more coating deposition precursors include a fluorine-containing precursor, and the fluorine-containing precursor is hydrogen fluoride (HF), ammonium fluoride (NH4). 4 F), ammonium difluoride ([NH 4 ]F・HF), HF-pyridine complex, nitrogen trifluoride (NF 3 ), hexafluoroisopropanol (HFIP), tetrafluoropropanol (TFP), hexafluoroacetylacetonate (HHFAC), titanium tetrafluoride (TiF 4 ), tantalum pentafluoride (TaF 5 ), or tungsten hexafluoride (WF 6 The processing method according to claim 1, comprising ), or fluorine-containing plasma.

8. The layer of the coating material is aluminum fluoride (AlF 3 ), aluminum oxyfluoride (AlO x F y ), calcium fluoride (CaF 2 ), calcium oxyfluoride (CaO x F y ), magnesium fluoride (MgF 2 ), yttrium fluoride (YF 3 ), yttrium oxyfluoride (YO x F y ), zirconium fluoride (ZrF 4 ), zirconium oxyfluoride (ZrO x F y ), scandium fluoride (ScF 3 ), or scandium oxyfluoride (ScO x F y The processing method according to claim 1, which includes, or a combination thereof.

9. The processing method according to claim 1, wherein the one or more coating deposition precursors further comprises an oxygen-containing precursor.

10. The oxygen-containing precursor is water vapor (H 2 O), molecular oxygen (O 2 ), ozone (O 3 ), nitrous oxide (N 2 O), hydrogen peroxide (H 2 O 2 The processing method according to claim 8, comprising oxygen-containing plasma, an alcohol-based compound, or an alcohol-based plasma.

11. The processing method according to claim 1, wherein the one or more coating deposition precursors further comprises a nitrogen-containing precursor.

12. The processing method according to claim 1, further comprising generating plasma emissions of one or more coating deposition precursors.

13. The processing method according to claim 1, wherein the temperature within the processing area is maintained at approximately 2000°C or less.

14. The semiconductor processing method according to claim 13, wherein the semiconductor processing components include a lid, nozzle, faceplate, gas distribution plate, heater, screw, substrate support, support platen, liner, edge ring, process kit ring, or lift pin.

15. A processing method, To provide semiconductor processing components to the processing area of ​​the processing chamber, The method involves depositing a layer of interface material on the semiconductor processing component within the processing region, wherein the layer of interface material includes an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-nitrogen-containing material, a material containing one or more metals and one or more of oxygen, fluorine, and nitrogen, or a combination thereof. The process includes depositing a layer of coating material on the layer of interface material within the processing region, wherein depositing the layer of coating material is Exposing the semiconductor processing component to the first coating precursor, Purging the aforementioned processing area, and This includes exposing the semiconductor processing component to a second coating precursor, A processing method comprising: a layer of the coating material comprising a reaction product of the first coating precursor and the second coating precursor, wherein the temperature in the processing chamber is maintained at approximately 400°C or higher.

16. The aforementioned semiconductor processing component is made of aluminum oxide (Al 2 O 3 ), aluminum oxyfluoride (AlO x F y ), yttrium oxide (Y 2 O 3 ), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium dioxide (TiO 2 ), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiO x N y The processing method according to claim 15, including ).

17. The processing method according to claim 15, wherein the layer of the coating material comprises a metal-fluorine-oxygen-containing material.

18. The processing method according to claim 15, further comprising generating plasma emitters of the first coating precursor, the second coating precursor, or both thereof.

19. A component for semiconductor processing, Ceramic, metal, or non-metallic parts for semiconductor processing, A layer of interface material on the semiconductor processing component, wherein the layer of interface material includes an oxygen-containing material, a nitrogen-containing material, a fluorine-containing material, a metal-oxygen-containing material, a metal-fluorine-containing material, a metal-nitrogen-containing material, a metal-oxygen-fluorine-nitrogen-containing material, a metal-oxygen-fluorine-nitrogen-containing material, a material containing one or more metals and one or more of oxygen, fluorine, and nitrogen, or a combination thereof, and A component for semiconductor processing, comprising a layer of coating material on the aforementioned interface material layer.

20. The semiconductor processing component according to claim 19, wherein the semiconductor processing component includes a lid, nozzle, faceplate, gas distribution plate, heater, screw, substrate support, support platen, liner, edge ring, process kit ring, or lift pin.

Images