Processing write requests based on queue identifiers

Abstract

Various embodiments provide processing of write requests on a memory system based on a queue identifier associated with the write request. Specifically, an input data stream may be received and stored by a submission queue in the memory system, and write requests within the input data stream may be partitioned based on a queue identifier associated with the submission queue, using an inline approach for writing data to the memory system, an offline approach for writing data to the memory system, or both.

Description

Technical Field

[0004]

[0001] Cross - Reference to Related Applications This application claims the benefit of priority of U.S. Provisional Application No. 63 / 526,509, filed on Jul. 13, 2023, which is hereby incorporated by reference in its entirety.

[0002] Embodiments of the present disclosure generally relate to memory devices, and more specifically, to processing write requests on a memory system based on a queue identifier associated with a write request.

Background Art

[0003] A memory subsystem can include one or more memory devices for storing data. The memory devices can be, for example, non - volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data in and retrieve data from the memory devices.

[0004] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be construed as limiting the present disclosure to specific embodiments, but are for illustrative and understanding purposes only.

Brief Description of the Drawings

[0005] [Figure 1] FIG. is a block diagram showing an exemplary computing system including a memory subsystem according to some embodiments of the present disclosure. [Figure 2] FIG. is a diagram showing an exemplary architecture of a host system and a memory subsystem according to some embodiments of the present disclosure. [Figure 3] FIG. shows an example of a filtering request for an exemplary write data stream according to some embodiments of the present disclosure. [Figure 4]This disclosure illustrates exemplary garbage collection operations of a superblock according to several embodiments of this disclosure. [Figure 5] This is a flowchart illustrating exemplary methods for processing write requests on a memory system based on a queue identifier associated with a write request, according to some embodiments of the present disclosure. [Figure 6] This is a flowchart illustrating exemplary methods for processing write requests on a memory system based on a queue identifier associated with a write request, according to some embodiments of the present disclosure. [Figure 7] This is a block diagram of an exemplary computer system that can be operated by embodiments of the present disclosure. [Modes for carrying out the invention]

[0006] Aspects of this disclosure relate to processing write requests on a memory system (e.g., a memory subsystem) based on a queue identifier associated with the write request. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below with reference to Figure 1. Generally, a host system can utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can store data in the memory subsystem and send access requests to the memory subsystem, such as for reading data from the memory subsystem.

[0007] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to, for example, store data in the memory subsystem's memory devices, read data from the memory subsystem's memory devices, or write or read constructors (e.g., submission queues and completion queues) to the memory subsystem's memory devices. The data to be read or written, as specified by a host request (e.g., a data access request or a command request), is hereafter referred to herein as "host data." A host request may include information about the logical address to the host data (e.g., a logical block address (LBA), namespace), which is the location that the host system associates with the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata for the host data. Metadata may also include error handling data (e.g., error-correcting code (ECC) codeword, parity code), data version (e.g., used to distinguish the elapsed time of written data), and valid bitmap (which LBA or logical transfer unit contains valid data).

[0008] The memory subsystem can initiate media management operations, such as write operations, on host data stored in the memory device. For example, the firmware of the memory subsystem can rewrite previously written host data from one location to a new location within the memory device as part of a garbage collection management operation. For example, data that is rewritten when initiated by the firmware will be referred to as "garbage collection data" in this specification.

[0009] Hereinafter, “user data” generally refers to host data and garbage collection data. Hereinafter, “system data” refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical memory address mapping tables (hereinafter also referred to as L2P tables), data from logging, scratchpad data, etc.).

[0010] Garbage collection (GC) typically involves operations to manage memory usage in NAND memory devices. When the free space on a NAND memory device becomes low, GC can recover free space on the NAND memory device so that new host data can be written. During GC, blocks of the NAND memory device are read, including pages (or sections of pages) with valid data and pages with old / invalid data (e.g., garbage). Pages (or sections of pages) of blocks with valid data are protected by writing valid data to free (e.g., fresh or erased) blocks on the NAND memory device at a new physical memory location (thus relocating the valid data to a new location). In addition, the logical block address (LBA) for the valid data is updated at the new physical memory location. Free blocks can be selected from a pool of free blocks. Pages with old / invalid data are marked for deletion and remain in the (old) block. After all valid data has been relocated from the old block, the entire old block (including pages containing old / invalid data) is erased, and the erased block can be added to the free block pool, which can then be used to write newly received data. Such data writing to pages and block erasure can lead to write amplification (WA). The numerical metric for WA can be determined using the ratio of the amount of data physically written to the NAND memory (e.g., physical writes) to the amount of data the host system was originally intended to write (e.g., write requests from the host system). The actual physical write is usually greater than the write requests from the host system, resulting in a WA metric greater than 1.

[0011] A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. In some types of non-volatile memory devices (e.g., NOT-AND (NAND) devices), each plane consists of a set of physical blocks. In some memory devices, a block is the smallest area that can be erased. Each block consists of a set of pages. Each page consists of a set of memory cells that store bits of data. A memory device can be a raw memory device (e.g., NAND) that is managed externally, for example by an external controller. A memory device can be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0012] Certain memory devices, such as NAND memory devices, contain one or more blocks (e.g., multiple blocks), each of which contains multiple memory cells. For example, a memory device may contain multiple pages (also called word lines), each of which contains a subset of the memory cells of the memory device. A memory device may contain one or more cache blocks and one or more non-cache blocks. When data is written to the memory device, it can be written first to one or more cache blocks to facilitate faster write performance. When data is stored in the cache blocks, it can eventually be moved (e.g., copied) to one or more non-cache blocks at a later time (e.g., by performing a block compaction operation when the memory device is idle), thereby facilitating a higher storage capacity in the memory device. A cache block may contain SLC blocks, which are single-level cells (SLCs), while a non-cache block may contain MLC blocks, which are multi-level cells (MLCs), TLC blocks, which are triple-level cells (TLCs), or QLC blocks, which are quad-level cells (QLCs). The initial writing to one or more SLC blocks can be called an SLC write cache. Generally, writing data to such a memory device involves programming the memory device (by programmatic operation) at the page level of the block, and erasing data from such a memory device involves erasing the memory device at the block level (for example, erasing data at the page level is not possible).

[0013] A compaction (or garbage collection) operation can be performed on a cache block (containing one or more memory cells) of a memory device (e.g., a NAND memory device) so that when data is stored in a cache block, it is copied (e.g., transferred) to a non-cache block. For example, if there are no cache blocks available to cache new data (e.g., cache newly written data), a compaction operation can be performed on a set of cache blocks. As used herein, a block compaction operation can be performed on a cache block and may include reading data stored in the cache block and writing the read data to a non-cache block (e.g., programming a non-cache block with data read from the cache block), thereby copying data from the cache block to the non-cache block. An exemplary block compaction operation may include a compaction operation from an SLC block to a QLC block. A block compaction operation can be performed, for example, if the available cache blocks in a memory device are full or approaching the write limit.

[0014] In conventional memory devices containing negative AND (NAND) memory cells (hereinafter referred to as NAND memory devices), sequential writing and erasing typically results in reduced or decreased write amplification (e.g., a decrease in the write amplification factor (WAF)) and improved data performance. Modern software on a host system (e.g., software applications, databases, and file systems) tends to read and write data sequentially to and from the memory system (e.g., a memory subsystem coupled to the host system). However, when such software is run on one or more multi-core hardware processors in the host system, the continuity of data access requests to the memory system (e.g., read and write requests) is typically lost. For example, when modern software runs on one or more multi-core hardware processors in the host system, the block layer of the host system typically divides the work performed by each process (of the software) across two or more cores of the multi-core hardware processor (e.g., so that the work is evenly distributed across the cores to achieve maximum throughput). Each core of the host system's hardware processor may continue to issue mostly sequential data access requests to the memory system, but these requests are typically mixed alternately (e.g., interleaved), appearing random or pseudo-random from the memory system's perspective. This may be due to data aggregation and request prioritization policies at the data link layer between the host system and the memory system. For example, memory systems with a Non-Volatile Memory Express (NVMe) architecture are typically designed to have a non-sequential traffic handshake between the host system and the memory system's controller for data performance reasons.

[0015] Aspects of this disclosure relate to processing write requests on a memory system (e.g., a memory subsystem) based on a queue identifier associated with the write request. Specifically, an input data stream may be stored in a submission queue of the memory system, and write requests within the input data stream may be partitioned based on a queue identifier associated with the submission queue, using an inline approach to write data to the memory system (e.g., to its medium), an offline approach to write data to the memory system (e.g., to its medium), or both. The memory systems of the various embodiments described herein utilize queue identifiers contained in the write requests and utilize the submission queue (associated with the queue identifier) ​​that receives the write requests to detect continuity and locality of data input / output (I / O) in write requests from a host system.

[0016] The architecture of conventional memory systems, such as those implemented by the NVMe standard, includes multiple queues for processing data access requests (e.g., read and write requests) from a host system. For example, a memory system based on the NVMe standard may include multiple queue pairs, each associated with a different queue identifier (QID), and each queue pair includes a submission queue for incoming requests that need to be completed / processed, and a completion queue for command requests that have already been completed / processed by the memory system. In this specification, a submission queue identifier (SQID) can refer to the submission queue of a given queue pair and can be equal to the QID of a given queue pair. The QID can be included as a parameter (e.g., a QID tag) in a data access request from the host system to the memory system and can function as a pointer to the submission queue on the memory system that receives the data access request. Generally, each core of a host system's hardware processor is individually associated with (e.g., assigned, mapped, and attached to) a different QID (e.g., different queue pairs on a memory system with unique QIDs), and data access requests from a given core (e.g., read and write requests) are received and stored by a submission queue having the queue identifier associated with that core. Furthermore, a given thread running on the host system (e.g., a software application or database on the host system) tends to start / run on the same core of the host system's hardware processor (e.g., threads on the host system have core affinity). A given core in the host system's hardware processor can have multiple threads (e.g., 4-5 threads) running on that core and having affinity to that core.

[0017] Given that selection threads tend to issue data access requests sequentially, that selection threads have affinity to selection cores in the host system's hardware processor, and that selection cores are associated with selection submission queues in a memory system having selection queue identifiers, various embodiments of a memory system can use the queue identifiers of the submission queue as a proxy for identifying one or more threads, each of which tends to generate or issue data access requests sequentially. By using the queue identifiers to identify one or more threads, various embodiments of a memory system can detect the continuity of data access requests (of those one or more threads) based on the queue identifiers and process the data access requests in a manner that maintains at least some level of continuity in the data access requests (e.g., read requests or write requests). For example, some embodiments described herein operate on the premise that write requests generated by one or more threads operating on a given hardware processor core and stored in a given submission queue of a memory system are likely to be correlated within a given time interval (e.g., an interval covering the length of a page stripe, i.e., a few seconds).

[0018] The following describes exemplary inline approaches for writing data to a memory system (e.g., to its medium) based on a queue identifier. According to various embodiments, write requests are received by the memory system from a host system via one or more submission queues of the memory system, and a submission queue associated with a particular queue identifier receives write requests having the same particular queue identifier. In some embodiments, when the memory system scans each submission queue for the next data access request, it initiates immediate processing (e.g., immediate execution, command merging, or staging execution) of any read requests it detects, and holds any write requests it detects for subsequent delayed processing (e.g., execution). For example, in the case of a write request from a submission queue having a particular queue identifier, in one embodiment, the memory system can hold the write request for delayed processing (e.g., execution) by adding the write request to a specific list of held write requests, where the specific list is associated with a particular queue identifier (e.g., a write_held(QID) list). In some embodiments, the memory system maintains a separate list of held write requests for each queue identifier. If the monitored time (e.g., timer) associated with a given list of pending write requests (for QID) expires, or if the number of write requests in the given list of pending write requests exceeds a threshold number (e.g., a predetermined number of write requests, such as 8 write requests), the memory system may initiate immediate processing (e.g., execution, immediate execution, command merging, or staging execution) by the memory system for at least some (e.g., all) of the write requests in the given list of pending write requests.According to some embodiments, since the write requests in a given list of pending write requests are expected to be highly sequential (for example, based on the core affinity of the threads and the fact that individual queue identifiers are associated with individual hardware processor cores), these write requests can be consolidated into larger sequential writes. For example, with respect to data access requests received and stored by a given submission queue associated with a given queue identifier, one embodiment described herein can cause the memory system to hold write requests (e.g., write commands) for delayed execution and consolidate those write requests into a single sequential write with a larger average size (e.g., about 6000 logical block addresses (LBA)) than write requests that are not held for delayed execution (e.g., write requests may have a smaller average size, such as 700 LBA). If there are many sequential writes based on the list of pending write requests, the granularity of the cursors on the memory system can be made coarser, reducing the workload (e.g., the number of I / O operations) performed between garbage collections.

[0019] The following describes an exemplary offline approach for writing data to a memory system (e.g., to its medium) based on a queue identifier. According to various embodiments, a write request is received by the memory system from a host system via one or more submission queues in the memory system, and a submission queue associated with a particular queue identifier receives write requests having the same particular queue identifier. Finally, when a given write request from a given submission queue is processed (e.g., using or not using the inline approach described herein), the given write request is processed such that the associated queue identifier (associated with a given submission queue / given write request) is stored in memory (e.g., as a QID tag) associated with the data (e.g., host data or user data) written to a set of blocks on the memory system by the given write request. For example, if data is written to a set of blocks in response to a write request from a submission queue, the data may include the queue identifier associated with the write request (e.g., SQID), or metadata associated with the set of blocks may include the queue identifier. In another example, when data is written to a set of blocks in response to a write request from a submission queue, the queue identifier (e.g., SQID) associated with the write request may be stored in a separate stream or storage area of ​​the memory system associated with the set of blocks. Finally, when garbage collection is performed on one or more source blocks (e.g., source superblocks) of the memory system, the queue identifiers stored in association with those blocks can be used to sequentially organize (e.g., sequentially write) data for common queue identifiers within a set of destination blocks (e.g., destination superblocks).Specifically, a memory system in one embodiment can identify the longest list of source memory units (e.g., pages or blocks) that store valid data and have a common queue identifier in one or more source blocks, and perform garbage collection on the blocks in the longest list. For example, data can be migrated from one or more pages in the longest list to a destination superblock (e.g., its page stripe) until that destination superblock is full or the list is exhausted. If the superblock is not full, the next longest list of source memory units (e.g., pages or blocks) that store valid data and have a common queue identifier is identified, and data can be migrated from one or more memory units in the next longest list to a destination superblock (e.g., its page stripe) until that destination superblock is full or the list is exhausted. This can be repeated until the destination superblock is full. As described herein, by performing garbage collection based on queue identifiers, in various embodiments, the probability that the entire set of destination memory units that received the migrated valid data (e.g., the entire destination superblock) will be erased when the migrated valid data is finally erased can be increased, resulting in improved performance and reduced garbage collection overhead.

[0020] Generally, by using the various embodiments described herein, more sequential storage (e.g., sorting) of data having a common queue identifier on a memory system will result. In other words, in various embodiments, data on the memory system can be sorted conditioned on a queue identifier (e.g., SQID), thereby protecting data sequentially provided by a submission queue. Sequential storage (e.g., sorting) of data having a common queue identifier can result in a reduction of write amplification, an improvement in the performance of the memory system, an improvement in performance per power unit (e.g., watt), or a combination thereof.

[0021] Data access requests and command requests are used interchangeably herein. As used herein, a data access request / command request can include a data access command to a memory system. Thus, a write request can include a write command to a memory system, and a read request can include a read command to a memory system.

[0022] As used herein, a superblock of a memory device (e.g., a memory system) includes a plurality of blocks (e.g., a set or group) of the memory device. For example, a superblock of a NAND-type memory device can include a plurality of blocks that share the same location in each plane of each NAND-type memory die of the NAND-type memory device.

[0023] Some examples of processing write requests on a memory system based on a queue identifier associated with a write request as described herein are disclosed herein.

[0024] FIG. 1 shows an exemplary computing system 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 can include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

[0025] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, secure digital (SD) cards, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an aircraft, a drone, a train, an automobile, or other means of transportation), an Internet of Things (IoT) device, an embedded computer (e.g., those included in vehicles, industrial equipment, or networked commercial devices), or such a computing device that includes memory and processing devices.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 shows an example of a host system 120 coupled to one memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to connections between components, whether wired or wireless, including electrical, optical, magnetic, and other connections, which may be indirect or direct communication connections (e.g., without intervening components).

[0028] The host system 120 may include a processor chipset and a software stack run by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110.

[0029] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, SATA interfaces, Peripheral Component Interconnect Express (PCIe) interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory buses, DIMM interfaces (e.g., DIMM socket interfaces that support DDR), Open NAND Flash Interface (ONFI), DDR, Low Power Double Data Rate (LPDDR), or any other interfaces. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130). The physical host interface can provide an interface for passing control signals, address signals, data signals, and other signals between the memory subsystem 110 and the host system 120. Figure 1 shows a memory subsystem 110 as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0030] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, a random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and write-in-place memory such as three-dimensional (3D) crosspoint memory devices, which are crosspoint arrays of non-volatile memory cells. A crosspoint array of non-volatile memory can work in conjunction with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, which allow the non-volatile memory cells to be programmed without prior erasure of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional (2D) NAND and three-dimensional NAND.

[0032] Each of the memory devices 130 may contain one or more arrays of memory cells. For example, one type of memory cell, such as SLC, can store one bit per cell. Other types of memory cells, such as MLC, TLC, QLC, and pentalevel cells (PLC), can store multiple or partial bits per cell. In some embodiments, each of the memory devices 130 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may contain SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory device 130 can be grouped as pages, which may refer to logical units of the memory device used to store data. In some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0033] As used herein, a block containing SLC may be called an SLC block, a block containing MLC may be called an MLC block, a block containing TLC may be called a TLC block, and a block containing QLC may be called a QLC block.

[0034] While non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D crosspoint arrays of non-volatile memory cells are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selection memory, other chalcogenide-based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random-access memory (FeRAM), magnetic random-access memory (MRAM), spin-transfer magnetization reversal (STT) MRAM, conductive bridge RAM (CBRAM), resistive random-access memory (RRAM), oxide-based RRAM (OxRAM), negative OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data in the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or separate components, buffer memory, or a combination thereof. The hardware may include digital circuits with dedicated (i.e., hardcoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other suitable processor.

[0036] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing routines that control the operation of the memory subsystem 110, including processing various processes, operations, logical flows, and communications between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, the local memory 119 may include memory registers for storing memory pointers, fetched data, and so on. The local memory 119 may also include ROM for storing microcode. The exemplary memory subsystem 110 in Figure 1 is shown to include a memory subsystem controller 115, but in other embodiments of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands, requests, or operations from the host system 120 and translate these commands, requests, or operations into instructions or appropriate commands to achieve desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may also perform other operations such as wear leveling operations, garbage collection operations, error detection and ECC operations, encryption operations, caching operations, and address translation between logical addresses (e.g., LBA, namespace) and physical memory addresses (e.g., physical block addresses), which are associated with memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions for accessing memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that receives addresses from the memory subsystem controller 115 and decodes the addresses to access the memory device 130.

[0040] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Each of the memory devices 130 and 140 includes memory dies 150 and 160. In some embodiments, each of the memory devices 130 and 140 represents a memory device including a printed circuit board, on which the respective memory dies 150 and 160 are soldered.

[0042] The memory subsystem controller 115 includes a queue identifier-based write processor 113, which enables or facilitates the memory subsystem controller 115 to process write requests based on the queue identifier associated with the write request, as described herein. In some embodiments, the queue identifier-based write processor 113 may be part of a larger queue identifier-based request processor (not shown). Alternatively, part or all of the queue identifier-based write processor 113 may be included by a local media controller 135, which enables or facilitates the local media controller 135 to process write requests based on the queue identifier associated with the write request, as described herein.

[0043] Figure 2 shows exemplary architectures 200 of the host system 120 and memory subsystem 110 of Figure 1, according to some embodiments of the present disclosure. In exemplary architecture 200, the host system 120 includes a plurality of hardware processor cores 214, a software application 210 running on the plurality of hardware processor cores 214, and a kernel 212 (e.g., of an operating system) running on the plurality of hardware processor cores 214. Furthermore, in exemplary architecture 200, the memory subsystem 110 includes a data stream identifier 220 (e.g., part of a queue identifier-based request processor) and a plurality of queue pairs 222, the plurality of queue pairs 222 including queue pairs associated with queue identifier 1 (QID-1) to queue identifier N (QID-N). The queue pair associated with queue identifier 1 (QID-1) includes submission queue 1 (SQ-1) and completion queue (CQ-1); the queue pair associated with queue identifier 2 (QID-2) includes submission queue 2 (SQ-2) and completion queue (CQ-2); the queue pair associated with queue identifier 3 (QID-3) includes submission queue 3 (SQ-3) and completion queue (CQ-3); the queue pair associated with queue identifier 4 (QID-4) includes submission queue 4 (SQ-4) and completion queue (CQ-4), and so on. During operation, the software application 210 can trigger the kernel 212 to execute processes (which have process identifiers (PROCESS_ID)), one or more of these processes may include generating sequential data access requests. The kernel 212 can execute at least one of the processes by dividing the process into multiple threads (each having a thread identifier (THREAD_ID)) executed by multiple hardware processor cores 214.Each thread can be assigned to run on one of several hardware processor cores 214 (for example, according to core affinity), and the execution of a thread by a given hardware processor core can cause the given hardware processor core to generate and issue one or more data access requests to the memory subsystem 110, each of which generates / issues a queue identifier (QID) of the given hardware processor core.

[0044] Since data access requests are generated and issued by multiple hardware processor cores 214, data access requests from each hardware processor core can be interleaved with requests generated and issued by one or more other hardware processor cores. Therefore, data access requests received by the memory subsystem 110 may appear random or pseudo-random to the memory subsystem 110.

[0045] Upon receiving a given data access request, the memory subsystem 110 can use the data stream identifier 220 to identify a given queue identifier for the given data access request, and the memory subsystem 110 can ensure that the given data access request is stored in the submission queue of the queue pair (of multiple queue pairs 222) corresponding to (e.g., matching) the given queue identifier (e.g., stored in an entry added to the submission queue). If the given data access request is being processed (e.g., executed) by the memory subsystem 110, the result of the given data access request can be stored in the completion queue of the queue pair (of multiple queue pairs 222) corresponding to (e.g., matching) the given queue identifier (e.g., stored in an entry added to the completion queue), from which the host system 120 can retrieve (e.g., collect) the result.

[0046] Figure 3 shows an example of filtering requests for an exemplary request data stream 300 according to several embodiments of the present disclosure. Specifically, the request data stream 300 includes a random or pseudo-random stream of requests (e.g., write requests and read requests), each having a corresponding queue identifier (e.g., SQ1, SQ4, SQ3, SQ8, SQ0, and SQ31) associated with a submission queue of the memory system. According to some embodiments, the memory system (e.g., a memory subsystem 110) includes a submission queue identifier (SQID) filter 310 (e.g., part of a queue identifier-based write processor 113) which can be configured to filter / decompose the request data stream 300 into sequential write streams 320, each of which has a common queue identifier and represents a collection of write requests that can be consolidated into one or more larger write requests. Depending on the embodiment, each of the sequential write streams 320 can be written to (e.g., mapped to) a set of blocks of memory devices (e.g., 130, 140) of the memory system (e.g., memory subsystem 110) using one or more different sequential data configurations (e.g., organizational configurations). For example, one of the sequential write streams 320 can be written to the NAND memory devices of the memory system in stripe units (e.g., page stripes of superblocks), superblock units, physical-to-logic (P2L) layer units, or 1 / N deck units (e.g., half-block units).

[0047] Figure 4 shows an exemplary garbage collection operation 400 of a superblock according to several embodiments of the present disclosure. Based on executing one or more write requests from the requested data stream 300 (each including a write request having a queue identifier), data (e.g., user data, host data) can be written to one or more pages (e.g., pages 412-1, 412-2, 412-3, 412-4) of one or more blocks (e.g., blocks 410-1, 410-2, 410-3, 410-4) of the superblocks 420-1, 420-2, 420-X, 420-Y. In Figure 4, pages 412-1, 412-2, 412-3, 412-4 show an example of a page stripe in superblock 420-1, and the page stripe spans blocks 410-1, 410-2, 410-3, 410-4 of superblock 420-1. Blank pages, such as page 414, represent empty pages or pages containing invalid data (e.g., marked for subsequent deletion). In some embodiments, write requests from a request data stream (e.g., 300) are filtered based on a queue identifier (e.g., SQID) and the write data stream is filtered / decomposed into one or more sequential write streams (e.g., 302), each of which represents a set of write requests having a common queue identifier. In various embodiments, each sequential write stream can be written to a memory device (e.g., a NAND memory device) in a sequential data configuration such as, for example, page stripe units, superblock units, or P2L granularity units. An exemplary page stripe unit write of a sequential write stream is shown by page stripe 424 of superblock 420-2.

[0048] According to various embodiments, when a single write request is processed (e.g., executed) by a memory system (e.g., memory subsystem 110), the data is written to one or more blocks of the memory device, and the queue identifier for the single write is also stored in the memory device in association with the written data. For example, by executing a single write request associated with the queue identifier of SQ4 (e.g., SQID), data is written to block 410-2 (of superblock 420-1), and the queue identifier of SQ4 is also stored in association with the data written to block 410-2. Similarly, by executing a single write request associated with the queue identifier of SQ8, data is written to block 410-3 (of superblock 1), and the queue identifier of SQ8 is also stored in association with the data written to block 410-3. In some embodiments, the queue identifier for a single write request may be included in the written data, stored in the metadata of the written data, or stored in a separate area of ​​the memory device. When garbage collection is initiated (e.g., invoked) for one or more superblocks, a list of memory units (e.g., pages or blocks) that store valid data is determined for each of the one or more superblocks, based on a queue identifier applicable to that superblock (e.g., each queue identifier associated with at least one block within that superblock). From the resulting list of memory units, a memory system in one embodiment can determine (e.g., identify) the longest list of memory units with a common identifier (e.g., the list with the largest number of memory units), and can initiate garbage collection on the memory units in the longest list, while valid data from those (source) memory units is migrated to other fresh / available (destination) memory units.This is illustrated, for example, in Figure 4, in which case the memory system can determine that the longest list of pages containing valid data is the list of pages associated with the queue identifier of SQ8 (e.g., pages 412-43 of superblock 420-1 and page 430 of superblock 420-Y), and can perform garbage collection on the pages in that list, thereby migrating valid data from the pages of superblocks 420-1 and 420-Y associated with the queue identifier of SQ8 to the page stripe 424 of superblock 420-2.

[0049] To determine the longest list of memory units, the memory system can rank the lists based on the total number of memory units in each list. Furthermore, if a destination memory unit is part of a set of (destination) memory units (such as the memory units in the superblock) and the set of destination memory units is not full, the next longest list of memory units can be determined (e.g., identified) from one or more lists of memory units, and the memory system can begin performing garbage collection on the memory units in the next longest list of memory units. In some embodiments, the determined (e.g., identified) next longest list of memory units is a list containing enough memory units to completely fill the memory unit that remains empty in the set of destination memory units.

[0050] For example, in Figure 4, even after migrating valid data from pages associated with SQ8, superblock 420-2 did not become full. As a result, the memory system can determine that the next longest list of pages that can fit into the remaining pages (e.g., page stripe) of superblock 420-2 is the list of pages associated with the queue identifier of SQ3 (e.g., page 440 of superblock 420-1 and page 450 of superblock 420-Y) (in contrast to the list of pages associated with SQ0, which does not fit into the remaining pages). The memory system can then perform garbage collection on the next longest list of pages, thereby migrating valid data from pages in superblocks 420-1 and 420-Y associated with the queue identifier of SQ3 to page stripe 426 of superblock 420-2. In this case as well, even if valid data is migrated from the pages associated with SQ3, the superblock 420-2 will not become full. Therefore, the memory system can determine that the next longest list of pages that can fit into the remaining pages of the superblock 420-2 (e.g., the page stripe) is the list of pages associated with the queue identifier of SQ0 (e.g., page 460 of the superblock 420-Y), and can perform garbage collection on the pages of this next longest list. This allows valid data from the pages of the superblock 420-Y associated with the queue identifier of SQ0 to be migrated to the page stripe 428 of the superblock 420-2.

[0051] Figures 5 and 6 are flowcharts of exemplary methods 500, 600 for processing write requests on a memory system based on a queue identifier associated with the write request, according to some embodiments of the present disclosure. Both methods 500, 600 can be carried out by processing logic that may include hardware (e.g., processing devices, circuits, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions actuated or executed by the processing device), or a combination thereof. In some embodiments, at least one of methods 500, 600 is executed by the memory subsystem controller 115 in Figure 1, based on a queue identifier-based write processor 113. Additionally, or alternatively, in some embodiments, at least one of methods 500, 600 is executed at least partially by the local media controller 135 of the memory device 130 in Figure 1. Although shown in a specific sequence or order, the order of processes can be modified unless otherwise specified. Therefore, the shown embodiments should be understood as examples only, the shown processes can be executed in a different order, and some processes can be executed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are used in all embodiments. Other process flows are also possible.

[0052] Referring now to Method 500 in Figure 5, Method 500 illustrates an example of delaying a write request based on a queue identifier associated with the write request, according to several embodiments.

[0053] In operation 502, a processing device (e.g., the processor 117 of the memory subsystem controller 115) receives a set of command requests from the host system (e.g., 120), and each individual command request in the set of command requests is stored in the individual submission queue of the memory system (e.g., the corresponding memory subsystem 110) associated with the individual queue identifier of the individual command request. In some embodiments, the command requests received from the host system include a queue identifier (e.g., including a QID tag) associated with the command request (e.g., based on the submission queue on the host side from which the command request originated).

[0054] Finally, in operation 504, the processing device (e.g., processor 117) scans one or more submission queues of the memory system (e.g., memory subsystem 110) for command requests to be executed (e.g., scans each submission queue). While scanning for a given submission, the processing device can determine (e.g., detect) whether the next command request taken from (e.g., captured) from a given submission queue is a write request or a read request. In doing so, the processing device can scan one or more commands arriving from various submission queues for the purpose of integration and processing. The scanning in operation 504 is configured so that any read requests found from one or more submission queues are to be processed immediately in operation 520 (e.g., executed, command merged, etc.), and any write requests found from one or more submission queues are to be delayed in operation 522 (e.g., executed, command merged, etc. are held for delayed processing), and designated as delayed write requests. During operation 520, the processing device may ensure that detected read requests (e.g., those associated with read streams) are processed for immediate or integrated execution. In some embodiments, delaying the execution processing of any write request (e.g., execution, command merging, etc.) and designating it as a delayed write request includes the processing device identifying the selection queue identifier of a selected write request detected from one or more submission queues, and adding the selected write request to a list of delayed (e.g., pending) write requests, the list of which is associated with the selection queue identifier of the selected write request.

[0055] During operation 506, the processing device (e.g., processor 117) determines whether a set of conditions for executing a delayed write request associated with a single queue identifier has been met. In some embodiments, determining whether a set of conditions for executing a delayed write request associated with a single queue identifier has been met includes the processing device determining whether a monitored time (e.g., a timer) associated with a list of delayed write requests associated with a single queue identifier has expired. Alternatively, in some embodiments, determining whether a set of conditions for executing a delayed write request associated with a single queue identifier has been met includes the processing device determining whether the number of write requests in the list of delayed write requests associated with a single queue identifier has exceeded a threshold number of write requests.

[0056] If it is determined at decision point 508 that the set of conditions is met, method 500 proceeds to operation 510. In some embodiments, if it is determined that the set of conditions is not met, method 500 may return to operation 504 when the next scan of the submission queue is performed.

[0057] In operation 510, the processing device (e.g., processor 117) triggers the execution of at least some (e.g., all) of the delayed write requests associated with a single queue identifier. In some embodiments, triggering the execution of at least some of the delayed write requests associated with a single queue identifier includes the processing device triggering the execution of at least one write request (e.g., all write requests) in a list of delayed write requests. In some embodiments, the processing device triggers the execution of the write requests (e.g., delayed write requests from the list) such that the queue identifier associated with the write requests is stored in the memory device (e.g., 130, 140) in association with the data written by the write requests to a set of blocks in the memory device. Including queue identifiers in this manner enables or facilitates garbage collection based on queue identifiers, as described in the various embodiments herein. Furthermore, if the memory devices (e.g., 130, 140) contain multiple superblocks, each containing multiple blocks, the processing device can trigger the execution of multiple write requests (e.g., from a list of delayed write requests) so that data is written to one or more superblocks by multiple delayed write requests in a sequential configuration (e.g., organizational configuration), such as in page stripe units, superblock units, physical-to-logic (P2L) layer units, or 1 / N deck units.

[0058] Finally, in operation 512, the processing device (e.g., processor 117) performs garbage collection on one or more blocks (e.g., superblocks) of the memory devices (e.g., 130, 140) based on a queue identifier (e.g., stored in association with data written to one or more blocks during operation 510). In this way, the processing device can perform garbage collection conditionally on the queue identifier. Figure 6 shows an example of how garbage collection may be performed during operation 512.

[0059] Referring here to Method 600 in Figure 6, Method 600 illustrates an example of performing garbage collection based on a queue identifier of a write request, according to several embodiments. In operation 602, a processing device (e.g., a processor 117 of the memory subsystem controller 115) triggers the execution of a write request (e.g., a delayed write request from a list) such that the queue identifier associated with the write request is stored in the memory device (e.g., 130, 140) in association with the data written to the set of blocks by the write request. In some embodiments, the queue identifier can be stored in the memory device in association with the data written to the set of blocks by including the queue identifier in metadata associated with the data written to the set of blocks, or by storing the queue identifier in a separate (e.g., reserved) area of ​​the memory device.

[0060] In operation 604, the processing device (e.g., processor 117) performs operations on one or more selected blocks in memory devices (e.g., 130, 140) based on queue identifiers stored in the memory devices in association with one or more selected blocks. During operation 604, the processing device (e.g., processor 117) performs one or more of operations 620, 622, 624, 626, and 628. In operation 620, the processing device determines (e.g., generates) one or more lists of memory units (e.g., blocks or pages) from one or more selected blocks, each list of which is associated with a different queue identifier and contains memory units (e.g., pages or blocks) that store valid data associated with the different queue identifier. Then, in operation 622, the processing device (e.g., processor 117) determines the longest list of memory units (e.g., blocks or pages) from the one or more lists of memory units determined in operation 620. Next, in operation 624, the processing device (e.g., processor 117) performs garbage collection operations on at least a portion (e.g., all) of the longest list of memory units. In some embodiments, valid data from the memory units in the longest list is migrated to a set of destination memory units (e.g., pages of the destination superblock) until the set of destination memory units is full, or until there are no more memory units left from the longest list from which valid data is being migrated. If, in operation 626, the processing device (e.g., processor 117) determines that the set of destination blocks (e.g., destination superblocks) is not full, method 600 proceeds to operation 628, where the next longest list of memory units is determined (e.g., identified), and method 600 returns to operation 624. However, if the processing device (e.g., processor 117) determines that the set of destination memory units (e.g., pages of the destination superblock) is full, method 600 may proceed to operation 606, where garbage collection for one or more selected blocks is terminated.

[0061] Figure 7 shows an exemplary machine of the form of computer system 700, in which a set of instructions can be executed to cause the machine to perform one or more of the methods described herein. In some embodiments, computer system 700 may correspond to, or be used to perform, an operation described herein, a host system (e.g., host system 120 in Figure 1) which is coupled to or utilizes a memory subsystem (e.g., memory subsystem 110 in Figure 1). In alternative embodiments, the machine may be connected to (e.g., network-connected to) other machines in a local area network (LAN), intranet, extranet, and / or the internet. The machine may function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0062] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify the actions to be taken by that machine. Furthermore, although a single machine is shown, the term “machine” shall also be interpreted as including any set of machines that individually or collectively execute a set (or set) of instructions to perform any one or more of the methods described herein.

[0063] An exemplary computer system 700 includes processing devices 702, main memory 704 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM)), static memory 706 (e.g., flash memory, static random access memory (SRAM)), and data storage devices 718, all of which communicate with each other via a bus 730.

[0064] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the same. More specifically, the processing device 702 may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processing device 702 may also be one or more dedicated processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the same. The processing device 702 is configured to execute instructions 726 for performing the operations and steps described herein. The computer system 700 may further include a network interface device 708 for communication over the network 720.

[0065] The data storage device 718 may include a machine-readable storage medium 724 (also known as a computer-readable medium) that stores one or more sets of instructions 726 or software that embody any one or more of the methods or functions described herein. The instructions 726 may also reside entirely or at least partially in the main memory 704 and / or the processing device 702 during their execution by the computer system 700, and the main memory 704 and the processing device 702 also constitute the machine-readable storage medium. The machine-readable storage medium 724, the data storage device 718, and / or the main memory 704 may correspond to the memory subsystem 110 in Figure 1.

[0066] In one embodiment, instruction 726 includes an instruction that implements a function corresponding to processing a write request based on a queue identifier associated with the write request, as described herein (e.g., the queue identifier-based write processor 113 in Figure 1). Although the machine-readable storage medium 724 is shown to be a single medium in exemplary embodiments, the term “machine-readable storage medium” should be interpreted as including a single or more mediums that store one or more sets of instructions. The term “machine-readable storage medium” should also be interpreted as including any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine to perform one or more of the methods of the present disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0067] Some of the preceding detailed explanations are presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. Such descriptions and representations of algorithms are methods used by those skilled in the art in data processing techniques to most effectively convey the essence of their operation. An algorithm is considered here, and generally, to be a self-consistent sequence of operations leading to a desired result. These operations require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has sometimes been found convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0068] However, it should be recognized that all these and similar terms should correspond to appropriate physical quantities and are merely convenient designations applied to those quantities. This disclosure may refer to the operation and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memory of a computer system and converts it into other data similarly represented as physical quantities in the memory or registers of a computer system or such information storage system.

[0069] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be configured specifically for a particular purpose of use, or may include a general-purpose computer that is selectively started or reconfigured by a computer program stored in the computer. Such a computer program may be stored in any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus, but is not limited to these.

[0070] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be programmed according to the teachings herein, or it may be advantageous to construct a more dedicated device for performing the method. The various structures of these systems will appear as described below. Furthermore, this disclosure does not describe any particular programming language. It should be understood that various programming languages ​​can be used to perform the teachings of this disclosure as described herein.

[0071] This disclosure may be presented as a computer program product or software that includes a machine-readable medium (e.g., non-temporary machine-readable medium) containing instructions that can be used to program a computer system (or other electronic device) to perform a process in accordance with this disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer)-readable storage media such as ROM, RAM, magnetic disk storage media, optical storage media, and flash memory components.

[0072] In the above-mentioned specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments. It is evident that various modifications can be made without departing from the broader intent and scope of the embodiments of the disclosure set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. It is a system, A plurality of submission queues, each of the plurality of submission queues is associated with a corresponding queue identifier, and each of the queue identifiers is associated with at least one hardware processor core of the host system, Memory devices and, A processing device operably coupled with the aforementioned memory device, Receiving a set of command requests from the host system, wherein each individual command request in the set of command requests includes an individual queue identifier, and is stored in an individual submission queue of a plurality of submission queues associated with the individual queue identifier, The process involves scanning one or more of the multiple submission queues for the command request to be executed, wherein the scan is configured to delay the execution of any write request detected from the one or more submission queues and to designate it as a delayed write request. Determining whether a set of conditions for executing a delayed write request associated with a single queue identifier is met, In response to determining that the set of conditions for executing the delayed write request associated with the single queue identifier is met, the execution of at least a portion of the delayed write requests associated with the single queue identifier is triggered. The processing device is configured to perform operations including, The system including the above.

2. Delaying the execution process of any write request detected from the one or more submission queues and designating it as a delayed write request means that Identifying the selection queue identifier of a selection write request detected from one or more submission queues, The system according to claim 1, comprising adding the selected write request to a list of delayed write requests, the list being associated with the selected queue identifier.

3. Determining whether the set of conditions for executing a delayed write request associated with the single queue identifier is met means The system according to claim 2, which includes determining whether a monitored time associated with a list of delayed write requests associated with a single queue identifier has ended, wherein causing the execution of at least some of the delayed write requests associated with the single queue identifier includes causing the execution of at least one write request in the list of delayed write requests.

4. Determining whether the set of conditions for executing a delayed write request associated with the single queue identifier is met means The system according to claim 2, which includes determining whether the number of write requests in the list of delayed write requests associated with the single queue identifier exceeds a threshold number of write requests, wherein causing the execution of at least some of the delayed write requests associated with the single queue identifier includes causing the execution of at least one write request in the list of delayed write requests.

5. The memory device includes a plurality of superblocks, each of which includes a plurality of blocks, and the execution of at least a portion of the delayed write requests associated with the single queue identifier is, The system according to claim 1, comprising triggering the execution of a plurality of delayed write requests associated with a single queue identifier such that data is written to one or more of the superblocks by the plurality of delayed write requests on a page stripe basis.

6. The memory device includes a plurality of superblocks, each of which includes a plurality of blocks, and the execution of at least a portion of the delayed write requests associated with the single queue identifier is, The system according to claim 1, comprising triggering the execution of a plurality of delayed write requests associated with a single queue identifier such that data is written to one or more of the superblocks by the plurality of delayed write requests on a superblock basis.

7. The memory device includes a plurality of superblocks, each of which includes a plurality of blocks, and the execution of at least a portion of the delayed write requests associated with the single queue identifier is, The system according to claim 1, comprising triggering the execution of a plurality of delayed write requests associated with a single queue identifier such that data is written to one or more of the superblocks by the plurality of delayed write requests in units of 1 / N of a deck.

8. The memory device includes a plurality of superblocks, each of which includes a plurality of blocks, and the execution of at least a portion of the delayed write requests associated with the single queue identifier is, The system according to claim 1, comprising triggering the execution of a plurality of delayed write requests associated with a single queue identifier such that data is written to one or more of the superblocks by the plurality of delayed write requests on a physical versus logical layer basis.

9. The execution of at least a portion of the delayed write requests associated with the single queue identifier is, The execution of a single delayed write request is included such that a single queue identifier associated with the single delayed write request is stored in the memory device in association with the data written to the set of blocks in the memory device by the single delayed write request, The aforementioned operation is, The system according to claim 1, comprising performing garbage collection on the one or more selected blocks in the memory device based on a queue identifier stored in the memory device in association with one or more selected blocks.

10. The system according to claim 9, wherein the single queue identifier is stored in the memory device in association with the data written to the set of blocks by including the single queue identifier in the metadata associated with the data written to the set of blocks.

11. Performing garbage collection on one or more selected blocks based on a queue identifier stored in the memory device in association with one or more selected blocks is: Determining one or more lists of memory units from the one or more selected blocks, wherein each list of the one or more lists is associated with a different queue identifier and includes a memory unit that stores valid data associated with the different queue identifier, The longest list of memory units is determined from one or more lists of the aforementioned memory units. The system according to claim 9, comprising performing garbage collection operations on at least a portion of the longest list of the memory units.

12. The memory device includes a plurality of superblocks, each of which includes a plurality of blocks, and the execution of at least a portion of the delayed write requests associated with the single queue identifier is, The execution of a single delayed write request is included such that a single queue identifier associated with the single delayed write request is stored in the memory device in association with the data written to the set of blocks in the memory device by the single delayed write request, The aforementioned operation is, This includes performing garbage collection on one or more superblocks of the memory device, and performing garbage collection on one or more superblocks is Determining one or more lists of memory units from the one or more superblocks, wherein each list of the one or more lists is associated with a different queue identifier and includes memory units of valid data associated with the different queue identifier, The longest list of memory units is determined from one or more lists of the aforementioned memory units. The system according to claim 1, further comprising performing a garbage collection operation on at least a portion of the longest list of the memory unit so that data from the blocks of the longest list are migrated to a destination superblock.

13. The longest list is a first longest list, and performing garbage collection on one or more superblocks is: After migrating data from all blocks in the first longest list to the destination superblock, in response to determining that the destination superblock is not full, Determining the second longest list of memory units from one or more of the aforementioned memory units, The system according to claim 12, comprising performing the garbage collection operation on at least a portion of the second longest list of memory units such that data from blocks in the second longest list is migrated to the destination superblock until the destination superblock is full or until there are no more memory units to migrate.

14. The system according to claim 12, wherein the scanning is configured to initiate immediate processing for any read requests detected from the one or more submission queues.

15. A non-temporary machine-readable storage medium, which, when executed by a processing device of the memory subsystem, includes instructions that cause the processing device to perform an operation, wherein the operation is Receiving a set of command requests from a host system, wherein the memory subsystem includes a plurality of submission queues, each of the plurality of submission queues is associated with a corresponding queue identifier, each of the queue identifiers is associated with at least one hardware processor core of the host system, and each individual command request in the set of command requests includes an individual queue identifier and is stored in an individual submission queue of the plurality of submission queues associated with the individual queue identifier, The process involves scanning one or more of the multiple submission queues for the command request to be executed, wherein the scan is configured to delay the execution of any write request detected from the one or more submission queues and to designate it as a delayed write request. Determining whether a set of conditions for executing a delayed write request associated with a single queue identifier is met, The at least one non-temporary machine-readable storage medium, which includes causing the execution of at least a portion of the delayed write requests associated with the single queue identifier in response to determining that the set of conditions for executing the delayed write requests associated with the single queue identifier are met.

16. Delaying the execution process of any write request detected from the one or more submission queues and designating it as a delayed write request means that Identifying the selection queue identifier of a selection write request detected from one or more submission queues, The addition of the selected write request to a list of delayed write requests, the list being associated with the selected queue identifier, the addition of at least one non-temporary machine-readable storage medium according to claim 15.

17. Determining whether the set of conditions for executing a delayed write request associated with the single queue identifier is met means The at least one non-temporary machine-readable storage medium according to claim 16, comprising determining whether a monitored time associated with a list of delayed write requests associated with a single queue identifier has ended, wherein causing the execution of at least some of the delayed write requests associated with the single queue identifier includes causing the execution of at least one write request in the list of delayed write requests.

18. Determining whether the set of conditions for executing a delayed write request associated with the single queue identifier is met means The at least one non-temporary machine-readable storage medium according to claim 16, comprising determining whether the number of write requests in the list of delayed write requests associated with the single queue identifier exceeds a threshold number of write requests, wherein causing the execution of at least some of the delayed write requests associated with the single queue identifier includes causing the execution of at least one write request in the list of delayed write requests.

19. The execution of at least a portion of the delayed write requests associated with the single queue identifier is, The execution of a single delayed write request is triggered such that a single queue identifier associated with a single delayed write request is stored in the memory device in association with the data written to the set of blocks in the memory device by the single delayed write request, The at least one non-temporary machine-readable storage medium according to claim 15, comprising performing garbage collection on the one or more selected blocks in the memory device based on a queue identifier stored in the memory device in association with one or more selected blocks.

20. It is a method, The receiving of a set of command requests from a host system to a memory subsystem, wherein the memory subsystem comprises a plurality of submissions, each of the plurality of submission queues is associated with a corresponding queue identifier, each of the queue identifiers is associated with at least one hardware processor core of the host system, and each individual command request in the set of command requests comprises an individual queue identifier and is stored in an individual submission queue of the plurality of submission queues associated with the individual queue identifier, The process involves scanning one or more of the multiple submission queues with respect to the command request to be executed, wherein the scanning is configured to delay the execution of any write request detected from the one or more submission queues and to designate it as a delayed write request. The processing device determines that a set of conditions for executing a delayed write request associated with a single queue identifier is met, The method, comprising: determining that the set of conditions for executing the delayed write requests associated with the single queue identifier are met, causing the processing device to execute at least a portion of the delayed write requests associated with the single queue identifier.

Images