Table-based write request status tracking for Replay Protection Memory Blocks (RPMBs).

Abstract

This disclosure provides a system, method, and device for a memory system that supports table-based write request status tracking for replay-protected memory blocks (RPMBs). In a first aspect, a method for accessing data in a flash memory system includes a host memory controller configured to perform operations including: sending a first write request to the memory system to write data to the RPMB portion of a memory module in the memory system; sending a first read request to the memory system to read the result of the first write request from a table of the RPMB portion of a memory module in the memory system; and receiving instructions from the memory system regarding the result of the first write request. Other aspects and features are also claimed and described.

Description

Technical Field

[0001]

[0001] Aspects of the present disclosure generally relate to apparatus and methods for controlling a memory device. Some aspects may more particularly relate to apparatus and methods for controlling operations for tracking the status of requests for writing data to a memory storage device.

Background Art

[0002]

[0002] As the value and use of information continue to increase, individuals and businesses are seeking additional ways to process and store information. In addition, the use of information in various locations and the desire for information portability are increasing. For this reason, users are increasingly turning to the use of portable electronic devices such as mobile phones, digital cameras, laptop computers, etc. Portable electronic devices generally employ a memory system that uses a memory device to store data. The memory system can be used as the main memory or auxiliary memory of a portable electronic device.

[0003]

[0003] The memory device of a memory system can include one type of storage or a combination of multiple types of storage. For example, a magnetic-based memory system such as hard disk drives (HDDs) stores data by encoding the data as a combination of small magnets. As another example, an optical-based memory system such as digital versatile discs (DVDs) and Blu-ray media stores data by encoding the data as physical bits that cause different reflections when irradiated by a light source. As a further example, an electronic memory device stores data as a collection of electrons that can be detected through voltage and / or current measurements. [[ID=仃]]

[0004]

[0004] Electronic memory devices can be advantageous in certain systems because they allow for quick access to data and consume less power. Examples of electronic memory devices with these advantages include universal serial bus (USB) memory devices (sometimes called "memory sticks"), memory cards (such as those used in some cameras and game systems), and solid state drives (SSDs) (such as those used in laptop computers). NAND flash memory is a type of memory device that can be used in electronic memory devices. NAND flash memory is manufactured as a memory card or flash disk. Examples of memory cards include compact flash (CF) cards, multimedia cards (eMMCs), smart media (SM) cards, and secure digital (SD) cards.

[0005]

[0005] The memory system may be integrated with or otherwise connected to a host device, such as an electronic device. For example, the memory system may be integrated with a host device in a system on a chip (SoC). One specific example is a flash memory system, which may be a universal flash storage (UFS) memory system, which may be integrated with an electronic device such as an access point (AP), station (STA), user equipment (UE), base station, modem, camera, automobile, or other system.

[0006]

[0006] One standard for the organization and operation of electronic memory devices is the Universal Flash Storage (UFS) standard. The UFS standard was introduced as a successor to the eMMC (embedded MultiMediaCard) standard to bring higher performance and lower power consumption for mobile and other embedded devices. UFS provides support for a wide range of features such as multi-lane configuration, command queuing, and power-saving modes, enabling high data transfer rates, low latency, and long battery life. The UFS standard specifies many parameters for structuring UFS-compliant memory devices, reading data from them, and writing data to them. For example, UFS-compliant devices may include digital cameras, mobile phones, consumer electronic devices, and other devices with internal memory capacity. UFS-compliant memory may include memory embedded in electronic devices and removable memory cards, and UFS memory devices may implement NAND flash memory. [Overview of the project]

[0007]

[0007] The following summarizes several aspects of the Disclosure in order to provide a basic understanding of the technology discussed. This summary is not intended to be a comprehensive overview of all conceivable features of the Disclosure, nor to identify any major or significant elements of all aspects of the Disclosure, nor to specify the scope of any or all aspects of the Disclosure. Its sole purpose is to present in summary form some concepts of one or more aspects of the Disclosure as an introduction to the more detailed descriptions to be presented later.

[0008]

[0008] Data stored in electronic memory may be used to protect electronic devices, protect content on electronic devices, or maintain user confidentiality. For example, memory may store information such as encryption keys, digital rights management (DRM) certificates that authorize access to specific copyrighted works, or similar. Protecting data such as these keys or certificates is important to protect users and / or information. A replay-protected memory block (RPMB) portion of a memory module may be used to store such information in a secure manner. The success of a write request to write information to the RPMB portion of memory may be tracked using bits in a result register associated with the RPMB. However, such success information can be inaccurate and may produce false positives or negatives when requesting the success status of a write operation. For example, inaccurate success information in the result register may result from overwriting the success information for a first write operation with success information from a second subsequent write operation mistakenly originating from another source, e.g., another virtual machine, or a malicious source. That is, if a first write request is received and the requested write is successfully executed, the result register may be set to indicate that the first write request was successful. However, if a second write request is received from another source, for example from another virtual machine or a malicious source, before the success information for the first write operation is read from the result register, and the second write request fails, the register may be overwritten to indicate that the write request failed. Subsequently, if the host device reads the result register to obtain the status of the first write request, it may receive an indication that the write request failed, even if the first write request was successful. Similarly, if the first write request fails and a second write request received before the success information for the first write request is read from the result register is successful, the indication that the first write request failed may be overwritten in the result status register with an indication of success.Subsequently, if the host device reads the result register to obtain the status of the first write request, it may receive a false positive, which it may interpret as indicating that the first write request was successful. Such false positives and negatives can lead to erroneous reads from the RPMB. For example, if the host device receives a false positive and interprets it as indicating that the write request was successful, even though the write request actually failed, the host device may read information from the RPMB assuming that its contents were updated in accordance with the write request. Therefore, based on having read a false positive from the result register, the host device may read obsolete data from the RPMB that was not updated in accordance with the failed write request.

[0009]

[0009] Aspects of the present disclosure provide a technique for storing result information for a request to write information to the RPMB portion of memory in a table rather than in a single register bit. For example, when a memory device receives a write request to write information to the RPMB portion of the memory device, an indication of success or failure of the write request may be stored in a table in association with the indication of the write request, and when a request to read the result of the write request is received, an indication of success or failure of the write request may be provided accordingly.

[0010]

[0010] In one aspect of the present disclosure, the memory device includes a memory controller, which is coupled to a memory module through a channel and configured to access data stored in the memory module through the channel, and is coupled to a host device through a memory interface and configured to communicate with the host device through the memory interface. The memory controller of the memory device may be configured to perform operations including receiving a first write request from the host device through the memory interface to write data to a replay-protected memory block (RPMB) portion of the memory module, determining the result of the first write request, and storing instructions for the result of the first write request, associated with the instructions for the first write request, in a table of the RPMB portion of the memory module. In another aspect of the present disclosure, a method for a processor to perform these operations by executing instructions stored in memory coupled to the processor is also disclosed. In an additional aspect of the present disclosure, a non-temporary computer-readable medium stores instructions, which, when executed by the processor, cause that processor to perform these operations.

[0011]

[0011] In additional aspects of the Disclosure, the device includes a memory controller of a host device configured to couple the host device to a memory system via a memory interface, the memory controller being configured to perform operations including: sending a first write request to the memory system via the memory interface to write data to a replay-protected memory block (RPMB) portion of a memory module of the memory system; sending a first read request to the memory system via the memory interface to read the result of the first write request from a table of the RPMB portion of the memory module of the memory system; and receiving instructions from the memory system via the memory interface regarding the result of the first write request. In another aspect of the Disclosure, a method is also disclosed for a processor to perform these operations by executing instructions stored in memory coupled to the processor. In additional aspects of the Disclosure, a non-temporary computer-readable medium stores instructions, and the instructions cause the processor to perform these operations when executed by the processor.

[0012]

[0012] The above provides a fairly broad overview of the features and technical advantages of the embodiments of this disclosure so that the following “Modes for Carrying Out the Invention” may be better understood. Additional features and advantages are described below. The concepts and specific embodiments disclosed may be readily used as a basis for modifying or designing other structures to accomplish the same objectives of this disclosure. Such equivalent structures shall not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein will be better understood from the following description by examining both their configuration and method of operation, along with the relevant advantages, in relation to the appended figures. Each of the figures is provided for illustrative and explanatory purposes and is not provided to define any limitation of the claims.

[0013]

[0013] While this application describes embodiments and implementations by example to several embodiments, those skilled in the art will understand that additional implementations and use cases may occur in many different configurations and scenarios. The innovations described herein can be realized across many different platform types, devices, systems, shapes, sizes, and packaging configurations. For example, embodiments and / or applications may be implemented in integrated chip implementations and other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (AI)-enabled devices, etc.). Some examples may or may not specifically target use cases or applications, but a wide range of combinations of the innovations described may be applicable. Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more embodiments of the innovations described. In some practical settings, devices incorporating the embodiments and features described may also necessarily include additional components and features for the implementation and practice of the claims and embodiments described. For example, wireless signal transmission and reception necessarily include several components (hardware components, such as antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors (one or more), interleavers, adders / analog adders, etc.) for analog and digital purposes. The innovations described herein are intended to be practiced in a wide variety of devices, chip-level components, systems, distributed configurations, end-user devices, etc., of various sizes, shapes, and structures. [Brief explanation of the drawing]

[0014]

[0014] Further understanding of the nature and advantages of this disclosure can be achieved by referring to the following drawings. In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by adding a dash and a second label that distinguishes similar components after the reference label. Where only the first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, notwithstanding the second reference label. [Figure 1]

[0015] Figure 1 is a block diagram showing a data processing system including a memory system according to one embodiment of the present invention. [Figure 2]

[0016] Figure 2 is a block diagram showing an exemplary electronic device, including a memory system, according to one or more aspects of the present disclosure. [Figure 3]

[0017] This block diagram shows components for facilitating access from a host device to a flash memory device according to some embodiments of the present disclosure. [Figure 4]

[0018] This is a block diagram showing an electronic device having an encryption channel to a replay-protected memory block (RPMB) of a storage device, according to one or more aspects of the present disclosure. [Figure 5A]

[0019] This block diagram shows an exemplary flow of a write request and subsequent status check between a host and a memory device including an RPMB, according to one or more aspects of the present disclosure. [Figure 5B]

[0020] This block diagram shows an exemplary flow of multiple write requests and subsequent status checks between a host and a memory device including an RPMB, according to one or more aspects of the present disclosure. [Figure 6A]

[0021] FIG. 6A is a chart showing exemplary contents of a security protocol in-message format including a virtual machine (VM) identifier (ID) according to one or more aspects of the present disclosure. [Figure 6B]

[0022] FIG. 6B is a chart showing exemplary contents of an RPMB message format including a virtual machine (VM) identifier (ID) according to one or more aspects of the present disclosure. [Figure 7]

[0023] An exemplary table for storing an indication of the result of an RPMB write request associated with an indication of each write request according to one or more aspects of the present disclosure. [Figure 8A]

[0024] A flowchart showing a method for table-based RPMB write request status tracking by a flash memory device according to one or more aspects of the present disclosure. [Figure 8B]

[0025] A flowchart showing a method for table-based RPMB write request status tracking by a host controller according to one or more aspects of the present disclosure. [Figure 9]

[0026] A block diagram showing details of an exemplary wireless communication system according to one or more aspects.

[0015]

[0027] Like reference numerals and names in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0028] Regarding the accompanying drawings, the "Mode for Carrying Out the Invention" described below is intended as an explanation of various configurations and is not intended to limit the scope of the present disclosure. Rather, the "Mode for Carrying Out the Invention" includes specific details aimed at providing a complete understanding of the subject matter of the present invention. It will be apparent to those skilled in the art that these specific details are not required in every case, and that in some instances, well-known structures and components are shown in block diagram form for clarity of explanation.

[0017]

[0029] The present disclosure provides a system, apparatus, method, and computer-readable medium that support data processing, including techniques for storing, retrieving, and organizing data within a memory system. In particular, aspects of the present disclosure provide table-based status tracking of write requests to protected portions of a memory system, such as a replay protected memory block (RPMB) portion of a memory module. For example, an indication of the success or failure of a write request can be stored in a table in association with the indication of each write request, and provided to a host device by the memory system in response to a status request received from the host device.

[0018]

[0030] Particular implementations of the subject matter described in the present disclosure may be realized to achieve one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides techniques for improving the reliability of RPMB write request status by storing an indication of the write request status associated with each write request in a table. Such an improvement in reliability can reduce the occurrence of misreading of data where a host device reads old data from the RPMB of a memory system in accordance with a received indication that a failed write request was successful. Further, the use of such a table may enable more reliable tracking of the success and / or failure of write requests associated with specific virtual machines (VMs) within a system including a multi-VM architecture.

[0019]

[0031] The memory may be used in a computing system organized as shown in Figure 1. Figure 1 shows a data processing system 100 that may be included in a mobile computing device according to one or more embodiments of the present disclosure. The memory system 110 may be coupled to a host device 102 via one or more channels. For example, the host device 102 and the memory system 110 may be coupled via a serial interface including a single channel for data transport, or via a parallel interface including two or more channels for data transport. In some embodiments, control data may be transferred via the same channel(s) as the data, or control data may be transferred via additional channels. The host device 102 may be a portable electronic device such as a mobile phone, MP3 player, or laptop computer, or a non-portable electronic device such as a desktop computer, game player, television (TV), media player, or projector. In another example, the host device 102 may be an automotive computer system. In some examples, the memory system 110 may be contained within the host device 102. Therefore, the data processing system 100 may be any of the exemplary host devices described herein, including the memory system 110. Additional exemplary host devices are shown and described with reference to Figure 6.

[0020]

[0032] The memory system 110 can perform operations in response to commands (e.g., requests) from the host device 102. For example, the memory system 110 can store data provided by the host device 102, and the memory system 110 can also provide the stored data to the host device 102. The memory system 110 can be used by the host device 102 as main memory, short-term memory, or long-term memory. As an example of main memory, the host device 102 may use the memory system 110 to supplement or replace system memory by using the memory system 110 to store temporary data such as data related to the operating system and / or threads running within the operating system. As an example of short-term memory, the host device 102 may use the memory system 110 to store a page file for the operating system. As an example of long-term memory, the host device 102 may use the memory system 110 to store user files (e.g., documents, videos, photos) and / or application files (e.g., word processing executables, game applications).

[0021]

[0033] The memory system 110 may implement one of various storage devices according to a host interface protocol for one or more channels connecting the memory system 110 to the host device 102. The memory system 110 may implement one of various storage devices such as a solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), microMMC, secure digital (SD) card, miniSD, microSD, universal serial bus (USB) storage device, universal flash storage (UFS) device, compact flash (CF) card, smartmedia (SM) card, or memory stick.

[0022]

[0034] The memory system 110 may include a memory module 150 and a controller 130 coupled to the memory module 150 via one or more channels. The memory module 150 stores and retrieves data in memory blocks 152, 154, and 156 under the control of the controller 130, and the controller 130 can execute commands received from the host device 102. The controller 130 is configured to control data exchange between the memory module 150 and the host device 102. Storage components such as blocks 152, 154, and 156 within the memory module 150 may be implemented as volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), or as non-volatile memory devices such as read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (SCRAM), or NAND flash memory.

[0023]

[0035] The controller 130 and the memory module 150 may be formed as an integrated circuit on one or more semiconductor dies (or other substrates). In some embodiments, the controller 130 and the memory module 150 may be integrated on a single chip. In some embodiments, the memory module 150 may include one or more chips coupled in series or parallel to each other and coupled to the controller 130, which is located on a separate chip. In some embodiments, the chips of the memory module 150 and the controller 130 are integrated on a single package, such as a package-on-package (PoP) system. In some embodiments, the memory system 110 is integrated on a single chip together with one or more or all of the components of a host device 102, such as a system-on-a-chip (SoC), including an application processor, system memory, digital signal processor, modem, graphics processor unit, memory interface, input / output interface, and network adapter. The controller 130 and the memory module 150 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, CompactFlash (CF) card, SmartMedia card (SMC), Memory Stick, Multimedia Card (MMC), RS-MMC, MicroMMC, Secure Digital (SD) card, MiniSD, MicroSD, SDHC, and Universal Flash Storage (UFS) device.

[0024]

[0036] The controller 130 of the memory system 110 can control the memory module 150 in response to commands from the host device 102. The controller 130 can execute read commands to provide data from the memory module 150 to the host device 102. The controller 130 can execute write commands to store data provided by the host device 102 in the memory module 150. The controller 130 can manage the data in the memory module 150 by executing other commands such as program commands and erase commands. The controller 130 can also manage control of the memory system 110, such as by executing other commands to set the configuration registers of the memory system 110. By executing commands according to the configuration specified in the configuration registers, the controller 130 can control the operation of the memory module 150, such as read, write, program, and erase operations.

[0025]

[0037] The controller 130 may include several components configured to execute received commands. For example, the controller 130 may include a host interface (I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a NAND flash controller (NFC) 142, and / or memory 144. The power management unit (PMU) 140 may provide and manage power for the components in the controller 130 and / or memory module 150.

[0026]

[0038] The host interface unit 132 can process commands and data provided by the host device 102 and can communicate with the host device 102 through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). For example, the host interface 132 may be a parallel interface such as the MMC interface, or a serial interface such as an ultra-high speed class 1 (UHS-I) / UHS class 2 (UHS-II) or Universal Flash Storage (UFS) interface.

[0027]

[0039] The ECC unit 138 can detect and correct errors in the data read from the memory module 150 during a read operation. If the number of error bits is greater than the threshold number of error bits that can be corrected, the ECC unit 138 may not correct the error bits, and as a result, the ECC unit 138 may output an error correction failure signal indicating that the correction of the error bits has failed. In some embodiments, the ECC unit 138 may not be provided, or the ECC unit 138 may be configured to be active for some or all of the memory module 150. The ECC unit 138 may perform error correction operations using coded modulation such as low-density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM).

[0028]

[0040] The NFC142 provides an interface between the controller 130 and the memory module 150, enabling the controller 130 to control the memory module 150 in response to commands received from the host device 102. The NFC142 can generate control signals for the memory module 150, such as low-line and bit-line signals, and process data under the control of the processor 134. Although the NFC142 is described as a NAND flash controller, other controllers may perform similar functions for other memory types used as the memory module 150.

[0029]

[0041] Memory 144 may function as working memory for the memory system 110 and controller 130. Memory 144 may store data to drive the memory system 110 and controller 130. If controller 130 controls the operation of memory module 150, such as read, write, program, or erase operations, memory 144 may store data used by controller 130 and memory module 150 for operation. Memory 144 may implement volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, memory 144 may store address mappings, program memory, data memory, write buffers, read buffers, map buffers, etc.

[0030]

[0042] The processor 134 can control the overall operation of the memory system 110 and can control write or read operations on the memory module 150 in response to write or read requests received from the host device 102. For example, the processor 134 may execute firmware sometimes called a flash translation layer (FTL) to control the overall operation of the memory system 110. The processor 134 may be implemented as, for example, a microprocessor, a central processing unit (CPU), or an application-specific integrated circuit (ASIC).

[0031]

[0043] Figure 2 is a block diagram illustrating an exemplary electronic device including a memory system 100 according to one or more aspects of the present disclosure. The electronic device 200 may include a user interface 210, memory 220, an application processor 230, a network adapter 240, and a storage system 250 (which may be an embodiment of the memory system 100 in Figure 1). The application processor 230 may be coupled to other components via a bus, such as a peripheral component interface (PCI) bus, including a PCI Express (PCIe) bus.

[0032]

[0044] The application processor 230 may execute computer program code, including applications, drivers, and operating systems, to coordinate the execution of tasks by components included in the electronic device 200. For example, the application processor 230 may execute a storage driver for accessing the storage system 250. The application processor 230 may be part of a system-on-a-chip (SoC) that includes one or more other components shown in the electronic device 200.

[0033]

[0045] Memory 220 may function as the main memory, working memory, buffer memory, or cache memory of the electronic device 200. Memory 220 may include volatile random access memories such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM, or non-volatile random access memories such as phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). In some embodiments, the application processor 230 and memory 220 may be combined using a package-on-package (POP).

[0034]

[0046] The network adapter 240 can communicate with external devices. For example, the network adapter 240 may support wired and / or various wireless communications such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, and wireless display (Wi-Di), thereby enabling communication with wired and / or wireless electronic devices, such as mobile electronic devices.

[0035]

[0047] The storage system 250 can store data, for example, data received from the application processor 230, and transmit the stored data to the application processor 230. The storage system 250 may be a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive random-access memory (ReRAM), NAND flash memory, NOR flash memory, or three-dimensional (3-D) NAND flash memory. The storage system 250 may also be a removable storage medium such as a memory card or an external drive. For example, the storage system 250 may correspond to the memory system 110 described above with reference to Figure 1, and may be an SSD, eMMC, UFS, or other flash memory system.

[0036]

[0048] The user interface 210 provides one or more graphical user interfaces (GUIs) for inputting data or commands to the application processor 230 or outputting data to an external device. For example, the user interface 210 may include user input interfaces such as a virtual keyboard, touchscreen, camera, microphone, gyroscope sensor, or vibration sensor, and user output interfaces such as a liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, light-emitting diode (LED), speaker, or tactile motor.

[0037]

[0049] Figure 3 is a block diagram showing components for facilitating access from a host device to a flash memory system according to some embodiments of the present disclosure. The host device 102 accesses the memory system 110 through a first interface 310. The first interface may be a memory interface, such as a physical interface (PHY) that connects the host device 102 to the memory system 110. The host device 102 may include a physical layer access block 312, which is configured to generate signals for output to the memory interface 310 and to process signals received through the memory interface 310. The memory system 110 includes a similarly configured physical layer access block 322 for communicating over the memory interface 310. One exemplary physical layer specification for communicating over the memory interface 310 is the MIPIM-PHY® physical layer specification.

[0038]

[0050] The host device 102 also includes a data link layer block 314 configured to format data frames for transmission over the memory interface 310. The frames may be provided to the physical layer access block 312 for transmission. The data link layer block 314 can receive frames from the physical layer access block 312 and decode the data frames received over the memory interface 310. The memory system 110 includes a similarly configured data link layer block 324 for processing frames transmitted or received over the memory interface 310 by the physical layer access block 322. One exemplary data link protocol for communication over a MIPI M-PHY® physical link is the MIPI UNIPRO® specification.

[0039]

[0051] The memory system 110 includes N logical units 350a to n, each containing a logical memory block for storing information including user data (e.g., user documents, application data) and configuration data (e.g., information about the operation of the memory system 110). The logical units 350a to n may be mapped to portions of physical memory blocks 152, 154, and 156. Some or parts of the logical units 350a to n may be configured as a specific memory type (e.g., default, system code, non-persistent, extended) with write protection, boot functionality, priority access, or as a replay-protected memory block (RPMB) with replay protection. The physical layer access block 322 and the data link layer block 324 perform the operation of a memory controller for the memory system 110 to store and retrieve data within the logical units 350a to n.

[0040]

[0052] The memory system 110 also includes a configuration structure 352. The configuration structure 352 may include information such as configuration descriptors for boot enable (bBootEnable), initial power mode (bInitPowerMode), RPMB active (bRPMBRegionEnable), and / or RPMB region size (bRPMBRegion1Size, bRPMBRegion2Size, bRPMBRegion3Size). Such configuration structures and / or parameters may be, for example, configuration structures and / or parameters identified by the UFS standard.

[0041]

[0053] The host device 102 may be configured to run one or more applications 334, such as user applications, which are executed by the operating system under the user's control, in order to receive user input and provide the user with information stored in the memory system 110. The host device 102 may include several components for interface the applications 334 to the memory system 110 through the memory interface 310. For example, a SCSI driver 332 and a UFS driver 330 may interface the applications 334 to a host memory controller which includes a data link layer block 314 and a physical layer access block 312. The SCSI driver 332 may run at the application layer to process transactions requested by the applications 334 using the memory system 110. The UFS driver 330 may run at the transport layer and manage the operation of the data link layer block 314, such as to operate the memory interface 310 in one of several operating modes. The operating mode may include two or more gear settings, such as one or more PWM-GEAR settings specifying one bitrate from 182MBps, 364MBps, 728MBps, and 1457MBps, and four or more HS-GEAR settings.

[0042]

[0054] The memory interface 310 may include one or more lines, including a reset RST line, a reference clock REF_CLK line, a data-in DIN line (for transmitting data from the host device 102 to the memory system 110), and a data-out DOUT line (for transmitting data from the memory system 110 to the host device 102). The DIN line and DOUT line may be two separate conductors, or the DIN line and DOUT line may include multiple conductors. In some embodiments, the DIN line and DOUT line may be asymmetrical, with a DIN line containing N conductors and a DOUT line containing M conductors, where N > M or M > N.

[0043]

[0055] The UFS driver 330 can generate and decrypt packets to execute a transaction requested by application 334. The packets are transmitted via the memory interface 310. The packets can be formatted as UFS Protocol Information Units (UPIUs). In a transaction with memory system 110, the host device 102 is the initiator and memory system 110 is the target. Based on the type of transaction, the UFS driver 330 can form one of several types of UPIUs to handle SCSI commands, data operations, task management operations, and / or query operations. Each transaction may include one command UPIU, zero or more DATA IN or DATA OUT UPIUs, and a response UPIU. Each UPIU may include a header followed by optional fields, depending on the type of UPIU.

[0044]

[0056] One exemplary transaction is a read operation. A read transaction may involve an initiator (e.g., host device 102) sending a command UPIU to a target (e.g., memory system 110) to perform a read operation requested by application 334. In response to the command UPIU, the target provides one or more DATA IN UPIUs, which contain the requested data. The read transaction is completed when the target sends a response UPIU.

[0045]

[0057] Another exemplary transaction is a write operation. A write operation may involve an initiator (e.g., host device 102) sending a command UPIU to a target (e.g., memory system 110) to perform a write operation requested by application 334. The target provides a Ready to Transfer UPIU signaling the initiator to begin transferring the write data. The initiator then sends one or more DATA OUT UPIUs, followed by Ready to Transfer UPIUs signaling the initiator to continue transferring the write data. The sequence of DATA OUT UPIUs and Ready to Transfer UPIUs continues until all the write data has been delivered to the target, after which the target provides a response UPIU to the initiator.

[0046]

[0058] A further exemplary transaction is a query operation. A query operation may involve an initiator (e.g., host device 102) requesting information about a target (e.g., memory system 110). The initiator may send a query request UPIU to request information such as the target's configuration, enumeration, device descriptors, flags, and / or attributes. Exemplary query operations include reading a descriptor, writing a descriptor, reading an attribute, writing an attribute, reading a flag, setting a flag, clearing a flag, and / or toggling a flag. Exemplary descriptors include device, configuration, unit, interconnect, string, geometry, power, and / or device health. Exemplary flags include fDeviceInit, fPermanenetWPEn, fPowerOnWPEn, fBackgroundOpsEn, fDeviceLifeSpanModeEn, fPurgeEnable, fRefreshEnable, fPhyResourceRemoval, fBusyRTC, and / or fPermanentlyDisableFwUpdate. Examples of attributes include bBootLunEn, bCurrentPowerMode, bActiveICCLevel, bOutOfORderDataEn, bBackgroundOpStatus, bPurgeStatus, bMaxDataInSize, bMaxDataOutSize, dDynCapNeeded, and bRefClkFreq. Such flags may be flags identified, for example, by the UFS standard.

[0047]

[0059] The operations and capabilities described above may be used for a memory system that supports storing the RPMB write request status associated with each write request to a table. Specifically, when an RPMB write request is received by a memory device and executed successfully or unsuccessfully, an indication of whether the request was successful or unsuccessful may be stored in a table, such as a table stored within the RPMB, in association with the write request indication.

[0048]

[0060] Figure 4 shows an electronic device that provides encryption protection for a memory interface. Figure 4 is a block diagram showing an electronic device having an encryption channel to a storage device according to one or more aspects of the present disclosure. The host device 400 may include software 410 running on hardware 420. The software 410 may include applications 412 running in the host operating system and / or one or more virtual machines 414, 416. The software 410 may run on an application processor core 422. The application processor core 422 may be coupled to a memory controller 424 that provides an interface between the application processor core 422 and the memory system 430 through one or more channels 442, such as one or more data channels. For example, a channel 442 may be a channel of the memory interface between the host device 400 and the memory system. One or more channels 442 may be, for example, physical channels. The memory controller 424 may also provide an interface to the memory system 430 for the virtual machines 414 and 416. In some embodiments, a memory controller 424 may be located within a host device 400, and another memory controller 436 may be located within a memory system 430. The memory controller 436 of the memory system 430 may communicate with the memory controller 424 of the host device 400 through one or more channels 442 of the memory interface. The memory controller 436 of the memory system 430 may communicate with one or more modules of the memory system 430, such as the RPMB 432 of the memory system 430, through one or more channels, such as one or more data channels.

[0049]

[0061] In some embodiments, the interface between the memory controller and the memory device may be a Universal Flash Storage (UFS) interface, where the memory controller 424 is a UFS memory controller and the memory system 430 is a UFS memory device 430. In some embodiments, the host device 400 and the memory system 430 may be integrated into a single package as two different integrated circuits using multi-chip packaging techniques. In some embodiments, the host device 400 and the memory system 430 may be a single integrated circuit in which the host device 400 and the memory system 430 are contained on a single semiconductor die. While exemplary embodiments of UFS may be described herein, aspects of this disclosure may also apply to other memory systems, including any of the memory systems described with reference to Figure 1.

[0050]

[0062] The memory system 430 may include a controller 436 for interfacing with the memory controller 424, such as through a channel 442, including a channel of the memory interface. In some embodiments, the controller 436 may communicate with the host device 400 through the interface. The memory system 430 may also include a replay-protected memory block (RPMB) portion 432 of a memory module configured to store secure application data that provides replay protection. For example, the RPMB portion 432 may protect data written to the area from being overwritten (e.g., through Write Protect Until Power Cycle or Permanent Write Protect status). The RPMB portion 432 may be used by software to mitigate or prevent downgrade attacks that override software version authentication, or by software for secure boot to prevent unwanted code from running on the device.

[0051]

[0063] The RPMB portion 432 may include one or more designated areas 434A to D. Areas 434A to D may be part of one of the memory blocks 152, 154, and 156 in Figure 1, or one of the memory blocks 152, 154, and 156 dedicated to the RPMB. Areas 434A to D may be allocated to different clients to store data specific to that client and may be protected from reading or writing by other clients. For example, a first application may store first data in area 434A, a second application may store second data in area 434B, and the virtual machine 414 may store third data in area 434C. The first application may be prevented by the memory system 430 from accessing the data stored in areas 434B and 434C. Areas 434A to D may be used by software 410 and / or virtual machines 414 and 416 to store information related to digital rights management (DRM) (e.g., keys for accessing protected media content within a media player application), biometric data (e.g., fingerprints, facial recognition data, iris recognition data), secure file system keys, user identifiers, passwords, and / or software rollback versions (e.g., anti-rollback versions of trusted applications).

[0052]

[0064] Each of the RPMB regions 434A-D may have corresponding information stored within the memory system 430. For example, the memory system 430 may separately track a write counter for each of the RPMB regions 434A-D that indicates the total amount of successful authenticated data write operations. The write counter may allow an application owning one of the RPMB regions to identify whether a malicious process or negligent action has overwritten data in the RPMB region. As another example of information corresponding to an RPMB region, the memory system 430 may separately store an authentication key for each of the RPMB regions 434A-D. The authentication key may be provisioned by a client (e.g., an application or virtual machine) by providing the memory system 430 with a seed key from which the authentication key is derived using a confidential hash algorithm.

[0053]

[0065] A cryptographic engine 432A for facilitating authentication operations related to read or write operations to RPMB regions 434A-D may be included within the RPMB portion 432 or elsewhere in the memory system 430. For example, the cryptographic engine 432A may include a key memory space for storing authorization keys. The key memory space may be sized or allocated from shared memory. As another example, the cryptographic engine 432A may also include a logic circuit mechanism for determining a hash value based on a specific input. The logic circuit mechanism for determining the hash value may be configured to compute a hash value based on input from the host device 400 (such as first information received from the host device 300 in an RPMB read request message) or from memory in the memory system 430 (such as second information stored or determined by the memory system 430 for RPMB regions 434A-D). Logic within the cryptographic engine 432A or the memory controller 436 may be configured to determine whether access to one of the regions 434A-D is authorized.

[0054]

[0066] In one embodiment, to access RPMB areas 434A-D, the memory controller 424 may send an authenticated data read request message. The read request message may share a common message structure as a response message, also sent through channel 442. The differing part of the message may be empty, 0, or some other null value when a field is not applicable to the request or response. Similarly, the memory controller 424 may send an authenticated data write request message, which may also share a common structure as a response message, also sent through channel 442.

[0055]

[0067] The success of an RPMB write request message can be tracked using RPMB result register bits. Figure 5A is a block diagram 500 showing an exemplary flow of a write request 510 and subsequent status checks between a host 502 and a memory device 506 containing an RPMB, according to one or more embodiments of the present disclosure. As shown in Figure 5A, the host device 502, which may be a host device similar to the host device 400 in Figure 4, may be connected to the memory device 506. In some embodiments, the host device 502 may include the memory device 506. For example, the memory device 506 may be integrated within the host device 502. The memory device 506 may be similar to the memory system 430 in Figure 4. The memory device 506 may be or include an RPMB for securely storing data, as described herein. The host device 502 may include a host controller interface 504 for communicating with the memory device 506. In some embodiments, the host controller interface 504 may facilitate communication between the memory controller of the host 502 and the memory device 506. In some embodiments, the host device 502 may run an operating system, such as the one described with respect to the host device 400 in Figure 4. The host device 502 and the memory device 506 may be configured to operate in accordance with the UFS standard, as described herein.

[0056]

[0068] The host device 502 may write information to the memory device 506, for example to the RPMB of the memory device 506, by sending a write request 510, such as an RPMB write request, to the memory 506. The write request may be, for example, an RPMB message data frame, or may include one, as described herein. In one specific example, the write request 510 may be an authenticated write request and may include a security protocol out (SPO) message. In some embodiments, the write request 510 may include an SPO message at the UFS command set (UCS) layer and a command UFS protocol information unit (UPIU) message at the UFS transport (UTP) layer. The memory device 506 may receive the write request 510. If the write request 510 is successful, the data associated with the write request 510 is written to the memory device 506, for example to the RPMB of the memory device 506. A write request 510 may succeed, for example, if the address and media access control (MAC) authentication of the write request 510 on the memory device 506 are successful. If the write request 510 fails, the data associated with the write request 510 is not written to the memory device 506, for example, to the RPMB of the memory device 506. A write request 510 may fail if the address and MAC authentication of the write request 510 fail. Based on whether the write request 510 was successful or not, the result register bits of the RPMB of the memory device 506 may be updated. For example, in the case of write request 510, the request may succeed and the result register bit 508 may be set to a value of 1. If the write request 510 is unsuccessful, the result register 508 may be set to a value of 0.

[0057]

[0069] To determine whether the write request 510 was successful, the host device 503 then sends a status request 512 to obtain the status of the result register 508. The status request 512 may include, for example, an SPO message in the UCS layer and a command UPIU message in the UTP layer. In some embodiments, the status request 512 may include an SPO message of type, result read request. The host device 502 may then send a result read request 514 to read the information stored in the result register 508. The result read request 514 may be or include an RPMB message data frame. The result read message 514 may include, for example, a Security Protocol In (SPI) message in the UCS layer and a command UPIU message in the UTP layer. The memory device 506 may accordingly send a response 516 to the host device 502, such as an RPMB result read response message, which includes instructions for the information stored in the result register 508. The response 516 may be, for example, an RPMB message data frame. The host device 502 may determine whether the write request 510 was successful based on the response 516. In some embodiments, the status request 512, the result read request 514, and the response 516 may be performed by the host device 502 as part of an authenticated data write verification process.

[0058]

[0070] However, using a single common status register to track the success of write request messages can make the system vulnerable to false positives or false negatives. For example, if a subsequent write request is sent to the memory device 506 after the first write request has been sent and received, and before the result of register 508 has been read, register 508 may be updated to reflect the result of the subsequent write request. As one specific example, under the UFS standard, any request received by the RPMB other than a result read request from any initiator will overwrite the current value of the result status register 508. Figure 5B is a block diagram 550, an exemplary flow of multiple write requests 552, 554 and subsequent status checks between a host 502 and a memory device 506 containing an RPMB, according to one or more aspects of this disclosure. As shown in Figure 5B, write request 552 may be sent by the host device 502, received by memory 506, and successfully executed, and the result status register 508 may be updated accordingly. However, if a subsequent write request 554, such as one from an attacker or resulting from a software error, is received by the memory device 506 before the result read request 558 is sent by the host device 502 and received by the memory device 506, the value of the result register 508 may be updated to reflect the status of the subsequent write request 554. For example, if the subsequent write request 554 fails for reasons such as address and / or MAC authentication failure, the result register 508 may be updated to reflect that the write request failed. Subsequently, when the host device 502 sends a status request 556 to obtain the status of the result register 508 and a result read request 558 to read the result register 508, a value indicating a write request failure may be returned from the memory device 506 to the host device 502 in response 560. Therefore, in practice, if the write request 552 was successful, while the subsequent write request 554 failed, the host device 502 may conclude that the write request 552 failed.Similarly, the first write request may fail, resulting in the status register 508 being set to indicate failure, and a subsequent write request may succeed, resulting in the status register 508 being overwritten to indicate success. Such a scenario can result in a false positive when the host device 502 requests to read the result register 508 from the memory device 506. The false positive can result in the host device 502 reading old or obsolete data from, for example, a portion of the RPMB, because the host device 502 may assume that the data has been updated based on the previous write request according to the false positive read from the result status register 508.

[0059]

[0071] In some embodiments, such as those described with respect to the host device 400 in Figure 4, multiple VMs may be run by the host device and information may be stored in a partition of the RPMB in memory 506. Therefore, for example, different write requests originating from different virtual machines of the host device 502 may result in the overwriting of register 508 upon success or failure, and the host device may become unable to track the status of a particular write request associated with a particular virtual machine. For example, the first write request 552 described above may be a write request from a first VM of the host device 502, and the subsequent write request 554 may be a write request from a second VM of the host device 502.

[0060]

[0072] Using a table instead of, or in addition to, a result status register to store the status of RPMB write requests received by memory device 506 can reduce the occurrence of false positives or false negatives. For example, when memory device 506 in Figure 5A receives a write request 510 from host device 502, memory device 506 may store an indicator in its table indicating whether the request was successful or failed. The indication of the write request status may be associated with the indication of write request 510 in the table. For example, write request 510 may be, or include, an RPMB write request message following the RPMB message format 650 in Figure 6B. In some embodiments, the RPMB message format 650 may include, in block 652, a VM identifier (ID) of the VM associated with the write request, such as the VM that issued the write request. In some embodiments, another identifier may be included in block 652, such as a unique identifier for RPMB messages in the RPMB message format 650. Block 652 for storing identifiers may be, for example, the 500th byte of an RPMB message data frame conforming to the UFS standard, or another set of bytes or bits of the RPMB message data frame structure, which is currently allocated for storing nonce. Such bytes may be reallocated for storing write request identifiers. In some embodiments, all or part of the nonce stored in bytes 485-499 or 500 of the RPMB message format 650 may be used as a write request identifier in place of or in addition to the VM ID. The VM ID, or any other identifiers unique to the write request 510 and contained therein, may be associated in a table with an indicator of the status of the write request 510. In some embodiments, such a table may be stored in the RPMB of memory device 506. In some embodiments, the table may be updated to include only indications of successful write requests.

[0061]

[0073] Figure 7 shows an exemplary table 700 for storing RPMB write request results. As shown in Figure 7, the table may contain multiple entries 702, 704, each entry associated with a specific write request. For example, each entry 702, 704 may include the VM ID associated with the write request, or another identifier for the write request, and a result code indicating the outcome of the write request. For example, the result code may include 1 for a successful write request and 0 for a failed write request. Additional entries may be added to table 700 as additional write requests are received and succeed or fail. In some embodiments, only indications of successful write requests may be stored in table 700. In some embodiments, table 700 may be a hash table, where the hash key is set to the VM ID associated with the write request, or another identifier associated with the write request. In some embodiments, after each write request, an entry may be added to table 700 before the response UPIU to the write request is sent from memory device 506 to host device 502. When the host device sends a result read request 514, the result read request 514 may include instructions for a corresponding write request. For example, the result read request 514 may include an SPI command message following the format 600 in Figure 6A. In block 602, the SPI command message may include instructions for the VM ID of the VM associated with the write request for which result information is being requested, or instructions for another identifier of the write request message for which results are being requested. Block 602 for storing the identifier may be, for example, the sixth byte of the SPI command format 600 following the UFS standard, or another set of bytes or bits of the SPI command format 600, which is currently allocated as reserved. Such bytes may be reallocated for storing the write request identifier. The memory device 506 may compare the instructions for the write request contained in the result read request 514 with instructions for a specific write request stored in a table associated with the corresponding result information, and may return the result information corresponding to the write request instructions.For example, if the result read request 514 includes an instruction for a specific VM ID, the memory device 506 may look up a table such as table 700 for the VM ID and return result information corresponding to the VM ID in response 516. Specifically, the memory device 506 may use the VM ID as a hash key input for looking up table 700. Response 516 may include an RPMB message data frame in format 650, and the result information may be included within the result block of the RPMB message data frame in format 650. Therefore, even if a subsequent write request is received before the result read request is sent for a particular write request, the result information for that particular write request can be retrieved from a table containing instructions for one or more write requests associated with each piece of result information.

[0062]

[0074] Figure 8A is a flowchart illustrating a method for tracking table-based RPMB write status requests by a flash memory system according to several embodiments of the present disclosure. The flash memory system may be configured, for example, according to the UFS standard, and may include an RPMB portion of a memory module in the memory system. The memory controller of the memory system may be coupled to the memory module via a channel and configured to access data stored in the memory module via the channel. The memory controller may be coupled to a host device via a memory interface and configured to communicate with the host device via the memory interface. The memory controller may be further configured to perform the operation of method 800. Method 800 includes, in block 802, receiving a first write request from the host device to write data to the RPMB portion of the memory module. The first write request may be, for example, an RPMB message data frame or include one. In some embodiments, the first write request may be an SPO command message or include one. In some embodiments, the write request may be a priority write request, such as a priority write request according to the UFS standard.

[0063]

[0075] In block 804, the memory controller may determine the result of the first write request. For example, the memory controller may determine whether the first write request is successful or unsuccessful. Such a determination may include, for example, performing address and MAC authentication for the write request. If address and MAC authentication is successful, the information of the write request may be written to the RPMB, and the write request may be successful. If address and MAC authentication is unsuccessful, the information of the write request may not be written to the RPMB, and the write request may be unsuccessful.

[0064]

[0076] In block 806, the memory controller may store the instructions for the results of the first write request, associated with the instructions for the first write request, in a table of the RPMB portion of the memory module. For example, such a table may contain a plurality of instructions for the results of the write request, each associated with the instructions for each write request. In some embodiments, the instructions for the first write request may include instructions for the VM ID contained within the first write request.

[0065]

[0077] In some embodiments, the memory controller may subsequently receive a first read request to read the result of the first write request. The first read request may include, for example, an SPI message. In some embodiments, the first read request may include instructions for the first write request, such as an instruction for the VM ID included in the first write request. The memory controller may send instructions for the result of the first write request to the host device based on the stored instructions for the result of the first write request associated with the instructions for the first write request. For example, the memory controller may use the instructions for the first write request included in the read request, such as the VM ID included in the read request, to look up a table of associated write request instructions and write request status instructions for the write request status instruction corresponding to the write request instruction.

[0066]

[0078] If a subsequent write request is received, the result instructions for the subsequent write request, associated with the instructions for the subsequent write request, may be stored in a table. Therefore, instead of a single result register bit that is overwritten by each successful request, a table of multiple result write requests may be maintained. For example, a memory controller may receive a second write request to write data to the RPMB portion of a memory module, and may determine that the result of the second write request was a failure. The memory controller may store the result instructions for the second write request, associated with the instructions for the second write request, in a table for the RPMB portion of the memory module. The second write request may be received, for example, before a read request to read the result of the first write request. Subsequently, even if the second write request is received before the read request, the memory controller may use the information stored in the table to send the result instructions for the first write request to the host device in response to the read request.

[0067]

[0079] Figure 8B is a flowchart illustrating a method for tracking a table-based RPMB write status request by a host controller, according to some embodiments of the present disclosure. For example, a memory controller of a host device may be configured to connect the host device to a memory system through a memory interface. In some embodiments, the memory system may be configured to operate in accordance with the UFS specification. The memory controller may be further configured to perform method 820, which includes, in block 822, the memory controller of the host device sending a first write request to write data to the RPMB portion of a memory module in the memory system. The first write request may be, for example, an RPMB message data frame or include one. In some embodiments, the first write request may be, for example, an SPO command message or include one. In some embodiments, the first write request may be a preferential write request, such as a preferential write request in accordance with the UFS specification. In some embodiments, the first write request may include an indication of a VM ID, such as the VM ID of the VM associated with the first write request. The VM ID may be, for example, the VM ID of the VM that initiated the first write request.

[0068]

[0080] In block 824, the memory controller of the host device may send a first read request to read the result of a first write request from a table in the RPMB portion of the memory module of the memory system. The table may be stored, for example, within the RPMB portion of the memory module. The table may contain, for example, multiple instructions for the results of each write request associated with each instruction of each write request. For example, the table may contain multiple instructions for the results of each write request associated with the VM ID associated with each write request. The first read request may contain, for example, instructions for the first write request, such as instructions for the VM ID that were included in and / or associated with the first write request. The instructions for the first write request may be used by the memory system to select the instructions for the results of the first write request from the table, for example, by searching the table for the instructions for the results associated with the instructions for the first write request.

[0069]

[0081] In block 826, the host device's memory controller may receive an instruction regarding the result of the first write request. This instruction may include whether the first write request was successful or unsuccessful. The host device's memory controller may use the received status when performing subsequent reads of information written in accordance with the first write request to the RPMB portion of the memory module. Therefore, the reliability of the write request status response can be improved through the use of a table for storing the write request result instruction associated with the write request instruction.

[0070]

[0082] The operation of Method 800 or Method 820 may be performed by a UE such as the UE described with reference to Figure 9. For example, an exemplary operation of Method 800 or Method 820 (also called “blocking”) may enable UE 915 to support higher user data confidentiality. Figure 9 is a block diagram detailing an exemplary wireless communication system in one or more embodiments. The wireless communication system may include a wireless network 900. The wireless network 900 may include, for example, a 5G wireless network. As will be understood by those skilled in the art, the components appearing in Figure 9 are likely to have related corresponding parts, including other network configurations, such as cellular and non-cellular network configurations (e.g., device-to-device, peer-to-peer, or ad-hoc network configurations).

[0071]

[0083] The wireless network 900 shown in Figure 9 includes several base stations 905 and other network entities. A base station may also be a station communicating with a UE and may be called an evolved node B (eNB), next-generation eNB (gNB), access point, etc. Each base station 905 may provide communication coverage to a specific geographic area. In 3GPP, the term “cell” may refer to this specific geographic coverage area of ​​a base station or base station subsystem serving a coverage area, depending on the context in which the term is used. In the implementations of the wireless network 900 described herein, base stations 905 may be associated with the same operator or different operators (for example, the wireless network 900 may include multiple operator wireless networks). In addition, in the implementations of the wireless network 900 described herein, base stations 905 may provide wireless communication using one or more of the same frequencies as adjacent cells (e.g., one or more frequency bands in the licensed spectrum, unlicensed spectrum, or a combination thereof). In some examples, individual base stations 905 or UE915 may be operated by two or more network operations entities. In some other examples, each base station 905 and UE915 may be operated by a single network operations entity.

[0072]

[0084] Base stations can provide communication coverage to macrocells, or small cells such as picocells or femtocells, or other types of cells. Macrocells generally cover relatively large geographical areas (e.g., a radius of several kilometers) and may enable unrestricted access by UEs (Users) subscribed to a network provider's service. Small cells such as picocells generally cover relatively small geographical areas and may enable unrestricted access by UEs subscribed to a network provider's service. Small cells such as femtocells also generally cover relatively small geographical areas (e.g., a home) and, in addition to unrestricted access, may also provide restricted access by UEs associated with the femtocell (e.g., UEs within a closed subscriber group (CSG), UEs for users in a home, etc.). Base stations for macrocells are sometimes called macro base stations. Base stations for small cells are sometimes called small cell base stations, pico base stations, femto base stations, or home base stations. In the example shown in Figure 9, base stations 905d and 905e are standard macro base stations, while base stations 905a–905c are macro base stations enabled with one of the following: 3D MIMO, full-dimension (FD) MIMO, or massive MIMO. Base stations 905a–905c leverage their higher-dimensional MIMO capabilities to utilize 3D beamforming in both high-level and azimuth beamforming, increasing coverage and capacity. Base station 905f is a small cell base station that can be a home node or a portable access point. A base station may support one or more (e.g., two, three, or four) cells.

[0073]

[0085] The wireless network 900 may support synchronous or asynchronous operation. In synchronous operation, base stations may have similar frame timings, and transmissions from different base stations may be approximately synchronized in time. In asynchronous operation, base stations may have different frame timings, and transmissions from different base stations may not be synchronized in time. In some scenarios, the network may be enabled or configured to handle dynamic switching between synchronous and asynchronous operation.

[0074]

[0086] UE915 is distributed throughout the entire wireless network 900, and each UE may be fixed or mobile. Mobile devices are generally referred to as UEs in the standards and specifications published by 3GPP, but it should be noted that such devices may also be referred to by those skilled in the art in additional or other ways as mobile station (MS), subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal (AT), mobile terminal, wireless terminal, remote terminal, handset, terminal, user agent, mobile client, client, game device, augmented reality device, vehicle component, vehicle device, or vehicle module, or any other appropriate term. For the purposes of this document, a “mobile” device or UE does not necessarily have to be mobile and may be fixed. Some non-exclusive examples of mobile devices that may include one or more implementations of UE915 include mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, laptops, personal computers (PCs), notebooks, netbooks, smartbooks, tablets, and personal digital assistants (PDAs).The mobile device may further include IoT or "Internet of Everything (IoE)" devices such as automobiles or other transport vehicles, satellite radios, global positioning system (GPS) devices, global navigation satellite system (GNSS) devices, logistics controllers, flight devices, smart energy or security devices, solar panels or solar arrays, urban lighting, water, or other infrastructure, industrial automation and enterprise devices, consumer and wearable devices such as eyewear, wearable cameras, smartwatches, health or fitness trackers, mammalian implantable devices, gesture tracking devices, medical devices, digital audio players (e.g., MP3 players), cameras, game consoles, and digital home or smart home devices such as home audio, video, and multimedia devices, home appliances, sensors, vending machines, intelligent lighting, home security systems, and smart meters. In one embodiment, the UE may be a device including a Universal Integrated Circuit Card (UICC). In another embodiment, the UE may be a device not including a UICC. In some embodiments, a UE that does not include UICC may also be called an IoE device. UEs 915a–915d in the implementation shown in Figure 9 are examples of mobile smartphone-type devices accessing the wireless network 900. UEs may also be machines specifically configured for connected communications, including machine-type communication (MTC), enhanced MTC (eMTC), and narrowband IoT (NB-IoT). UEs 915e–915k shown in Figure 9 are examples of various machines configured for communications accessing the wireless network 900.

[0075]

[0087] Mobile devices such as the UE915 may be able to communicate with any type of base station, including macro base stations, pico base stations, femto base stations, and repeaters. In Figure 9, the communication links (represented as lightning bolts) show wireless transmissions between the UE and a serving base station, which is a base station designated to service the UE on the downlink or uplink, or desired transmissions between base stations, and backhaul transmissions between base stations. In some scenarios, the UE may act as a base station or other network node. Backhaul communication between base stations in the wireless network 900 may be performed using wired or wireless communication links.

[0076]

[0088] In operation within the wireless network 900, base stations 905a–905c serve UEs 915a and 915b using coordinated spatial techniques such as 3D beamforming and coordinated multipoint (CoMP) or multi-connectivity. Macro base station 905d performs backhaul communication with base stations 905a–905c and small cell base station 905f. Macro base station 905d also transmits multicast services that UEs 915c and 915d subscribe to and receive. Such multicast services may include mobile television or stream video, or other services to provide community information, such as weather emergencies or alerts such as amber alerts or gray alerts.

[0077]

[0089] The implemented wireless network 900 supports mission-critical communications using ultra-high reliability redundant links for mission-critical devices such as the UE915e, which is an aircraft vehicle. The redundant communication links with the UE915e include those from macro base stations 905d and 905e, as well as from small cell base station 905f. Other mechanical devices such as the UE915f (thermometer), UE915g (smart meter), and UE915h (wearable device) can communicate via the wireless network 900, either directly with base stations such as the small cell base station 905f and macro base station 905e, or with other user devices that relay their information to the network in a multi-hop configuration. For example, the UE915f can communicate temperature measurement information to the smart meter UE915g, and then that information can be reported to the network via the small cell base station 905f. The wireless network 900 can also provide further network efficiency through dynamic low-latency TDD communication or low-latency FDD communication in vehicle-to-vehicle (V2V) mesh networks between UE915i~915k communicating with macro base stations 905e.

[0078]

[0090] In various implementations, techniques and devices may be used for wireless communication networks such as code division multiple access (CDMA) networks, time division multiple access (TDMA) networks, frequency division multiple access (FDMA) networks, orthogonal FDMA (OFDMA) networks, single-carrier FDMA (SC-FDMA) networks, LTE networks, GSM networks, 5th generation (5G) or new radio (NR) networks (sometimes referred to as "5G NR" networks, systems, or devices), and other communication networks. The terms "network" and "system" as used herein may be used interchangeably. For example, a CDMA network may implement wireless technologies such as universal terrestrial radio access (UTRA) and cdma2000. UTRA includes wideband-CDMA (W-CDMA) and low chip rate (LCR). CDMA2000 covers the IS-2000, IS-95, and IS-856 standards. TDMA networks can implement wireless technologies such as Global System for Mobile Communications (GSM). The 3rd Generation Partnership Project (3GPP), also known as GERAN, defines standards for GSM EDGE (GSM Evolutionary High-Speed ​​Data Rate) radio access networks (RAN). OFDMA networks can implement wireless technologies such as evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, and flash OFDM.UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunication System (UMTS). In particular, Long-Term Evolution (LTE) is a UMTS release that uses E-UTRA. Various different network types may use different radio access technologies (RATs) and RANs.

[0079]

[0091] While this application describes embodiments and implementations by example to several embodiments, those skilled in the art will understand that additional implementations and use cases may arise in many different configurations and scenarios. The innovations described herein can be realized across many different platform types, devices, systems, forms, sizes, and packaging configurations. For example, implementations or applications may occur via integrated chip implementations or other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail or purchasing devices, medical devices, AI-enabled devices, etc.). Some examples may or may not specifically address use cases or applications, but a wide range of applicable combinations of the innovations described may arise. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more of the described embodiments. In some practical settings, devices incorporating the embodiments and features described may also necessarily include additional components and features for the implementation and practice of the claims and embodiments described. The innovations described herein can be implemented in a wide variety of implementation forms, including both large and small devices of various sizes, shapes, and structures, chip-level components, multi-component systems (e.g., radio frequency (RF) chains, communication interfaces, processors), distributed configurations, and end-user devices.

[0080]

[0092] In one or more embodiments, techniques for supporting data storage and / or data transmission may include additional embodiments, such as any single embodiment or any combination of embodiments, described below or elsewhere in this specification with respect to one or more other processes or devices. In a first embodiment, an electronic device such as a UE may be a device such as a host device that includes a memory controller configured to interface to a memory system, and the memory system may be integrated with the host device or coupled externally to the host device. The memory system may include a memory controller which is coupled to the memory system through a channel and configured to access data stored in the memory system through the channel, is coupled to a host device through a memory interface and configured to communicate with the host device through the memory interface. The operation may be performed as part of an initialization operation, a read operation, or a write operation.

[0081]

[0093] In a first embodiment, the memory controller of a memory system may be configured to perform operations including receiving a first write request from a host device through a memory interface to write data to a replay-protected memory block (RPMB) portion of a memory module; determining the result of the first write request; and storing the instruction for the result of the first write request, associated with the instruction for the first write request, in a table of the RPMB portion of the memory module.

[0082]

[0094] In a second embodiment, in combination with the first embodiment, the memory controller of the memory system may be further configured to perform operations including receiving a first read request from a host device through the memory interface for reading the result of a first write request, and sending a first write request result instruction to the host device through the memory interface based on a stored instruction for the first write request result associated with the instruction for the first write request.

[0083]

[0095] In a third aspect, in combination with one or more of the first or second aspects, the first write request includes an instruction for a virtual machine (VM) identifier (ID), and the stored instruction of the first write request includes an instruction for a VM ID.

[0084]

[0096] In the fourth aspect, in combination with one or more of the first to third aspects, the first read request includes an instruction for the VM ID.

[0085]

[0097] In a fifth aspect, in combination with one or more of the first to fourth aspects, determining the result of a first write request includes determining that the write request was successful, the memory controller is further configured to perform an operation including receiving a second write request to write data to the RPMB portion of the memory module, determining that the result of the second write request was unsuccessful, and storing the instruction for the result of the second write request associated with the instruction for the second write request in a table of the RPMB portion of the memory module, and transmitting the instruction for the result of the first write request includes transmitting an instruction that the first write request was successful.

[0086]

[0098] In the sixth aspect, the first write request is a priority write request, in combination with one or more of the first to fifth aspects.

[0087]

[0099] In the seventh aspect, in combination with one or more of the first to sixth aspects, the table includes multiple instructions for the results of each write request associated with each instruction of each write request.

[0088]

[0100] In the eighth aspect, determining the result of a first write request in combination with one or more of the first to seventh aspects includes determining whether the first write request is successful or unsuccessful.

[0089]

[0101] In the ninth aspect, the apparatus, including the method, comprises a universal flash storage (UFS) device, in combination with one or more of the first to eighth aspects.

[0090]

[0102] In a tenth aspect, the host device's memory controller is configured to perform operations including: sending a first write request to the memory system via a memory interface to write data to a replay-protected memory block (RPMB) portion of a memory module in the memory system; sending a first read request to the memory system via a memory interface to read the result of the first write request from a table of the RPMB portion of a memory module in the memory system; and receiving instructions from the memory system via a memory interface regarding the result of the first write request.

[0091]

[0103] In the eleventh aspect, in combination with the tenth aspect, the first write request includes an instruction for a virtual machine (VM) identifier (ID).

[0092]

[0104] In the twelfth aspect, in combination with one or more of the tenth to eleventh aspects, the first read request includes an instruction for the VM ID.

[0093]

[0105] In the 13th aspect, the first write request is a priority write request, in combination with one or more of the 10th to 12th aspects.

[0094]

[0106] In the 14th aspect, in combination with one or more of the 10th to 13th aspects, the table includes multiple instructions for the results of each write request associated with each instruction of each write request.

[0095]

[0107] In the 15th aspect, in combination with one or more of the 10th to 14th aspects, the indication of the result of the first write request includes an indication of whether the first write request was successful or unsuccessful.

[0096]

[0108] In the sixteenth aspect, the memory system includes a universal flash storage (UFS) device in combination with one or more of the tenth to fifteenth aspects.

[0097]

[0109] Those skilled in the art will understand that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips which may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0098]

[0110] With respect to Figures 1 to 6, the components, functional blocks, and modules described herein include, in particular, processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, or any combination thereof. Software, whether called software, firmware, middleware, microcode, hardware description language, or otherwise, should be broadly interpreted in the examples to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, and / or functions. In addition, the features discussed herein may be implemented via dedicated processor circuits, via executable instructions, or a combination thereof.

[0099]

[0111] Those skilled in the art will know that one or more blocks (or actions) described with reference to Figure 4, Figure 5, or Figure 6 can be combined with one or more blocks (or actions) described with reference to another of the figures. For example, one or more blocks (or actions) in Figure 1 can be combined with one or more blocks (or actions) in Figure 3. As another example, one or more blocks associated with Figure 1 can be combined with one or more blocks (or actions) associated with Figure 4, Figure 5, or Figure 6. As an addition or alternative, one or more actions described above with reference to Figures 1-3 can be combined with one or more actions described with reference to Figures 4-6.

[0100]

[0112] Those skilled in the art will further understand that various exemplary logic blocks, modules, circuits, and algorithmic steps described herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware-software compatibility, various exemplary components, blocks, modules, circuits, and steps have been outlined above in relation to their functions. Whether such functions are implemented as hardware or executed as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways for specific applications, but such decisions regarding implementation should not be construed as causing a departure from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure may be combined or implemented in ways other than those shown and described herein.

[0101]

[0113] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in relation to the implementations disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. Hardware and software compatibility is generally described in terms of functionality and is shown in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0102]

[0114] Hardware and data processing devices used to implement the various exemplary logics, logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or realized using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration. In some implementations, specific processes and methods may be performed by circuit mechanisms specific to a given function.

[0103]

[0115] In one or more embodiments, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, or any combination thereof, including the structures disclosed herein and their structural equivalents. Implementations of the subject matter described herein may also be implemented as one or more computer programs, which are one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device.

[0104]

[0116] When implemented in software, the functionality may be stored on or transmitted via a computer-readable medium as one or more instructions or code. The processes of the methods or algorithms disclosed herein may be executed in a processor-executable software module that resides on a computer-readable medium. Computer-readable medium includes both computer storage media and communication media, including any media that can enable the transfer of computer programs from one location to another. Storage media may be any available media that can be accessed by a computer. Such computer-readable media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Any connection may also be appropriately referred to as computer-readable medium. The terms "Disk" and "Disc" as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disk typically reproduces data magnetically, while a disc reproduces data optically using a laser. Any combination of these should also be included within the scope of computer-readable media. In addition, the operation of a method or algorithm may reside on machine-readable and computer-readable media, which may be incorporated into computer program products as one or any combination or set of code and instructions.

[0105]

[0117] Various modifications of the implementations described herein may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to several other implementations without departing from the spirit or scope of this disclosure. Accordingly, the claims should not be limited to the implementations shown herein, but should be given the broadest scope consistent with this disclosure, the principles disclosed herein, and novel features.

[0106]

[0118] In addition, it will be readily understood by those skilled in the art that antonyms such as "top" and "bottom," or "front" and "back," or "upper" and "lower," or "front" and "rear," are sometimes used to facilitate the description of a figure and indicate a relative position corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device being implemented.

[0107]

[0119] Some features described herein in the context of separate implementations may also be realized in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be realized separately or in any suitable partial combination in multiple implementations. Furthermore, even if features have been described above as functioning in a particular combination and are initially claimed as such, one or more features from the claimed combination may, in some cases, be removed from that combination, and the claimed combination may cover partial combinations or variations of partial combinations.

[0108]

[0120] Similarly, while actions are shown in a specific order in the diagrams, this should not be understood as requiring that such actions be performed in a specific or sequential order shown, or that all shown actions be performed, in order to achieve the desired result. Furthermore, diagrams may schematically represent one or more exemplary processes in the form of flow charts. However, other actions not shown may be incorporated into the schematicly represented exemplary processes. For example, one or more additional actions may be performed before, after, simultaneously with, or between any of the shown actions. In some situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementation forms described above should not be understood as requiring such separation in all implementation forms, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. In addition, several other implementation forms fall within the scope of the following claims. In some cases, the actions enumerated in the claims may be performed in a different order and still achieve the desired result.

[0109]

[0121] As used herein, including in the claims, the term “or” means that, when used in a list of two or more items, any one of the listed items may be taken alone, or any combination of two or more of the listed items may be taken. For example, if a composition is described as containing component A, B, or C, the composition may include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C. Also, as used herein, including in the claims, “or” means a disjunctive list, such as when the list “at least one of A, B, or C” means any of these in A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C), or any combination thereof. As those skilled in the art will understand, the term “substantially” means the majority of what is specified (for example, substantially 90 degrees includes 90 degrees, substantially parallel includes parallel), but not necessarily the whole. In any disclosed implementation, the term “substantially” may be replaced with “within [percentage] of” the specified percentage, including 0.1 percent, 1 percent, 5 percent, or 10 percent.

[0110]

[0122] The above description in this disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. It is a device, It is a memory controller, It is connected to a memory module through a channel and is configured to access data stored in the memory module through the channel. A memory controller is connected to a host device via a memory interface and configured to communicate with the host device via the memory interface, The aforementioned memory controller The memory interface receives a first write request from the host device to write data to the replay-protected memory block (RPMB) portion of the memory module, Determine the result of the first write request, The instruction for the result of the first write request, associated with the instruction for the first write request, is stored in the table of the RPMB portion of the memory module. A device configured to perform operations including those mentioned above.

2. The aforementioned memory controller The memory interface receives a first read request from the host device for reading the result of the first write request, To transmit instructions for the result of the first write request to the host device via the memory interface, based on the stored instructions for the result of the first write request associated with the instructions for the first write request, The apparatus according to claim 1, further configured to perform an operation including the operation.

3. The apparatus according to claim 2, wherein the first write request includes an instruction for a virtual machine (VM) identifier (ID), and the stored instruction of the first write request includes an instruction for the VM ID.

4. The apparatus according to claim 3, wherein the first read request includes an instruction for the VM ID.

5. Determining the result of the first write request includes determining that the write request was successful, and the memory controller Receiving a second write request to write data to the RPMB portion of the memory module, The result of the second write request described above is determined to be a failure, The instruction for the result of the second write request, associated with the instruction for the second write request, is stored in the table of the RPMB portion of the memory module. It is further configured to perform actions including, The apparatus according to claim 2, wherein transmitting the instruction for the result of the first write request includes transmitting an instruction that the first write request was successful.

6. The apparatus according to claim 1, wherein the first write request is a priority write request.

7. The apparatus according to claim 1, wherein the table includes a plurality of instructions for the results of each write request associated with each instruction of each write request.

8. The apparatus according to claim 1, wherein determining the result of the first write request includes determining whether the first write request is successful or unsuccessful.

9. The apparatus according to claim 1, wherein the apparatus comprises a universal flash storage (UFS) device.

10. It is a method, The memory controller of the memory system receives a first write request through the memory interface that connects the memory system to a host device, for writing data to the replay-protected memory block (RPMB) portion of a memory module in the memory system. Determine the result of the first write request, The instruction for the result of the first write request, associated with the instruction for the first write request, is stored in the table of the RPMB portion of the memory module. Methods that include...

11. The memory interface receives a first read request from the host device for reading the result of the first write request, To transmit the instruction for the result of the first write request to the host device via the memory interface, based on the stored instruction for the result of the first write request, The method according to claim 10, further comprising:

12. The method according to claim 11, wherein the first write request includes an instruction for a virtual machine (VM) identifier (ID), and the stored instruction of the first write request includes an instruction for the VM ID.

13. The method according to claim 12, wherein the first read request includes an instruction for the VM ID.

14. Determining the result of the first write request includes determining that the write request was successful. Receiving a second write request to write data to the RPMB portion of the memory module, The result of the second write request described above is determined to be a failure, The instruction for the result of the second write request, associated with the instruction for the second write request, is stored in the table of the RPMB portion of the memory module. It further includes, The method according to claim 11, wherein transmitting the instruction for the result of the first write request includes transmitting an instruction that the first write request was successful.

15. The method according to claim 10, wherein the first write request is a priority write request.

16. The method according to claim 10, wherein the table includes a plurality of instructions for the results of each write request associated with each instruction of each write request.

17. The method according to claim 10, wherein determining the result of the first write request includes determining whether the first write request is successful or unsuccessful.

18. The method according to claim 11, wherein the memory system includes a universal flash storage (UFS) device.

19. It is a device, The host device comprises a memory controller configured to connect the host device to a memory system via a memory interface, wherein the memory controller Sending a first write request to the memory system via the memory interface for writing data to the replay protection memory block (RPMB) portion of the memory module of the memory system, A first read request is sent to the memory system via the memory interface to read the result of the first write request from the table of the RPMB portion of the memory module of the memory system. The memory system receives an instruction for the result of the first write request through the memory interface, A device configured to perform operations including those mentioned above.

20. The apparatus according to claim 19, wherein the first write request includes an instruction for a virtual machine (VM) identifier (ID).

21. The apparatus according to claim 20, wherein the first read request includes an instruction for the VM ID.

22. The apparatus according to claim 19, wherein the first write request is a priority write request.

23. The apparatus according to claim 19, wherein the table includes a plurality of instructions for the results of each write request associated with each instruction of each write request.

24. The apparatus according to claim 19, wherein the instruction for the result of the first write request includes an instruction indicating whether the first write request was successful or unsuccessful.

25. The apparatus according to claim 19, wherein the memory system includes a universal flash storage (UFS) device.

26. It is a method, The host device's memory controller transmits a first write request to the memory system coupled to the host device via the memory interface, for writing data to the replay-protected memory block (RPMB) portion of the memory module of the memory system. A first read request is sent to the memory system via the memory interface to read the result of the first write request from the table of the RPMB portion of the memory module of the memory system. The memory system receives an instruction for the result of the first write request through the memory interface, Methods that include...

27. The method according to claim 26, wherein the first write request includes an instruction for a virtual machine (VM) identifier (ID).

28. The method according to claim 27, wherein the first read request includes an instruction for the VM ID.

29. The method according to claim 26, wherein the first write request is a priority write request.

30. The method according to claim 26, wherein the table includes a plurality of instructions for the results of each write request associated with each instruction of each write request.

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