Rear-side power supply network-type embedded chiplet

Abstract

The electronic assembly may include a base element having a base substrate having a front side and a back side opposite to the front side with active circuit components, a first bonding layer provided on the front side of the base substrate, and a signal pad for sending electrical signals to the active circuit components on the front side of the base substrate. The electronic assembly may include a first functional element having a first semiconductor substrate having a front side and a back side opposite to the front side with active circuit components, and a second bonding layer provided on the front side of the first semiconductor substrate, wherein the back side of the first functional element has a first contact feature portion for connection to a power source or ground, and the first bonding layer is hybrid-bonded to the second bonding layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor device structures and methods. In particular, some embodiments relate to methods and structures for providing backside power delivery to embedded chiplets.

[0002]

Citation of Related Applications

Background Art

[0003] The approaches described in this section are possible approaches, but are not necessarily approaches that have been previously conceived or achieved. Accordingly, unless otherwise indicated, any of the approaches described in this section should not be regarded as having the status of prior art merely by virtue of being incorporated in this section.

Summary of the Invention

Problems to be Solved by the Invention

[0004] As the feature components of semiconductor devices continue to miniaturize, concerns about power supply issues are increasing. Electrical isolation problems, constraints on feature size due to high-density circuit elements and interconnects, and losses due to power flow across numerous metal layers can make it difficult to efficiently supply power to semiconductor devices. The close spacing between back-side interconnects can also cause interference between power supply and signal transmission. Therefore, improvements to semiconductor device assemblies are necessary. [Means for solving the problem]

[0005] Each of the systems, methods, and apparatus described herein has several aspects, and not just one of these aspects represents its desired attribute. Now, without limiting the scope of this disclosure, we will broadly describe some non-limiting features.

[0006] In some embodiments, the technology described herein relates to an electronic assembly, the electronic assembly including a base substrate having a front side and a back side opposite to the front side on which active circuit components are provided, a first bonding layer provided on the front side of the base substrate, the first bonding layer having signal pads for sending electrical signals to active circuit components on the front side of the base substrate, the electronic assembly further includes a first semiconductor substrate having a front side and a back side opposite to the front side on which active circuit components are provided, and a first functional element having a second bonding layer provided on the front side of the first semiconductor substrate, the back side of the first functional element having a first contact feature portion for connection to a power source or ground, and the first bonding layer is hybrid-bonded to the second bonding layer.

[0007] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further comprising an insulating material provided along the side surface of a first functional element and on a first bonding layer.

[0008] In some respects, the technology described herein relates to electronic assemblies, where the insulating material consists of an inorganic dielectric.

[0009] In some respects, the technology described herein relates to electronic assemblies, where the insulating material is silicon oxide.

[0010] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material consists of an organic dielectric.

[0011] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material is made of low-temperature tetraethyl orthosilicate.

[0012] In some respects, the technology described herein relates to an electronic assembly, which further includes an interconnect structure provided on the back surface of a first functional element and electrically connected to a first contact feature portion.

[0013] In some respects, the technology described herein relates to electronic assemblies, where the interconnect structure consists of redistribution layers.

[0014] In some respects, the technology described herein relates to electronic assemblies, where the interconnect structure comprises one or more metallization layers.

[0015] In some respects, the technology described herein relates to an electronic assembly, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back surface of the interconnect structure, and the global interconnect layer being located on the intermediate interconnect layer and closer to the front surface of the interconnect structure than the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect layer.

[0016] In some respects, the technology described herein relates to an electronic assembly in which the interconnect structure further has input / output (IO) pads located near the front surface of the interconnect structure, the IO pads being in electrical contact with a global interconnect layer, and the IO pads being exposed at the front surface of the interconnect structure.

[0017] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further includes a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side.

[0018] In some respects, the technology described herein relates to an electronic assembly in which a second functional element has a third bonding layer provided on the front side of a second semiconductor substrate, the third bonding layer being hybrid-bonded to a first bonding layer.

[0019] In some respects, the technology described herein relates to an electronic assembly in which the back side of a second functional element is hybrid-bonded to a first bonding layer, and the second functional element has a second contact feature portion provided on the front surface of the second functional element.

[0020] In some embodiments, the technology described herein relates to an electronic assembly, the electronic assembly comprising a base element having a base substrate having a front side and a back side opposite to the front side, and a first bonding layer provided on the front side of the base substrate; the electronic assembly further comprises a first functional element having a first semiconductor substrate having a front side and a back side opposite to the front side on which active circuit components are provided, and a second bonding layer provided on the front side of the first semiconductor substrate, wherein the back side of the first functional element has a first contact feature portion connected to a power source or ground; the electronic assembly further comprises a second functional element having a second semiconductor substrate having a front side and a back side opposite to the front side on which active circuit components are provided, wherein the first bonding layer is hybrid-bonded to the second bonding layer, and the second semiconductor element is hybrid-bonded to the base element.

[0021] In some respects, the technology described herein relates to an electronic assembly in which the back side of a second semiconductor substrate is hybrid-bonded to a base element, and the second functional element has a second contact feature provided on the front side of the second functional element for connection to a power source or ground.

[0022] In some respects, the technology described herein relates to an electronic assembly in which the front side of a second functional element is hybrid-bonded to the front surface of a base substrate, and the back side of the second functional element has a second contact feature portion connected to a power source or ground.

[0023] In some respects, the technology described herein relates to an electronic assembly in which a first bonding layer has contact features for transmitting electrical signals to active circuit components on the front side of a base substrate.

[0024] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further includes an insulating material provided along the side surface of a first functional element and on a first bonding layer.

[0025] In some aspects, the technology described herein relates to an electronic assembly, and the insulating material is made of an inorganic dielectric.

[0026] In some aspects, the technology described herein relates to an electronic assembly, and the insulating material is made of silicon oxide.

[0027] In some aspects, the technology described herein relates to an electronic assembly, and the insulating material is made of an organic dielectric.

[0028] In some aspects, the technology described herein relates to an electronic assembly, and the insulating material is made of low-temperature tetraethyl orthosilicate.

[0029] In some aspects, the technology described herein relates to an electronic assembly, the electronic assembly is provided on the back side of a first semiconductor substrate, and further includes an interconnect structure electrically connected to a first contact feature.

[0030] In some aspects, the technology described herein relates to an electronic assembly, and the interconnect structure is made of a redistribution layer.

[0031] In some aspects, the technology described herein relates to an electronic assembly, and the interconnect structure is made of one or more metallization layers.

[0032] In some aspects, the technology described herein relates to an electronic assembly, the interconnect structure has an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer is provided near the back surface of the interconnect structure, the global interconnect layer is provided on the intermediate interconnect layer closer to the front surface of the interconnect structure than the intermediate interconnect layer, and the intermediate interconnect layer is in electrical communication with the global interconnect layer.

[0033] In some respects, the technology described herein relates to an electronic assembly in which the interconnect structure further has input / output (IO) pads located near the front surface of the interconnect structure, the IO pads being in electrical contact with a global interconnect layer, and the IO pads being exposed at the front surface of the interconnect structure.

[0034] In some respects, the technology described herein relates to an electronic assembly, which further includes a base logic substrate having a front and back side on which an active region is provided, and a base interconnect layer provided on the front side of the base logic substrate, the base interconnect layer being hybrid bonded to the back side of a first semiconductor substrate.

[0035] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further includes an interconnect structure having a front surface and a back surface, the back surface of the interconnect structure being located on the back side of a base logic board.

[0036] In some embodiments, the technology described herein relates to an electronic assembly, the electronic assembly comprising a base element having a front surface and a back surface opposite to the front surface, and a first functional element having a substrate having a front surface and a back surface opposite to the front surface, wherein the front surface of the first functional element is electrically connected to the front surface of the base element while being provided on the front surface of the base element, the electronic assembly further comprises a second functional element having a substrate having a front surface and a back surface opposite to the front surface on which an active region is provided, and an interconnect structure being electrically connected to the back surface of the substrate of the first functional element while being provided on the back surface of the substrate, the first functional element having power and ground connections provided on the back surface, the first functional element having signal connections provided on the front surface, and the front surface of the first functional element is hybrid bonded to the front surface of the base element.

[0037] In some respects, the technology described herein relates to an electronic assembly, wherein the base element further comprises a base die substrate having a front side and a back side, and a base die interconnect structure provided on the front side of the base die substrate.

[0038] In some respects, the technology described herein relates to an electronic assembly, wherein the base die substrate further comprises a base die active region provided on the front side of the base die substrate.

[0039] In some respects, the technology described herein relates to an electronic assembly, wherein the base die interconnect structure has a local interconnect layer and an intermediate interconnect layer, the local interconnect layer of the base die interconnect structure is electrically connected to the base die active region, the intermediate interconnect layer of the base die interconnect structure is electrically connected to the local interconnect layer of the base die interconnect structure, and the intermediate interconnect layer of the base die interconnect structure is electrically connected to the interconnect structure.

[0040] In some respects, the technology described herein relates to electronic assemblies, and the interconnect structure has a redistribution layer.

[0041] In some respects, the technology described herein relates to electronic assemblies, wherein the interconnect structure has one or more metallization layers.

[0042] In some respects, the technology described herein relates to electronic assemblies, in which the base die interconnect structure has a redistribution layer.

[0043] In some respects, the technology described herein relates to an electronic assembly in which the base die interconnect structure has one or more metallization layers.

[0044] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further comprising an insulating material provided along the side surface of a first functional element and on a first bonding layer.

[0045] In some respects, the technology described herein relates to electronic assemblies, where the insulating material consists of an inorganic dielectric.

[0046] In some respects, the technology described herein relates to electronic assemblies, where the inorganic dielectric is silicon oxide.

[0047] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material consists of an organic dielectric.

[0048] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material is made of low-temperature tetraethyl orthosilicate.

[0049] In some respects, the technology described herein relates to an electronic assembly, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back of the interconnect structure, the global interconnect layer being located on top of the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect.

[0050] In some respects, the technology described herein relates to an electronic assembly in which the interconnect structure further has input / output (IO) pads provided on the top surface of a global interconnect layer, the IO pads being exposed at the top surface of the interconnect structure, and the top surface of the global interconnect layer is one side of the global interconnect layer furthest from the first functional element.

[0051] In some respects, the technology described herein relates to an electronic assembly in which the first functional element further has a plurality of vias extending from the back of the first functional element to the active region of the first functional element to electrically connect an interconnect structure to the active region of the first functional element.

[0052] In some respects, the technology described herein relates to an electronic assembly, wherein the second functional element comprises a front surface and a back surface.

[0053] In some respects, the technology described herein relates to an electronic assembly in which the front surface of a second functional element is provided on the front surface of a base element, and the interconnect structure is further provided on the back surface of the second functional element.

[0054] In some respects, the technology described herein relates to an electronic assembly in which the back surface of a second functional element is located on the front surface of a base element.

[0055] In some respects, the technology described herein relates to an electronic assembly in which the front surface of a first functional element is hybrid-bonded to the front surface of a base element, and the front surface of a second functional element is hybrid-bonded to the front surface of a base element.

[0056] In some respects, the technology described herein relates to an electronic assembly in which the back surface of a second functional element is hybrid-bonded to the front surface of a base element.

[0057] In some respects, the technology described herein relates to an electronic assembly in which a second functional element is electrically connected to either a power source or ground via the back side of the second functional element.

[0058] In some respects, the technology described herein relates to an electronic assembly in which a second functional element is electrically connected to a power source or ground via the back surface of the second functional element, and the second functional element has signal and electrical contact features provided on the front surface of the second functional element.

[0059] In some respects, the technology described herein relates to an electronic assembly, wherein the base element has a base die interconnect structure, and the base die interconnect structure has an integrated voltage regulator.

[0060] In some respects, the technology described herein relates to an electronic assembly in which a first functional element directly receives power from a base die interconnect structure at a first voltage, a second functional element receives power at a second voltage different from the first voltage, and the second functional element receives power routed from the base die interconnect structure to an integrated voltage regulator.

[0061] In some respects, the technology described herein relates to an electronic assembly, wherein the second functional element has power and ground electrical contact features provided on the back surface of the second functional element.

[0062] In some respects, the technology described herein relates to an electronic assembly, wherein the second functional element has power and ground electrical connections provided on the front side of the second functional element.

[0063] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further includes vias extending from an interconnect structure to the front surface of a base element.

[0064] In some respects, the technology described herein relates to electronic assemblies, and the interconnect structure further comprises mixed-signal elements.

[0065] In some respects, the technology described herein relates to electronic assemblies, and the interconnect structure further comprises passive elements.

[0066] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further includes a heat spreader provided on the back surface of a base element.

[0067] In some respects, the technology described herein relates to an electronic assembly, which further includes a base logic substrate having a front and back side on which an active region is provided, and a base interconnect layer provided on the front side of the base logic substrate, the base interconnect layer being hybrid bonded to the back side of a first functional element.

[0068] In some respects, the technique described herein relates to a method, the method comprising the step of preparing a base element, the base element having a front surface, a back surface, and a base element contact feature portion provided on the front surface of the base element to electrically connect to a first functional element having a front surface and a back surface, the method further comprising the steps of bonding the front surface of the first functional element to the front surface of the base element, forming an insulating material on the side surface of the first functional element, and forming an interconnect structure on the back surface of the first functional element and the insulating material, the back surface of the first functional element having a power and ground electrical contact feature portion, the front surface of the first functional element having a signal and electrical contact feature portion, and the interconnect structure being electrically connected to the power and ground electrical contact feature portion of the first functional element.

[0069] In some respects, the techniques described herein relate to methods, where the step of bonding the front surface of a first functional element to the front surface of a base element includes the step of hybrid bonding the front surface of the first functional element to the front surface of a base element.

[0070] In some respects, the techniques described herein relate to methods, wherein the base element further comprises a base die substrate having a front side and a back side, and a base die interconnect structure provided on the front side of the base substrate.

[0071] In some respects, the techniques described herein relate to methods, wherein the base die substrate has a base die active region provided on the front side of the base die substrate.

[0072] In some respects, the technique described herein relates to a method wherein the base die interconnect structure has a local interconnect layer and an intermediate interconnect layer, the local interconnect layer of the base die interconnect structure is electrically connected to the base die active region, the intermediate interconnect layer of the base die interconnect structure is electrically connected to the local interconnect layer of the base die interconnect structure, and the intermediate interconnect layer of the base die interconnect structure is electrically connected to the interconnect structure.

[0073] In some respects, the techniques described herein relate to methods in which the interconnect structure has a rewiring layer. The method described in section 63.

[0074] In some respects, the techniques described herein relate to methods in which the interconnect structure has one or more metallization layers.

[0075] In some respects, the techniques described herein relate to methods in which the base die interconnect structure has a redistribution layer.

[0076] In some respects, the techniques described herein relate to methods in which the base die interconnect structure has one or more metallization layers.

[0077] In some respects, the techniques described herein relate to methods, where the insulating material consists of an inorganic dielectric.

[0078] In some respects, the techniques described herein relate to methods in which the inorganic dielectric consists of silicon oxide.

[0079] In some respects, the techniques described herein relate to methods, where the insulating material consists of an organic dielectric.

[0080] In some respects, the techniques described herein relate to methods in which the insulating material is made of low-temperature tetraethyl orthosilicate.

[0081] In some respects, the technique described herein relates to a method, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back of the interconnect structure, the global interconnect layer being located on top of the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect.

[0082] In some respects, the techniques described herein relate to methods, wherein the interconnect structure further comprises input / output (IO) pads located on the top surface of the global interconnect layer, the IO pads being exposed at the top surface of the interconnect structure.

[0083] In some respects, the technique described herein relates to a method wherein the first functional element further comprises a first functional element active region located near the front surface of the first functional element, and the interconnect structure supplies power or ground to the first functional element active region via the back surface of the first functional element.

[0084] In some respects, the techniques described herein relate to methods in which the interconnect structure has a plurality of nanovias extending from the back surface of the first functional element to the active region of the first functional element.

[0085] In some respects, the technique described herein relates to a method, further comprising the step of bonding a second functional element to the front surface of a base element, wherein the second functional element has a front surface and a back surface, and the second functional element is bonded to the front surface of the base element via the front surface of the second functional element.

[0086] In some respects, the technique described herein relates to a method in which the front surface of a second functional element is hybrid-bonded to the front surface of a base element.

[0087] In some respects, the technique described herein relates to a method in which the front surface of a first functional element is hybrid-bonded to the front surface of a base element.

[0088] In some respects, the technique described herein relates to a method in which the front surface of a first functional element is hybrid-bonded to the front surface of a base element, and the front surface of a second functional element is hybrid-bonded to the front surface of a base element.

[0089] In some respects, the technique described herein relates to a method, wherein the second functional element is electrically connected to a power source or ground via the front surface of the second functional element.

[0090] In some respects, the techniques described herein relate to methods, wherein the second functional element has electrical connections to a power supply and ground provided on the back surface of the second functional element, and the second functional element has electrical connections to a signal and electrical connection provided on the front surface of the functional element.

[0091] In some respects, the technique described herein relates to a method, the method further comprising the step of forming an electrical interconnect extending from the top surface of an insulating material to the bottom surface of an insulating material, the bottom surface of the insulating material being in contact with the top surface of a base element.

[0092] In some respects, the techniques described herein relate to methods, wherein the interconnect structure further comprises mixed-signal elements.

[0093] In some respects, the techniques described herein relate to methods, and the interconnect structure further comprises passive elements.

[0094] In some respects, the techniques described herein relate to methods, the methods further comprising the step of placing a heat spreader in thermal contact with the back surface of a base element.

[0095] In some respects, the techniques described herein relate to methods in which the base element has a base die interconnect structure with an integrated voltage regulator.

[0096] In some respects, the technique described herein relates to a method in which a first functional element directly receives power from a base die interconnect structure at a first voltage, a second functional element receives power at a second voltage different from the first voltage, and the second functional element receives power routed from the base die interconnect structure to an integrated voltage regulator.

[0097] In some respects, the techniques described herein relate to methods, the methods further comprising the steps of: forming a base logic substrate having a front side and a back side on which an active region is provided; forming a base interconnect layer provided on the front side of the base logic substrate; and hybrid bonding the base interconnect layer to the back side of a first functional element.

[0098] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming a base die interconnect structure having a front surface and a back surface, the back surface of the base die interconnect structure being provided on the back side of a base logic substrate.

[0099] In some embodiments, the technology described herein relates to a method, the method comprising the step of preparing a base element, the base element having a base substrate having a front side on which an active circuit component is provided and a back side opposite to the front side, and a first bonding layer provided on the front side of the base substrate, the first bonding layer having contact features for sending electrical signals to the active circuit component; the method further comprises the step of preparing a first functional element, the first functional element having a first semiconductor substrate having a front side on which an active circuit component is provided and a back side opposite to the front side, a first contact feature provided on the back side of the first functional element and also configured to be connected to a power source or ground, and a second bonding layer provided on the front side of the first semiconductor substrate; the method further comprises the step of hybrid bonding the first bonding layer of the base element to the second bonding layer of the first functional element.

[0100] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming an insulating material along the side surface of a first functional element and provided on a first bonding layer.

[0101] In some respects, the techniques described herein relate to methods, where the insulating material consists of an inorganic dielectric.

[0102] In some respects, the techniques described herein relate to methods, where the insulating material consists of silicon oxide.

[0103] In some respects, the techniques described herein relate to methods, where the insulating material consists of an organic dielectric.

[0104] In some respects, the techniques described herein relate to methods in which the insulating material is made from low-temperature tetraethyl orthosilicate.

[0105] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming an interconnect structure that is provided on the back surface of a first functional element and is also electrically connected to a first contact feature portion.

[0106] In some respects, the techniques described herein relate to methods in which the interconnect structure has a rewiring layer.

[0107] In some respects, the techniques described herein relate to methods in which the interconnect structure has one or more metallization layers.

[0108] In some respects, the technique described herein relates to a method, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back surface of the interconnect structure, and the global interconnect layer being located on the intermediate interconnect layer and closer to the front surface of the interconnect structure than the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect layer.

[0109] In some respects, the technique described herein relates to a method wherein the interconnect structure further comprises input / output (IO) pads located near the front surface of the interconnect structure, the IO pads being in electrical contact with the global interconnect layer, and the IO pads being exposed at the front surface of the interconnect structure.

[0110] In some respects, the techniques described herein further include, with respect to the method, the step of providing a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side.

[0111] In some respects, the technique described herein relates to a method, wherein the second functional element has a third bonding layer provided on the front side of a second semiconductor substrate, and the third bonding layer is hybrid-bonded to the first bonding layer.

[0112] In some respects, the technology described herein relates to a method, the method further comprising the step of hybrid bonding the back side of a second functional element to a first bonding layer, wherein the second functional element has a second contact feature provided on the front surface of the second functional element.

[0113] In some embodiments, the technology described herein relates to a method, the method comprising the step of preparing a base element, the base element having a base substrate having a front side and a back side opposite to the front side, and a first bonding layer provided on the front side of the base substrate; the method further comprises the step of providing a first functional element, the first functional element having a first semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, and a second bonding layer provided on the front side of the first semiconductor substrate, the back side of the first semiconductor substrate having a first contact feature portion connected to a power source or ground; the method further comprises the step of providing a second functional element, the second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, the method further comprises the step of hybrid bonding the first bonding layer to the second bonding layer, and the step of hybrid bonding the second functional element to the first bonding layer.

[0114] In some respects, the techniques described herein, relating to a method, further include the step of hybrid bonding the back side of a second semiconductor substrate to a base element, wherein the second functional element has a second contact feature provided on the front side of the second semiconductor substrate for connection to a power source or ground.

[0115] In some respects, the technology described herein relates to a method, the method further comprising the step of hybrid bonding the front side of a second functional element to a first bonding layer, the back side of the second semiconductor element having a second contact feature for connection to a power source or ground.

[0116] In some respects, the techniques described herein relate to methods, wherein the first bonding layer has contact features for transmitting electrical signals to active circuit components.

[0117] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming along the side surface of a first functional element and on a first bonding layer.

[0118] In some respects, the techniques described herein relate to methods, where the insulating material consists of an inorganic dielectric.

[0119] In some respects, the techniques described herein relate to methods, where the insulating material consists of silicon oxide.

[0120] In some respects, the techniques described herein relate to methods, where the insulating material consists of an organic dielectric.

[0121] In some respects, the techniques described herein relate to methods in which the insulating material is made from low-temperature tetraethyl orthosilicate.

[0122] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming an interconnect structure that is provided on the back side of a first semiconductor substrate and is also electrically connected to a first contact feature portion.

[0123] In some respects, the techniques described herein relate to methods in which the interconnect structure has a rewiring layer.

[0124] In some respects, the techniques described herein relate to methods in which the interconnect structure has one or more metallization layers.

[0125] In some respects, the technique described herein relates to a method, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back surface of the interconnect structure, and the global interconnect layer being located on the intermediate interconnect layer and closer to the front surface of the interconnect structure than the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect layer.

[0126] In some respects, the technique described herein relates to a method wherein the interconnect structure further comprises input / output (IO) pads located near the front surface of the interconnect structure, the IO pads being in electrical contact with the global interconnect layer, and the IO pads being exposed at the front surface of the interconnect structure.

[0127] In some respects, the techniques described herein relate to methods, the methods further comprising the steps of: preparing a base logic substrate having a front side and a back side on which an active region is provided; preparing a base interconnect layer provided on the front side of the base logic substrate; and hybrid bonding the base interconnect layer to the back side of a first semiconductor substrate.

[0128] In some respects, the techniques described herein relate to methods, the methods further comprising the step of forming an interconnect structure having a front surface and a back surface, the back surface of the interconnect structure being provided on the back side of a base logic board.

[0129] In some embodiments, the technology described herein relates to an electronic assembly, the electronic assembly comprising an interconnect structure having one or more input / output (IO) pads, and a first functional element having a first semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, wherein the front surface of the first functional element has a first contact feature portion connected to one or more IO pads, and the electronic assembly further comprises a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, wherein the back surface of the second functional element has a second contact feature portion connected to one or more IO pads.

[0130] In some respects, the technology described herein relates to an electronic assembly in which the first and second contact features are configured to be connected to a power source or ground.

[0131] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further comprising a base element, and a first functional element and a second functional element provided on the base element.

[0132] In some respects, the technology described herein relates to an electronic assembly, wherein the base element further comprises a base substrate having a front side on which active circuit components are provided and a back side opposite to the front side, a first bonding layer provided on the front side of the base substrate, and signal pads for sending electrical signals to the active circuit components on the front side of the base substrate.

[0133] In some respects, the technology described herein relates to an electronic assembly, which further includes a second bonding layer provided on the front side of a first semiconductor substrate, and a third bonding layer provided on the front side of the second semiconductor substrate, wherein the first bonding layer is hybrid-bonded to the second bonding layer, and the third bonding layer is hybrid-bonded to the first bonding layer.

[0134] In some respects, the technology described herein relates to an electronic assembly, the electronic assembly further comprising an insulating material provided along the side surface of a first functional element and on a first bonding layer.

[0135] In some respects, the technology described herein relates to electronic assemblies, where the insulating material consists of an inorganic dielectric.

[0136] In some respects, the technology described herein relates to electronic assemblies, where the insulating material is silicon oxide.

[0137] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material consists of an organic dielectric.

[0138] In some respects, the techniques described herein relate to electronic assemblies, where the insulating material is made of low-temperature tetraethyl orthosilicate.

[0139] In some respects, the technology described herein relates to an electronic assembly, which further includes an interconnect structure provided on the back side of a second semiconductor substrate and electrically connected to a second contact feature portion.

[0140] In some respects, the technology described herein relates to electronic assemblies, and the interconnect structure has a redistribution layer.

[0141] In some respects, the technology described herein relates to electronic assemblies, wherein the interconnect structure has one or more metallization layers.

[0142] In some respects, the technology described herein relates to an electronic assembly, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, the intermediate interconnect layer being located near the back surface of the interconnect structure, and the global interconnect layer being located on the intermediate interconnect layer and closer to the front surface of the interconnect structure than the intermediate interconnect layer, and the intermediate interconnect layer being in electrical contact with the global interconnect layer.

[0143] In some respects, the technology described herein relates to an electronic assembly in which the interconnect structure further has input / output (IO) pads located near the front surface of the interconnect structure, the IO pads being in electrical contact with a global interconnect layer, and the IO pads being exposed at the front surface of the interconnect structure.

[0144] Various combinations of the features, embodiments, and perspectives described above and below are also disclosed and assumed by this disclosure.

[0145] Additional embodiments of this disclosure are described below with reference to the appended claims, and these additional embodiments may serve as an additional summary of this disclosure.

[0146] These features, views, and advantages of the disclosure, as well as other features, views, and advantages, will be described with reference to drawings of certain embodiments, which are intended to illustrate the content of the disclosure but are not limited thereto. It should be understood that the accompanying drawings incorporated into and forming part of this specification are for illustrative purposes only and are not drawn to scale. [Brief explanation of the drawing]

[0147] [Figure 1] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 2] This diagram schematically illustrates a semiconductor device assembly according to several embodiments. [Figure 3] This diagram schematically shows power and ground delivery paths according to several embodiments. [Figure 4] This diagram schematically illustrates a semiconductor device assembly according to several embodiments. [Figure 5A] This figure schematically illustrates an example of a means of communication or contact between a base element and a functional element, according to several embodiments. [Figure 5B] This is a schematic diagram showing the means of communication between the first functional element and the second functional element. [Figure 6A] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 6B] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 7] This is a schematic plan view of an exemplary semiconductor device assembly according to several embodiments. [Figure 8] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 9] This figure schematically illustrates an example of a semiconductor device assembly according to several embodiments. [Figure 10A] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 10B] This figure schematically illustrates an exemplary semiconductor device assembly according to several embodiments. [Figure 11A] This diagram schematically illustrates the direct bonding process according to several embodiments. [Figure 11B] This diagram schematically illustrates the direct bonding process according to several embodiments. [Modes for carrying out the invention]

[0148] Several embodiments, examples, and illustrations are disclosed below, but as those skilled in the art will understand, the disclosures described herein extend beyond the embodiments, examples, and illustrations specifically disclosed, and also include other uses of the disclosure and obvious modifications and equivalents thereof. Examples are described with reference to the accompanying drawings, where the same reference numerals refer to the same elements throughout the specification. The terms used in the descriptions herein are not intended to be construed in any limiting or restrictive manner, as they are used simply in connection with detailed descriptions of some specific embodiments of the disclosure. In addition, embodiments may have some novel features. No single feature constitutes a desirable attribute, nor is it essential for carrying out the disclosures described herein.

[0149] Backside power supply addresses several problems associated with increased density and reduced feature area size by separating power supply from signal routing, for example, by having power supply delivered via the backside of the semiconductor device while signal routing is delivered via the frontside. However, backside power supply can be challenging to implement. In semiconductor devices utilizing functional elements (e.g., chiplets), it may be advantageous to provide backside power supply to some functional elements while using frontside power supply for others. The term "functional element" as used herein preferably consists of an integrated device die with active circuit components (e.g., one or more transistors). For example, certain functional elements, such as those used for processing units (CPUs) and graphics processing units (GPUs), may be manufactured using state-of-the-art process nodes with very small feature area sizes, while other functional elements, such as communication circuit components, may be manufactured using older process nodes with larger feature area sizes, in which case backside power supply offers only limited advantages. Some embodiments described herein can enable easier and / or less expensive deployment of back-side power supply in devices using multiple functional elements. In some cases, different functional elements manufactured at the same process technology node can employ different power supply methods. For example, a CPU can use back-side power supply, while static random-access memory (SRAM), which can be manufactured at the same technology node, can use front-side power supply, or vice versa. In some cases, front-side power supply may be suitable for functional elements with a conventional structure. For example, a memory functional element (e.g., SRAM) may have regularly arranged transistors or other circuit components, thereby simplifying power and signal routing compared to functional elements with less regular layouts, such as a CPU or GPU.

[0150] The terms "element" as used herein (for example, functional elements and / or base elements, each of which may consist of a semiconductor element in various embodiments) may have a front side and a back side. Examples of elements include substrates having a front side and a back side. An active region may be located in or on the substrate on or near the front side of the substrate (for example, closer to the front side than the back side). An interconnect may be located on top of the active region. The active region may include active circuit components, such as transistors. The active region may also be called a logic region or logic layer.

[0151] In conventional semiconductor devices, both signal transmission and power supply are achieved through the front side of the device. However, as device features continue to miniaturize, providing both power and signals through the front side of the device is becoming increasingly difficult. For example, as the density and complexity of semiconductor devices increase, with each advanced process node increasing the number of transistors or computer cells per unit area, the number of metal layers containing signal and power (or ground) lines for supplying these transistors also tends to increase, effectively increasing the path length of the wires carrying power and / or signals. As a result of the increased density of transistors in the active device region, the density of power and signal circuit components may increase accordingly. To accommodate this increased density, it is advisable to reduce the cross-sectional area of ​​vias and / or other circuit components. However, this may result in higher impedance and increased power loss. Reducing the cross-sectional area and / or increasing the length of power lines can lead to significant power loss, for example, because the resistance of thin copper commonly used for front-side power supply is high. For example, various devices may be designed to tolerate approximately 10% power supply loss (e.g., voltage drop) from the power source to the active device region via the metal layer path during transmission. However, significantly larger drops can be observed, especially in relatively small or advanced manufacturing nodes, particularly when many metal layers are present (e.g., around 10, 15, or 20 or more). In some processes, metal interconnects are often made of alternative materials, such as cobalt, at low back-end-of-line (BEOL) levels, thereby reducing power loss. However, the advantages of using other conductive materials are limited, and furthermore, as semiconductor device feature areas continue to miniaturize, a fundamentally different approach may be required to address power and signal delivery problems. In addition, power lines occupy a considerable amount of real space on the front side of the device.This means that the area of ​​a semiconductor device may be significantly larger than its active device area in order to obtain sufficient space for power and signal transmission lines to coexist on the front side of the device simultaneously.

[0152] Backside power supply can mitigate some of the problems associated with scaling semiconductor devices to smaller process nodes. For example, backside power supply can reduce congestion on the front side by eliminating or reducing the need to route power through the front side. Backside power supply enables wider and thicker power supply and / or signal transmission lines. Backside power supply can shorten the electrical path length between the power supply and the active device area. In some embodiments, backside power supply can reduce the number of metal layers carrying signals on the front side of the device, thereby shortening the path length for the signals. Such lines can have low impedance, thereby reducing power loss and / or improving signal quality. In addition, backside power supply circuit components can improve signal quality without increasing the cross-sectional area of ​​the lines, for example, by allowing power supply circuit components to be located relatively far away from signal transmission circuit components, thereby reducing the risk of power transmission electromagnetically interfering with signal transmission.

[0153] In addition to reducing losses and improving signal quality, back-side power supply can be used as a tool to enable designers to create more compact devices. As mentioned above, semiconductor devices may be larger than necessary for the active device area if both power and signal circuit components are located on the same side of the device, unless otherwise configured. Such design decisions can play an increasingly important role when scaling towards miniaturization, and more advanced technology nodes bring about feedback reduction.

[0154] In this specification, the terms "rear-side power supply," "rear-side power supply network," "front-side power," and "front-side power supply network" are generally understood to include power, ground (also referred to as earth or ground, but these terms have the same meaning), and both.

[0155] Traditional integrated circuit design is a monolithic design, where numerous functional circuit blocks can be placed on a common chip or integrated circuit die. However, this approach has several drawbacks. In some cases, a design with numerous functional elements (e.g., chiplets) can be used as an alternative to a monolithic design. Functional element designs allow for the integration of numerous functional elements (e.g., chiplets) to form an electronic assembly. Functional elements are best selected to optimize the semiconductor device for a specific purpose, for example. Using functional elements can improve yield and reduce costs. For example, in monolithic designs, integrated circuits can be relatively large. If an integrated circuit has defects, the entire integrated circuit may become unusable, its performance may be degraded, and parts of it may become unusable (e.g., a CPU core may become non-functional, or some memory may become non-functional). The area of ​​an individual functional element may be smaller than the area of ​​a monolithic integrated circuit containing the features of two or more functional elements. Thus, the risk of an individual functional element containing an unacceptable number of defects or defects in unacceptable locations can be reduced. Functional elements should be selected and grouped so that only known-good functional elements are used in the manufacture of integrated circuits (e.g., semiconductor devices using chiplets) that utilize functional elements. Functional element design can reduce costs by allowing the manufacturing process to be tailored to the specific requirements of the functional element. For example, functional elements that can be used to perform CPUs, GPUs, or other computer-intensive tasks are often manufactured using more advanced manufacturing processes, while other components, such as cache memory (e.g., level 3 cache memory), input / output circuit components, and communication circuit components, can be manufactured using older processes or in ways different from some other components, thereby increasing yield, simplifying the manufacturing process, and reducing costs.As described in detail herein, it is advisable to use advanced technologies, such as back-side power supply, for some functional elements, and to avoid using them for other functional elements within the same system-on-a-chip (SOC).

[0156] Using functional elements can simplify the design and reduce the resources required to design new semiconductor devices. For example, functional element design allows for the reuse of parts of a semiconductor device while updating other parts. For instance, an IOC device including a CPU, GPU, and communication circuit components can be updated with a different CPU, without changing the GPU and communication circuit components. Functional elements also enable relatively easy customization of semiconductor devices. For example, a semiconductor device manufacturer might want to offer two versions of an SOC containing many common components, but these versions might have, for example, different amounts of memory, different accelerating elements (e.g., cryptographic accelerating chiplets), or different numbers and / or types of CPU cores.

[0157] SOCs can offer many advantages. However, as mentioned above, many challenges exist in relation to the use of functional elements. Therefore, there is a need for methods to form functional element-based semiconductor devices that utilize technological advancements, such as back-side power supply, when beneficial, as well as functional elements that do not utilize back-side power supply.

[0158] In some embodiments, a semiconductor device assembly (hereinafter also simply referred to as "assembly" or "electronic assembly") may include a base element (also called a base die) and one or more functional elements. In some embodiments, the base element may be a functionally limited interposer. For example, an interposer-type base element may include an interconnection layer, a redistribution layer, etc., but may not have active circuit components, such as logic, communication, memory, or other similar functions. In some embodiments, the base element may consist of a chip or integrated device die with various functions. For example, the base element may include memory (e.g., SRAM), logic, communication, and / or other functions. In some embodiments, the semiconductor device assembly may include at least one dummy element. For example, the dummy element may be configured to include a plurality of vias, or it may be configured for temperature or thermal diffusion purposes.

[0159] In some embodiments, the base element may include a base element substrate, base element logic, and a base element interconnect structure. In some embodiments, the base element interconnect structure may have multiple layers. For example, the base element interconnect structure may include a local interconnect layer, an intermediate interconnect layer, or both. In some embodiments, contact pads may be provided on the top surface of the base element and may also be in electrical contact with the intermediate interconnect layer, which may be in contact with the local interconnect layer, which may be in contact with the base element logic (e.g., active circuit components). In some embodiments, the interconnect structure may include a redistribution layer. As described above, in some embodiments, the base element may be an interposer. In such embodiments, the base element may not have base element logic, or may have only limited base element logic (for example, less than 20%, less than 15%, or less than 10% of the front surface of the base element may have active circuit components).

[0160] The interconnect layer is preferably subdivided into local, intermediate, and global (and in some cases, semi-global) interconnects. The different interconnect levels are preferably indicated, for example, by the signal propagation distance supported by the interconnect level. However, while such terminology is commonly used, it does not have to have a fixed definition. Generally, the local, intermediate, and global interconnect levels are based on different sets of layout rules and dimensions (e.g., minimum metal pitch, metal thickness, etc.), and these interconnect levels are preferably based on different sets of RC delays. For example, the RC delay value is preferably decreased from the local level to the intermediate level and then to the global interconnect level.

[0161] The limit dimensions of different interconnect levels may vary among different technologies. For example, a 10nm technology node may have a local interconnect level with a metal pitch of approximately 35 to 45nm, an intermediate interconnect level with a metal pitch of approximately 50 to 115nm, a semi-global interconnect level with a metal pitch of approximately 160 to 180nm, and a global interconnect level with an even larger metal pitch. As another example, a 4nm technology node may have a local interconnect level with a metal pitch of approximately 25 to 40nm, an intermediate interconnect level with a metal pitch of approximately 70 to 80nm, and a global interconnect level with a metal pitch of approximately 700 to 750nm. In some embodiments, the local interconnect level may have a limiting dimension requiring the use of extreme ultraviolet lithography, sublithographic patterning, or other advanced lithography techniques, while the intermediate interconnect level may utilize single-exposure lithography.

[0162] In some embodiments, if relatively small RC delay interconnect levels are not accessible, the distance that the interconnect can reach can be extended, for example, by using buffers, restores, and / or other circuit components located at various points along a long interconnect.

[0163] In some embodiments, the wafer fabrication of one or more functional elements and base elements may include local and several intermediate interconnects. In this case, global wiring may be deposited after bonding and reconfiguration. This fabrication method can reduce fabrication costs, fabrication time, etc., compared to the fabrication of a typical wafer with local, intermediate, and global interconnects / wiring.

[0164] As used herein, the term “global interconnect” may refer to the thickest, widest, and most spaced interconnect; “intermediate interconnect” may refer to an interconnect that is thinner and / or more densely packed than the global interconnect; and “local interconnect” may refer to an interconnect that is thinner and / or more densely packed than the intermediate interconnect or the global interconnect. The global interconnect is preferably electrically connected to the intermediate interconnect, and the intermediate interconnect is preferably electrically connected to the local interconnect. The local interconnect is preferably electrically connected to an element (e.g., to the active circuit components of the element) to provide power, ground, and / or signal connections.

[0165] Typically, the global interconnect may be located closest to the surface (e.g., the front side) of the semiconductor element, and such a global interconnect is preferably connected to a conductive contact feature (e.g., a contact pad) configured to connect to an external device (e.g., an integrated device die, a package substrate, etc.). The global interconnect may have one, two, three, four, or more interconnect layers. The global interconnect may have characteristics such as relatively low resistance and a relatively small RC time constant. The global interconnect layer can be used for various purposes, such as clock distribution, power distribution, and long-distance communication. The local interconnect may be the lowest interconnect layer or the layer located closest to the active area of ​​the element (e.g., the layer located closest to the front side of the element). The local interconnect may have characteristics such as a relatively narrow width and a relatively dense pitch. In some embodiments, local interconnects are preferably used to enable signal and / or power transmission over relatively short distances. For example, local interconnects can be used for local connections of transistor elements within a macrocell or subcircuit. Intermediate interconnects are preferably larger than local interconnects but smaller than global interconnects. Intermediate interconnect layers are preferably characterized by a relatively low via density (e.g., compared to local interconnect layers). Intermediate interconnects can be used, for example, for communication with large circuit blocks and / or communication between small circuit blocks. Because the via density in the intermediate interconnect layer is relatively low, empty space can be utilized as a result. In some embodiments, circuit elements are preferably located within the intermediate interconnect layer. For example, power management circuits, mixed-signal devices, passive circuit components such as capacitors, resistors, and inductors are preferably located in one or more intermediate layers. In some embodiments, such circuit elements may span two or more intermediate interconnect layers.Interconnect layers (e.g., global interconnect layer, intermediate interconnect layer, and / or local interconnect layer) are sometimes also called metallization layers. The metallization layers are preferably composed of conductive traces and / or embedded insulating materials (e.g., inorganic dielectrics, e.g., silicon oxide). The interconnect layers are preferably connected to each other by vias extending perpendicularly to these layers.

[0166] In some embodiments, the base element may have features such as power supply and power regulation. In some embodiments, different functional elements may have different voltage requirements. In some embodiments, the power supplied to the semiconductor device assembly may be different from the power requirements of the functional elements or the base element. For example, the functional elements and / or circuit components in the base element may operate at a voltage different from the voltage supplied to the semiconductor device assembly. In some embodiments, the base element may have one or more integrated voltage regulators, which may be used to define one or more power domains. In some embodiments, the integrated voltage regulator (IVR) may be provided in the base element interconnect structure. For example, in some embodiments, the IVR may have a small portion of the base element transistors and associated base element local and / or intermediate interconnects. In some embodiments, the power supply may be shared among functional elements within the same power domain, as will be described in detail below. In some embodiments, the base element may have a number of integrated voltage regulators. In some embodiments, the base element may include various passive components, such as inductors, capacitors, resistors, etc.

[0167] In some embodiments, the functional element can directly receive some or all of the power from the base element. For example, this approach is desirable when the base element and the functional element share the same voltage.

[0168] Figure 1 is a block diagram illustrating an exemplary semiconductor device assembly according to several embodiments. As shown in Figure 1, the semiconductor device assembly may include a base element 102, an interconnect structure 108, a first functional element 146, and a second functional element 148. The first functional element 146, the second functional element 148, or both, may have an integrated circuit die or chiplet on which active circuit components are formed and housed. The base element 102 may have a base element substrate 110, an active region 112, and a base element interconnect structure 114. The first functional element 146 may have an active region 120, an interconnect structure 122, and a functional element substrate 152. Similarly, the second functional element 148 may have an active region 120', an interconnect structure 122', and a functional element substrate 152'. For example, in various embodiments, the substrates 110, 152, 152' may have semiconductor portions (e.g., silicon or other suitable semiconductors) of the respective elements 102, 146, 148, and the active regions 112, 120, 120' may have device portions of the respective elements 102, 146, 148 that include active circuit components (e.g., transistors) patterned or formed in or on the semiconductor portions. The interconnect structures 114, 122, 122' may include back-end-of-line (BEOL) structures deposited on the respective active regions 112, 120, 120'. For example, the interconnect structures 114, 122, 122' may have an inorganic dielectric (e.g., silicon oxide, silicon nitride, etc.) with embedded conductors (e.g., embedded conductive vias and / or traces).

[0169] The first functional element 146 and the second functional element 148 are preferably provided on the front surface 160 of the base element 102. For example, the front surface 166 of the first functional element 146, the front surface 166' of the second functional element 148, or both, are preferably bonded to the front surface 160 of the base element 102 along the bonding interface 162 (e.g., hybrid bonding). For example, in some embodiments, contact features (see, for example, Figures 11A and 11B) are preferably provided on the respective front surfaces 160, 166, 166' of the base element 102, the first functional element 146, and / or the second functional element 148 to form electrical contacts between the base element 102 and the functional elements 146, 148. In some embodiments, signals are preferably provided through the contact features (e.g., signal pads provided on the front side of the base substrate and also configured to send electrical signals to active circuit components on the front side of the base substrate).

[0170] The insulating material 124 is preferably provided between at least the first functional element 146 and the second functional element 148. The interconnect structure 108 is preferably provided on the back surfaces 168, 168' of the first functional element 146 and the second functional element 148, respectively. As will be described in detail below, the interconnect structure 108 is preferably provided with input / output pads on its front surface 164. The front surface 164 is preferably an exposed or partially exposed surface. The interconnect structure 108 is preferably provided with one or more interconnect layers, which may be, for example, a global interconnect, an intermediate interconnect, or both. The semiconductor device assembly in Figure 1 is preferably provided with through-substrate vias (TSVs) 136, insulating material through-vias 138, and / or through-substrate vias (TSVs) 150. Vias 136, 138, and 150 enable electrical connections between the interconnect structure 108 and the base element 102 and the functional elements 146 and 148, as described herein. Although not shown in Figure 1, the interconnect structures 122, 122', 114, and 108 may additionally or alternatively have conductive traces embedded in the insulating material to route signals and / or power laterally or horizontally.

[0171] In some embodiments, the interconnect structure 108 is preferably bonded to the functional element and / or insulator 124 (e.g., hybrid bonded). In some embodiments, the interconnect structure 108 is preferably deposited on the functional element and / or insulator. In some embodiments, circuit components for supplying power / ground to the active circuit component or functional element are preferably or substantially excluded from the front side of the active region (e.g., from the interconnect layer of the functional element), and instead, power / ground is preferably supplied substantially or entirely via direct metal contacts, nanovias, or microvias extending from the back side of the functional element to the active region of the functional element, for example. In some embodiments, the global interconnect and / or intermediate interconnect are preferably not provided in the base element and / or functional element. For example, in some embodiments, input / output (IO) pads, a global interconnect, and / or an intermediate interconnect are preferably provided in the interconnector structure 108, and vias are preferably used to connect to functional elements, base elements, etc. In some embodiments, the functional elements preferably have signal connections on their front surface. In some embodiments, the base elements preferably have one or more interconnect levels (e.g., local and / or intermediate interconnects) near their front surface, but do not preferably include a global interconnect, IO pads, or both.

[0172] In some embodiments, the insulating material may be an inorganic dielectric. In some embodiments, the insulating material may be an organic dielectric. In some embodiments, the insulating material may be silicon oxide or silicon nitride. In some embodiments, the insulating material may be formed using a low-temperature tetraethyl orthosilicate (TEOS) process. The insulating material 124 may be a gap-filling dielectric between adjacent functional elements. Forming the insulating material 124 can be challenging, for example, because the insulating material 124 may be relatively thick (e.g., about 20 micrometers or more). It is important that the insulating material 124 is substantially free of voids, cracks, and / or other defects. It is also important to employ a process that does not result in excessive wafer warping. In some embodiments, chemical vapor deposition may be carried out at a relatively low temperature using TEOS.

[0173] As described above, in some embodiments, the semiconductor device assembly often includes functional elements configured for front-side power supply, back-side power supply, or a mixture of functional elements, some of which are configured for front-side power supply, and others for back-side power supply.

[0174] In the exemplary embodiment shown in Figure 1, the first functional element 146 is configured for front-side power supply, and the second functional element 148 is configured for back-side power supply. As shown in Figure 1, via 136 extends from the back surface 168' of the second functional element 148 to the active region 120' of the second functional element 148. Via 136 may provide power and ground from the interconnect structure 108 to the second functional element 148 (for example, to the transistor in the active region 120' of the second functional element 148). Via 138 may extend from the back surface 101 of the interconnect structure 108 to the front surface 160 of the base element 102, for example to the base element interconnect structure 114. Power, ground, and / or signal connections may be made from via 138 to the active region 112 via electrical interconnects (e.g., lateral traces) within the base element interconnect structure 114. In some embodiments, the base element interconnect structure 114 may have an intermediate interconnect and a local interconnect, as described in detail herein.

[0175] In some embodiments, the functional element substrate 152' may undergo a chemical mechanical polishing (CMP) process. In some embodiments, depending on the back-side power supply technology used, the thickness of the functional element substrate 152' after polishing may be from about 0 nm (for example, the functional element substrate 152' may be completely or almost completely removed) to about 5 micrometers, about 10 micrometers, or about 20 micrometers. For example, the thickness of the functional element substrate 152' may be from about 300 nm to about 500 nm, or from about 2 micrometers to about 5 micrometers. Thus, the via 136 may be a direct metal via, a direct metal contact, a nanoTSV, or a microTSV. In some embodiments, once the functional element substrate 152' is completely removed, a shallow trench isolation feature in the active region 120' can be used as a CMP stop. In some embodiments, when the thickness of the functional element substrate 152' after polishing is in the nanometer or micrometer range, a thin SiGe layer or any other suitable dielectric layer (e.g., oxide, buried oxide, etc.) is preferably used as an etching stop layer between the active region 120' and the original bulk substrate on which the second functional element 148 was fabricated.

[0176] In some embodiments, front-side power can be supplied to the front surface of the base element 102 (for example, to the wire bonding pad of the base element 102) via wire bonding. The wire can be electrically connected to an area located outside the chiplet. The interconnect layer can supply power and ground from the wire bonding pad to the circuit components of the device. However, using wire bonding may result in longer electrical paths (which may lead to voltage drops, inductance loops, etc.), increased semiconductor device assembly size, and other issues. Furthermore, power and ground connections may compete for limited space with signal connections.

[0177] In some embodiments, the first functional element 146 may have vias 150 extending from the front surface 166 to the back surface 168 of the first functional element 146. The vias 150 can offer several advantages. For example, even without vias passing through the functional element, signals flowing to and / or from the base element 102 are constrained to take a path that avoids the functional element. For example, signals may pass through vias 138 of the insulating material 124 between functional elements. In some embodiments, such conduction does not pose a significant disadvantage. For example, if the base element 102 is an interposer that does not have an active region 112, or has only minimal logic in the active region 112, then flowing around the functional element does not pose a major problem or disadvantage. However, if there is significant signal processing within the base element 102 (for example, within the active region 112 of the base element 102), restricting the signal flow only to the vias 138 of the insulating material 124 may severely limit useful signal routing paths (for example, there may be limited space between functional elements and / or the usability of the space between functional elements may be limited or zero, since usability is used to facilitate high-speed and / or high-bandwidth communication between functional elements), which may severely limit performance.

[0178] Although the TSV is shown passing through a first functional element 146 which may be configured for front-side power supply, as recognized, such a TSV may be located within a functional element configured for back-side power supply. Although the via 150 extends through the interconnect structure 122, the active region 120, and the functional element substrate 152 in Figure 1, as recognized, other configurations are possible. For example, in some embodiments, the via 150 may extend only partially through the interconnect structure 122 rather than penetrating it from beginning to end.

[0179] In some embodiments, the base element may be an interposer with no active circuit components or a limited number of active circuit components. In some embodiments, the base element may have active circuit components, such as logic and memory. The area of ​​the active circuit components in the base element may be referred to as the functional area in this specification. In some embodiments, the functional elements can be arranged on the top of the base element in various advantageous ways. For example, a functional element including a CPU die may be arranged on the base element above the area including memory. The memory may be, for example, a CPU substitute level 3 cache memory. By arranging the CPU die functional element on top of the memory functional area of ​​the base element, relatively high speed, relatively high bandwidth, and / or low latency can be achieved. In some embodiments, thermal considerations can inform the arrangement of the functional elements on the base element. For example, if the base element has a GPU area, it may be desirable not to place the CPU or GPU functional element on top of the CPU area of ​​the base element in order to avoid concentrating functional elements with high thermal output and the base element functional area too close together.

[0180] In some embodiments, the front surface of the functional element is preferably provided on the front surface of the base element. In some embodiments, the functional element is preferably having a plurality of contact feature portions provided on the front surface of the functional element. The contact feature portions of the functional element are preferably in electrical contact with the contact feature portions of the base element. In some embodiments, the front surface of the base element and / or the front surface of the functional element are preferably having a bonding surface, and the front surface of the functional element can be bonded to the base element. For example, in some embodiments, the functional element can be hybrid bonded to the base element. For example, the front surface of the functional element can be bonded to the front surface of the base element (e.g., hybrid bonding can be performed). Direct bonding (e.g., hybrid bonding) will be described in more detail herein with reference to, for example, Figures 11A and 11B.

[0181] Although the back side 116' of the second functional element substrate 152' is shown to be identical to the back side 168' of the second functional element 148 in Figure 1 (for example, the surface made of silicon with exposed vias), these surfaces do not need to be identical. For example, an interconnect layer or bonding layer may be deposited onto the back side 116' of the second substrate element 152' as part of the process of forming the second functional element 148, and the back side 168' of the second functional element 148 may include an oxide layer on which conductive pads are located.

[0182] Figure 2 shows an exemplary semiconductor device assembly 100 according to several embodiments. As shown in Figure 2, the assembly 100 preferably includes a base element 102, a first functional element 104, a second functional element 106, and an interconnect structure 108. The assembly 100 preferably includes a front surface 132 and a back surface 134. The base element 102 preferably has a base element substrate 110 (e.g., a semiconductor portion), a base element active region 112 (which preferably includes an active circuit component, such as a transistor), and a base element interconnect structure 114. The first functional element 104 and the second functional element 106 each preferably have a substrate 170 with a back surface 116 and a front surface 118. The first functional element 104 and the second functional element 106 each preferably have an active region 120 (which preferably includes an active circuit component, such as a transistor) and an interconnect structure 122 formed on the substrate 170. The first and second functional elements 104 and 106 are preferably bonded to the base element 102 at the bonding interface 172 (for example, by hybrid bonding). The first functional element 104 and the second functional element 106 are preferably surrounded on each side by one or more insulating materials 124. The insulating material 124 is preferably composed of one or more insulating layers. For example, in some embodiments, the insulating material is preferably made of silicon oxide. In some embodiments, the insulating material 124 is preferably composed of multiple layers. For example, the insulating material 124 is preferably composed of a first dielectric layer (e.g., silicon nitride or silicon oxide) conformally covering the elements 104 and 106, and a second dielectric layer (e.g., silicon oxide) filling or substantially filling the space between the elements 104 and 106. Region 108 may include an intermediate interconnect layer 126, a global interconnect layer 128, and input / output (IO) pads 130 configured to be electrically connected to external devices (e.g., by direct bonding or by solder balls or other electrical connectors). In a back-side power supply configuration, the first functional element 104 and the second functional element 106 may have vias 136 (e.g., nanovias) extending from the back side of the substrate 170 to the active region 120.In some embodiments, via 136 may be a via that does not penetrate the functional element from beginning to end. Assembly 100 may include via 138, which extends through the insulating material 124 to electrically connect the intermediate interconnect layer 126 of the interconnect structure 108 to the base element interconnect structure 114.

[0183] In some embodiments, power / ground is preferably delivered substantially or completely by an intermediate interconnect layer 126 and / or a global interconnect layer 128 via the back surfaces of the first and second functional elements 104 and 2. In some embodiments, the intermediate interconnect layer 126 and / or global interconnect layer 128 of the interconnect structure 108 can act as an intermediate and / or global interconnect for the assembly 100. For example, the intermediate interconnect layer 126 and / or global interconnect layer 128 can be used for power, ground, and clock distribution between adjacent functional elements, communication, and long-distance communication from end to end of the assembly 100.

[0184] In some embodiments, the substrate 170 may have a thickness of 0 nm or about 0 nm (e.g., the substrate 170 may be removed or almost completely removed), about 300 nm to about 500 nm, about 2 micrometers to about 5 micrometers, or more or less. When the thickness of the substrate 170 is 0 nm or about 0 nm (e.g., completely or almost completely removed), shallow trench isolation features can be used as CMP stops, and the substrate 170 can become discontinuous residue between the shallow trench isolation features. In some embodiments, it is preferable to completely remove the substrate 170. In some embodiments, it is preferable that direct power, ground, and / or signal paths are provided through the functional elements.

[0185] As described above with reference to Figure 1, in some embodiments, via 136 may extend further than in the case shown in Figure 2. For example, in some embodiments, via 136 may extend through the active region 120 and through or partially through the interconnect structure 122.

[0186] Figure 3 shows examples of various power and ground delivery paths according to several embodiments. The assembly 300 shown in Figure 3 is substantially the same as the assembly 100 in Figure 2, but the assembly 300 includes an integrated voltage regulator (IVR) provided within the base element. As shown in Figure 3, power / ground can be supplied directly to the back side 116 of the substrate 170 of the first functional element 104 or the second functional element 106, as indicated by circle 1. The electrical path may extend from the IO pad 130 through the global interconnect layer 128, through the intermediate interconnect layer 126, to the contact feature area 115b, and to via 136, where power can be delivered through a portion of the second functional element to the active region 120 of the second functional element 106. Thus, power can be supplied to the active region 120 of the second functional element 106 from the back side, thereby providing various advantages as described herein, such as the advantage of enabling the use of thick interconnects, the advantage of reducing the density of the front-side interconnects of the functional element 106, and the advantage of reducing the interconnect path length.

[0187] In some embodiments, power can be supplied directly to the base element 102. As shown in the path indicated by circle 2, power can be sent from the IO pad 130 to the global interconnect layer 128, from the global interconnect layer 128 to the intermediate interconnect layer 126, and then from the via 138 to the interconnect structure 114 of the base element 102. Using the power supplied to the base element 102, power can be supplied to the base element 102 (for example, the active region 112 of the base element 102). The power supplied to the base element 102 can be supplied additionally or alternatively to one or more elements, for example, a first functional element 104 and / or a second functional element 106. For example, power can be taken at a first voltage via the path indicated by circle 2. The base element 102 may have an integrated voltage regulator (IVR) 140. The integrated voltage regulator 140 may be configured to receive a first voltage and output a second voltage. It is preferable to send the second voltage to the back side of one element, for example, the first functional element 104 and / or the second functional element 106, by which the second voltage travels along the path shown by circle 3, from the integrated voltage regulator 140 to via 138, then to the intermediate interconnect layer 126, then to the global interconnect layer 128, then back to the intermediate interconnect layer 126, and then back to elements 104 and / or 106 through via 136. As shown in Figure 3, it is preferable to electrically connect the first metal part 142 to the second metal part 144 in one layer of the global interconnect layer 128. Thus, it is preferable that the first metal part 142 and the second metal part 144 are in the same voltage state, for example, the second voltage. The connection between different metal parts within the interconnect layer reduces the amount of routing required to and from the integrated voltage regulator within the interconnect structure 108 of the base element 102. For example, by using a shared power supply line, power can be supplied to adjacent elements. In some embodiments, the second voltage is preferably the output of an integrated voltage regulator 140.In some embodiments, the second voltage is preferably sent to an SOC chip power supply network, which preferably includes an intermediate interconnect layer 126 and / or a global interconnect layer 128. The SOC chip power supply network can supply power to a number of functional elements (e.g., 104 and 106) from their backsides, and can also supply power to other parts of the base element. Similarly, a signal generated in the circuitry within the base element 102, or a clock signal received from the I / O pads through a similar path highlighted by circle 3 and buffered by the circuitry within element 102, is preferably sent to an SOC chip clock delivery network, which preferably includes an intermediate interconnect layer 126 and / or a global interconnect layer 128, and supplies the clock to one or more functional elements (e.g., functional elements 104, 106) from their backsides. In some embodiments, the chip clock delivery network can supply the clock to other parts of the base element. In some embodiments, power and / or clock signals are often supplied directly from the I / O pads to an SOC chip power / clock distribution network, which may include a global interconnect layer 128 and / or an intermediate interconnect layer 126 (not shown in Figure 3), thereby enabling the SOC chip power / clock distribution network to supply power / clock to one or more functional elements and / or circuits in the base element 102 from their back sides. As shown in circle 4, in some embodiments, power is preferably supplied from the interconnect structure 114 of the base element 102 to the front side of one element, for example, a first functional element 104 and / or a second functional element 106. For example, even for an element designed for back-side power supply, it may be desirable to provide at least some power via the front side of the element.

[0188] In some embodiments, the contact feature portions 115a and 115b may be conductive feature portions or structures exposed on the front or back surface of the functional element. For example, the contact feature portion 115a may consist of a copper pad at least partially embedded in a dielectric on the front or back surface of the functional element, and the contact feature portion 115b may consist of the exposed end of a via 136 extending through the functional element. The contact feature portions may be directly bonded to opposing feature portions, or deposited on conductive feature portions so that a conductive interconnect makes contact.

[0189] In the above-disclosed embodiments, power is delivered along the illustrated paths, but it should be recognized that these paths can be used for power or ground. For example, the paths can provide potential to various elements (e.g., functional elements, base elements, etc.). The potential may be a non-zero voltage or ground (e.g., zero volts).

[0190] As described above, in some cases it is desirable to use several elements (e.g., chiplets), and among these elements, some use back-side power supply while others use front-side power supply. Figure 4 shows an exemplary embodiment of an assembly according to several embodiments. Assembly 400 is substantially the same as assembly 100 in Figure 2 and assembly 300 in Figure 3. However, unlike Figures 2 and 3 in which both the first functional element 104 and the second functional element 106 are configured for back-side power supply, Figure 4 shows a first functional element 146 configured for front-side power supply and a second element 148 configured for back-side power supply. For example, it is preferable that the power and ground connection parts be provided on the front surface of the first functional element 146. For example, the front surface 166 of the first functional element 146 is preferably provided with contact features for providing electrical contact to the active circuit components of the first functional element 146. The first functional element 146 and / or the second functional element 148 are preferably bonded to the base element 102 (for example, hybrid bonding).

[0191] In some embodiments, the assembly 400 may include an interconnect structure 108 having one or more input / output (IO) pads 130, a first functional element 146, and a second functional element 148. The first functional element 146 may have a first semiconductor substrate 170 having a front side 111 on which active circuit components are provided and a back side 113 opposite to the front side 111.

[0192] The front surface 166 of the first functional element 146 preferably has a first contact feature portion 115a connected to one or more I / O pads 130. Power is preferably supplied to the first functional element 146 via the I / O pads 130 leading to the global interconnect layer 128, and then to the intermediate interconnect layer 126. The intermediate interconnect layer 126 can supply power to the base element interconnect structure 114 of the base element 102 via vias 138. Power is preferably supplied from the base element interconnect 114 (for example, via the intermediate layer of the base element interconnect structure 114) to the front surface 166 of the first functional element 146 (for example, the first contact feature portion 115a on the front side 111 of the first functional element 146).

[0193] The second functional element 148 preferably has a second semiconductor substrate 170 having a front side 111 on which active circuit components are provided and a back side 113 opposite to the front side 111. The back side 168 of the second functional element 148 preferably has a second contact feature portion 115b connected to one or more I / O pads 130.

[0194] Power is supplied to the second functional element 148 via an I / O pad 130 leading to a global interconnect layer 128, then to an intermediate interconnect layer 126, to the back side 113 of the second functional element 148 (e.g., a second contact feature 115b), and then to a via 136, where the power is preferably delivered to the active region 120 of the second functional element 148 through a portion of the second functional element 148. In some embodiments, the intermediate interconnect layer 126 is often deposited on the exposed end of the via 136 (e.g., to make electrical contact between the corresponding contact feature of the intermediate interconnect layer 126 and the back side of the functional element), and the second contact feature 115b is the exposed end of the via 136. In the above-disclosed description of the embodiments, power is delivered along the illustrated paths, but it should be recognized that these paths can be used for power or ground. In some embodiments, the intermediate interconnect layer 126 is preferably directly bonded to the back surface of the functional element.

[0195] In some embodiments, different elements (e.g., chiplets) may communicate with each other via local and intermediate interconnect levels of the base element interconnect structure 114 of the base element 102. For example, the first element may be a CPU chiplet, and the second element may be a memory chiplet (e.g., an SRAM chiplet). In some embodiments, the first and second elements may have high-density contact pads near one or more edges of the elements. The contact pads may be, for example, hybrid bonding-capable contact pads to the base element 102. The base element 102 may have high-density interconnects within the base element interconnect structure 114 to facilitate the transmission and reception of signals between adjacent elements (e.g., between a CPU chiplet and an SRAM chiplet). Therefore, in some embodiments, it may be desirable to limit or eliminate circuit components of the base element 102 in the space between elements (e.g., the space between chiplets) in order to maximize the number of interconnects available to facilitate communication between adjacent elements.

[0196] In some embodiments, the base element may have various functions. For example, the base element may include circuit components for providing memory, computer processing functions (e.g., CPU, GPU), etc.

[0197] In some embodiments, the base element 102 may have an active region 112. The active region 112 can provide various functions, such as memory, GPU, CPU, acceleration, etc.

[0198] In some embodiments, high-speed, high-bandwidth, and / or low-latency communication can be provided between functional elements (e.g., between chiplets) and / or between functional elements and base elements (e.g., functional areas of base elements). For example, such communication circuit components may be important when there is a large amount of data transmission between one element and another, for example, to write to or load into memory (e.g., SRAM cache memory). In some embodiments, communication between functional elements (e.g., chiplets) is preferably performed via an interconnect provided by the base element. As will be described in detail herein, in some embodiments, the base element may have various components, such as integrated voltage regulators, functional areas (e.g., SRAM, CPU, GPU, cryptographic accelerator, coding / decoding accelerator, and / or passive components). In some embodiments, such features may be arranged such that they do not undesirably restrict communication between elements. For example, in response to the need for communication between two elements, the circuit component connecting these two elements may have some functionality (including no functionality at all), rather than providing an interconnect between functional elements.

[0199] Figure 5A shows an example of communication between a base element and a functional element according to several embodiments. As shown in Figure 5A, the base element preferably has a base element substrate 110, an active region 112, and a base element interconnect structure 114. The functional element preferably has an interconnect structure 122, an active region 120, and a functional element substrate 152. The interconnect structure 122 and the base element interconnect structure 114 are preferably in electrical contact with each other. For example, the interconnect structure 122 and the base element interconnect structure 114 may have contact features such as contact pads or vias. In some embodiments, the front surface of the functional element is preferably bonded to the front surface of the base element (e.g., hybrid bonding).

[0200] Figure 5B shows an example of communication between a first functional element 180a and a second functional element 180b. The front surface of the first functional element 180a is preferably bonded to the front surface of the base element 102 (for example, hybrid bonding). The front surface of the second functional element 180b is preferably bonded to the front surface of the base element 102 (for example, hybrid bonding). The base element 102 preferably has a base element substrate 110, an active region 112, and a base element interconnect structure 114. The first functional element 180a preferably has a first functional element interconnect structure 122a, a first functional element active region 120a, and a first functional element substrate 152a. The second functional element 180b preferably has a second functional element interconnect structure 122b, a second functional element active region 120b, and a second functional element substrate 152b. In some embodiments, the functional elements 180a and 180b may not have substrates 152a and 152b. The first functional element 180a and the second functional element 180b may be separated only by a gap. In some embodiments, the gap may be filled with one or more insulating materials as described herein. The first functional element 180a and the second functional element 180b can communicate with each other through the base element interconnect structure 114 of the base element. In some embodiments, the region of the base element in which the interconnect structure 114 is used to facilitate communication between the first functional element 180a and the second functional element 180b may be kept relatively free of modification components used for purposes other than facilitating communication between the functional elements.

[0201] As outlined above, in some embodiments, the base element may have a logic layer. In some embodiments, the base element may have an interposer that enables electrical connections but does not provide other functions, or provides only limited functions. For example, in some embodiments, the base element in Figure 5B may not have an active region.

[0202] Figures 6A and 6B show illustrative semiconductor device assemblies according to several embodiments. The device assembly preferably includes a base element 610. The base element 610 preferably has functional regions 612 to 618. The functional elements 602 to 608 are preferably provided on the front surface of the base element 610. For example, in some embodiments, the functional elements 602 to 608 are preferably bonded (e.g., hybrid bonded) to the front surface of the base element 610. In some embodiments, the intermediate and global interconnects of the combinational SOC chip are preferably provided above the functional elements 602 to 608 (not shown in Figure 6B). In some embodiments, one or more of the functional elements 602 to 608 are preferably configured to supply power from the back side. In some embodiments, one or more of the functional elements 602 to 608 are preferably configured to supply power from the front side. In some embodiments, at least one of the functional elements 602-608 is preferably configured to supply power from the back, and at least one other of the functional elements 602-608 is preferably configured to supply power from the front. The functional elements 602-608 are shown hybrid-bonded to and aligned with the functional regions 612-618 of the base element 610, but these functional elements are preferably partially and substantially offset with respect to the functional regions 612-618. In some embodiments, one or more functional elements may overlap one or more functional regions of the base element. In some embodiments, at least one of the functional elements may be a dummy element or a through-hole element (e.g., providing only wiring and TSV) or one or more passive elements with or without through-hole wiring.

[0203] Figures 6A and 6B show semiconductor device assemblies in which the number of functional regions in the base element is the same as the number of functional elements bonded to the front surface of the base element 610. However, as can be seen, the number of functional regions in the base element 610 and the number of functional elements do not necessarily have to be the same.

[0204] The functional regions 612-618 and functional elements 602-608 may have various functions. For example, the functional regions 612-618 and functional elements 602-608 may have memory (e.g., SRAM), CPU, GPU, and / or other functions. In some embodiments, the functional regions and functional elements may be arranged to prevent or limit the stacking of elements that each have high heat dissipation requirements. For example, in some embodiments, CPU functional elements may not be stacked on top of the GPU functional region. In some embodiments, the functional regions and functional elements may be arranged to facilitate communication between different functional elements, between different functional regions, and / or between functional elements and functional regions. As an example, functional element 602 may be a GPU or CPU core, and functional region 612 may be SRAM. Functional element 602 may be located on top of functional region 612. For example, the functional area 612 may be a cache memory or other memory oriented towards the functional element 602. In some embodiments, one or more of the functional areas may be identical or substantially identical to one or more of the functional elements. For example, SRAM elements may be stacked on top of SRAM to extend the entire SRAM of the SOC. Similarly, CPUs / cores may be stacked directly on top of other CPUs / cores to provide a high-density multicore structure.

[0205] Figure 7 is a plan view of an exemplary semiconductor device assembly according to several embodiments. In Figure 7, the base element 702 preferably has functional areas 704, 706, and 708. In Figure 7, the functional areas of the base element 702 are indicated by dashed rectangles. The functional element (e.g., a chiplet) preferably has feature areas 710 to 730. The feature areas 710 to 730 preferably include various types of functions, such as a CPU core, GPU core, SRAM, high-speed communication circuit component, etc. For example, feature areas 710, 712, 714, and 716 may be CPU cores, and functional area 706 may be SRAM. For example, feature areas 718, 720, 722, and 724 may be CPU cores, and functional area 708 may be SRAM. Feature area 726 may be SRAM, and functional area 704 may be a CPU core. The feature sections 728 and 730 may, for example, be communication interfaces. As shown in Figure 7, it is preferable to have a one-to-one correspondence between the feature section of the functional element and the functional area of ​​the base element, for example, between feature section 726 and functional area 704. Other ratios are also possible. For example, in the illustrated embodiment, four CPU cores are paired with one SRAM functional area (706 or 708). In some cases, the feature section of the functional element, for example, the feature sections 728 and 730 in the illustrated embodiment, may not have a corresponding functional area in the base element.

[0206] Although shown as a single functional element (e.g., a single chiplet) in Figure 7, as can be seen, in some embodiments, the feature portions 710-730 are separate functional elements (e.g., separate chiplets) each bonded (e.g., directly bonded) to the base element 702.

[0207] As described above, it is sometimes desirable to provide high-speed, high-bandwidth, and / or low-latency communication between functional elements. Figure 8 shows an exemplary semiconductor device assembly according to several embodiments. This assembly may include a base element 802, a functional element 804, and a functional element 806. In some embodiments, one or both of the functional elements 804 and 806 may be configured for back-side power supply. In some embodiments, the functional elements 804 and / or 806 may be bonded to the base element 802 (e.g., hybrid bonded). The functional element 804 may include a region of high-density contact feature area 808. The functional element 806 may include a region of high-density contact feature area 810. The base element 802 may have an interconnect 812 that can be used to connect the high-density contact feature area 808 and the high-density contact feature area 810 to each other. In some embodiments, it is preferable that there are few or no additional circuit components or functions in the base element region of the interconnect 812.

[0208] In some embodiments, it may be desirable to include additional features within the interconnect structure. For example, the interconnect structure may include passive devices, electrostatic discharge (ESD) protection devices, mixed-signal devices, etc. Examples of ESD / passive devices include resistors, capacitors, diodes (e.g., Zener diodes, transient voltage suppressor diodes, etc.), fuses, relays, reverse bias diodes, inductors, etc. In some embodiments, the mixed-signal device may be configured for both analog and digital processing. For example, the mixed-signal device may include digital-to-analog converters, analog-to-digital converters, error checking and correction circuit components, etc.

[0209] Figure 9 shows an example of a semiconductor device assembly according to several embodiments. Assembly 900 is preferably substantially the same as assembly 100 in Figure 2. Compared to assembly 100, assembly 900 may include additional features. For example, the mixed-signal device 904 may be located within the global interconnect layer 128 and / or the intermediate interconnect layer 126. The mixed-signal device 904 may have a contact feature portion 908. The contact feature portion 908 allows for electrical contact with the interconnect structure 108, for example, the intermediate interconnect layer 126 of the interconnect structure 108. Assembly 900 may include an ESD / passive device 902. The passive device 902 is preferably located within the global interconnect layer 128 and / or the intermediate interconnect layer 126. The passive device 902 may have a contact feature portion 906. The contact feature portion 906 can enable electrical contact with the interconnect structure 108, for example, the intermediate interconnect layer 126 of the interconnect structure 108.

[0210] In some embodiments, the passive device 902, the mixed-signal device 904, or both thereof, may be hybrid-bonded to the intermediate interconnect layer 126 and / or the global interconnect layer 128. In some embodiments, after hybrid bonding, the passive device 902, the mixed-signal device 904, or both thereof, may be encapsulated in the insulating / dielectric layer of the intermediate interconnect layer 126 and / or the global interconnect layer 128.

[0211] In some embodiments, it is preferable to have more devices, fewer devices, and / or different devices within the semiconductor device assembly. For example, in some embodiments, the assembly may include one or more passive devices but not mixed-signal devices, or the assembly may include one or more mixed-signal devices but not passive devices.

[0212] Figure 9 shows one embodiment in which the first functional element 104 and the second functional element 106 are configured to be powered from the back; however, as can be seen, it is not necessary for the functional elements to be configured to be powered from the back. In some embodiments, the assembly may include at least one functional element configured to be powered from the back and at least one functional element configured to be powered from the front.

[0213] In some embodiments, the front surface of the semiconductor device assembly may have contact features, such as I / O pads. In some embodiments, a thermal solution may be applied to the back surface of the semiconductor device assembly. Examples of thermal solutions include, but are not limited to, heat sinks, heat spreaders, cold plates, and / or other employings. In some embodiments, the base element may not be the primary heat source compared to one or more functional elements. Thus, in some embodiments, it may be desirable to position the functional elements near the back surface of the semiconductor device assembly.

[0214] In some embodiments, the layers within the semiconductor device assembly are preferably arranged such that the functional elements are located near the back surface of the semiconductor device assembly.

[0215] Figure 10A shows an exemplary semiconductor device assembly according to several embodiments. Assembly 1000 may share similarities with other semiconductor device assemblies described herein. However, assembly 1000 has several differences from other semiconductor device assemblies described herein. As shown in Figure 10A, assembly 1000 may include a base element 1002, a base interconnect structure 1018, an interconnect structure 1004, a first functional element 1010, and a second functional element 1012. In Figure 10A, the first functional element 1010 and the second functional element 1012 are configured for back-side power supply. Assembly 1000 may include a front surface 1022 and a back surface 1014. The thermal solution means 1050 may be provided on the back surface 1014. As with the other embodiments described herein, the number of functional elements may vary, and it will be recognized that some elements may be configured to supply power from the front side, while others may be configured to supply power from the back side.

[0216] The base element 1002 preferably has a base substrate 1016 and a base interconnect structure 1018. The interconnect structure 1004 preferably has I / O pads 1020 and / or other contact features. The interconnect structure 1004 preferably has a global interconnect 1024 and an intermediate interconnect 1026. The assembly 1000 preferably includes a base logic substrate 1028, a base logic layer 1006, and a base interconnect 1008. As shown in Figure 10A, the back surface 1003 of the interconnect structure 1004 is preferably provided on the back surface 1005 of the base logic substrate 1028. The base logic layer 1006 is preferably provided on or near the front surface 1007 of the base logic substrate 1028. The interconnect 1008 is preferably provided on the front surface 1009 of the base logic layer 1006. The front surface 1011 of the interconnect 1008 preferably has contact features (e.g., contact pads, vias, etc.) provided on the front surface. In some embodiments, the back surfaces 1013 of the first functional element 1010 and the second functional element 1012 preferably lies on the front surface 1015 of the base interconnect structure 1018 (for example, they may be directly hybrid bonded to it). In some embodiments, the front surfaces 1017 of the first functional element 1010 and the second functional element 1012 preferably lies on the front surface 1011 of the interconnect 1008 (for example, they may be hybrid bonded to it). The front surfaces 1017 of the first functional element 1010 and the second functional element 1012 preferably lies on the front surface 1011 of the interconnect 1008.

[0217] In some embodiments, the interconnect 1008 is preferably deposited on the first functional element 1010, the second functional element 1012, and the insulating material 1036. In some embodiments, the base logic substrate 1028 (with the base logic layer 1006 provided on its front surface) is preferably bonded to the interconnect 1008 (e.g., hybrid bonded). In some embodiments, the base logic substrate 1028, the base logic layer 1006, and the interconnect 1008 are preferably formed as components that are preferably bonded to the first functional element 1010, the second functional element 1012, and the insulating material 1036 (e.g., hybrid bonded).

[0218] In some embodiments, the front surface of the interconnect 1008 and the front surfaces of the first functional element 1010 and / or the second functional element 1012 can serve as bonding layers. For example, the front surface of the interconnect 1008 may be bonded to the front surfaces of the first functional element 1010 and / or the second functional element 1012 (e.g., hybrid bonding). The back surface of the first functional element 1010, the back surface of the second functional element 1012, and / or the front surface of the base interconnect structure 1018 can serve as bonding layers. For example, the back surface of the first functional element 1010 and / or the back surface of the second functional element 1012 may be bonded to the front surface of the base interconnect structure 1018 (e.g., hybrid bonding).

[0219] The first functional element 1010 and the second functional element 1012 preferably have an interconnect region 1030, an active region 1032, and a substrate 1034.

[0220] Figure 10B is a detail view of a portion of assembly 1000 of Figure 10A, shown by the dashed box in Figure 10A, according to several embodiments. Power, ground, and / or signals can flow from the intermediate interconnect 1026 to the interconnect 1008 via via 1038. The via 1038 may extend from the intermediate interconnect 1026 through the base logic board 1028 and the base logic layer 1006 to the interconnect 1008. In some embodiments, the base logic layer 1006 may be configured to face-side power supply, which can be provided by the interconnect 1008. The interconnect 1008 may be used additionally or alternatively to send and receive signals to and from the interconnect 1008. The interconnect 1008 may have a plurality of contact features 1040 provided on the front surface 1011 of the interconnect 1008. The multiple contact feature portions 1040 are preferably electrically connected to the interconnect region 1030 of the functional element 1012 to transmit and receive signal routing (enclosed in the dashed box in Figure 10B). The multiple contact feature portions 1040 are preferably electrically connected to the base interconnect structure 1018 via via 1042. The via 1042 preferably penetrates the insulating material 1036. As described herein, the insulating material 1036 may consist of an inorganic dielectric, an organic dielectric, or both. The base interconnect structure 1018 is preferably electrically connected to the active region 1032 via via 1044 through the back side 1019 of the second functional element 1012. Although vias are shown in Figure 10B, it will be recognized that in some embodiments, the base interconnect structure 1018 may have contact features, such as contact pads, that can interface with contact features (e.g., contact pads, vias, etc.) of the second functional element 1012. For example, contact features may be provided on the front side 1021 of the base interconnect structure 1018 and on the back side 1019 of the second functional element 1012. The contact features of the base interconnect structure 1018 and the contact features of the second functional element 1012 may be electrically connected to each other.

[0221] Direct bonding Various embodiments disclosed herein relate to direct-bonded structures in which two or more elements can be directly bonded to each other without the use of intervening adhesives. Such processes and structures are referred to herein as “direct bonding” processes or “direct-bonded” structures. Direct bonding allows one material on one element to be bonded to one material on another element without the use of traditional adhesives (also referred to herein as “uniform” direct bonding), in which case the materials on the different elements do not need to be identical. Direct bonding also allows for the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0222] In several concrete examples (not shown), each bonding layer contains one material. In these uniform direct bonding processes, only one material on each element is directly bonded. The exemplary uniform direct bonding processes include the ZIBOND® technology, commercially available from Adeia, Inc., San Jose, California. The materials of opposing bonding layers on different elements may be the same or different, and these materials may consist of elemental materials or compounds. For example, in some embodiments, the non-conductive bonding layer may be a blanket deposited on a base substrate portion (e.g., without pads) without patterning conductive features. In other embodiments, the bonding layers may be patterned on one or both elements, and these bonding layers may be the same or different, but one material on each element is directly bonded across the entire surface of the element (or across the entire surface of the smaller element if the elements are of different sizes) without adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may include one or more conductive features, but these conductive features are not included during bonding. For example, in some embodiments, opposing non-conductive bonding layers are uniformly direct-bonded to each other, and after bonding, through-substrate vias (TSVs) are formed through one of the elements, thereby enabling electrical communication to the other element.

[0223] In various embodiments, the bonding layers 1108a and / or 1108b (see Figures 11A and 11B) are often made of a nonconductive material, such as a dielectric or an undoped semiconductor material, such as undoped silicon, such as a natural oxide. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, such as silicon carbide, oxycarbonite, low-K dielectrics, SiCOH dielectrics, silicon carbonite, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic despite containing carbon. In some embodiments, the dielectric at the bonding surface does not include polymer materials, such as epoxy (e.g., epoxy adhesives, cured epoxy, or epoxy composites, such as FR-4), resins, or molding materials.

[0224] In other embodiments, the bonding layer may consist of an electrically conductive material, such as a vapor-deposited conductive oxide material, such as indium tin oxide (ITO) as disclosed in U.S. Provisional Patent Application No. 63 / 524,564 filed June 30, 2023, which is incorporated herein by reference and whose entire description provides an example of a conductive bonding layer that does not short-circuit the contacts through the interface.

[0225] In direct bonding, a first element and a second element can be directly bonded to each other without adhesive, which differs from the vapor deposition process and results in a structurally different interface compared to the interface obtained by vapor deposition. In one application, the width of the first element in the bonded structure is approximately the same as the width of the second element. In several other embodiments, the width of the first element in the bonded structure is different from the width of the second element. The width or area of ​​the larger element in the bonded structure is preferably at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between direct bonded structures may contain defect regions where nanometer-scale voids (nanovoids) exist, unlike interfaces beneath a vapor deposition layer. Nanovoids may be formed as a result of activation of one or both of the bonding surfaces (e.g., exposure to plasma as described below).

[0226] The bond interfaces between nonconductive bonding surfaces may contain higher concentrations of material from the activation and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may be formed at the bond interface. The nitrogen peak can be detected using a secondary ion mass spectrometer (SIMS). In various embodiments, for example, nitrogen-terminated treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can be used to replace the OH groups of the hydrolyzed (OH-terminated) surface with NH2 molecules, thereby creating a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may be formed at the bond interface. In some embodiments, the bond interface may consist of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, direct bonds include covalent bonds, which are stronger than van der Waals bonds. The bonding layer may further have a polished surface planarized to a high degree of smoothness.

[0227] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded to each other without an intervening adhesive. In non-direct bonding processes that utilize adhesives, an intervening material is typically applied to one or both elements to achieve a physical bond between them. For example, in some adhesive-based processes, a fluid adhesive (e.g., an organic adhesive, e.g., epoxy) which preferably contains a conductive filler material, is applied to one or a number of elements and cured to form a physical bond (rather than a chemical or covalent bond) between them. Typical organic adhesives do not form strong chemical or covalent bonds with either element. In such processes, the bond between elements is weak and / or easily invalidated by, for example, reheating or flux removal (defluxing).

[0228] In contrast, direct bonding processes join two elements together by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in direct bonding processes between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically pre-treated (e.g., activated and / or end-bound) so that when these elements are brought into contact with each other, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than van der Waals forces or hydrogen bonds. In some specific examples (e.g., between opposing dielectric surfaces, e.g., between opposing silicon oxide surfaces), the chemical bonds may spontaneously occur at room temperature upon contact. In some specific examples, the chemical bonds between opposing nonconductive materials can be strengthened after annealing these elements.

[0229] As described above, hybrid bonding is a type of direct bonding in which both non-conductive feature parts directly bond to other non-conductive feature parts, and the conductive feature part directly bonds to the conductive feature part of the element being bonded. The interface with the non-conductive bonding material is preferably as described above, while the conductive bond is preferably formed as, for example, a direct intermetallic bond. In conventional metal bonding processes, a soluble metal alloy (e.g., solder) is often placed between the conductors of two elements and heated to melt the alloy, and then cooled to form a bond between the two elements. The resulting bond often creates a sharp interface with the conductors from both elements, and then undergoes a reversal phenomenon by reheating. In contrast, direct metal bonding, used in hybrid bonding, does not require melting or intermediate soluble metal alloys. As a result, strong mechanical and electrical bonds can be obtained without using the extremely high temperatures and pressures of thermal compression bonding, and in many cases, interdiffusion of bonded conductive features occurs throughout the bonding interface between elements, where grain growth is observed.

[0230] Figures 11A and 11B schematically show cross-sectional side views of the first and second elements 1102 and 1104, respectively, before and after the process of forming a direct-bonded structure, particularly a hybrid-bonded structure, according to several embodiments. In Figure 1B, the bonded structure 1100 has first and second elements 1102 and 1104 that are directly bonded to each other at a bond interface 1118 without intervening adhesive. The conductive feature portion 1106a of the first element 1102 is preferably electrically connected to the corresponding conductive feature portion 1106b of the second element 1104. In the illustrated hybrid-bonded structure 1100, the conductive feature portion 1106a is directly bonded to the corresponding conductive feature portion 1106b without intervening solder or conductive adhesive.

[0231] In the illustrated embodiment, the conductive feature portions 1106a and 1106b are embedded in the first bonding layer 1108a of the first element 1102 and the second bonding layer 11108b of the second element 1104, respectively, and these conductive feature portions 1106a and 1106b can be made part of the bonding layers 1108a and 1108b. The field regions of the bonding layers 1108a and 1108b extend between the conductive feature portions 1108a and 1108b and partially or completely surround them. The bonding layers 1108a and 11108b preferably have a layer of non-conductive material suitable for direct bonding as described above, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 1108a and 1108b are preferably provided on the front surfaces 1114a and 1114b of the base substrate portions 1110a and 1110b, respectively.

[0232] The first and second elements 1102 and 1104 are preferably made of ultra-miniature electronic elements, such as semiconductor elements, and examples of such semiconductor elements include integrated device dies, wafers, passive devices, discrete active devices, such as power switches and MEMS. In some embodiments, the base substrate portion preferably has a device portion, such as a bulk semiconductor (e.g., silicon) portion of elements 1102 and 1104, and a back-end-of-line (BEOL) interconnect layer on such semiconductor portion. The bonding layers 1108a and 1108b are preferably provided as part of such BEOL layer during device fabrication, as part of a surface wiring or redistribution layer (RDL), or as a specific bonding layer added to an existing device, and extend from a contact where a bond pad is located below. The active devices and / or circuit components are preferably patterned within or on the base substrate portions 1110a, 1110b and / or provided in a different manner, and the active devices and / or circuit components are preferably electrically communicated with at least some of the conductive feature portions 1108a, 1108b. The active devices and / or circuit components are preferably provided on or near the front surfaces 1114a, 1114b of the base substrate portions 1110a, 1110b and / or on or near the opposite back surfaces (back sides) 1116a, 1116b of the base substrate portions 1110a, 1110b. In other embodiments, the base substrate portions 1110a, 1110b may not contain active circuit components, but may instead include dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, grids, lenses), etc. Although the bonding layers 1108a and 1108b are shown as being provided on the front surface of the element, similar bonding layers may be provided additionally or alternatively on the back surface of the element.

[0233] In some embodiments, the base substrate portions 1110a and 1110b may have significantly different coefficients of thermal expansion (CTE), and a bonding element including such different base substrate portions can form a heterogeneous bonded structure. The difference in CTE between the bulk semiconductor (typically single crystal) portions of the base substrate portions 1110a and 1110b is preferably higher than 5 ppm / °C or higher than 10 ppm / °C. For example, the difference in CTE between the base substrate portions 1110a and 1110b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0234] In some embodiments, one of the base substrate portions 1110a and 1110b is often made of a photoelectron single crystal material useful for photoelectric or pyroelectric applications, while the other of the base substrate portions 1110a and 1110b is made of a more conventional substrate material. For example, one of the base substrate portions 1110a and 1110b is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the base substrate portions 1110a and 1110b is made of silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 1110a and 1110b is made of a single semiconductor material of Group III to V, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other base substrate portion 1110a and 1110b is preferably made of a non-Group III to V semiconductor material, such as silicon (Si), or other material having a similar CTE, such as quartz, fused silica glass, sapphire, or glass. In yet another embodiment, one of the base substrate portions 1110a and 1110b is made of a semiconductor material, and the other base substrate portion 1110a and 1110b is made of a packaging material, such as glass, organic, or ceramic substrate.

[0235] In some configurations, the first element 1102 may consist of a standalone element, such as a standalone integrated device die. In other configurations, the first element 1102 may consist of a carrier or substrate (e.g., a semiconductor wafer) containing multiple (e.g., tens, hundreds, or more) device regions that form multiple integrated device dies when standalone, although in other embodiments, such a carrier may consist of a package substrate or a passive or active interposer. Similarly, the second element 1104 may consist of a standalone element, such as a standalone integrated device die. In other configurations, the second element 1104 may consist of a carrier or substrate (e.g., a semiconductor wafer). Accordingly, the embodiments disclosed herein can be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In the W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding), and then standalone using a suitable standalone process. After individualization, the side edges of the individualized structure (e.g., the side edges of two bonded elements) are preferably located substantially on the same plane (substantially aligned in the x-y dimensions), and / or the edges of the bonding interface for both bonded and individualized elements are preferably of the same extent, and these edges preferably include markers representing a common individualization process for bonded structures (e.g., sawtooth marks if a sawtooth individualization process is used).

[0236] Although only two elements 1102 and 1104 are shown, any number of elements can be stacked in the bonded structure 1100. For example, a third element (not shown) can be stacked on the second element 1104, a fourth element (not shown) can be stacked on the third element, and so on. In such embodiments, through-substrate vias (TSVs) can be formed to enable vertical electrical communication between and / or within the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 1102. In some embodiments, the additional elements stacked laterally are preferably smaller than the second element. In some embodiments, the bonded structure is preferably wrapped in an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxycarbonitride, etc.). One or more insulating layers are preferably provided on the bonded structure. For example, in some specific examples, the first insulating layer can be deposited identically onto the bonded structure, and a second insulating layer (which may be made of the same or different material as the first insulating layer) can be provided on the first insulating layer.

[0237] To achieve direct bonding between bonding layers 1108a and 1108b, it is preferable to pre-treat the bonding layers 1108a and 1108b to enable direct bonding. It is preferable to pre-treat the non-conductive bonding 1112a and 1112b on the upper or outer surface of bonding layers 1108a and 1108b to enable direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 1112a and 1112b should be less than 15 Årms. For example, the roughness of the bonding surfaces 1112a and 1112b should be in the range of approximately 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. Furthermore, it is preferable to optimize the polishing process so that the conductive feature portions 1106a and 1106b are recessed relative to the field regions of the bonding layers 1108a and 1108b.

[0238] In the pretreatment that enables direct bonding, it is preferable to further clean one or both of the bonding surfaces 1112a and 1112b, and then activate at least one of the surfaces 1112a and 1112b by exposure to plasma and / or an etching agent. In some embodiments, it is preferable to end-group one or both of the surfaces 1112a and 1112b with chemical species after or during activation (e.g., during the plasma and / or etching process). Although not bound by theory, in some embodiments, the activation process is often carried out to break the chemical bonds at the bonding surfaces 1112a and 1112b, and the end-grouping process can provide additional chemical species at the bonding surfaces 1112a and 1112b, which alter the chemical bonds and / or improve the bonding energy during direct bonding. In some embodiments, activation and / or end-binding are performed in the same step, for example, in a plasma, thereby activating and end-binding the surfaces 1112a and 1112b. In other embodiments, one or both of the bonding surfaces 1112a and 1112b may be end-binding by a separate treatment to provide additional chemical species for direct bonding. In various embodiments, the end-binding species may consist of nitrogen. For example, in some embodiments, the bonding surfaces 1112a and 1112b may be exposed to a nitrogen-containing plasma. Other end-binding species may be suitable for improving the bonding energy, depending on the material of the bonding surfaces 1112a and 1112b. Furthermore, in some embodiments, the bonding surfaces 1112a and 1112b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bond interface 1118 between the first element 1102 and the second element 1104. Typically, fluorine concentration peaks occur at the interfaces between material layers.Examples of additional activation and / or end-forming treatments are found in U.S. Patent No. 9,391,143, lines 55-3 of column 5 to 3 of column 7, lines 52-45 of column 8 to 45 of column 9, lines 24-36 of column 10, lines 24-32 of column 11, lines 42-47, lines 52-55, and lines 60-64 of column 12 to 3 to 14, lines 31-33, and lines 55-67, and lines 38-40 of column 14. , and lines 44-50, and lines 41-50, column 4, lines 7-22, line 39, lines 55-61, column 8, lines 25-31, lines 35-40, lines 49-56, and column 12, lines 46-61 of the same U.S. Patent Application No. 10,434,749, which are cited by reference and whose teachings on activation and end-forming are incorporated herein by reference.

[0239] Thus, in the direct bonded structure 1100, the bond interface 1118 between the two nonconductive materials (e.g., bonding layers 1108a, 1108b) preferably has a very smooth interface with a relatively high nitrogen (or other end-grouping species) content and / or a fluorine concentration peak at the bond interface 1118. In some embodiments, the nitrogen and / or fluorine concentration peaks can be detected using various forms of inspection techniques, such as SIMS techniques. The polished bonding surfaces 1112a, 1112b may be slightly rough after the activation process (e.g., about 1 Årms to 30 Årms, 3 Årms to 20 Årms, or possibly rougher). In some embodiments, a slightly smooth surface can be obtained if, as a result of activation and / or end-grouping, prior to bonding, for example, plasma treatment preferentially erodes the high points on the bonding surface.

[0240] The nonconductive bonding layers 1108a and 1108b can be directly bonded to each other without adhesive. In some embodiments, elements 1102 and 104 are bonded at room temperature, in which case no voltage is required, nor is it necessary to apply external pressure or force exceeding the external pressure or force used to avoid mutual contact between the two elements 1102 and 1104. Contact alone can cause direct bonding (e.g., coelectric bonding) between the nonconductive layer surfaces of bonding layers 1108a and 1108b. Subsequent annealing of the bonded structure 1100 allows the conductive feature portions 1106a and 1106b to be directly bonded to each other.

[0241] In some embodiments, prior to direct bonding, the conductive feature portions 1106a and 1106b are recessed relative to the surrounding field region, resulting in a total gap between opposing contacts after dielectric bonding and before annealing being less than 15 nm or less than 10 nm. Since the recess depth of the conductive feature portions 1106a and 1106b may vary across the entire element due to process variations, the gap may represent the maximum or average gap between corresponding conductive feature portions 1106a and 1106b of the two junction elements (before annealing). During annealing, the conductive feature portions 1106a and 1106b expand and come into contact with each other, thereby forming an intermetallic direct bond.

[0242] During annealing, the conductive feature portions 1106a, 1106b (e.g., metallic material) can expand while the direct bond between the nonconductive materials surrounding the bonding layers 1108a, 1108b resists separation of the elements. As a result, thermal expansion increases the internal contact pressure between the opposing conductive feature portions. Annealing can also induce metal grain growth across the bonding interface, resulting in grains from one element migrating across the bonding interface into the other element, and vice versa. Thus, in some hybrid bonding embodiments, the opposing conductive materials are joined without heating above the melting temperature of the conductive material, and as a result, the bond can be formed at a lower annealing temperature compared to soldering or thermocompression bonding.

[0243] In various embodiments, the conductive feature portions 1106a, 1106b may have separate pads, contacts, electrodes, or traces at least partially embedded within the non-conductive field regions of the bonding layers 1108a, 1108b. In some embodiments, the conductive feature portions 1106a, 1106b may have exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0244] As described above, in some embodiments, in elements 1102 and 1104 of Figure 1A before direct bonding, it is common to recess a portion of each conductive feature portion 1106a and 1106b below the nonconductive bonding surface 1111a and 1111b, for example, by less than 30 nm, less than 20 nm, 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to process variations, both dielectric thicknesses and conductor recess depths may vary across the entire element. Therefore, the recess depth ranges described above may apply to individual conductive feature portions 1106a and 1106b, or to the average depth of the recess relative to the local nonconductive field region. Even in the case of individual conductive feature portions 1106a and 1106b, the depth of the vertical recess may vary throughout the entire conductive feature portion. Therefore, it is preferable to measure the depth of such vertical recess in the lateral middle or center of the cavity formed in a given conductive feature portion 1106a or 1106b, or near thereto, or to measure it on the side of the cavity.

[0245] Beneficial, the use of hybrid bonding technology (e.g., Direct Bond Interconnect, i.e., DBI® technology, commercially available from Adeia, Inc. in San Jose, California) enables high density of connections between conductive feature portions 1106a, 1106b across the entire direct bond interface 1118 (e.g., small or fine pitch compared to a typical array).

[0246] In some embodiments, the pitch p of the conductive feature portions 1106a, 1106b, for example, the conductive trace embedded in the bonding surface of one of the bonded elements, is preferably less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive feature portions 1106a, 1106b to one of the lateral dimensions of the bonding pad (e.g., diameter) is less than 20, less than 10, less than 5, or less than 3, and in some cases preferably less than 2. In various embodiments, the conductive feature portions 1106a, 1106b and / or traces are preferably made of copper or a copper alloy, but other metals, such as nickel, aluminum, or alloys thereof, may be suitable. The conductive feature portions disclosed herein, for example, the conductive feature portions 1106a, 1106b, are preferably made of metal nanoparticles (e.g., copper nanoparticles). Furthermore, the larger lateral dimension (for example, the pad diameter) should also be small, preferably in the range of 0.25 μm to 30 μm, approximately 0.25 μm to 5 μm, or approximately 0.5 μm to 5 μm.

[0247] With respect to the hybrid bonded elements 1102 and 1104, as shown in the figure, it is preferable that the orientations of one or more conductive feature portions 1106a and 1106b, as viewed from opposing elements, be opposite to each other. As is known in the art, conductive feature portions in general are preferable to have side walls at a near-perpendicular angle, especially when directional reactive ion etching (RIE) directly etches the conductive material, or when directional reactive ion etching (RIE) indirectly etches the surrounding insulator, forming the conductor side walls. However, there may be some slight taper to the conductor side walls, and the conductor becomes thinner as it moves away from the surface first exposed to etching. The taper may be even more pronounced when the conductive side walls are formed directly or indirectly by isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature portion 1106b (and / or at least one internal conductive feature portion, e.g., BEOL feature portion) in the bonding layer 1108b of the upper element 1104 may taper or narrow upward away from the bonding surface 1112b. In contrast, at least one conductive feature portion 1106a (and / or at least one internal conductive feature portion, e.g., BEOL feature portion) in the bonding layer 1108a of the lower element 1102 may taper or narrow downward away from the bonding surface 1110a. Similarly, any bonding layer (not shown) on the back sides 1116a, 1116b of elements 1102, 1104 may taper or narrow away from the back side, having the opposite taper direction to the front side conductive feature portions 1106a, 1106b of the same element.

[0248] As described above, in the annealing phase of hybrid bonding, the conductive feature portions 1106a and 1106b expand and come into contact with each other, thereby forming an intermetallic direct bond. In some embodiments, the materials of the conductive feature portions 1106a and 1106b of opposing elements 1102 and 1104 can interdiffuse during the annealing process. In some embodiments, metal crystal grains grow across the bond interface 1118 and interpenetrate each other. In some embodiments, the metal is or contains copper, which preferably has crystal grains oriented along the 111 crystal plane to improve the degree of copper diffusion across the bond interface 1118. In some embodiments, the conductive feature portions 1106a and 1106b preferably contain a nanotwinned copper crystal structure, which can help the bonding of the conductive feature portions during high-temperature annealing. There is no substantial gap between the non-conductive bonding layers 1108a, 1108b at or near the bonded conductive feature portions 1106a, 1106b. In some embodiments, the barrier layer is preferably provided beneath or laterally surrounding the conductive feature portions 1106a, 1106b (which may, for example, contain copper). However, in other embodiments, there may be no barrier layer beneath the conductive feature portions 1106a, 1106b.

[0249] Additional Embodiments Unless otherwise explicitly stated in the context, throughout the original specification and claims, terms such as “comprise” (often translated as “having,” “comprising,” “include,” and “including” should be understood in a comprehensive sense, not in an exclusive or exhaustive sense, that is, in the sense of “including, but not limited to.” The term “combined” as commonly used herein means two or more elements that are directly linked to each other or linked to each other by one or more intermediate elements. Similarly, the term “linked” as commonly used herein means two or more elements that are directly linked to each other or linked to each other by one or more intermediate elements. Furthermore, the terms “herein” (often translated as “in this specification”), “above” (meaning “above” or “on top of”), “below” (meaning “below” or “below”), and similar terms used in this application refer to the application as a whole and not to any particular part thereof. Moreover, where it is stated that the first element is “on top of” or “covering” the second element, as used in this specification, the first element may be directly located on or covering the second element such that the first and second elements are in direct contact, or the first element may be indirectly located on or covering the second element such that one or more elements are interposed between the first and second elements. Where the context allows, the terms in the above detailed descriptions, whether singular or plural, may each include plural or singular forms. With respect to a list of two or more items, the term "or" includes the following interpretations of this term: any item in the list, all items in the list, and any combination of items in the list.

[0250] Furthermore, conditional words used in the original specification, particularly "can" ("it would be good to" or "it may be"), "could," "might," "may," "eg," "for example," and "such as," generally mean, unless explicitly specified otherwise or understood differently in the context in which they are used, that a particular embodiment includes a particular feature, element, and / or state, while other embodiments do not include a particular feature, element, and / or state. Thus, such conditional words generally do not mean that a feature, element, and / or state exists in any way necessary for one or more embodiments.

[0251] While certain embodiments have been described, these embodiments are provided for illustrative purposes only and do not limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein can be embodied in various other forms, and furthermore, various omissions, substitutions, and modifications in the forms of methods and systems described herein can be carried out without departing from the scope of the invention. For example, while blocks are shown in a given arrangement, modified embodiments can perform substantially the same function with different components and / or circuit topologies, and some blocks can be removed, moved, added, divided, combined, and / or modified. Each of these blocks can be embodied in a wide variety of ways. Any suitable combination of elements and functions of the various embodiments described above can be combined to provide another embodiment. The scope of the invention as described in the appended claims and its equivalents includes such forms or modifications that fall within the scope and spirit of the invention.

[0252] Some specific feature elements described in this disclosure in relation to separate embodiment examples can also be embodied in combination in a single embodiment example. Conversely, various feature elements described in relation to a single embodiment example can also be embodied separately or in any appropriate subcombination in multiple embodiment examples. Furthermore, if a feature element has been described above as functioning in some particular combination, one or more feature elements described in a claimed combination may, in some cases, be removed from the combination, and such combination may be claimed as a subcombination or a variation of a subcombination.

[0253] Furthermore, while illustrated embodiments have been described, any embodiments having equivalent elements, modifications, omissions, and / or combinations are also within the scope of this disclosure. Moreover, while certain viewpoints, advantages, and novel features have been described herein, not all of such advantages are necessarily achieved according to any particular embodiment. For example, some embodiments within the scope of this disclosure achieve one or a group of advantages without necessarily achieving other advantages taught or suggested herein, as taught herein. Furthermore, some embodiments may achieve advantages different from those taught or suggested herein.

[0254] Several embodiments have been described in conjunction with the accompanying drawings. These drawings may or may not be drawn to scale, and such scale is not limiting to the invention, as dimensions and ratios other than those shown are assumed and are within the scope of the disclosed invention. Distances, angles, etc., are illustrative and do not necessarily have an exact relationship to the actual dimensions and layout of the illustrated devices. Components can be added, omitted, and / or rearranged. Furthermore, any specific features, viewpoints, methods, properties, characteristics, qualities, attributes, elements, etc., disclosed herein in relation to various embodiments can be used in other embodiments described herein. In addition, any method described herein can be carried out using any device suitable for performing the listed steps.

[0255] For the purpose of summarizing the present invention, certain particular views, advantages, and features of the present invention have been described herein. None of these advantages are necessarily achieved, or any of them are not achieved, according to any particular embodiment of the present invention disclosed herein. There are no essential or necessary views of the present invention. In many embodiments, devices, systems, and methods may be configured in ways different from the illustrated configuration or the description herein. For example, various methods provided by the illustrated methods can be combined, reconfigured, added, or deleted. In some embodiment, additional or different processors or modules can perform some or all of the functions described and illustrated with respect to the embodiments described. Many modifications of the specific examples are possible. Any of the features, structures, steps, or processes disclosed herein can be said to be included in any embodiment.

[0256] Furthermore, various modifications and variations can be made to the methods and devices described herein, the specific embodiments of which are shown in the drawings and described in detail herein. However, it should be understood that these embodiments are not limited to any particular form or method disclosed, but rather the embodiments extend to any modifications, equivalents, and variations that fall within the spirit and scope of the invention as described in the claims and the various embodiments described herein. Furthermore, any specific features, views, methods, characteristics, features, qualities, attributes, elements, etc., disclosed herein in relation to an embodiment or example, may be used in all embodiments or examples described herein. The methods disclosed herein do not need to be performed in the order described herein. The methods disclosed herein may include certain actions performed by the practitioner, and such methods may further include, explicitly or implicitly, the instruction of any third party to perform such actions. Also, the scope disclosed herein includes any and all overlaps, partial scopes, and combinations thereof. For example, terms such as “up to,” “at least,” “more than,” “less than,” and “between,” include the numbers described. For example, numbers following "approximately" or "nearly" include the stated number, and such numbers should be interpreted on a case-by-case basis (e.g., as accurate as reasonably possible under such circumstances, e.g., ±5%, ±10%, ±15%). For example, "approximately 3.5 mm" means "including 3.5 mm." For example, phrases following the term "substantially" include the stated phrase, and such phrases should be interpreted on a case-by-case basis (e.g., as much as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are taken under standard conditions, including temperature and pressure.

[0257] The expression "at least one of" the list of items used herein refers to any combination of such items, which includes only one element. For example, "at least one of A, B, or C" includes A, B, C, A·B, A·C, B·C, and A·B·C. Conjunctions, such as "at least one of X, Y, and Z," are understood in the context in which they are commonly used to mean that an item, term, etc., may be at least one of X, Y, or Z, unless otherwise specified. Thus, such conjunctions do not mean that a particular embodiment must each contain at least one X, at least one Y, and at least one Z. Headings, if present herein, are provided for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0258] Therefore, the inventions described in the claims are not limited to the embodiments shown herein, but rather provide the broadest scope consistent with the inventions, principles, and novel features disclosed herein.

Claims

1. It is an electronic assembly, The base includes a base substrate having a front side on which active circuit components are provided and a back side opposite to the front side, a first bonding layer provided on the front side of the base substrate, and a base element having a signal pad for sending electrical signals to the active circuit components on the front side of the base substrate, An electronic assembly comprising a first semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, and a first functional element having a second bonding layer provided on the front side of the first semiconductor substrate, wherein the back side of the first functional element has a first contact feature portion connected to a power source or ground, and the first bonding layer is hybrid-bonded to the second bonding layer.

2. The electronic assembly according to claim 1, further comprising an insulating material provided along the side surface of the first functional element and on the first bonding layer.

3. The electronic assembly according to claim 2, wherein the insulating material is made of an inorganic dielectric.

4. The electronic assembly according to claim 3, wherein the insulating material is made of silicon oxide.

5. The electronic assembly according to claim 2, wherein the insulating material is made of an organic dielectric.

6. The electronic assembly according to claim 2, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

7. The electronic assembly according to claim 1, further comprising an interconnect structure provided on the back surface of the first functional element and electrically connected to the first contact feature portion.

8. The electronic assembly according to claim 7, wherein the interconnect structure has a rewiring layer.

9. The electronic assembly according to claim 7, wherein the interconnect structure has one or more metallization layers.

10. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on the intermediate interconnect layer, closer to the front surface of the interconnect structure than the intermediate interconnect layer. The electronic assembly according to claim 7, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

11. The interconnect structure further includes input / output (IO) pads provided near the front surface of the interconnect structure. The I / O pad is in electrical contact with the global interconnect layer. The electronic assembly according to claim 10, wherein the I / O pads are exposed on the front surface of the interconnect structure.

12. The electronic assembly according to claim 1, further comprising a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side.

13. The electronic assembly according to claim 12, wherein the second functional element has a third bonding layer provided on the front side of the second semiconductor substrate, and the third bonding layer is hybrid-bonded to the first bonding layer.

14. The back side of the second functional element is hybrid bonded to the first bonding layer. The electronic assembly according to claim 12, wherein the second functional element has a second contact feature portion provided on the front surface of the second functional element.

15. It is an electronic assembly, The base includes a base substrate having a front side and a back side opposite to the front side, and a base element having a first bonding layer provided on the front side of the base substrate. The first semiconductor substrate includes a front side on which active circuit components are provided and a back side opposite to the front side, and a first functional element having a second bonding layer provided on the front side of the first semiconductor substrate, wherein the back side of the first functional element has a first contact feature portion that connects to a power source or ground. The second functional element includes a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, An electronic assembly in which the first bonding layer is hybrid-bonded to the second bonding layer, and the second semiconductor element is hybrid-bonded to the base element.

16. The electronic assembly according to claim 15, wherein the back side of the second semiconductor substrate is hybrid-bonded to the base element, and the second functional element has a second contact feature portion provided on the front surface of the second functional element for connection to a power source or ground.

17. The electronic assembly according to claim 15, wherein the front side of the second functional element is hybrid-bonded to the front surface of the base substrate, and the back side of the second functional element has a second contact feature portion for connection to a power supply or ground.

18. The electronic assembly according to claim 15, wherein the first bonding layer has contact features for sending electrical signals to the active circuit components on the front side of the base substrate.

19. The electronic assembly according to claim 15, further comprising an insulating material provided along the side surface of the first functional element and on the first bonding layer.

20. The electronic assembly according to claim 19, wherein the insulating material is made of an inorganic dielectric.

21. The electronic assembly according to claim 20, wherein the insulating material is made of silicon oxide.

22. The electronic assembly according to claim 19, wherein the insulating material is made of an organic dielectric.

23. The electronic assembly according to claim 19, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

24. The electronic assembly according to claim 15, further comprising an interconnect structure provided on the back side of the first semiconductor substrate and electrically connected to the first contact feature portion.

25. The electronic assembly according to claim 24, wherein the interconnect structure has a rewiring layer.

26. The electronic assembly according to claim 24, wherein the interconnect structure has one or more metallization layers.

27. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on the intermediate interconnect layer, closer to the front surface of the interconnect structure than the intermediate interconnect layer. The electronic assembly according to claim 24, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

28. The interconnect structure further includes input / output (IO) pads provided near the front surface of the interconnect structure. The I / O pad is in electrical contact with the global interconnect layer. The electronic assembly according to claim 27, wherein the I / O pads are exposed on the front surface of the interconnect structure.

29. A base logic board having a front side and a back side in which an active area is provided, The base logic board further includes a base interconnect layer provided on the front side of the base logic board, The electronic assembly according to claim 15, wherein the base interconnect layer is hybrid bonded to the back surface of the first semiconductor substrate.

30. The electronic assembly according to claim 29, further comprising an interconnect structure having a front surface and a back surface, wherein the back surface of the interconnect structure is provided on the back side of the base logic board.

31. It is an electronic assembly, It includes a base element having a front surface and a back surface opposite to the front surface, The first functional element includes a substrate having a front side and a back side opposite to the front side, wherein the front side of the first functional element is electrically connected to the front surface of the base element while being provided on the front surface of the base element. The second functional element includes a substrate having a front side on which an active region is provided and a back side opposite to the front side, The first functional element includes an interconnect structure that is provided on the back side of the substrate and electrically connected to the back side, The first functional element has power and ground connection parts provided on its back side, The first functional element has a signal connection portion provided on the front side, An electronic assembly in which the front side of the first functional element is hybrid-bonded to the front surface of the base element.

32. The aforementioned base device is A base die substrate having a front side and a back side, The electronic assembly according to claim 31, further comprising a base die interconnect structure provided on the front side of the base die substrate.

33. The electronic assembly according to claim 32, wherein the base die substrate further comprises a base die active region provided on the front side of the base die substrate.

34. The base die interconnect structure has a local interconnect layer and an intermediate interconnect layer. The local interconnect layer of the base die interconnect structure is electrically connected to the base die active region. The intermediate interconnect layer of the base die interconnect structure is electrically connected to the local interconnect layer of the base die interconnect structure. The electronic assembly according to claim 33, wherein the intermediate interconnect layer of the base die interconnect structure is electrically connected to the interconnect structure.

35. The electronic assembly according to claim 31, wherein the interconnect structure has a rewiring layer.

36. The electronic assembly according to claim 31, wherein the interconnect structure has one or more metallization layers.

37. The electronic assembly according to claim 32, wherein the base die interconnect structure has a redistribution layer.

38. The electronic assembly according to claim 32, wherein the base die interconnect structure has one or more metallization layers.

39. The electronic assembly according to claim 31, further comprising an insulating material provided along the side surface of the first functional element and on the first bonding layer.

40. The electronic assembly according to claim 39, wherein the insulating material is made of an inorganic dielectric.

41. The electronic assembly according to claim 40, wherein the inorganic dielectric is made of silicon oxide.

42. The electronic assembly according to claim 39, wherein the insulating material is made of an organic dielectric.

43. The electronic assembly according to claim 39, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

44. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on top of the intermediate interconnect layer, The electronic assembly according to claim 31, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

45. The interconnect structure further includes input / output (I / O) pads provided on the top surface of the global interconnect layer, The I / O pad is exposed at the top surface of the interconnect structure. The electronic assembly according to claim 44, wherein the top surface of the global interconnect layer is one side of the global interconnect layer that is furthest from the first functional element.

46. The first functional element is, The electronic assembly according to claim 31, further comprising a plurality of vias extending from the back side of the first functional element to the active region of the first functional element so as to electrically connect the interconnect structure to the active region of the first functional element.

47. The electronic assembly according to claim 31, wherein the second functional element comprises a front surface and a back surface.

48. The front surface of the second functional element is provided on the front surface of the base element, The electronic assembly according to claim 47, wherein the interconnect structure is further provided on the back side of the second functional element.

49. The electronic assembly according to claim 47, wherein the back surface of the second functional element is provided on the front surface of the base element.

50. The electronic assembly according to claim 47, wherein the front surface of the first functional element is hybrid-bonded to the front surface of the base element, and the front surface of the second functional element is hybrid-bonded to the front surface of the base element.

51. The electronic assembly according to claim 49, wherein the back surface of the second functional element is hybrid-bonded to the front surface of the base element.

52. The electronic assembly according to claim 47, wherein the second functional element is electrically connected to either a power source or ground via the back side of the second functional element.

53. The second functional element is electrically connected to a power supply or ground via the back surface of the second functional element. The electronic assembly according to claim 47, wherein the second functional element has a signal and electrical contact feature portion provided on the front surface of the second functional element.

54. The base element has a base die interconnect structure, The electronic assembly according to claim 47, wherein the base die interconnect structure has an integrated voltage regulator.

55. The first functional element directly receives power from the base die interconnect structure at a first voltage. The second functional element receives power at a second voltage different from the first voltage. The electronic assembly according to claim 54, wherein the second functional element receives power routed from the base die interconnect structure to the integrated voltage regulator.

56. The electronic assembly according to claim 55, wherein the second functional element has power supply and ground electrical contact features provided on the back surface of the second functional element.

57. The electronic assembly according to claim 47, wherein the second functional element has power supply and ground electrical connection portions provided on the front side of the second functional element.

58. The electronic assembly according to claim 39, further comprising vias extending from the interconnect structure to the front surface of the base element.

59. The electronic assembly according to claim 31, wherein the interconnect structure further comprises a mixed signal element.

60. The electronic assembly according to claim 31, wherein the interconnect structure further comprises a passive element.

61. The electronic assembly according to claim 31, further comprising a heat spreader provided on the back surface of the base element.

62. A base logic board having a front side and a back side in which an active area is provided, The base logic board further includes a base interconnect layer provided on the front side of the base logic board, The electronic assembly according to claim 31, wherein the base interconnect layer is hybrid bonded to the back surface of the first functional element.

63. It is a method, The process includes the step of preparing a base element, wherein the base element has a front surface, a back surface, and a base element contact feature portion provided on the front surface of the base element to electrically connect to a first functional element having the front surface and the back surface. The process includes the step of bonding the front surface of the first functional element to the front surface of the base element, The process includes the step of forming an insulating material on the side surface of the first functional element, The process includes the step of forming the interconnect structure on the back surface of the first functional element and on the insulating material, The first functional element has power supply and ground electrical contact features provided on the back surface of the first functional element, The first functional element has signal and electrical contact feature portions provided on the front surface of the first functional element, The interconnect structure is electrically connected to the power supply and ground electrical contact features of the first functional element.

64. The method according to claim 63, wherein the step of bonding the front surface of the first functional element to the front surface of the base element includes the step of hybrid bonding the front surface of the first functional element to the front surface of the base element.

65. The aforementioned base device is A base die substrate having a front side and a back side, The method according to claim 63, further comprising a base die interconnect structure provided on the front side of the base substrate.

66. The method according to claim 65, wherein the base die substrate has a base die active region provided on the front side of the base die substrate.

67. The base die interconnect structure has a local interconnect layer and an intermediate interconnect layer. The local interconnect layer of the base die interconnect structure is electrically connected to the base die active region. The intermediate interconnect layer of the base die interconnect structure is electrically connected to the local interconnect layer of the base die interconnect structure. The method according to claim 66, wherein the intermediate interconnect layer of the base die interconnect structure is electrically connected to the interconnect structure.

68. The method according to claim 63, wherein the interconnect structure has a rewiring layer.

69. The method according to claim 63, wherein the interconnect structure has one or more metallization layers.

70. The method according to claim 65, wherein the base die interconnect structure has a rewiring layer.

71. The method according to claim 65, wherein the base die interconnect structure has one or more metallization layers.

72. The method according to claim 63, wherein the insulating material is made of an inorganic dielectric.

73. The method according to claim 72, wherein the inorganic dielectric is silicon oxide.

74. The method according to claim 63, wherein the insulating material is an organic dielectric.

75. The method according to claim 63, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

76. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The method according to claim 63, wherein the global interconnect layer is provided on top of the intermediate interconnect layer.

77. The interconnect structure further includes input / output (I / O) pads provided on the top surface of the global interconnect layer, The method according to claim 76, wherein the I / O pad is exposed at the top surface of the interconnect structure.

78. The first functional element is, The first functional element further comprises an active region of the first functional element provided near the front surface of the first functional element, The method according to claim 63, wherein the interconnect structure sends power or ground to the active region of the first functional element via the back surface of the first functional element.

79. The method according to claim 78, wherein the interconnect structure has a plurality of nanovias extending from the back surface of the first functional element to the active region of the first functional element.

80. The method according to claim 63, further comprising the step of bonding a second functional element to the front surface of the base element, wherein the second functional element has a front surface and a back surface, and the second functional element is bonded to the front surface of the base element via the front surface of the second functional element.

81. The method according to claim 80, wherein the front surface of the second functional element is hybrid-bonded to the front surface of the base element.

82. The method according to claim 63, wherein the front surface of the first functional element is hybrid-bonded to the front surface of the base element.

83. The method according to claim 80, wherein the front surface of the first functional element is hybrid-bonded to the front surface of the base element, and the front surface of the second functional element is hybrid-bonded to the front surface of the base element.

84. The method according to claim 80, wherein the second functional element is electrically connected to a power source or ground via the front surface of the second functional element.

85. The second functional element has an electrical connection portion to a power supply and ground provided on the back surface of the second functional element. The method according to claim 80, wherein the second functional element has a signal and electrical connection portion provided on the front surface of the second functional element.

86. The method according to claim 63, further comprising the step of forming an electrical interconnect extending from the top surface of the insulating material to the bottom surface of the insulating material, wherein the bottom surface of the insulating material is in contact with the front surface of the base element.

87. The method according to claim 73, wherein the interconnect structure further comprises a mixed signal element.

88. The method according to claim 63, wherein the interconnect structure further comprises a passive element.

89. The method according to claim 63, further comprising the step of placing the heat spreader in thermal contact with the back surface of the base element.

90. The method according to claim 80, wherein the base element has a base die interconnect structure equipped with an integrated voltage regulator.

91. The first functional element directly receives power from the base die interconnect structure at a first voltage. The second functional element receives power at a second voltage different from the first voltage. The method according to claim 90, wherein the second functional element receives power routed from the base die interconnect structure to the integrated voltage regulator.

92. The steps include forming a base logic board having a front side and a back side on which an active area is provided, The steps include forming a base interconnect layer on the front side of the base logic board, The method according to claim 63, further comprising the step of hybrid bonding the base interconnect layer to the back surface of the first functional element.

93. The method according to claim 92, further comprising the step of forming a base die interconnect structure having a front surface and a back surface, wherein the back surface of the base die interconnect structure is provided on the back side of the base logic board.

94. It is a method, The step includes preparing a base element, the base element being The base board has a front side on which active circuit components are provided and a back side opposite to the front side, The base substrate has a first bonding layer provided on the front side, and the first bonding layer has contact features for sending electrical signals to the active circuit component. The step includes preparing a first functional element, the first functional element being The first semiconductor substrate has a front side on which active circuit components are provided and a back side opposite to the front side, The first functional element has a first contact feature portion provided on its back surface and configured to be connected to a power source or ground, The first semiconductor substrate has a second bonding layer provided on the front side, A method comprising the step of hybrid bonding the first bonding layer of the base element to the second bonding layer of the first functional element.

95. The method according to claim 94, further comprising the step of forming an insulating material along the side surface of the first functional element and on the first bonding layer.

96. The method according to claim 95, wherein the insulating material is made of an inorganic dielectric.

97. The method according to claim 96, wherein the insulating material is made of silicon oxide.

98. The method according to claim 95, wherein the insulating material is an organic dielectric.

99. The method according to claim 95, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

100. The method according to claim 94, further comprising the step of forming an interconnect structure provided on the back surface of the first functional element and also electrically connected to the first contact feature portion.

101. The method according to claim 100, wherein the interconnect structure has a rewiring layer.

102. The method according to claim 100, wherein the interconnect structure has one or more metallization layers.

103. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on the intermediate interconnect layer, closer to the front surface of the interconnect structure than the intermediate interconnect layer. The method according to claim 100, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

104. The interconnect structure further includes input / output (IO) pads provided near the front surface of the interconnect structure. The I / O pad is in electrical contact with the global interconnect layer. The method according to claim 103, wherein the I / O pad is exposed on the front surface of the interconnect structure.

105. The method according to claim 94, further comprising the step of providing a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side.

106. The method according to claim 105, wherein the second functional element has a third bonding layer provided on the front side of the second semiconductor substrate, and the third bonding layer is hybrid-bonded to the first bonding layer.

107. The process further includes the step of hybrid bonding the back side of the second functional element to the first bonding layer, The method according to claim 105, wherein the second functional element has a second contact feature portion provided on the front surface of the second functional element.

108. It is a method, The step includes preparing a base element, the base element being A base substrate having a front side and a back side opposite to the front side, The base substrate has a first bonding layer provided on the front side, The step includes providing a first functional element, wherein the first functional element is A first semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, The first semiconductor substrate has a second bonding layer provided on the front side, and the back side of the first semiconductor substrate has a first contact feature portion connected to a power source or ground. The step includes providing a second functional element, wherein the second functional element is The semiconductor substrate has a front side on which active circuit components are provided and a back side opposite to the front side, The process includes the step of hybrid bonding the first bonding layer to the second bonding layer, A method comprising the step of hybrid bonding the second functional element to the first bonding layer.

109. The method according to claim 108, further comprising the step of hybrid bonding the back side of the second semiconductor substrate to the base element, wherein the second functional element has a second contact feature provided on the front side of the second semiconductor substrate for connection to a power source or ground.

110. The method according to claim 108, further comprising the step of hybrid bonding the front side of the second functional element to the first bonding layer, wherein the back side of the second semiconductor element has a second contact feature for connection to a power source or ground.

111. The method according to claim 108, wherein the first bonding layer has contact features for sending an electrical signal to the active circuit component.

112. The method according to claim 108, further comprising the step of forming an insulating material along the side surface of the first functional element and on the first bonding layer.

113. The method according to claim 112, wherein the insulating material is made of an inorganic dielectric.

114. The method according to claim 113, wherein the insulating material is made of silicon oxide.

115. The method according to claim 112, wherein the insulating material is made of an organic dielectric.

116. The method according to claim 112, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

117. The method according to claim 108, further comprising the step of forming an interconnect structure provided on the back side of the first semiconductor substrate and also electrically connected to the first contact feature portion.

118. The method according to claim 117, wherein the interconnect structure has a rewiring layer.

119. The method according to claim 117, wherein the interconnect structure has one or more metallization layers.

120. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on the intermediate interconnect layer, closer to the front surface of the interconnect structure than the intermediate interconnect layer. The method according to claim 117, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

121. The interconnect structure further includes input / output (IO) pads provided near the front surface of the interconnect structure. The I / O pad is in electrical contact with the global interconnect layer. The method according to claim 120, wherein the I / O pad is exposed on the front surface of the interconnect structure.

122. The steps include: preparing a base logic board having a front side and a back side in which an active area is provided; The steps include: preparing a base interconnect layer provided on the front side of the base logic board; The method according to claim 108, further comprising the step of hybrid bonding the base interconnect layer to the back surface of the first semiconductor substrate.

123. The method according to claim 122, further comprising the step of forming an interconnect structure having a front surface and a back surface, wherein the back surface of the interconnect structure is provided on the back side of the base logic board.

124. It is an electronic assembly, Includes an interconnect structure with one or more input / output (I / O) pads, The first functional element includes a first semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, wherein the front surface of the first functional element has a first contact feature portion connected to one or more I / O pads. An electronic assembly comprising a second functional element having a second semiconductor substrate having a front side on which active circuit components are provided and a back side opposite to the front side, wherein the back surface of the second functional element has a second contact feature portion connected to one or more I / O pads.

125. The electronic assembly according to claim 124, wherein the first and second contact features are configured to be connected to a power source or ground.

126. The electronic assembly according to claim 124, further comprising a base element, wherein the first functional element and the second functional element are provided on the base element.

127. The electronic assembly according to claim 126, wherein the base element further comprises a base substrate having a front side on which an active circuit component is provided and a back side opposite to the front side, a first bonding layer provided on the front side of the base substrate, and a signal pad for sending an electrical signal to the active circuit component on the front side of the base substrate.

128. The electronic assembly according to claim 127, further comprising a second bonding layer provided on the front side of a first semiconductor substrate, and a third bonding layer provided on the front side of the second semiconductor substrate, wherein the first bonding layer is hybrid-bonded to the second bonding layer, and the third bonding layer is hybrid-bonded to the first bonding layer.

129. The electronic assembly according to claim 128, further comprising an insulating material provided along the side surface of the first functional element and on the first bonding layer.

130. The electronic assembly according to claim 129, wherein the insulating material is made of an inorganic dielectric.

131. The electronic assembly according to claim 130, wherein the insulating material is made of silicon oxide.

132. The electronic assembly according to claim 129, wherein the insulating material is made of an organic dielectric.

133. The electronic assembly according to claim 129, wherein the insulating material is made of low-temperature tetraethyl orthosilicate.

134. The electronic assembly according to claim 124, further comprising an interconnect structure provided on the back side of the second semiconductor substrate and electrically connected to the second contact feature portion.

135. The electronic assembly according to claim 134, wherein the interconnect structure has a rewiring layer.

136. The electronic assembly according to claim 134, wherein the interconnect structure has one or more metallization layers.

137. The interconnect structure comprises an intermediate interconnect layer and a global interconnect layer. The intermediate interconnect layer is provided near the back surface of the interconnect structure. The global interconnect layer is provided on the intermediate interconnect layer, closer to the front surface of the interconnect structure than the intermediate interconnect layer. The electronic assembly according to claim 134, wherein the intermediate interconnect layer is in electrical contact with the global interconnect layer.

138. The interconnect structure further includes input / output (IO) pads provided near the front surface of the interconnect structure. The aforementioned I / O pad is in electrical contact with the global interconnect layer. The electronic assembly according to claim 134, wherein the I / O pads are exposed on the front surface of the interconnect structure.

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