Compression of check node data in memory systems

Abstract

This application relates to compressing check node data for electronic devices. The electronic device identifies check nodes corresponding to a subset of codeword symbols in a data block and determines check node data indicating the likelihood that the subset of codeword symbols is incorrect. A set of data bits is determined based on the combination of values ​​of the data items in the check node data to uniquely identify a combination of values ​​within a set of value combinations selected according to a predetermined relationship. The electronic device stores in a memory block a set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits than the set of data bits to represent all possible values ​​of the corresponding data item.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application is a continuation of and claims priority to U.S. Patent Application No. 18 / 221,819, titled "Compression of Check Node Data in a Memory System", filed on July 13, 2023; U.S. Patent Application No. 18 / 236,849, titled "Compression of Check Node Data in a Memory System", filed on August 22, 2023; and U.S. Patent Application No. 18 / 236,861, titled "Data Structure Reconfiguration of Low - Density Parity - Check (LDPC) in a Memory System", filed on August 22, 2023, and each application is incorporated by reference in its entirety.

[0002] This application generally relates to memory management including, but not limited to, methods, systems, and non - transitory computer - readable storage media for compressing check node data applied to data verification in a memory system (e.g., a solid - state drive).

Background Art

[0003] Memory is used in computer systems to store instructions and data. Data is processed by one or more processors in the computer system according to the instructions stored in memory. Multiple memory units are used to perform different functions in different parts of the computer system. Specifically, computer systems include non-volatile memory, which functions as secondary memory to retain stored data even when the computer system is disconnected from power. Examples of secondary memory include, but are not limited to, hard disk drives (HDDs) and solid-state drives (SSDs). min-sum is a popular algorithm for identifying and / or correcting bit errors in user data stored in memory along with integrity data (e.g., low-density parity check (LDPC) codes). When a memory controller identifies or corrects bit errors based on LDPC codes during the integrity check process, it generates check node data and temporarily stores it in a register. This is beneficial for compressing the check node data used in the integrity check process, reducing the use of expensive registers and enhancing memory access performance. [Overview of the Initiative]

[0004] Various embodiments of this application relate to methods, systems, devices, and non-temporary computer-readable storage media for compressing check node data temporarily stored in registers during an integrity check process performed by a memory system (e.g., an SSD). Check node data is applied to identify or correct bit errors in codeword symbols extracted from the memory system, and the codeword symbols are stored including integrity data (e.g., LDPC codes) representing a type of error correction code used to provide error correction for data storage errors in the memory system. In one example, min-sum is a popular algorithm applied to correct bit errors in codeword symbols stored in a memory system. LDPC decoding is typically visualized as a bipartite Tanner graph having variable nodes and check nodes, and messages are exchanged between variable nodes and check nodes on the Tanner graph during the integrity check process. In some embodiments, memory (e.g., registers) is assigned to each check node to store a plurality of data items summarizing information of a set of variable nodes connected to the corresponding check node. Various embodiments of this application relate to compressing check node data generated and temporarily stored during an integrity check process, thereby reducing the use of expensive registers and enhancing memory access performance.

[0005] In one embodiment, a method is implemented in an electronic device for compressing check node data on a memory system (e.g., a solid-state drive). The method includes the step of identifying a plurality of check nodes associated with a data block. Each check node corresponds to a subset of codeword symbols in the data block and has corresponding check node data indicating the likelihood that the subset of codeword symbols is incorrect. The method further includes the step of identifying, for each of the subsets of check nodes, a set of most significant bits (MSBs) of one or more data items in the corresponding check node data. The method further includes the step of determining a set of data bits based on a plurality of MSB sets of the subset of check nodes. The plurality of MSB sets include a set of MSBs of one or more data items in the corresponding check node data of each of the subsets of check nodes. The method further includes the step of storing the set of data bits associated with the subset of check nodes in a memory block (e.g., a register file, one or more registers) allocated to the plurality of check nodes. The plurality of MSB sets have a total of a first number of bits, and the set of data bits has a second number of bits. The first number is greater than the second number.

[0006] In another embodiment, a method is implemented in an electronic device for compressing check node data on a memory system (e.g., a solid-state drive). This method includes the steps of identifying a check node corresponding to a subset of codeword symbols in a data block, and determining check node data comprising a plurality of data items. The check node data indicates the likelihood that the subset of codeword symbols is incorrect. This method further includes the step of determining a set of data bits based on a combination of values ​​of the plurality of data items. The set of data bits uniquely identifies a combination of values ​​within a selected set of value combinations, depending on a predetermined relationship. This method further includes storing in a memory block a set of data bits representing a plurality of data items of the check node data of the check node. Each of the plurality of data items requires at least a first number of data bits to represent all possible values ​​of the corresponding data item, and the set of data bits has a second number of data bits. The second number is less than the sum of the first numbers for each of the plurality of data items.

[0007] In yet another embodiment, a method is implemented in an electronic device for adaptively storing check node data on a memory system (e.g., a solid-state drive). This method includes the step of acquiring a data block corresponding to a plurality of first check nodes. Each first check node corresponds to a first subset of codeword symbols in the data block and has corresponding first check node data indicating the likelihood that the first subset of codeword symbols is incorrect. This method further includes the step of identifying a memory block allocated to store the first check node data of the plurality of first check nodes, and the step of regrouping the data bits of the data block to form a plurality of second check nodes. Each second check node corresponds to a second subset of codeword symbols in the data block and has corresponding second check node data indicating the likelihood that the second subset of codeword symbols is incorrect. This method further includes the step of reconfiguring the memory block to store the second check node data of the plurality of second check nodes. The plurality of second check nodes have a different number of check nodes than the plurality of first check nodes.

[0008] Some embodiments of this application include an electronic device comprising one or more processors and a memory that, when executed by the one or more processors, stores instructions causing the processors to perform any of the methods described above on a memory system (e.g., a solid-state drive).

[0009] Some embodiments include a non-temporary, computer-readable storage medium for storing one or more programs. When executed by one or more processors, the one or more programs include instructions that cause the processors to perform one of the methods described above on a memory system (e.g., a solid-state drive).

[0010] In some embodiments, the above-described methods, electronic devices, or non-temporary computer-readable storage media for managing LDPC-based check node data are also used for communications (e.g., wireless communications using 5G or Wi-Fi technology, satellite communications, Ethernet communications, and communications over fiber optic networks).

[0011] These exemplary embodiments and forms are mentioned not to limit or define this disclosure, but to provide examples for ease of understanding. Additional embodiments are discussed in “Modes for Carrying Out the Invention,” where further explanation is provided.

[0012] To better understand the various embodiments described, refer to the following “Modes for Carrying Out the Invention” in conjunction with the following drawings, where the same reference numerals throughout the drawings refer to corresponding parts. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram of an exemplary system module in a typical electronic device, according to several embodiments. [Figure 2] This is a block diagram of an exemplary electronic device memory system having one or more memory access queues, according to several embodiments. [Figure 3] This is a block diagram of an exemplary integrity check system for a memory system for processing codewords, according to several embodiments. [Figure 4A] This is a Tanner graph applied to perform LDPC coding using check nodes and variable nodes, according to several embodiments. [Figure 4B] This is a simplified Tanner graph in which a single check node is combined with a set of variable nodes, according to several embodiments. [Figure 5A] This is a schematic diagram of a sequence of check node calculations performed to determine the check node data of a check node during LDPC decoding, according to some embodiments. [Figure 5B] This is a schematic diagram of a sequence of variable node operations performed to determine the variable node data of a variable node during LDPC decoding, according to some embodiments. [Figure 6] The following are illustrative data structures of check node data for a set of check nodes having one or more data compression schemes according to several embodiments. [Figure 7A] Two tables are shown illustrating possible combinations of two data items for the check node data of each check node, according to several embodiments. [Figure 7B] The following are illustrative data structures of a subset of check node data compressed based on the table shown in Figure 7A, according to several embodiments. [Figure 7C] This document shows a comparison of the original check node data and the corresponding compressed check node data for a subset of check nodes according to several embodiments. [Figure 8A] This shows another exemplary data structure for a subset of check node data having an index-based compression scheme according to several embodiments. [Figure 8B] Figure 8B shows a comparison of check node data for a subset of check nodes and the corresponding compressed check node data according to several embodiments. [Figure 9] This is a flowchart illustrating an exemplary method for compressing check node data for electronic devices, according to several embodiments. [Figure 10] This is a data map showing exemplary combinations of values ​​for two likelihood data items in the check node data for each check node, according to several embodiments. [Figure 11] The following are lookup tables and expressions applied to associate a combination of values ​​for two data items in check node data with a set of data bits, according to several embodiments. [Figure 12]Another exemplary data map showing an exemplary combination of values of two likelihood data items of check node data for each check node according to some embodiments. [Figure 13] An exemplary data map showing a combination of different non-invertible values of two data items of check node data for each check node according to some embodiments. [Figure 14] An exemplary data map showing a combination of different non-invertible values of two data items of check node data for each check node according to some embodiments. [Figure 15] An exemplary data map showing a combination of different non-invertible values of two data items of check node data for each check node according to some embodiments. [Figure 16] An exemplary data map showing a combination of different non-invertible values of two data items of check node data for each check node according to some embodiments. [Figure 17] Shows the data structure of exemplary check node data of a check node having one or more data compression schemes according to some embodiments. [Figure 18] A flowchart of an exemplary method for compressing check node data for an electronic device according to some embodiments. [Figure 19] A diagram showing two exemplary data structures of check node data temporarily stored in a memory block according to some embodiments. [Figure 20] A flowchart of an exemplary method for adaptively storing check node data in an electronic device according to some embodiments. **DETAILED DESCRIPTION OF THE INVENTION**

[0014] Throughout the several figures of the drawings, like reference numerals refer to corresponding parts.

[0015] Herein, specific embodiments will be referenced in detail, examples of which are shown in the accompanying drawings. In the following detailed description, a number of non-limiting specifics will be described in order to facilitate the understanding of the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternative means may be used without departing from the scope of the claims, and that the subject matter can be carried out without these specifics. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented in a number of types of electronic devices having digital video capabilities.

[0016] This application relates to compressing check node data temporarily stored in registers during an integrity check process performed by a memory system (e.g., an SSD). Check node data is applied to identify or correct bit errors in codeword symbols extracted from the memory system, and the codeword symbols include integrity data (e.g., LDPC codes) representing a type of error correction code used to provide error correction for data in the memory system. For example, min-sum is a popular algorithm applied to correct bit errors in LDPC codes. LDPC decoding is typically visualized as a Tanner graph having variable nodes and check nodes, and messages are exchanged between variable nodes and check nodes on the Tanner graph during the integrity check process. In some embodiments, memory (e.g., registers) is allocated to each check node to store multiple data items summarizing information about a set of variable nodes connected to the corresponding check node. Since the generated and temporarily stored check node data is compressed during the integrity check process, the use of expensive registers is reduced and memory access performance is enhanced.

[0017] In one example, each check node stores a symbol, the size of the minimum message (Min1), the size of the second smallest message (Min2), an index identifying the variable node that provides the minimum message (Min1 index), and a Min2 index identifying the variable node that selectively provides the second smallest message (Min2 index). Since the size of Min1 is always less than or equal to the size of Min2, it becomes possible to create a method for data compression. Furthermore, in some embodiments, the Min1 and Min2 indices are limited to the maximum check node degree (i.e., the number of variable nodes joined to each check node) which is not a power of 2, and some index values ​​used for data compression are never used. In some embodiments, the size of Min2 and the Min2 index are less important than the size of Min1 and the Min1 index, so some bits can be truncated without noticeable adverse effects. In some embodiments, the decoder is reused for multiple matrices. For example, a relatively small matrix with a relatively high check node degree is reconfigured to be interchangeable with a relatively large matrix with a relatively low check node degree. A portion of the unused memory space in the larger matrix is ​​selectively used to increase the size of the Min1 and Min2 indices in the smaller matrix. Conversely, the index size of the smaller matrix is ​​reduced to increase the number of check nodes stored in the larger matrix. Memory systems of electronic devices

[0018] Figure 1 is a block diagram of an exemplary system module 100 in a typical electronic device according to several embodiments. The system module 100 in this electronic device includes at least a processor module 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces such as a network interface 108, and one or more communication buses 140 for interconnecting these components. In some embodiments, the I / O controller 106 enables the processor module 102 to communicate with I / O devices (e.g., keyboards, mice, or trackpads) via a universal serial bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each enabling the electronic device to exchange data with an external source (e.g., a server or another electronic device). In some embodiments, the communication bus 140 comprises a circuitry system (sometimes called a chipset) that interconnects the various system components included in the system module 100 and controls communication between them.

[0019] In some embodiments, the memory module 104 comprises high-speed random-access memory such as DRAM, static random-access memory (SRAM), double data rate (DDR), dynamic random-access memory (RAM), or other random-access solid-state memory devices. In some embodiments, the memory module 104 comprises non-volatile memory such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, the memory module 104, or alternatively the non-volatile memory device in the memory module 104, comprises a non-temporary computer-readable storage medium. In some embodiments, a memory slot for housing the memory module 104 is reserved on the system module 100. When the memory module 104 is inserted into the memory slot, it is integrated into the system module 100.

[0020] In some embodiments, the system module 100 further comprises one or more components selected from a memory controller 110, an SSD 112, a hard disk drive (HDD) 114, a power management integrated circuit (PMIC) 118, a graphics module 120, and a sound module 122. The memory controller 110 is configured to control communication between the processor module 102 in the electronic device and the memory components, including the memory module 104. The SSD 112 is configured to store data in the electronic device by applying an integrated circuit assembly, and in many embodiments is based on a NAND or NOR memory configuration. The HDD 114 is a conventional data storage device used to store and retrieve digital information based on an electromechanical magnetic disk. The power connector 116 is electrically coupled to receive an external power supply. The PMIC 118 is configured to modulate the received external power supply to other desired DC voltage levels (e.g., 5V, 3.3V, or 1.8V) as required by various components or circuits in the electronic device (e.g., the processor module 102). The graphics module 120 is configured to generate output image feeds to one or more display devices according to their desired image / video formats. The sound module 122 is configured to facilitate the input and output of audio signals to and from electronic devices under the control of a computer program.

[0021] Furthermore, the communication bus 140 interconnects various system components, including components 110-122, and controls communication between them.

[0022] Furthermore, as novel data storage technologies are developed for storing information in non-temporary computer-readable storage media in the memory module 104 and SSD 112, it is well known to those skilled in the art that other non-temporary computer-readable storage media can be used. These novel non-temporary computer-readable storage media include, but are not limited to, biological materials, nanowires, carbon nanotubes, and those manufactured from individual molecules. However, the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0023] Some embodiments of this application relate to an integrity checking process performed by a memory system (e.g., SSD 112, memory module 104, hard drive 114, memory controller 110) that stores codeword symbols containing integrity data (e.g., LDPC codes). The integrity checking process, also known as a decoding process, is visualized by a Tanner graph having variable nodes and check nodes. The variable nodes correspond to codeword symbols extracted from the memory system. Each check node has check node data that corresponds to a different set of variable nodes and is configured to identify or correct bit errors in the codeword symbols corresponding to the different sets of variable nodes. Specifically, the check node data is updated by exchanging messages between the variable nodes and check nodes on the Tanner graph until bit errors in the codeword symbols are identified and corrected. During the integrity checking process, check node data is generated and temporarily stored in a register or register file of the memory system. In some embodiments, the check node data of two or more check nodes are jointly compressed, for example, reversibly, to save one or more bits in the register or register file. In some embodiments, two or more data items of check node data for a single check node are jointly compressed, for example, reversibly or irreversibly, to save one or more bits in a register or register file. In some embodiments, the memory space is reconfigured to store check node data for two different numbers of check nodes, and the data structure of the check node data is adjusted when the check node data is switched between two data structures corresponding to two different numbers of check nodes. These means reduce the register space allocated to registers or register files and efficiently utilize the memory system's storage space with little or no impact on the performance of the data integrity checking process.

[0024] Figure 2 is a block diagram of a memory system 200 of an exemplary electronic device having one or more memory access queues according to several embodiments. The memory system 200 is coupled to a host device 220 (e.g., the processor module 102 in Figure 1) and is configured to store instructions and data for extended periods, for example, when the electronic device is in a sleep, hibernation, or shutdown state. The host device 220 is configured to access the instructions and data stored in the memory system 200, process the instructions and data to operate the operating system, and run user applications. The memory system 200 further includes a controller 202 and a plurality of memory channels 204. Each memory channel 204 contains a plurality of memory cells. The controller 202 is configured to run firmware-level software to bridge the plurality of memory channels 204 to the host device 220.

[0025] Each memory channel 204 comprises one or more memory packages 206 (e.g., two memory chips, two memory dies). In one example, each memory package 206 corresponds to one memory die. Each memory package 206 includes multiple memory planes 208, and each memory plane 208 further includes multiple memory pages 210. Each memory page 210 includes an ordered set of memory cells, each memory cell identified by its corresponding physical address. In some embodiments, the memory system 200 comprises a single-level cell (SLC) NAND flash memory chip, where each memory cell stores a single data bit. In some embodiments, the memory system 200 comprises a multi-level cell (MLC) NAND flash memory chip, where each memory cell of the MLC NAND flash memory chip stores two data bits. In one example, each memory cell of a triple-level cell (TLC) NAND flash memory chip stores three data bits. In another example, each memory cell in a quad-level cell (QLC) NAND flash memory chip stores four data bits. In yet another example, each memory cell in a penta-level cell (PLC) NAND flash memory chip stores five data bits. In some embodiments, each memory cell can store any appropriate number of data bits. Compared to non-SLC NAND flash memory chips (e.g., MLC SSDs, TLC SSDs, QLC SSDs, PLC SSDs), SSDs with SLC NAND flash memory chips operate faster, more reliably, and have a longer lifespan, but have lower device density and are more expensive.

[0026] Each memory channel 204 is coupled to a corresponding channel controller 214 configured to control internal and external requests for accessing memory cells in the corresponding memory channel 204. In some embodiments, each memory package 206 (e.g., each memory die) corresponds to a corresponding queue 216 of memory access requests. In some embodiments, each memory channel 204 corresponds to a corresponding queue 216 of memory access requests. Also in some embodiments, each memory channel 204 corresponds to a distinct and separate queue 216 of memory access requests. In some embodiments, a subset (less than all) of multiple memory channels 204 correspond to a distinct queue 216 of memory access requests. In some embodiments, all of the multiple memory channels 204 of the memory system 200 correspond to a single queue 216 of memory access requests. Each memory access request is selectively received internally from the memory system 200 to manage the corresponding memory channel 204, or externally from a host device 220 to write or read data stored in the corresponding channel 204. Specifically, each memory access request includes one of the following: a system write request received from the memory system 200 to write to the corresponding memory channel 204; a system read request received from the memory system 200 to read from the corresponding memory channel 204; a host write request originating from the host device 220 to write to the corresponding memory channel 204; and a host read request received from the host device 220 to read from the corresponding memory channel 204. System read requests (also called background read requests or non-host read requests) and system write requests are dispatched by the memory controller to perform internal memory management functions. These internal memory management functions include, but are not limited to, garbage collection, wear leveling, read disturb mitigation, memory snapshot capture, memory mirroring, caching, and memory sparing.

[0027] In some embodiments, in addition to the channel controller 214, the controller 202 further includes a local memory processor 218, a host interface controller 222, an SRAM buffer 224, and a DRAM controller 226. The local memory processor 218 accesses multiple memory channels 204 based on one or more queues 216 of memory access requests. In some embodiments, the local memory processor 218 writes to and reads to and from the multiple memory channels 204 in memory block units. Data in one or more memory blocks is written to or read together to or from the multiple channels. Data in the same memory block is not written simultaneously by two or more operations. Each memory block selectively corresponds to one or more memory pages. In one example, the size of each memory block written to or read together in the multiple memory channels 204 is 16KB (e.g., 1 memory page). In another example, the size of each memory block written to or read together in the multiple memory channels 204 is 64KB (e.g., 4 memory pages). In some embodiments, each page has 16KB of user data and 2KB of metadata. Furthermore, the number of memory blocks accessed together and the size of each memory block can be configured for each of the following operations: system read, host read, system write, and host write.

[0028] In some embodiments, the local memory processor 218 stores data written to or read from each memory block in the multiple memory channels 204 in the SRAM buffer 224 of the controller 202. Alternatively, in some embodiments, the local memory processor 218 stores data written to or read from each memory block in the multiple memory channels 204 in the DRAM buffer 228 in the memory system 200. Alternatively, in some embodiments, the local memory processor 218 stores data written to or read from each memory block in the multiple memory channels 204 in the DRAM buffer 228, which is the main memory used by the processor module 102 (Figure 1). The local memory processor 218 of the controller 202 accesses the DRAM buffer 228 via the host interface controller 222.

[0029] In some embodiments, data in multiple memory channels 204 is grouped into coding blocks, each coding block being called a codeword (Figure 3, 302). For example, each codeword contains n bits, of which k bits correspond to user data and (nk) corresponds to integrity data of the user data, where k and n are positive integers. In some embodiments, the memory system 200 comprises an integrity engine 230 (e.g., an LDPC engine) and a register 232 coupled to the integrity engine 230, which includes multiple registers, or SRAM cells, or flip-flops. The integrity engine 230 is coupled to the memory channels 204 via a channel controller 214 and an SRAM buffer 224. Specifically, in some embodiments, the integrity engine 230 has a data path connection to the SRAM buffer 224, which is further connected to the channel controller 214 via a data path controlled by a local memory processor 218. The integrity engine 230 is configured to verify the data integrity of each coding block in memory channel 204 using variable nodes and check nodes, and messages are exchanged between the variable nodes and check nodes during the integrity check process. A subset of these messages is selected and temporarily stored in register 232 as variable node data or check node data.

[0030] Various embodiments of this application relate to compressing check node data temporarily stored in registers during an integrity check process 232 performed by a memory system 200 (e.g., an SSD). In some embodiments, check node data for a set of check nodes are jointly compressed by an integrity engine 230 to save, for example, one or more bits in registers, register files, or SRAM cells, or flip-flops, for example, reversibly. In some embodiments, multiple data items of check node data for a single check node are jointly compressed by an integrity engine 230 to save, for example, one or more bits in registers, register files, or SRAM cells, or flip-flops, for example, reversibly or irreversibly. In some embodiments, the memory space is reconfigured to store check node data for two different numbers of check nodes, and the data structure of the check node data is adjusted when the check node data is switched between two different numbers of check nodes. These means reduce the storage space allocated to registers, register files, SRAM cells, and / or flip-flops, and the storage space of the memory system is efficiently utilized with little or no impact on the performance of the data integrity check process. Data integrity check based on low-density parity check (LDPC) coding.

[0031] Figure 3 is a block diagram of an exemplary integrity checking system 300 for a memory system 200 for processing codewords 302, according to several embodiments. The integrity checking system 300 includes a plurality of memory channels 204, an integrity engine 230 (e.g., an LDPC engine), and registers 232. Data stored in the memory channels 204 of the memory system 200 (Figure 2) is grouped into coding blocks, each coding block being called a codeword 302. Each codeword 302 further contains n data bits, of which k data bits are user data 302D and (nk) data bits are integrity data 302I of the user data 302D, where k and n are positive integers. The integrity checking system 300 is configured to verify the data integrity of each codeword 302 in the memory channel 204 using a variable node 404 and a check node 402 (Figure 4).

[0032] In some embodiments, the integrity engine 230 further comprises one or more of the following: a compression module 304, an error correction code (ECC) encoder 306, a scrambler 308, a descrambler 310, an ECC decoder 312, and a decompression module 314. The compression module 304 takes user data 302D and processes the user data 302D (e.g., compress, encrypt). The ECC encoder 306 takes user data 302D that has been selectively processed by the compression module 304 and applies a parity data generation matrix G(316) to the user data 302D to encode the codeword 302. The matrix G(316) has k rows and n columns. A systematic form of matrix G includes an identification matrix I configured to store the user data 302D in the codeword 302, and a parity matrix P configured to generate integrity data 302I from the user data 302D. In some embodiments, the matrix G(316) is not unique and contains a set of basis vectors in the vector space of valid codewords 302. The scrambler 308 takes a codeword 302 containing n data bits and converts the n data bits into a scrambled codeword 318 having an output string of seemingly random n data bits. The scrambled codeword 318 is stored in memory channel 204 of the memory system 200.

[0033] During decoding, the scrambled codeword 318 is extracted from memory channel 204 of the memory system 200. The descrambler 310 reconstructs the codeword 302' from the scrambled codeword 318, and the ECC decoder 312 verifies whether the reconstructed codeword 302' is valid and corrects any error bits in the reconstructed codeword 302' to provide a valid codeword 302 containing valid user data 302D. In some cases, the bits of the reconstructed codeword 302' are "1" and match the corresponding bits ("1") in codeword 302. The bits of the reconstructed codeword 302' are correct. Conversely, in some cases, the bits of the reconstructed codeword 302' are "1" and do not match the corresponding bits ("0") in codeword 302. The bits of the reconstructed codeword 302' are incorrect. In some cases, the bits of the recovered codeword 302' are "0", which matches the corresponding bits ("0") in codeword 302. The bits of the recovered codeword 302' are correct. Conversely, in some cases, the bits of the recovered codeword 302' are "0", which does not match the corresponding bits ("1") in codeword 302. The bits of the recovered codeword 302' are incorrect.

[0034] In some embodiments, the decompression module 314 acquires user data 302D and processes the user data 302D (e.g., decompresses, decodes). In some embodiments, for integrity checking, the ECC decoder 312 applies a parity check matrix H(320) to the recovered codeword 302' to generate a syndrome vector S. The parity check matrix H(320) contains nk rows corresponding to nk parity check equations and n columns corresponding to n codeword bits. The relationship between the recovered codeword 302' and the syndrome vector S is expressed as follows:

number

number

[0035] Figure 4A shows a Tanner graph 400 applied to perform LDPC coding using check nodes 402 and variable nodes 404 according to several embodiments. Data stored in the memory system 200 (Figure 2) is verified on a codeword basis. Each codeword 302 contains n data bits, of which k data bits are user data 302D and nk data bits are integrity data 302I of the user data 302D, where k and n are positive integers. In some embodiments, a parity check matrix H(320) is applied without distinguishing between user data 302D and integrity data 302I during integrity checks. The parity check matrix H(320) contains nk rows corresponding to nk parity check equations and n columns corresponding to n codeword bits, where k and n are positive integers. Each parity check equation corresponds to a combination of the corresponding n codeword bits (also called codeword symbols) and therefore to a check node 402 connected up to a subset or all of the n variable nodes 404. In some embodiments, in the parity check matrix H(320) for the row corresponding to the check node 402, only j of the n codeword bits correspond to 1, where j is an integer less than n, and the check node 402 is connected to j variable nodes 404. In some embodiments, each and all check nodes 402 are connected to the same number of variable nodes 404 (e.g., j variable nodes 404). Alternatively, in some embodiments, each check node 402 is connected to a corresponding number of variable nodes 404, and at least two check nodes 402 are connected to different numbers of variable nodes 404.

[0036] Referring to Figure 4A, in this example, codeword 302 has 10 codeword symbols (also called codeword bits). Five parity check equations are applied to perform a completeness check on codeword 302, each parity check equation being applied to a set of four codeword symbols (j=4). Thus, the Tanner graph 400 contains five check nodes 402 (f0~f4), each check node 402 is connected to four corresponding variable nodes 404, each variable node 404 corresponding to a different set of the four codeword symbols of codeword 302.

[0037] In some embodiments, the ECC decoder 312 solves equation (2) to obtain an error vector e and identifies one or more error bits in the codeword 302 by an iterative integrity check process. Messages are exchanged between variable nodes 404 and check nodes 402 on the Tanner graph 400 until one or more error bits in the codeword 302 are identified or corrected. Each variable node 404 is assigned initial variable node data. In some embodiments, the initial variable node data includes a log-likelihood ratio (LLR) determined based on data measured when the read reference voltage is adjusted for the memory system 200. Each check node 402 is connected to a set of variable nodes 404 and receives messages from the set of variable nodes 404 containing the initial variable node data. For each check node 402, the check node data is determined based on the initial variable node data of the set of variable nodes 404 and indicates the likelihood that the set of codeword symbols corresponding to the set of variable nodes 404 is incorrect. Conversely, each variable node 404 is also connected to a set of check nodes 402 on the Tanner graph 400 and receives messages containing check node data from the set of check nodes 402. For each variable node 404, the variable node data is updated based on the check node data 422 of the set of variable nodes 404. Through these means, messages are exchanged between the check nodes 402 and the variable nodes 404 until the integrity check requirement is met, and one or more error bits are identified or corrected based on the variable node data or check node data. In some embodiments, the integrity check requirement is met if the symbol 424 is 0 for all check nodes 402.

[0038] Figure 4B shows a simplified Tanner graph 420 in which a single check node 402 is connected to a set of variable nodes, according to one of several embodiments. The check node 402 receives message data v1, v2, v3, ..., v from j variable nodes 404 to the check node. j The following is received, where j is the order d of the check node. cAlso known as . After the check node has been updated based on the min-sum algorithm, check node 402 sends message data u1, u2, u3, ..., u from the check node to the variable nodes. j to d c Send the number of variables to node 404. k(k is in the range [1,d c The details of the check node update calculation for the integer of ] are as follows:

number

number

number

[0039] Figure 5A is a schematic diagram of a sequence of check node operations 500 performed to determine the check node data of check node 402 during LDPC decoding, according to some embodiments. LDPC decoding is performed based on the min-sum method. The integrity engine 230 (Figure 2) organizes multiple operation units and registers 232 to execute instructions corresponding to the min-sum method without frequent interaction with the local memory processor 218. Specifically, each check node 402 corresponds to a parity check equation that combines n corresponding codeword symbols (also called codeword bits) and is connected to a subset of n variable nodes 404. In some embodiments, only j of the n codeword symbols are associated with the non-zero coefficients of the parity check equation, and the check node 402 is connected to the j variable nodes 404. For each check node 402, multiple operation units include a comparator operator 502 coupled to a flip-flop 504 in registers 232 (Figure 2). The comparison operator 502 receives variable node-to-check node message data and check node data 422 from a subset of j variable nodes 404 connected to the check node 402, and determines the first likelihood data item 426 and the second likelihood data item 428, respectively, corresponding to the smallest variable node-to-check node message data (Min1) and the second smallest variable node-to-check node message data (Min2) from the set of j variable nodes 404. The first likelihood data item 426 and the second likelihood data item 428 are stored in the flip-flop 504 of register 232. In some embodiments, the variable node-to-check node message data from each of the set of j variable nodes 404 includes LLR determined based on data measured when the read reference voltage is adjusted for the memory system 200.

[0040] Figure 5B is a schematic diagram of a sequence of check node and variable node operations 540 performed to determine message data from a variable node 404 to a check node during LDPC decoding, according to some embodiments. For each variable node 404, a plurality of operation units organized by the integrity engine 230 include a symbolic operator 506, a multiplexer 508, a combiner 510, a summation operator 512, an index identifier 514, and one or more random access memories (RAMs) 516. The RAMs 516 temporarily store the data involved in the check node and variable node operations 540. In some embodiments, registers 232 further include RAMs 516 associated with these check node and variable node operations 540. Each variable node 404 is connected to a set of check nodes 402, which are applied to a set of parity check equations corresponding to the set of check nodes 402. One of the set of check nodes 402 is stored in the flip-flop 504 and corresponds to check node data including a symbol bit 424, a first likelihood data item 426, a second likelihood data item 428, and a first index data item 430. The message data symbol from a previous variable node to the check node, stored in RAM 516A, is combined with the symbol bit 424 by the symbol operator 506 to form the LLR symbol 518. The index identifier 514 compares the index k of a variable node 404, which uniquely identifies one of the j variable nodes connected to a single check node 402, with the first index data item 430. Depending on the comparison result, the multiplexer 508 selects one of the likelihood data items 426 and 428 as likelihood data item 520, and the combiner 510 generates a symbolized LLR data item 522 that is sent from the check node 402 to the variable node 404 based on the LLR symbol 518 and the likelihood data item 520. Specifically, in some embodiments, in response to the determination that the index k of the variable node 404 is equal to the first index data item 430, the multiplexer 508 selects the second likelihood data item 428 as likelihood data item 520.Conversely, in some embodiments, in response to the determination that the index k of variable node 404 is not equal to the first index data item 430, the multiplexer 508 selects the first likelihood data item 426 as the likelihood data item 520.

[0041] The summation operator 512 combines the unique LLR data stored in RAM 516B with the LLR data items 522 of the set of check nodes 402 to update the variable node data associated with the variable node 404. In some embodiments, the unique LLR data corresponds to the initial variable node data of each variable node 404 associated with the corresponding codeword symbol of the codeword 302. The unique LLR data is determined based on the log-likelihood ratio (LLR) approximated as follows:

number

[0042] During LDPC decoding, the integrity engine 230 relies on register 232, which contains an array of registers for temporarily storing check node data associated with each check node 402. The more check nodes 402 there are, the larger register 232 becomes. The larger the size of the check node data for each check node 402, the larger register 232 becomes. Register 232 operates at high speed, allowing the integrity engine 230 or the local memory processor 218 to directly access and manipulate the data stored in register 232 in one clock cycle or more. Register 232 is expensive. For these reasons, it is beneficial to compress the check node data generated and temporarily stored during the integrity checking process (e.g., LDPC decoding), thereby reducing the use of expensive registers and enhancing memory access performance. Joint compression of check node data from multiple check nodes

[0043] Figure 6 shows an exemplary data structure 600 of check node data for a set of check nodes 402 having one or more data compression schemes according to some embodiments. Data stored in the memory system 200 is verified on a codeword basis. Each codeword 302 contains n data bits, of which k data bits are user data 302D and nk data bits are integrity data 302I generated based on the user data 302D, where k and n are positive integers. The codeword 302 is verified using nk parity check equations. Each parity check equation combines j different codeword bits out of a total of n codeword bits and thus corresponds to a check node 402 coupled to j different variable nodes out of n variable nodes 404. In some embodiments, the set of check nodes 402 includes a plurality of check nodes 402 associated with data blocks stored in the memory system 200. Each check node 402 corresponds to a subset of codeword symbols in a data block (e.g., j codeword bits) and has corresponding check node data 422 indicating the likelihood that the subset of codeword symbols is incorrect.

[0044] In one example, a data block corresponds to nk parity check equations and nk check nodes 402-1, 402-2, ..., and 402-nk. The integrity engine 230 generates check node data 422-1, 422-2, ..., and 422-nk. For each check node, the corresponding check node data 422 includes one or more data items, for example, a symbol bit 424, a first likelihood data item 426, a second likelihood data item 428, and a first index data item 430, as determined based on a min-sum method (equations (3) to (5)). Each data item of the check node data 422 has a corresponding number of bits. For example, for each check node 402, the symbol bit 424 is 1 bit. The first likelihood data item 426 has 2 to 5 bits, and so does the second likelihood data item 428. The first index data item 430 has 6 to 7 bits, and the second index data item 432 (if any) has similar bits. Each of the one or more data items has one or more corresponding most significant bits (MSBs). For example, the symbol bit 424 has at most one MSB. Each of the likelihood data items 426 and 428 has one or more corresponding MSBs (e.g., one MSB, two MSBs, three MSBs). Each index data item 430 or 432 has one or more corresponding MSBs (e.g., one MSB, two MSBs, three MSBs).

[0045] nk check nodes 402-1, 402-2, ..., and 402-nk each contain a subset of check nodes (e.g., two or more check nodes 402) corresponding to a subset of check node data compressed and stored together in a memory block (e.g., register 232 in Figure 2). Specifically, each of the check node subsets 402 has a set 602 of the most significant bits (MSB) of one or more data items in the corresponding check node data 422. Multiple MSB sets 602 of the check node subsets 402 are compressed into a set of data bits 604, each MSB set 602 containing an MSB set 602 of one or more data items in the corresponding check node data 422 of the check node subset 402. Multiple MSB sets 602 have a total of a first number of bits, and the set of data bits 604 has a second number of bits. The first number is greater than the second number. In one example, each of the three check nodes has one MSB each for likelihood data items 426 and 428, and the total of six MSBs from the three check nodes are jointly compressed into a set of five data bits 604. Since the set of data bits 604 is stored in place of multiple MSB sets 602 of a subset of check node 402, at least one data bit is saved for the memory block allocated to store the check node data for nk check nodes 402.

[0046] Figure 7A shows two tables 700 and 710, which illustrate possible combinations of two data items 426 and 428 of the check node data 422 for each check node 402 according to several embodiments. Figure 7B shows an exemplary data structure 720 of the check node data 422 for a subset of check nodes 402 compressed based on the tables shown in Figure 7A according to several embodiments. Figure 7C shows a comparison of the original check node data 422 and the corresponding compressed check node data 722 for a subset of check nodes 402 according to several embodiments.

[0047] For each check node 402, a first likelihood data item 426 and a second likelihood data item 428 are applied in min-sum based LDPC decoding, and each likelihood data item 426 or 428 has an MSB. Referring to Figure 7A, the first likelihood data item 426 is either less than or equal to the second likelihood data item 428. It never occurs that the MSB of the first likelihood data item 426 is equal to 1 and the MSB of the second likelihood data item 428 is equal to 0. The combination of the two MSBs of likelihood data items 426 and 428 is never equal to (1,0), but there are three possible combinations of the two MSBs of likelihood data items 426 and 428 (e.g., (0,0), (0,1), (1,1)). Referring to Figure 7B, in some embodiments, a subset of check nodes 402 includes three check nodes 402. The first likelihood data item 426 and the second likelihood data item 428 of the three check nodes 402 are compressed together. Each likelihood data item 426 or 408 has one MSB 602, and the three check nodes 402 have a total of six MSBs 602. These six MSBs 602 correspond to 27 (i.e., 3 × 3 × 3) combinations of values ​​that can be represented by a set of five data bits 604. In this way, by compressing the six MSBs 602 of the likelihood data items 426 and 428 of the three check nodes 402 and storing them together in a set of five data bits 604, space in register 232 is saved by one data bit for every three check nodes 402 (i.e., an average of 1 / 3 bit saved for each check node 402).

[0048] Referring to Figure 7B, in some embodiments, for each of the subsets of check nodes 402, the corresponding check node data 422-1, 422-2, or 422-3 includes a first likelihood data item 426 corresponding to a first codeword symbol and a second likelihood data item 428 corresponding to a second codeword symbol. One or more data items of each check node 402 include the first likelihood data item 426 and the second likelihood data item 428, and the set of MSBs 602 includes a third number of MSBs (e.g., one MSB) for the first likelihood data item 426 and a fourth number of MSBs (e.g., one MSB) for the second likelihood data item 428. Multiple MSB sets 602 have a total of a first number (e.g., six) bits, and the set of data bits 604 has a second number (e.g., five) bits. The first number is either, for example, 1 or 2 more than the second number, or it is another positive integer.

[0049] For each of the subsets of check nodes 402, the set of MSBs 602 has three combinations of MSB values ​​for the first likelihood data item 426 and the second likelihood data item 428 (e.g., (0,0), (0,1), and (1,1) in Figure 7A). In one example, the subset of check nodes 402 contains three or four check nodes. The first number is one greater than the second number. On average, each check node 402 saves 1 / 3 or 1 / 4 bit of memory space. In another example, the subset of check nodes 402 contains five, six, or seven check nodes. The first number is two greater than the second number. On average, each check node 402 saves 1 / 3 or 2 / 7 bit of memory space.

[0050] Referring to Figure 7C, in some embodiments, a subset of check node 402 includes three check nodes. For each of the subsets of check node 402, the first likelihood data item 426 and the second likelihood data item 428 each have 6 bits. The first likelihood data item 426 and the second likelihood data item 428 of the original check node data 422 of the subset of check node 402 have a total of 36 bits. Each of the first likelihood data item 426 and the second likelihood data item 428 has only one MSB, and the 6 MSBs of the first likelihood data item 426 and the second likelihood data item 428 of the check node data 422 are compressed to 5 MSBs, i.e., "compressed column [4:0]". The first likelihood data item 426 and the second likelihood data item 428 of the compressed check node data 722 of the subset of check node 402 have a total of 35 bits. Therefore, the compressed check node data 722 saves 1 bit compared to the original check node data 422 of the subset of the three check nodes 402.

[0051] In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of a subset of check nodes 402 using the following logic, which is selectively loaded into register 232. x[3:0]=column1[1:0]+column2[1:0]*3(uselookuptableorlogic) If (x[3] == 0) compressed_columns[4:0]={column3[1:0],x[2:0] else compressed_columns[4:0]={2'b11,x[2],column3[1:0] In some embodiments, the integrity engine 230 is configured to decode the compressed check node data 422 of a subset of check nodes 402 using the following logic, which is selectively loaded into register 232. If(compressed_columns[4:3]<3) x[2:0]=compressed_columns[2:0] column1[1:0]=x[2:0]%3 column2[1:0]=x[2:0] / 3 column3[1:0]=compressed_columns[4:0] else x[3:0]=8 column1[1:0]=2 column2[1:0]=2 column3[1:0]=compressed_columns[1:0]

[0052] In some embodiments, the integrity engine 230 saves 1 / 3 bit of memory space in register 232 for each check node 402 while adding data compression and decompression logic. Thus, the compression of the MSB of a subset of check nodes helps save expensive register space, resulting in a reduction in the net number of gates in the integrity check system 300.

[0053] Figure 8A shows another exemplary data structure 800 of check node data 422 for a subset of three check nodes 402 having an index-based compression scheme according to one embodiment. Figure 8B shows a comparison of the check node data 422 for a subset of three check nodes 402 and the compressed corresponding check node data 822 according to one embodiment. For each of the subsets of check nodes 402 (e.g., 402-1, 402-2, or 402-3), the corresponding check node data 422 (e.g., 422-1, 422-2, or 422-3) includes a first likelihood data item 426 and an index data item 430 that identifies one of a subset of codeword symbols corresponding to the first likelihood data item 426. For example, check node 402 is connected to six variable nodes 404 on a Tanner graph 400, and the index data item 430 identifies that the third variable node has the smallest size among the six variable nodes 404. For each check node 402-1, 402-2, 402-3, a set of MSBs 602 (e.g., two MSBs) of the index data item 430 is identified in the corresponding check node data 422-1, 422-2, or 422-3. The set of data bits 604 is determined based on multiple MSB sets 602 of the index data item 430 for the subset of check node 402. The multiple MSB sets 602 include the sets of MSBs 602 of the index data item 430 in each corresponding check node data 422 of the subset of check node 402. The set of data bits 604 is stored in a memory block allocated to the multiple check nodes 402 (e.g., register 232 containing an array of registers), associated with the subset of check nodes 402. The multiple MSB sets 602 have a total of a first number of bits, and the set of data bits 604 has a second number of bits. The first number is greater than the second number.

[0054] Alternatively, in some embodiments, one or more data items of the compressed check node data 422 include an index data item 432 corresponding to a second likelihood data item 428. For example, a check node 402 is connected to six variable nodes 404 on a Tanner graph 400, and the index data item 432 identifies that the fifth variable node among the six variable nodes 404 has the second smallest size. The set of data bits 604 is determined based on multiple MSB sets 602 of the index data item 430 for a subset of the check node 402. The multiple MSB sets 602 include the set of MSBs 602 of the index data item 430 in each corresponding check node data 422 of the subset of the check node 402. By compressing the set of MSBs 602 of the index data item 430, at least one bit is saved. Additionally and alternatively, in some embodiments, both the set of MSBs 602 of the index data items 430 and 432 are compressed. The set of data bits 604 is determined based on multiple MSB sets 602 for both index data items 430 and 432 of a subset of check node 402. The multiple MSB sets 602 include the MSB sets 602 for index data items 430 and 432 in their respective corresponding check node data 422 of the subset of check node 402. By compressing the MSB sets 602 for index data items 430 and 432, at least one bit is saved.

[0055] Referring to Figure 8B, in some embodiments, a subset of checknodes 402 includes three checknodes. For each of the subsets of checknodes 402, the first index data item 430 has 6 bits. The first index data item 430 of the original checknode data 422 of the subset of checknodes 402 has a total of 18 bits. Each first index data item 430 has 2 MSBs, and the 6 MSBs of the first index data item 430 of the checknode data 422 are compressed into a set of 5 MSBs, i.e., "compressed Min1 index MSB[4:0]". The set of 5 data bits is stored together with several remaining bit sets of the subset of checknodes 402 (e.g., "Min1 index[3:0]"). The first index data item 430 of the compressed checknode data 822 of the subset of checknodes 402 has a total of 17 bits. Therefore, the compressed check node data 822 saves 1 bit compared to the original check node data 422 of the subset of the three check nodes 402.

[0056] In some embodiments, the set of data bits 604 is determined based on multiple MSB sets 602 by identifying a lookup table 824. Combinations of multiple MSB sets 604 of a subset of check nodes 402 are identified in the lookup table 824. The lookup table 824 is checked to determine the set of data bits 604 based on combinations of multiple MSB sets. Alternatively, in some embodiments, the set of data bits 604 is determined based on multiple MSB sets 602 by identifying a given equation 826. Multiple input values ​​are determined based on multiple MSB sets 602 of a subset of check nodes 402. Output values ​​are determined based on a given equation 826 and multiple input values ​​and converted to a set of data bits 604. The set of data bits 604 is uniquely determined based on multiple MSB sets 602 in the lookup table 824 or equation 826.

[0057] In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of a subset of check nodes 402 using the following logic, which is selectively loaded into register 232. x[3:0]=min_index_msb1[1:0]+min_index_msb2[1:0]*3 If (x[3] == 0) compressed_min_index_msbs[4:0]={min_index_msb3[1:0],x[2:0]} else compressed_min_index_msbs[4:0]={2'b11,x[2],min_index_msb3[1:0]} In some embodiments, the integrity engine 230 is configured to decode the compressed check node data 422 of a subset of check nodes 402 using the following logic, which is selectively loaded into register 232. If(compressed_min_index_msbs[4:3]<3) x[2:0]=compressed_min_index_msbs[2:0] min_index_msb1[1:0]=x[2:0]%3 min_index_msb2[1:0]=x[2:0] / 3 min_index_msb3[1:0]=compressed_min_index_msbs[4:0] else x[3:0]=8 min_index_msb1[1:0]=2 min_index_msb2[1:0]=2 min_index_msb3[1:0]=compressed_min_index_msbs[1:0]

[0058] In some embodiments, the integrity engine 230 saves 1 / 3 bit of memory space in register 232 for each check node 402 while adding data compression and decompression logic. Thus, the compression of the MSB of a subset of check nodes helps save expensive register space, resulting in a reduction in the net number of gates in the integrity check system 300.

[0059] Figure 9 is a flowchart of a method 900 for compressing check node data 422 for an electronic device according to several embodiments. The method 900 is implemented in an electronic device comprising a memory system 200 (Figure 2). In step 902, the electronic device identifies a plurality of check nodes 402 associated with a data block. In step 904, each check node has corresponding check node data 422 that corresponds to a subset of codeword symbols in the data block and indicates the likelihood that the subset of codeword symbols is incorrect. In step 906, for each of the subsets of check nodes 402, the electronic device identifies a set 602 of the most significant bits (MSBs) of one or more data items (e.g., likelihood data items 426 and 428) in the corresponding check node data 422 (Figure 6). In step 908, the electronic device determines a set of data bits 604 based on the plurality of MSB sets 602 of the subset of check nodes 402 (Figure 6). In step 910, the multiple MSB sets 602 include sets of MSBs 602 for one or more data items in the corresponding check node data 422 of each of the subsets of check node 402. In step 912, the electronic device stores sets of data bits 604 associated with the subsets of check node 402 in a memory block (e.g., register 232) allocated to the multiple check nodes 402. In step 914, the multiple MSB sets 602 have a total of a first number of bits, and the data bit sets 604 have a second number of bits, the first number being greater than the second number.

[0060] In some embodiments, for each of the subsets of check nodes 402, the corresponding check node data 422 includes a first likelihood data item 426 and an index data item 430 that identifies one of the subsets of codeword symbols corresponding to the first likelihood data item 426, and one or more data items include the index data item 430. In some embodiments, the subset of check nodes 402 includes three check nodes 402, and for each of the subsets of check nodes 402, the MSB set 604 of one or more data items in the corresponding check node data 422 includes the two MSBs of the index data item 430.

[0061] In some embodiments, for each of the subsets of check nodes 402, the corresponding check node data 422 includes a first likelihood data item 426 corresponding to a first codeword symbol and a second likelihood data item 428 corresponding to a second codeword symbol. One or more data items include the first likelihood data item 426 and the second likelihood data item 428, and the MSB set 604 includes the MSB of the third number of the first likelihood data item 426 and the MSB of the fourth number of the second likelihood data item 428. Also in some embodiments, the first likelihood data item 426 is less than or equal to the second likelihood data item, and the third and fourth numbers are equal to 1. Furthermore, in some embodiments, the subset of check nodes 402 includes three check nodes 402, and the multiple MSB sets of the subset of check nodes 402 include a total of 6 bits. For each of the subsets of check node 402, the set of MSBs has three combinations of MSB values ​​for the first likelihood data item 426 and the second likelihood data item 428. Multiple MSB sets of the subset of check node 402 have 3 × 3 × 3 combinations of MSB values ​​for the first likelihood data item 426 and the second likelihood data item 428, and the set of data bits 604 has 5 bits to represent the 3 × 3 × 3 combinations of values. The first number is 1 greater than the second number. In some embodiments, the subset of check node 402 includes 5, 6, or 7 check nodes 402, and for each of the subsets of check node 402, the set of MSBs has three combinations of MSB values ​​for the first and second likelihood data items, and the first number is 2 greater than the second number.

[0062] In some embodiments, determining a set of data bits 604 based on multiple MSB sets further includes identifying a lookup table, identifying combinations of multiple MSB sets of a subset of check nodes 402 within the lookup table, and checking the lookup table to determine a set of data bits 604 based on combinations of multiple MSB sets.

[0063] In some embodiments, determining a set of data bits 604 based on multiple MSB sets further includes identifying a given equation, determining multiple input values ​​based on multiple MSB sets of a subset of check nodes 402, determining an output value based on the given equation and the multiple input values, and determining a set of data bits 604 from the output value.

[0064] In some embodiments, storing a set of data bits 604 in association with a subset of check nodes 402 further includes storing the set of data bits 604 together with a plurality of remaining bit sets of the subset of check nodes 402, the plurality of remaining bit sets including the remaining bit sets of one or more data items in each of the check node data 422 of the subset of check nodes 402.

[0065] In some embodiments, for each check node 402, a subset of codeword symbols corresponds to a set of likelihood data items. Each likelihood data item indicates the likelihood that the corresponding codeword symbol is incorrect. The electronic device identifies the first likelihood data item 426 and the second likelihood data item 428 based on the determination that the second likelihood data item 428 is greater than or equal to the first likelihood data item 426, and less than or equal to the remaining likelihood data items of the subset of codeword symbols. In some embodiments, each likelihood data item for the corresponding codeword symbol is determined based on the log-likelihood ratio (LLR) approximated by equation (6).

[0066] In some embodiments, for each check node, the check node data 422 of check node 402 further includes a first index data item 430 that identifies one of a subset of codeword symbols corresponding to a first likelihood data item 426 of the check node data 422.

[0067] In some embodiments, each of the subsets of codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data 422 of check node 402 further includes symbol bits 424 which are a combination of symbols of the corresponding likelihood data items of the subset of codeword symbols.

[0068] Memory is also used to store instructions and data associated with Method 900 and includes high-speed random-access memory such as DRAM, SRAM, or other random-access solid-state memory devices, and optionally includes non-volatile memory such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid-state storage devices. Memory optionally includes one or more storage devices located remotely from one or more processing units. Memory or non-volatile memory within memory includes a non-temporary computer-readable storage medium. In some embodiments, memory or the non-temporary computer-readable storage medium within memory stores programs, modules, and data structures, or subsets or supersets, for carrying out Method 900.

[0069] Several embodiments of this application relate to the compression of check node data in electronic devices. The electronic device identifies check nodes associated with data blocks. Each check node corresponds to a subset of codeword symbols in a data block and has corresponding check node data indicating the likelihood that the codeword symbols are incorrect. For each of the subsets of check nodes, a set of most significant bits (MSBs) is identified in the corresponding check node data. The electronic device determines a set of data bits based on the MSB set of the check node subsets, which includes the set of MSBs identified for each of the subsets of check nodes. The set of data bits is stored together with the check node subsets in a memory block allocated to the check node. The MSB set has a total number of bits greater than the set of data bits. More specifically, several embodiments of this application are described in the following sections.

[0070] Clause 1. A method for compressing check node data in an electronic device, comprising the steps of: identifying a plurality of check nodes associated with a data block, each check node having corresponding check node data that corresponds to a subset of codeword symbols in the data block and indicates the likelihood that the subset of codeword symbols is incorrect; identifying a set of most significant bits (MSBs) of one or more data items in the corresponding check node data for each of the subsets of check nodes; determining a set of data bits based on a plurality of MSB sets of the subset of check nodes, wherein the plurality of MSB sets include the set of MSBs of one or more data items in the corresponding check node data for each of the subsets of check nodes; and storing the set of data bits associated with the subset of check nodes in a memory block allocated to the plurality of check nodes, wherein the plurality of MSB sets have a total of a first number of bits, and the set of data bits has a second number of bits, the first number being greater than the second number.

[0071] Clause 2. The method according to Clause 1, wherein for each of the subsets of check nodes, the corresponding check node data includes a first likelihood data item and an index data item that identifies one of the subsets of codeword symbols corresponding to the first likelihood data item, and the one or more data items include the index data item.

[0072] Clause 3. The method according to Clause 1 or 2, wherein the subset of check nodes includes three check nodes, and for each of the subsets of check nodes, the set of MSBs of the one or more data items in the corresponding check node data includes two MSBs of the index data item.

[0073] Clause 4. The method according to any one of Clauses 1 to 3, wherein for each subset of the check nodes, the corresponding check node data includes a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol, and the one or more data items include the first likelihood data item and the second likelihood data item, and the MSB set includes a third number of MSBs of the first likelihood data item and a fourth number of MSBs of the second likelihood data item.

[0074] Clause 5. The method according to Clause 4, wherein the first likelihood data item is less than or equal to the second likelihood data item, and the third number and the fourth number are equal to 1.

[0075] Clause 6. The method according to Clause 5, wherein the subset of check nodes comprises three check nodes, the plurality of MSB sets of the subset of check nodes comprises a total of six bits, for each of the subset of check nodes, the MSB set has a combination of three values ​​of the MSB of the first and second likelihood data items, the plurality of MSB sets of the subset of check nodes has a combination of 3 × 3 × 3 values ​​of the MSB of the first and second likelihood data items, the set of data bits has five bits to represent the combination of 3 × 3 × 3 values, and the first number is one greater than the second number.

[0076] Clause 7. The method according to Clause 5 or 6, wherein the subset of check nodes comprises 5, 6, or 7 check nodes, and for each of the subsets of check nodes, the MSB set has three combinations of MSB values ​​for the first and second likelihood data items, with the first number being 2 greater than the second number.

[0077] Clause 8. The method according to any one of Clauses 1 to 7, wherein the step of determining the set of data bits based on the plurality of MSB sets further comprises identifying a lookup table, identifying combinations of the plurality of MSB sets of a subset of check nodes within the lookup table, and checking the lookup table to determine the set of data bits based on the combinations of the plurality of MSB sets.

[0078] Clause 9. The method according to any one of Clauses 1 to 8, wherein the step of determining the set of data bits based on the set of multiple MSBs further comprises identifying a predetermined equation, determining a set of input values ​​based on the set of multiple MSBs of a subset of the check nodes, determining an output value based on the predetermined equation and the set of input values, and determining the set of data bits from the output value.

[0079] The method according to any one of the clauses 1 to 9, wherein the step of storing the set of data bits in association with the subset of check nodes further comprises storing together the set of data bits and a plurality of remaining bit sets of the subset of check nodes, the plurality of remaining bit sets comprising the remaining bit sets of the one or more data items in the check node data of each of the subset of check nodes.

[0080] Clause 11. The method according to any one of Clauses 1 to 10, wherein for each check node, the subset of codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicates the likelihood that the corresponding codeword symbol is incorrect, and the method further includes the step of identifying the first likelihood data item and the second likelihood data item in response to a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to the remaining likelihood data items of the subset of codeword symbols.

[0081] Clause 12. Each likelihood data item of the corresponding codeword symbol is determined based on the approximated log-likelihood ratio (LLR) as follows:

number

[0082] Clause 13. The method according to any one of Clauses 1 to 12, wherein for each check node, the check node data of the check node further includes a first index data item that identifies one of the subsets of the codeword symbols corresponding to a first likelihood data item of the check node data.

[0083] Clause 14. The method according to any one of Clauses 1 to 13, wherein each of the subsets of the codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data of the check node further includes symbol bits which are a combination of symbols of the corresponding likelihood data items of the subset of the codeword symbols.

[0084] An electronic device comprising one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the processors to perform the method described in any one of the paragraphs 1 to 14.

[0085] Clause 16. A non-temporary computer-readable storage medium that, when executed by one or more processors, stores instructions causing those processors to perform the method described in any one of Clauses 1 to 14. Compression of multiple data items in the check node data for each check node.

[0086] Figure 10 is a data map 1000 showing exemplary value combinations of two likelihood data items 426 and 428 of the check node data 422 for each check node 402, according to several embodiments. The check node 402 corresponds to a subset of codeword symbols in a data block (e.g., 50 codeword bits). The check node data 422 contains multiple data items (e.g., likelihood data items 426 and 428) indicating the likelihood that the subset of codeword symbols is incorrect. The set of data bits 1002 is determined based on a combination of values ​​of the multiple data items and, according to a predetermined relationship, uniquely identifies the combination of values ​​within a set of selected value combinations 1006. The set of data bits 1002 is stored in a memory block (e.g., register 232) to represent the multiple data items of the check node data 422 for the check node 402. Each of the multiple data items requires at least a first number of data bits to represent all possible values ​​of the corresponding data item, and the set of data bits 1002 has a second number of data bits that is less than the sum of the first number of each of the multiple data items. These means that at least one bit of register space is saved by storing the set of data bits 1002 instead of the multiple data items of the check node 402.

[0087] In some embodiments, for each check node 402, the first likelihood data item 426 and the second likelihood data item 428 are applied to min-sum based LDPC decoding. The data map 1000 has columns of the first number and rows of the second number. Each row corresponds to a fixed value of the second likelihood data item 428, and the first likelihood data item 426 increases from left to right. Each column corresponds to a fixed value of the first likelihood data item 426, and the second likelihood data item 428 increases from top to bottom. The data map 1000 shows the combinations of discrete values ​​of the first number of the first likelihood data item 426 and discrete values ​​of the second number of the second likelihood data item 428. Referring to Figure 10, in this example, 64 combinations of values ​​are formed by the eight values ​​of the first likelihood data item 426 and the eight values ​​of the second likelihood data item 428 and are enumerated in the data map 1000. Furthermore, the first likelihood data item 426 is less than or equal to the second likelihood data item 428, the second likelihood data item 428 is more than or equal to the first likelihood data item 426, and less than or equal to the remaining likelihood data items of the subset of codeword symbols corresponding to the set of variable nodes 404 of the corresponding check node 402. Assuming that the first likelihood data item 426 is less than the second likelihood data item 428, the first set 1004-1 of the removed value combinations for likelihood data items 426 and 428 is marked with "×" and does not exist. Data map 1000 contains the first set 1004-1 of the removed value combinations for likelihood data items 426 and 428 and 36 remaining value combinations that are different.

[0088] In some embodiments, a subset of the 36 remaining value combinations is associated with a set of data bits 1002. Each of the subsets of the 36 remaining value combinations is represented by the corresponding set of data bits 1002. For example, the subset of the 36 remaining value combinations includes 32 remaining value combinations, excluding the second set 1004-2 of value combinations for likelihood data items 426 and 428. The removed second set 1004-2 of value combinations corresponds to the second likelihood data item 428 equal to 6 and the first likelihood data item 426 equal to any of 0 to 3. The 32 remaining value combinations 1006, labeled "0", are uniquely represented by a set of five data bits 1002. For example, the 32 remaining value combinations are each represented by 00000, 00001, 00010, ..., 11111. The first likelihood data item 426 and the second likelihood data item 428 correspond to 36 possible value combinations, and the binary data items representing these 36 possible value combinations are at least 6 bits, which is 1 bit more than the set of data bits 1002. In other words, the first likelihood data item 426 and the second likelihood data item 428 are represented irreversibly by the set of data bits 1002 (for example, by making the second set 1004-2 of value combinations for likelihood data items 426 and 428 unavailable), thereby saving 1 bit of register space per check node 402.

[0089] Referring to Figure 10, in some embodiments, the 32 remaining value combinations labeled "0" correspond to the selected set of value combinations 1006, which does not include the first set 1004-1 and the second set 1004-2 of the removed value combinations. The selected set of value combinations 1006 is complementary to the set of removed value combinations 1004, which combines the first set 1004-1 and the second set 1004-2. In some embodiments, for each of the sets of removed value combinations 1004, the first likelihood data item 426 is in the first removal range, and the second likelihood data item 428 is in the second removal range. For example, for the second set 1004-2 of value combinations, the first removal range is [0,3] and the second removal range includes the value 6.

[0090] In some embodiments, during decoding, depending on the determination that the combination of values ​​1012 (e.g., (1,6)) for likelihood data items 426 and 428 belongs to the set of removed value combinations 1004, the second likelihood data item 428 is approximated to the nearest available value (e.g., 5 or 7), while the value of the first likelihood data item 426 (e.g., 1) is maintained. The value combination 1012 is updated based on the approximate value of the second likelihood data item 428, and the set of data bits 1002 is determined based on the updated value combination 1014. For example, the value combination (1,6) is updated to (1,7) associated with the data bit set 1002 of "11001". In another example, the value combination (1,6) is updated to (1,5).

[0091] Figure 11 shows a lookup table 1102 and formula 1104 applied to associate a combination of values ​​1006 of two data items of check node data 422 with a set of data bits 1002, according to some embodiments. The set of data bits 1002 is determined based on a combination of values ​​of multiple data items compressed for each check node 402. The set of data bits uniquely identifies a combination of values ​​within a set of selected combinations of values ​​1006, according to a predetermined relationship. In some embodiments, the predetermined relationship is defined by a lookup table 1102 that associates the set of data bits 1002 with the set of selected combinations of values ​​1006 (e.g., uniquely). In one example (e.g., Figure 10), the selected combinations of values ​​1006 are numbered sequentially from 0 to 31, and each selected combination of values ​​1006 is represented by the set of data bits 1002 corresponding to the corresponding sequential number. Alternatively, in some embodiments, the predetermined relationship is defined by formula 1104 that associates the set of data bits 1002 with the set of selected combinations of values ​​1006 (e.g., uniquely).

[0092] The first likelihood data item 426 corresponds to the first codeword symbol, and the second likelihood data item 428 corresponds to the second codeword symbol. The second likelihood data item 428 is greater than or equal to the first likelihood data item 426. During encoding, if the lookup table 1102 determines that a combination of values ​​corresponding to the values ​​of likelihood data items 426 and 428 is included in the lookup table 1102, the completeness engine 230 determines a set of data bits 1002 from the lookup table 1102 based on the combination of values. Conversely, if the lookup table 1102 determines that the lookup table 1102 does not include a combination of values ​​corresponding to the values ​​of likelihood data items 426 and 428, the completeness engine 230 approximates at least one of the values ​​of likelihood data items 426 and 428 based on a value approximation rule (e.g., using the closest available value) and determines a set of data bits 1002 from the lookup table 1102 based on the corresponding combination of approximate values. During decoding, the integrity engine 230 determines the combination of values ​​and corresponding values ​​for likelihood data items 426 and 428 based on the set of data bits 1002.

[0093] In some embodiments, during encoding, the integrity engine 230 determines a set of data bits 1002 from equation 1104 based on the combination of values ​​corresponding to the values ​​of likelihood data items 426 and 428 contained in the lookup table 1102. During decoding, the integrity engine 230 determines the combination of values ​​and corresponding values ​​of likelihood data items 426 and 428 from equation 1104 based on the set of data bits 1002.

[0094] Figure 12 is another exemplary data map 1200 showing exemplary value combinations of two likelihood data items 426 and 428 of the check node data 422 for each check node 402 according to some embodiment. The check node data 422 includes multiple data items (e.g., likelihood data items 426 and 428) that indicate the likelihood that a subset of codeword symbols is incorrect. A set of data bits 1002 is determined based on a combination of values ​​of the multiple data items and, depending on a predetermined relationship (e.g., lookup table 1102 and equation 1104 in Figure 11), uniquely identifies the combination of values ​​within a set of selected value combinations 1006 (e.g., 1006-1, 1006-2, and 1006-3). The set of data bits 1002 is stored in a memory block (e.g., register 232) to represent the multiple data items of the check node data 422 for the check node 402, thereby saving at least one bit of register space. Data map 1200 has columns for the first number and rows for the second number. Each row corresponds to a fixed value of the second likelihood data item 428, and the first likelihood data item 426 increases from left to right. Each column corresponds to a fixed value of the first likelihood data item 426, and the second likelihood data item 428 increases from top to bottom. Data map 1200 shows the combinations of discrete values ​​of the first number of the first likelihood data item 426 and discrete values ​​of the second number of the second likelihood data item 428. Referring to Figure 12, in this example, 64 combinations of values ​​are formed by the eight values ​​of the first likelihood data item 426 and the eight values ​​of the second likelihood data item 428, and are enumerated in data map 1200.

[0095] The data map 1200 includes a set of selected value combinations 1006 (e.g., 1006-1, 1006-2, and 1006-3) and a set of removed value combinations 1004 (e.g., 1004-1, 1004-2, and 1004-3) that are complementary to the set of selected value combinations 1006. Referring to Figure 12, in some embodiments, the second likelihood data item 428 has a most significant bit (MSB) and a least significant bit (LSB), and for each of the sets of removed value combinations 1004 (e.g., 1004-2 and 1004-3), the MSB and LSB of the second likelihood data item 428 are equal to "1" and "0", respectively, independently of the first likelihood data item 426. In some embodiments, during encoding, depending on the determination that the combination of values ​​1202 (e.g., (1,6)) for likelihood data items 426 and 428 belongs to the set of removed value combinations 1004, the second likelihood data item 428 is approximated to the nearest available value (e.g., 5 or 7), while the value of the first likelihood data item 426 (e.g., 1) is preserved. The value combination 1202 is updated based on the approximate value of the second likelihood data item 428, and the set of data bits 1002 is determined based on the updated value combination 1204. For example, the value combination (1,6) is updated to (1,7) associated with the data bit set 1002 of "11001". During decoding, the data bit set 1002 is decoded to (1,7) without being changed to (1,6), and such a data compression scheme results in the loss of the value combination (1,6) for likelihood data items 426 and 428.

[0096] In some embodiments, for each of the sets of removed value combinations 1004, the first likelihood data item 426 is within the first removal range and the second likelihood data item 428 is within the second removal range. For example, for the second set 1004-2 and the third set 1004-3 of value combinations, the first value range is [0,7] and the second value range includes two discrete values, 4 and 6.

[0097] In some embodiments, the MSB of the second likelihood data item 428 is identified. In response to a determination that the MSB of the second likelihood data item 428 is equal to 0, the completeness engine 230 does not store the MSB of the first likelihood data item 426 (which is also equal to 0). In response to a determination that the MSB of the second likelihood data item 428 is equal to 1, the completeness engine 230 does not store the LSB of the second likelihood data item 428 and sets it to 1. In other words, the completeness engine 230 stores either the MSB of the first likelihood data item 426 or the LSB of the second likelihood data item 428.

[0098] In some embodiments, the integrity engine 230 saves one bit of storage space in register 232 for each check node 402 while adding data compression and decompression logic. Thus, the compression of the likelihood data items for each check node 402 helps save expensive register space, reducing the net number of gates in the compression and decompression logic of the integrity check system 300, while having little to no adverse effect on the BER of the data read from the memory system 200.

[0099] Figures 13-16 are exemplary data maps 1300, 1400, 1500, and 1600 showing different irreversible value combinations of two 5-bit data items of check node data 422 for each check node 402, according to several embodiments. The check node data 422 includes multiple data items (e.g., likelihood data items 426 and 428). The set of data bits 1002 is determined based on the combination of values ​​of the multiple data items and, according to a predetermined relationship (e.g., lookup table 1102 and equation 1104 in Figure 11), uniquely identifies the combination of values ​​within a set of selected value combinations 1006 (e.g., marked with "0"). The set of data bits 1002 is stored in a memory block (e.g., register 232) to represent the multiple data items of the check node data 422 for the check node 402, thereby saving at least one bit of register space.

[0100] Each data map 1300, 1400, 1500, or 1600 contains combinations of values ​​for the first likelihood data item 426 and the second likelihood data item 428, and has columns of the first number (e.g., 32 columns) and rows of the second number (e.g., 32 rows). Each row corresponds to a fixed value of the second likelihood data item 428, and the first likelihood data item 426 increases from left to right (e.g., from 0 to 31). Each column corresponds to a fixed value of the first likelihood data item 426, and the second likelihood data item 428 increases from top to bottom (e.g., from 0 to 31). Each data map 1300, 1400, 1500, or 1600 shows combinations of discrete values ​​for the first number of the first likelihood data item 426 and discrete values ​​for the second number of the second likelihood data item 428. Referring to Figures 13-16, in these examples, the 32x32 value combinations are formed by the 32 values ​​of the first likelihood data item 426 and the 32 values ​​of the second likelihood data item 428, and are enumerated in the data map 1000. In some embodiments, 5 bits are used to represent each likelihood data item 426 or 428, and 10 bits are used to represent all 32x32 value combinations.

[0101] Each data map 1300, 1400, 1500, or 1600 includes a set of selected value combinations 1006 and a set of removed value combinations 1004 that are complementary to the set of selected value combinations 1006. Referring to Figure 13, in some embodiments, the set of removed value combinations 1004 covers value combinations where the second likelihood data item 428 is less than the first likelihood data item 426, or equal to an even integer between 16 and 30. Since the set of selected value combinations 1006 is fully represented by 9 bits in the set of data bits 1002, one bit of register space is saved for each check node 402. Referring to Figure 14, in some embodiments, the set of removed value combinations 1004 covers value combinations where the second likelihood data item 428 is less than the first likelihood data item 426, or equal to one of the sets of numbers including 8, 10, 12, 14, 16-18, 20-22, 24-26, and 28-30. Since the set of selected value combinations 1006 is fully represented by 8 bits in the set of data bits 1002, 2 bits of register space are saved for each check node 402. Referring to Figure 15, in some embodiments, the set of removed value combinations 1004 covers value combinations where the second likelihood data item 428 is less than the first likelihood data item 426, or where the LSB of 16 or more second likelihood data items 428 is not equal to the MSB of the first likelihood data item 426. Such a compression scheme reduces the number of multiplexers applied to the completeness coding. Since the set of 1006 selected value combinations is fully represented by 9 bits in the set of data bits 1002, one bit of register space is saved for each check node 402.Referring to Figure 16, in some embodiments, the set of removed value combinations 1004 covers value combinations where the second likelihood data items 428 are fewer than the first likelihood data items 426, or where the LSBs of eight or more but less than 16 second likelihood data items 428 are not equal to the MSB of the first likelihood data item 426, or where two LSBs of sixteen or more second likelihood data items 428 are not equal to two MSBs of the first likelihood data item 426. Such a compression scheme reduces the number of multiplexers applied to the completeness coding. Since the set of selected value combinations 1006 is fully represented by eight bits in the set of data bits 1002, two bits of register space are saved for each check node 402.

[0102] In some embodiments, for each of the 1006 sets of selected value combinations, the first likelihood data item 426 lies within a first value range, and the second likelihood data item 428 lies within a second value range that selectively depends on the first value range. Also in some embodiments, the first value range includes one or more discontinuous first data subranges, one or more predetermined first data values, or a combination thereof. The second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof. Referring to Figure 13, in one example, for the 1006 sets of selected value combinations, the first value range is between 0 and the second likelihood data item 428 (including both ends). The second value range includes the data subrange [0-15] and eight predetermined second data values, including 17, 19, 21, 23, 25, 27, 29, and 31. In other words, in some embodiments, for each of the 1006 sets of selected value combinations, the second likelihood data item 428 is in a second value range that includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof. The first likelihood data item 426 is not limited except that it is less than or equal to the second likelihood data item 428.

[0103] Figure 17 shows the data structure of exemplary check node data 422 of a check node 402 having one or more data compression schemes according to some embodiments. The check node data 422 includes a symbol bit 424, a first likelihood data item 426, a second likelihood data item 428, and a first index data item 430. According to equation (4), the symbol bit 424 is the variable check node data (v1~v) from the set of variable nodes 404. m It is generated based on the symbol of ). The first likelihood data item 426 and the second likelihood data item 428 each contain message data (Min1) from the variable node with the smallest size in the set of variable nodes 404 to the check node and message data (Min2) from the variable node with the second smallest size to the check node. The first index data item 430 identifies one of the sets of variable nodes 404 corresponding to the first likelihood data item 426. In some embodiments, the check node data 422 further includes a second index data item 432 that identifies one of the sets of variable nodes corresponding to the second likelihood data item 428.

[0104] In some embodiments, for each check node 402, the jointly compressed data items include a first likelihood data item 426 and a second likelihood data item 428 (for example, Figures 10-16). In some embodiments, the set of data bits 1002 is determined by selecting only one of the MSBs of the first likelihood data item 426 and the LSB of the second index data item 432 to include in the set of data bits 1002, based on the MSB of the second likelihood data item 428. Also in some embodiments, during encoding, in response to a determination that the MSB of the second likelihood data item 428 is equal to "0", the integrity engine 230 determines the set of data bits 1002 based on the LSB of the second index data item 432 and independently of the MSB of the first likelihood data item 426. In response to the determination that the MSB of the second likelihood data item is equal to "1", the completeness engine 230 determines the set of data bits 1002 based on the MSB of the first likelihood data item 426 and independently of the LSB of the second index data item 432.

[0105] Alternatively, in some embodiments, for each check node 402, the jointly compressed data items include one of the likelihood data items 426 and 428 and one of the index data items 430 and 432. In one example, the integrity engine 230 stores either the MSB of the first likelihood data item 426 or the LSB of the second index data item 432. In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of a subset of check nodes 402 using the following logic, which is selectively loaded into register 232. (If Min2 size ≥ 8, Set the LSB of the Min2 index to 0. (If Min2 size ≥ 16, Set the LSB size of min2 to 1. After compression, the set of data bits 1002 requires only one or two fewer data bits than the sum of the data bits of multiple data items to represent all possible values ​​of the data items in the set of selected value combinations 1006. Compressing these data items in each check node 402 helps save expensive register space, reduces the number of gates in the compression and decompression logic of the integrity check system 300, and has little to no adverse effect on the BER of the data read from the memory system 200.

[0106] Figure 18 is a flowchart of a method 1800 for compressing check node data 422 for an electronic device according to several embodiments. The method 1800 is implemented in an electronic device comprising a memory system 200 (Figure 2). In steps 1802 and 1804, the electronic device identifies check nodes 402 corresponding to a subset of codeword symbols in a data block and determines check node data 422 containing multiple data items. The check node data 422 indicates the likelihood that a subset of codeword symbols is incorrect. In step 1806, the electronic device determines a set of data bits 1002 based on a combination of values ​​for multiple data items. In step 1808, the set of data bits 1002 uniquely identifies a combination of values ​​in a set of selected combinations of values ​​1006 according to a predetermined relationship (e.g., lookup table 1102 and equation 1104 in Figure 11). In step 1810, the electronic device stores in a memory block a set of data bits 1002 representing multiple data items of the check node data 422 of the check node 402. In step 1812, each of the multiple data items requires at least a first number of data bits to represent all possible values ​​of the corresponding data item, and the set of data bits 1002 has a second number of data bits. In step 1814, the second number is, for example, one or two bits less than the sum of the first numbers of each of the multiple data items.

[0107] In some embodiments, in step 1816, the multiple data items correspond to the total number of possible value combinations, and the binary data item representing that total number has more bits than the set of data bits 1002, indicating that the compression of the multiple data items is irreversible.

[0108] In some embodiments, in step 1818, the plurality of data items include a first likelihood data item 426 corresponding to a first codeword symbol and a second likelihood data item 428 corresponding to a second codeword symbol, wherein the second likelihood data item 428 is greater than or equal to the first likelihood data item 426. The set of selected value combinations 1006 is complementary to the set of removed value combinations 1004. In some embodiments, determining the set of data bits 1002 further includes approximating the second likelihood data item 428 with available neighbor values ​​while maintaining the value of the first likelihood data item 426 in response to the determination that the value combination belongs to the set of removed value combinations 1004, updating the value combinations of the plurality of data items based on the approximation of the second likelihood data item 428, and determining the set of data bits 1002 based on the updated value combinations.

[0109] In some embodiments, for each of the 1006 sets of selected value combinations, the first likelihood data item 426 is within a first value range, and the second likelihood data item 428 is within a second value range. Also in some embodiments, the first value range includes one or more discontinuous first data subranges, one or more predetermined first data values, or a combination thereof. The second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

[0110] In some embodiments, for each of the set of selected value combinations 1006, the second likelihood data item 428 within the second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

[0111] In some embodiments, the second likelihood data item 428 has a most significant bit (MSB) and a least significant bit (LSB). For each of the 1006 sets of selected value combinations, the MSB and LSB of the second likelihood data item 428 are not equal to "1" and "0", respectively, independently of the first likelihood data item 426.

[0112] In some embodiments, the data items include a first likelihood data item 426 corresponding to a first codeword symbol, a second likelihood data item 428 corresponding to a second codeword symbol, and a second index data item identifying one of a subset of codeword symbols corresponding to the second likelihood data item 428 of the check node data 422. The second likelihood data item 428 is greater than or equal to the first likelihood data item 426. Determining the set of data bits 1002 further includes selecting only one of the MSB of the first likelihood data item 426 and the LSB of the second index data item to include in the set of data bits 1002, based on the MSB of the second likelihood data item 428. Furthermore, in some embodiments, selecting only one of the MSB of the first likelihood data item 426 and the LSB of the second index data item further includes determining a set of data bits 1002 based on the LSB of the second index data item and independently of the MSB of the first likelihood data item 426, in response to a determination that the MSB of the second likelihood data item 428 is equal to "0", and determining a set of data bits 1002 based on the MSB of the first likelihood data item 426 and independently of the LSB of the second index data item, in response to a determination that the MSB of the second likelihood data item 428 is equal to "1".

[0113] In some embodiments, the second number is one or two less than the sum of the first numbers for each of the multiple data items, thereby saving one or two bits for storing the check node data 422.

[0114] In some embodiments, a subset of codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect. The electronic device identifies the first likelihood data item 426 and the second likelihood data item 428 based on the determination that the second likelihood data item 428 is greater than or equal to the first likelihood data item 426 and less than or equal to the remaining likelihood data items of the subset of codeword symbols. In some embodiments, each likelihood data item of the corresponding codeword symbol is determined based on the log-likelihood ratio (LLR) approximated by equation (6).

[0115] In some embodiments, in step 1820, the plurality of data items further include at least one of a first index data item 430 that identifies one of a subset of codeword symbols corresponding to a first likelihood data item 426 of the check node data 422, and a second index data item 432 that identifies one of a subset of codeword symbols corresponding to a second likelihood data item 428 of the check node data 422.

[0116] In some embodiments, each of the subsets of codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data 422 of check node 402 further includes symbol bits which are combinations of symbols of the corresponding likelihood data items of the subset of codeword symbols.

[0117] Memory is also used to store instructions and data associated with Method 1800 and includes high-speed random-access memory such as DRAM, SRAM, or other random-access solid-state memory devices, and optionally includes non-volatile memory such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid-state storage devices. Memory optionally includes one or more storage devices located remotely from one or more processing units. Memory or non-volatile memory within memory includes a non-temporary computer-readable storage medium. In some embodiments, memory or the non-temporary computer-readable storage medium within memory stores programs, modules, and data structures, or subsets or supersets, for carrying out Method 1800.

[0118] Several embodiments of this application relate to compressing check node data for electronic devices. The electronic device identifies check nodes corresponding to a subset of codeword symbols in a data block and determines check node data indicating the likelihood that the subset of codeword symbols is incorrect. The set of data bits is determined based on a combination of values ​​for data items in the check node data to uniquely identify the combination of values ​​within a set of value combinations selected according to a predetermined relationship. The electronic device stores in a memory block a set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits than the set of data bits to represent all possible values ​​for the corresponding data item. More specifically, several embodiments of this application are described in the following sections.

[0119] Clause 1. A method for compressing check node data in an electronic device, comprising the steps of: identifying a check node corresponding to a subset of codeword symbols in a data block; determining check node data comprising a plurality of data items, wherein the check node data indicates the likelihood that the subset of codeword symbols is incorrect; determining a set of data bits based on a combination of values ​​of the plurality of data items, wherein the set of data bits uniquely identifies the combination of values ​​in a set of selected combinations of values ​​according to a predetermined relationship; and storing in a memory block the set of data bits representing the plurality of data items of the check node data of the check node, wherein each of the plurality of data items requires at least a first number of data bits to represent all possible values ​​of the corresponding data item, and the set of data bits has a second number of data bits, wherein the second number is less than the sum of the first numbers for each of the plurality of data items.

[0120] Clause 2. The method according to Clause 1, wherein the plurality of data items correspond to the total number of possible value combinations, and the binary data item representing the total number has more bits than the set of data bits.

[0121] Clause 3. The method according to Clause 1 or 2, wherein the plurality of data items include a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol, wherein the second likelihood data items are greater than or equal to the first likelihood data items, and the set of selected value combinations is complementary to the set of removed value combinations.

[0122] The method of Clause 4. The step of determining the set of data bits further comprises approximating the second likelihood data item with available neighbor values, while maintaining the value of the first likelihood data item, in response to a determination that the combination of values ​​belongs to the set of removed value combinations; updating the combination of values ​​of the plurality of data items based on the approximate value of the second likelihood data item; and determining the set of data bits based on the updated combination of values.

[0123] Clause 5. The method according to any one of Clauses 1 to 4, wherein for each of the sets of selected value combinations, the first likelihood data item is within a first value range and the second likelihood data item is within a second value range.

[0124] Clause 6. The method according to Clause 5, wherein the first value range includes one or more discontinuous first data subranges, one or more predetermined first data values, or a combination thereof, and the second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

[0125] Clause 7. The method according to any one of Clauses 1 to 6, wherein for each of the sets of selected value combinations, the second likelihood data item within the second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

[0126] Clause 8. The method according to any one of Clauses 1 to 7, wherein the second likelihood data item has a most significant bit (MSB) and a least significant bit (LSB), and for each of the set of selected value combinations, the MSB and LSB of the second likelihood data item are, independently of the first likelihood data item, not equal to "1" and "0", respectively.

[0127] Clause 9. The method according to any one of Clauses 1 to 8, wherein the plurality of data items include a first likelihood data item corresponding to a first codeword symbol, a second likelihood data item corresponding to a second codeword symbol, and a second index data item identifying one of a subset of the codeword symbols corresponding to the second likelihood data item of the check node data, wherein the second likelihood data items are greater than or equal to the first likelihood data items, and the step of determining the set of data bits further includes selecting only one of the MSB of the first likelihood data item and the LSB of the second index data item to include in the set of data bits, based on the MSB of the second likelihood data item.

[0128] Clause 10. The method according to Clause 9, wherein selecting only one of the MSB of the first likelihood data item and the LSB of the second index data item further comprises determining the set of data bits based on the LSB of the second index data item and independently of the MSB of the first likelihood data item in response to a determination that the MSB of the second likelihood data item is equal to "0", and determining the set of data bits based on the MSB of the first likelihood data item and independently of the LSB of the second index data item in response to a determination that the MSB of the second likelihood data item is equal to "1".

[0129] Clause 11. The method according to any one of Clauses 1 to 10, wherein the second number is one or two less than the sum of the first numbers for each of the plurality of data items, thereby saving one or two bits for storing the check node data.

[0130] Clause 12. The method according to any one of Clauses 1 to 11, wherein a subset of the codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicating the likelihood for which the corresponding codeword symbol is incorrect, and the method further includes the step of identifying the first likelihood data item and the second likelihood data item in response to a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to the remaining likelihood data items of the subset of the codeword symbols.

[0131] Clause 13. Each likelihood data item of the corresponding codeword symbol is determined based on the approximated log-likelihood ratio (LLR) as follows:

number

[0132] Clause 14. The method according to any one of Clauses 1 to 13, wherein the plurality of data items further include at least one of a first index data item that identifies one of the subsets of the codeword symbols corresponding to a first likelihood data of the check node data, and a second index data item that identifies one of the subsets of the codeword symbols corresponding to a second likelihood data of the check node data.

[0133] Clause 15. The method according to any one of Clauses 1 to 14, wherein each of the subsets of the codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data of the check node further includes symbol bits which are a combination of symbols of the corresponding likelihood data items of the subset of the codeword symbols.

[0134] An electronic device comprising one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the processors to perform the method described in any one of the paragraphs 1 to 15.

[0135] Clause 17. A non-temporary computer-readable storage medium that stores instructions, when executed by one or more processors, causing those processors to perform the actions described in any one of Clauses 1 to 15. Reconfiguration of registers for different low-density parity checks

[0136] Figure 19 shows two exemplary data structures 1900 of check node data 422 temporarily stored in a memory block (e.g., register 232 in Figure 2) according to several embodiments. The same memory block is adaptively applied to store check node data 422 depending on two different data structures 1900A and 1900B. The data block corresponds to a plurality of first check nodes 402A, each first check node 402A corresponding to a first subset of codeword symbols in the data block and having corresponding first check node data 422A indicating the likelihood that the first subset of codeword symbols is incorrect. Depending on the first data structure 1900A, the memory block is allocated to store the first check node data 422A of the plurality of first check nodes 402A. The data bits of the data block are regrouped by, for example, the integrity engine 230 in Figure 2 to form a plurality of second check nodes 402B. Each second check node 402B (e.g., 402B-1, 402B-2, or other second check nodes not shown) corresponds to a second subset of the codeword symbols in the data block and has corresponding second check node data 422B (e.g., 422B-1, 422B-2, or other second node data not shown) indicating the likelihood that the second subset of codeword symbols is incorrect. Depending on the second data structure 1900B, a memory block is allocated to store the second check node data 422B of multiple second check nodes 402B. Multiple second check nodes 402B have a different number of check nodes than multiple first check nodes 402A.

[0137] In some embodiments, the first check node 402A has more check nodes than the second check node 402B. For brevity, in one example, the data block contains 1280 codeword symbols, each corresponding to 40 first check nodes 402A associated with 32 codeword symbols. For each first check node 402A, the 32 codeword symbols are identified by a 5-bit first index data item 430 (i.e., z=4 in the first index data item 430). The check node data 422A for the 40 first check nodes 402A is organized according to a first data structure 1900A. The 1280 codeword symbols are then grouped again according to 32 second check nodes 402B, each associated with 40 codeword symbols. For each second check node 402B, 40 codeword symbols are identified by a 6-bit first index data item 430 (for example, the first index data item 430 requires one additional data bit). The second check node data 422B for the 32 second check nodes 402B are organized according to the second data structure 1900B.

[0138] In some embodiments, the integrity engine 230 identifies one or more overcheck nodes 402A-1 and 402A-2 in a plurality of first check nodes 402A. The overcheck node data 422A of one or more overcheck nodes 402A-1 and 402A-2 forms a plurality of overbits 1902. The plurality of overbits 1902 are reassigned to store second check node data 422B-1 or 422B-2 of a plurality of second check nodes 402B. In some embodiments, the excess bits 1902 are reassigned by assigning a first set 1902A of excess bits of the excess check node data of the first excess check node 402A-1 to store the second check node data 422B-1 of the first subset of the plurality of second check nodes 402B, and by assigning a second set 1902B of excess bits of the excess check node data of the second excess check node 402A-2 to store the second check node data 422B-1 of the first subset or second subset of the plurality of second check nodes 402B. For example, the set of excess bits 1902A created by the first check node 402A-1 is used to add one more bit (e.g., Min1 index[5]) to a subset of the second check node 402B or to all of the first index data items 430, and the set of excess bits 1902B created by the first check node 402A-1 is used to add a subset of the second check node 402B or to a subset or all of the second index data items 432.

[0139] In some embodiments, the multiple excess bits 1902 include at least one remaining bit 1904 that is not assigned to any of the second check node data 422B of the multiple second check nodes 402B. In some embodiments, in the multiple first check nodes 402A, a set of excess check nodes (e.g., 402A-1 and 402A-2) is identified to provide the multiple excess bits 1902, and the corresponding subset of the multiple excess bits is assigned to the second check node data (e.g., Min1 index[5]) of each and all of the second check nodes 402B.

[0140] In other words, in some embodiments, the first subset of codeword symbols corresponding to each first check node 402A includes a first number of codeword symbols, and the second subset of codeword symbols corresponding to each second check node 402B includes a second number of codeword symbols, where the first number is less than the second number. An excess check node 402A-1 or 402A-2 has excess check node data that includes a plurality of excess bits 1902. The plurality of excess bits 1902 are assigned to index data items 430 or 432 of the second check node data 422B of a plurality of second check nodes 402B.

[0141] In some embodiments, the second check node 402B has a greater number of check nodes than the first check node 402A. For brevity, in one example, the data block contains 1280 codeword symbols, each corresponding to 32 first check nodes 402A associated with 40 codeword symbols. For each first check node 402A, the 40 codeword symbols are identified by a 6-bit first index data item 430 (i.e., z=5 in the first index data item 430). The check node data 422A for the 32 first check nodes 402A is organized according to the first data structure 1900A. The 1280 codeword symbols are then grouped again according to 40 second check nodes 402B, each associated with 32 codeword symbols. For each second check node 402B, 32 codeword symbols are identified by a 5-bit first index data item 430, with, for example, one extra data bit being saved from each first index data item 430. The second check node data 422B for the 40 second check nodes 402B are organized according to the second data structure 1900B.

[0142] In some embodiments, the integrity engine 230 identifies one or more excess bits 1906 in the corresponding first check node data 422A of each of the plurality of first check nodes 402A (e.g., Min1 index of the first index data item 430[5]). The excess bits 1906 of the corresponding first check node data 422A of a first subset of the plurality of first check nodes 402A (e.g., less than all, all) are grouped together to store additional check node data 422B of additional check nodes 402B of the plurality of second check nodes 402B. Specifically, in some embodiments, one extra bit (e.g., the Min1 index of the first index data item 430[5]) is identified in the corresponding first check node data 422A of each of the multiple first check nodes 402A, and the extra bits 1906 of the corresponding first check node data of the multiple first check nodes are grouped to store additional check node data for two or more additional check nodes, including additional check nodes 402B-1 or 402B-2 of the multiple second check nodes 402B. For example, the Min1 index[5] of each first index data item 430 of each check node 402A is combined and applied to store the symbol bit 424 of the additional check node 402B-1 or 402B-2, the first likelihood data item 426, the second likelihood data item 428, and the first index data item 430. In another example, two or more bits 1906 of each first index data item 430 of each check node 402A are merged and applied to store check node data for one or more additional check nodes 402B. In some embodiments, data items 424, 426, 428, and 430 of additional check nodes 402B-1 or 402B-2 are converted from the first check node data 422A and stored distributed in a subset of the corresponding second check node data 422B.

[0143] In some embodiments, an additional check node includes a first additional check node 402B-1. The excess bits 1906 of the corresponding first check node data of a second subset (e.g., all less than all, all) of a plurality of first check nodes 402A are grouped to store the additional check node data 422B of the first additional check node 402A-1 or the second additional check node 402B-2 of a plurality of second check nodes 402B. For example, the first unused excess bits 1906 of the first index data items 430 of the top 50 check nodes 402A are merged and applied to store the check node data 422B of check node 402B-1. The second different excess bits 1906 of the first index data items 430 of the remaining 50 check nodes 402A are merged and applied to store the check node data 422B of check node 402B-2. In another example, the first unused excess bits 1906 of the first index data item 430 of all check nodes 402A are merged and applied to store the check node data 422B of check node 402B-1. The second different excess bits 1906 of the first index data item 430 of all check nodes 402A are merged and applied to store the check node data 422B of check node 402B-2.

[0144] In some embodiments, for a third subset of a plurality of first check nodes 402A, a subset or all of the excess bits of the corresponding first check node data 422A are not reallocated to store any additional check node data 422B of a plurality of second check nodes 422B.

[0145] In some embodiments, for each of the plurality of first check nodes 402A and the plurality of second check nodes 402B, the corresponding check node data 422 includes a first likelihood data item 426 and an index data item 430 that identifies one of the corresponding subsets of codeword symbols corresponding to the first likelihood data item 426. Also in some embodiments, the first subset of codeword symbols corresponding to each first check node 402A includes a first number of codeword symbols, and the second subset of codeword symbols corresponding to each second check node 402B includes a second number of codeword symbols, where the first number is greater than the second number. Each index data item 430 of the plurality of first check nodes 402A includes at least one extra bit (e.g., 1906) to address a first number of codeword symbols than each index data item 430 of the plurality of second check nodes 402B. Each of the multiple first check nodes 402A has at least one extra bit which forms a multiple extra bit 1906 which is reconfigured to store the second check node data 422B of at least one additional second check node 402B-1 or 402B-2.

[0146] In some embodiments, the integrity engine 230 includes a min-sum decoder for performing LDPC min-sum based decoding. Referring to Figure 4, in LDPC decoding, each check node 402 stores an index (i.e., a first index data item 430) representing a variable node 404 that provides the smallest message value (i.e., a first likelihood data item 426). The range of the index depends on the number of variable nodes 404 connected to the check node 402 in the Tanner graph 400. The number of variable nodes 404 connected to each check node 402 is called the check node order or row weight of the parity check H matrix. If the integrity engine 230 reuses the same min-sum decoder hardware for different LDPC codes, there is a trade-off between the number of check nodes and the number of minimum index bits (e.g., index data items 430 or 432). As a result, the total number of flip-flops decreases because the number of minimum index bits decreases when a larger number of check nodes are required.

[0147] In some embodiments, the integrity engine 230 reuses the same hardware (e.g., logic and registers) to decode different LDPC codes. Some LDPC matrices require 6 bits for the first likelihood data item 426, depending on the row weights of the H matrix, while others require 7 bits. In some situations, LDPC matrices with relatively high sign rates require more bits for the first index data item 430 because they have fewer check nodes and relatively higher row weights. For example, the integrity engine 230 uses a multiplexer to use the same flip-flop for check nodes with 6-bit index data items 430, or for relatively few check nodes with more than 6-bit index data items 430. More specifically, in one example, the integrity engine 230 saves 1 bit of storage space in register 232 for each check node 402. Thus, the MSB compression of a subset of check nodes helps save expensive register space in the integrity checking system 300.

[0148] Figure 20 is a flowchart of a method 2000 for adaptively storing check node data 422 in an electronic device according to several embodiments. The method 2000 is implemented in an electronic device comprising a memory system 200 (Figure 2). In step 2002, the electronic device acquires a data block corresponding to a plurality of first check nodes 402A. In step 2004, each first check node has corresponding first check node data 422A that corresponds to a first subset of codeword symbols in the data block and indicates the likelihood that the first subset of codeword symbols is incorrect. In step 2006, the electronic device identifies a memory block allocated to store the first check node data of the plurality of first check nodes 402A. In step 2008, the electronic device regroups the data bits of the data block to form a plurality of second check nodes 402B. In step 2010, each second check node 402B corresponds to a second subset of codeword symbols in the data block and has corresponding second check node data 422B indicating the likelihood that the second subset of codeword symbols is incorrect. In step 2012, the electronic device reconfigures the memory block to store the second check node data of the multiple second check nodes 402B. In step 2014, the multiple second check nodes 402B have a different number of check nodes than the multiple first check nodes 402A.

[0149] In some embodiments, in step 2016, the electronic device identifies one or more excess bits 1906 in the corresponding first check node data 422A of each of the plurality of first check nodes 402A. In step 2018, the electronic device groups the excess bits 1906 of the corresponding first check node data 422A of 11 subsets of the plurality of first check nodes 402A to store additional check node data for additional check nodes 402B-1 or 402B-2 of the plurality of second check nodes 402B. In some embodiments, the additional check nodes also include the first additional check node 402B-1. The electronic device groups the excess bits 1906 of the corresponding first check node data 422A of a second subset of the plurality of first check nodes 402A to store additional check node data for a second additional check node 402B-2 of the plurality of second check nodes 402B. In some embodiments, for a third subset of a plurality of first check nodes 402A, a subset or all of the excess bits of the corresponding first check node data 422A are not reallocated to store any additional check node data of a plurality of second check nodes 402B. In some embodiments, one excess bit 1906 is identified in the corresponding first check node data 422A of each of the plurality of first check nodes 402A, and the excess bits 1906 of the corresponding first check node data 422A of the plurality of first check nodes 402A are grouped to store additional check node data of two or more additional check nodes 402B-1 or 402B-2 of the plurality of second check nodes 402B, including additional check nodes.

[0150] In some embodiments, in step 2020, the electronic device identifies one or more overcheck nodes 402A-1 or 402A-2 from among a plurality of first check nodes 402A. The overcheck node data of one or more overcheck nodes 402A-1 or 402A-2 forms a plurality of overbits 1902. In step 2022, the electronic device assigns the plurality of overbits 1902 to the second check node data 422B of a plurality of second check nodes 402B. In some embodiments, assigning a plurality of excess bits 1902 to the second check node data 422B of a plurality of second check nodes 402B further includes (1) assigning a first set 1902A of excess bits of the excess check node data of a first excess check node to store the second check node data 422B of a first subset of the plurality of second check nodes 402B, and (2) assigning a second set 1902B of excess bits of the excess check node data of a second excess check node to store the second check node data 422B of a second subset of the plurality of second check nodes 402B. In some embodiments, the plurality of excess bits 1902 include at least one remaining bit 1904 that is not assigned to any of the second check node data 422B of the plurality of second check nodes 402B. In some embodiments, one excess check node is identified in each of several first check nodes 402A to provide multiple excess bits, and corresponding subsets of the multiple excess bits are assigned to the second check data of each and all second check nodes.

[0151] In some embodiments, for each of the plurality of first check nodes 402A and the plurality of second check nodes 402B, the corresponding check node data includes a first likelihood data item 426 and an index data item 430 that identifies one of the corresponding subsets of codeword symbols corresponding to the first likelihood data item 426. Also in some embodiments, the first subset of codeword symbols includes a first number of codeword symbols, and the second subset of codeword symbols includes a second number of codeword symbols, where the first number is greater than the second number. Each index data item 430 of the plurality of first check nodes 402A includes at least one extra bit 1906 to address a first number of codeword symbols than each index data item of the plurality of second check nodes 402B. Each of the multiple first check nodes 402A has at least one extra bit 1906 which is reconfigured to store the second check node data 422B of at least one additional second check node 402B-1 or 402B-2. In some embodiments, the first subset of codeword symbols includes a first number of codeword symbols, and the second subset of codeword symbols includes a second number of codeword symbols, the first number being less than the second number. The extra check node 402A-1 or 402A-2 has extra check node data 422A which includes the multiple extra bits 1902 which are assigned to index data items 430 or 432 of the second check node data 422B of the multiple second check nodes 402B.

[0152] In some embodiments, for each of the first and second check nodes, a subset of codeword symbols corresponds to a set of likelihood data items. Each likelihood data item indicates the likelihood that the corresponding codeword symbol is incorrect. The electronic device identifies the first likelihood data item 426 and the second likelihood data item 428 based on the determination that the second likelihood data item 428 is greater than or equal to the first likelihood data item 426, and less than or equal to the remaining likelihood data items of the subset of codeword symbols. In some embodiments, each likelihood data item for the corresponding codeword symbol is determined based on the log-likelihood ratio (LLR) approximated by equation (6).

[0153] In some embodiments, for each of the first and second check nodes, the check node data for the corresponding check node further includes a first index data item that identifies one of a subset of codeword symbols corresponding to the first likelihood data of the check node data 422.

[0154] In some embodiments, each of the subsets of codeword symbols corresponds to a corresponding likelihood data item that indicates the likelihood that the corresponding codeword symbol is incorrect. The check node data of a check node further includes symbol bits, which are combinations of symbols of the corresponding likelihood data items in the subset of codeword symbols.

[0155] Memory is also used to store instructions and data associated with Method 2000 and includes high-speed random-access memory such as DRAM, SRAM, DDR RAM, or other random-access solid-state memory devices, and optionally includes non-volatile memory such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid-state storage devices. Memory optionally includes one or more storage devices located remotely from one or more processing units. Memory or non-volatile memory within memory includes a non-temporary computer-readable storage medium. In some embodiments, memory or the non-temporary computer-readable storage medium within memory stores programs, modules, and data structures, or subsets or supersets, for carrying out Method 2000.

[0156] Several embodiments of this application relate to adaptively storing check node data in an electronic device. The electronic device acquires a data block corresponding to a first check node, each first check node having corresponding first check node data indicating the likelihood that a first subset of the codeword symbols in the data block is incorrect. The electronic device identifies a memory block allocated to store the first check node data of the first check node and regroups the data bits of the data block to form a second check node. Each second check node has corresponding second check node data indicating the likelihood that a second subset of the codeword symbols in the data block is incorrect. The electronic device reconfigures the memory block to store the second check node data of the second check node. The second check node has a different number of check nodes than the first check node. More specifically, several embodiments of this application are described in the following sections.

[0157] Clause 1. A method for adaptively storing check node data in an electronic device, comprising the steps of: acquiring a data block corresponding to a plurality of first check nodes, each first check node having corresponding first check node data corresponding to a first subset of codeword symbols of the data block and indicating the likelihood that the first subset of codeword symbols is incorrect; identifying a memory block allocated to store the first check node data of the plurality of first check nodes; regrouping the data bits of the data block to form a plurality of second check nodes, each second check node having corresponding second check node data corresponding to a second subset of codeword symbols of the data block and indicating the likelihood that the second subset of codeword symbols is incorrect; and reconfiguring the memory block to store the second check node data of the plurality of second check nodes, the plurality of second check nodes having a different number of check nodes than the plurality of first check nodes.

[0158] Clause 2. The method according to Clause 1, further comprising the steps of identifying one or more excess bits in the corresponding first check node data of each of the plurality of first check nodes, and grouping the excess bits of the corresponding first check node data of a first subset of the plurality of first check nodes to store additional check node data for additional check nodes of the plurality of second check nodes.

[0159] Clause 3. The method according to Clause 2, wherein the additional check node includes a first additional check node, and the method further includes the step of grouping excess bits of the corresponding first check node data of a second subset of the plurality of first check nodes to store additional check node data of the second additional check node of the plurality of second check nodes.

[0160] Clause 4. With respect to a third subset of the plurality of first check nodes, the subset or all of the excess bits of the corresponding first check node data shall not be reallocated to store any additional check node data of the plurality of second check nodes.

[0161] Clause 5. The method according to any one of Clauses 2 to 4, wherein one extra bit is identified in the corresponding first check node data of each of the plurality of first check nodes, and the extra bit of the corresponding first check node data of the plurality of first check nodes is grouped to store the additional check node data of two or more additional check nodes, including the additional check node, among the plurality of second check nodes.

[0162] Clause 6. The method according to Clause 1, further comprising the steps of identifying one or more overcheck nodes in the plurality of first check nodes, the overcheck node data of the one or more overcheck nodes forming a plurality of overbites, and assigning the plurality of overbites to the second check node data of the plurality of second check nodes.

[0163] The method according to Clause 7. The step of assigning the plurality of excess bits to the second check node data of the plurality of second check nodes further comprises assigning a first set of excess bits of the excess check node data of a first excess check node to store the second check node data of a first subset of the plurality of second check nodes, and assigning a second set of excess bits of the excess check node data of a second excess check node to store the second check node data of a second subset of the plurality of second check nodes.

[0164] Clause 8. The method according to Clause 6 or 7, wherein the plurality of excess bits include at least one remaining bit that is not assigned to any of the second check node data of the plurality of second check nodes.

[0165] The method according to any one of the clauses 6 to 8, wherein one excess check node is identified in each of the plurality of first check nodes to provide the plurality of excess bits, and a corresponding subset of the plurality of excess bits is assigned to the second check data of each and all second check nodes.

[0166] Clause 10. The method according to any one of Clauses 1 to 9, wherein for each of the plurality of first check nodes and the plurality of second check nodes, the corresponding check node data includes a first likelihood data item and an index data item that identifies one of the corresponding subsets of the codeword symbols corresponding to the first likelihood data item.

[0167] Clause 11. The method according to Clause 10, wherein a first subset of the codeword symbols comprises a first number of codeword symbols, a second subset of the codeword symbols comprises a second number of codeword symbols, the first number being greater than the second number, and each of the plurality of first check nodes' index data items comprises at least one extra bit to address the first number of codeword symbols more than each of the plurality of second check nodes' index data items, and each of the plurality of first check nodes' at least one extra bit forms a plurality of extra bits that are reconfigured to store the second check node data of at least one additional second check node.

[0168] Clause 12. The method according to Clause 10, wherein a first subset of the codeword symbols comprises a first number of codeword symbols, a second subset of the codeword symbols comprises a second number of codeword symbols, the first number being less than the second number, an overcheck node has overcheck node data comprising a plurality of overbits, the plurality of overbits being assigned to index data items of the second check node data of the plurality of second check nodes.

[0169] Clause 13. The method according to any one of Clauses 1 to 12, wherein for each check node, the subset of the corresponding codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicates the likelihood that the corresponding codeword symbol is incorrect, and the method further includes the step of identifying the first likelihood data item and the second likelihood data item in response to a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to the remaining likelihood data items of the subset of the codeword symbols.

[0170] Clause 14. Each likelihood data item for a corresponding codeword symbol is determined based on the log-likelihood ratio (LLR) expressed as follows:

number

[0171] Clause 15. The method according to any one of Clauses 1 to 14, wherein for each check node, the check node data of the check node further includes a first index data item that identifies one of the subsets of the codeword symbols corresponding to the first likelihood data of the check node data.

[0172] Clause 16. The method according to any one of Clauses 1 to 15, wherein each of the subsets of the codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data of the check node further includes symbol bits which are a combination of symbols of the corresponding likelihood data items of the subset of the codeword symbols.

[0173] An electronic device comprising one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the processors to perform the method described in any one of the paragraphs 1 to 16.

[0174] Clause 18. A non-temporary computer-readable storage medium that, when executed by one or more processors, stores instructions causing those processors to perform the actions described in any one of Clauses 1 to 16.

[0175] Each of the elements identified above may be stored in one or more of the aforementioned memory devices and correspond to a set of instructions for performing the functions described above. The modules or programs (i.e., sets of instructions) identified above do not need to be implemented as separate software programs, procedures, modules, or data structures, and therefore various subsets of these modules may be combined or rearranged in various embodiments. In some embodiments, memory selectively stores a subset of the modules and data structures identified above. Furthermore, memory selectively stores additional modules and data structures not described above.

[0176] The terminology used in describing the various embodiments described herein is intended solely to describe specific embodiments and not to limit them. When used in the descriptions of the various embodiments and in the appended claims, the singular forms “one,” “one,” and “the said” are intended to include the plural unless the context explicitly indicates otherwise. Furthermore, the term “and / or” as used herein is understood to refer to and encompass one or more of the related enumerated items, any and all possible combinations. Additionally, when used herein, the terms “include,” “contains,” “equip,” and / or “equip” identify the presence of a described feature, integer, step, operation, element, and / or component, but not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, while terms such as “first,” “second,” etc., may be used herein to describe various elements, it is understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another.

[0177] When used herein, the term “case” is interpreted selectively, depending on the context, to mean “when,” “on the occasion,” “in response to a determination,” “in response to detection,” or “in response to a determination that.” Similarly, the phrases “when determined” or “when ‘the described condition or event’ is detected” are interpreted selectively, depending on the context, to mean “when determined,” “in response to a determination,” “when ‘the described condition or event’ is detected,” “in response to the detection of ‘the described condition or event’,” or “in response to the determination that ‘the described condition or event’ has been detected.”

[0178] The above description is written with reference to specific embodiments for interpretive purposes. However, the above exemplary discussion is not intended to be exhaustive, nor is it intended to limit the claims to the exact form disclosed. In light of the above teachings, many modifications and variations are possible. The embodiments have been selected and described to best illustrate the operating principles and practical applications, and thereby to be understandable to those skilled in the art.

[0179] Various drawings illustrate several logical stages in a specific order, but the order-independent stages may be rearranged, and other stages may be combined or divided. While some rearrangements or other groupings are specifically mentioned, other rearrangements or groupings are obvious to those skilled in the art, and therefore the rearrangements and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that these stages may be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. A method for compressing check node data in an electronic device, Steps include identifying check nodes corresponding to a subset of codeword symbols in a data block, A step of determining check node data that includes multiple data items, the step of indicating the likelihood that the check node data indicates that a subset of the codeword symbols is incorrect, A step of determining a set of data bits based on a combination of values ​​of the plurality of data items, wherein the set of data bits uniquely identifies the combination of values ​​within a set of selected value combinations according to a predetermined relationship. The further step includes storing in a memory block the set of data bits representing the plurality of data items of the check node data of the check node, A method wherein each of the plurality of data items requires at least a first number of data bits to represent all possible values ​​of the corresponding data item, and the set of data bits has a second number of data bits, the second number being less than the sum of the first numbers for each of the plurality of data items.

2. The method according to claim 1, wherein the plurality of data items correspond to the total number of possible value combinations, and the binary data item representing the total number has more bits than the set of data bits.

3. The plurality of data items include a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol, wherein the second likelihood data item is greater than or equal to the first likelihood data item. The set of selected value combinations is complementary to the set of removed value combinations. The method according to claim 1 or 2.

4. The step of determining the set of data bits is performed in response to the determination that the combination of values ​​belongs to the set of combinations of values ​​that have been removed. The second likelihood data item is approximated by available neighbor values ​​while maintaining the value of the first likelihood data item, Based on the approximate value of the second likelihood data item, the combination of the values ​​of the plurality of data items is updated, The method according to claim 3, further comprising determining the set of data bits based on the updated combination of values.

5. The method according to any one of claims 1 to 4, wherein for each of the set of selected value combinations, the first likelihood data item is within a first value range and the second likelihood data item is within a second value range.

6. The method according to claim 5, wherein the first value range includes one or more discontinuous first data subranges, one or more predetermined first data values, or a combination thereof, and the second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

7. The method according to any one of claims 1 to 6, wherein for each of the set of selected value combinations, the second likelihood data item in the second value range includes one or more discontinuous second data subranges, one or more predetermined second data values, or a combination thereof.

8. The method according to any one of claims 1 to 7, wherein the second likelihood data item has a most significant bit (MSB) and a least significant bit (LSB), and for each of the set of selected value combinations, the MSB and LSB of the second likelihood data item are not equal to "1" and "0", respectively, independently of the first likelihood data item.

9. The plurality of data items include a first likelihood data item corresponding to a first codeword symbol, a second likelihood data item corresponding to a second codeword symbol, and a second index data item that identifies one of the subsets of the codeword symbols corresponding to the second likelihood data item of the check node data, The second likelihood data item is greater than or equal to the first likelihood data item. The step of determining the set of data bits further includes selecting only one of the MSB of the first likelihood data item and the LSB of the second index data item to include in the set of data bits, based on the MSB of the second likelihood data item. The method according to any one of claims 1 to 8.

10. Selecting only one of the MSB of the first likelihood data item and the LSB of the second index data item is: In response to the determination that the MSB of the second likelihood data item is equal to "0", the set of data bits is determined based on the LSB of the second index data item, and independently of the MSB of the first likelihood data item, or The method according to claim 9, further comprising determining the set of data bits based on the MSB of the first likelihood data item and independently of the LSB of the second index data item, in response to the determination that the MSB of the second likelihood data item is equal to "1".

11. The method according to any one of claims 1 to 10, wherein the second number is one or two less than the sum of the first numbers for each of the plurality of data items, thereby saving one or two bits for storing the check node data.

12. The subset of the codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicates the likelihood for which the corresponding codeword symbol is incorrect, and the one or more programs The method according to any one of claims 1 to 11, comprising instructions for identifying the first likelihood data items and the second likelihood data items in response to a determination that the second likelihood data items are more than or equal to the first likelihood data items and fewer than or equal to the remaining likelihood data items of the subset of codeword symbols.

13. Each likelihood data item of the corresponding codeword symbol is determined based on the approximated log-likelihood ratio (LLR) as follows: [Math 1] The method according to claim 12, wherein p(|) is the probability of a combination of data values, x is the value stored for the corresponding codeword symbol, and y is the correct value for the corresponding codeword symbol.

14. The method according to any one of claims 1 to 13, wherein the plurality of data items further include at least one of a first index data item that identifies one of the subsets of the codeword symbols corresponding to a first likelihood data item of the check node data, and a second index data item that identifies one of the subsets of the codeword symbols corresponding to a second likelihood data item of the check node data.

15. The method according to any one of claims 1 to 14, wherein each of the subsets of the codeword symbols corresponds to a corresponding likelihood data item indicating the likelihood that the corresponding codeword symbol is incorrect, and the check node data of the check node further includes symbol bits which are a combination of symbols of the corresponding likelihood data items of the subset of the codeword symbols.

16. A non-temporary computer-readable storage medium that, when executed by one or more processors, stores instructions causing the processors to perform the method described in any one of claims 1 to 15.

17. One or more processors, A memory containing instructions that, when executed by one or more processors, cause the processors to perform the method described in any one of claims 1 to 15, An electronic device equipped with the following features.

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