High-voltage wake signaling input / output for 10BASE-T1S system-based chips

Abstract

The method may include the steps of: receiving a signaling signal on a system-based chip implementing a 10SPE PHY transceiver; changing the signaling signal on the system-based chip from a first voltage level incompatible with the voltage domain of a microcontroller (MCU) implementing a 10SPE PHY controller to a second voltage level compatible with the voltage domain of the MCU; and communicating the changed signaling signal to the MCU.

Description

Technical Field

[0001] (Claiming Priority) This application claims the benefit of the filing date of International Patent Application No. PCT / CN2023 / 107647, filed on July 17, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

[0002] Embodiments generally relate to a 10SPE physical layer (PHY). Some embodiments generally relate to a system basis chip implementing a transceiver of a 10SPE PHY and a microcontroller implementing a controller of the 10SPE PHY. Some embodiments generally relate to a system basis chip that processes high-voltage signaling to the PHY and interfaces the high-voltage signaling with a low-voltage region of a microcontroller.

Background Art

[0003] A system basis chip (SBC) is an integrated circuit (IC) that combines multiple functions necessary for the operation of an electronic system. ICs and SBCs are utilized in various operational contexts.

Brief Description of the Drawings

[0004] To easily identify any consideration of a particular element or action, the most significant digit(s) of the reference number refer to the figure number in which the element was first introduced. [Figure 1] A block diagram depicting a system implementing, among other things, a 10SPE PHY according to one or more embodiments. [Figure 2] A circuit diagram depicting high-voltage input / output for a system basis chip (SBC) such as the SBC of FIG. 1 according to one or more embodiments. [Figure 3] A schematic diagram of a system for driving high-voltage GPIO of an SBC according to one or more embodiments. [Figure 4] This is a schematic diagram illustrating a system for generating internal signals via the high-voltage I / O shown in Figure 2, based on one or more embodiments. [Figure 5] This is a state diagram illustrating the behavior of an SBC that manages high-voltage GPIOs in one or more embodiments. [Figure 6] This flowchart illustrates a process for processing high-voltage signals and interfaced high-voltage signals with a low-voltage MCU, based on one or more embodiments. [Figure 7] In some embodiments, these are block diagrams of circuits that may be used to implement various functions, operations, actions, processes, or methods disclosed herein. [Modes for carrying out the invention]

[0005] The following detailed description refers to the accompanying drawings, which form part of this specification and illustrate specific examples of embodiments that can carry out the disclosure. These embodiments are described in sufficient detail to enable those skilled in the art to carry out the disclosure. However, other embodiments may be utilized, and structural, material, and process variations may be made without departing from the scope of the disclosure.

[0006] The illustrative diagrams presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristics.

[0007] The following specification may include examples to help enable those skilled in the art to carry out the disclosed examples. The use of the terms “exemplary,” “as an example,” and “for example” means that the relevant descriptions are illustrative, and the scope of this disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of this disclosure to specified components, steps, features, functions, etc.

[0008] It will be readily apparent that the components of the embodiments described herein and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following description of numerous embodiments is not intended to limit the scope of this disclosure, but merely to represent a number of embodiments. While numerous aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations illustrated and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Conversely, the specific implementations illustrated and described are merely illustrative and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic between various blocks are examples of specific implementations. It will be readily apparent to those skilled in the art that this disclosure can be implemented by numerous other partitioning solutions. For the most part, details such as timing considerations are omitted, as such details are not necessary for a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. Some drawings may illustrate a signal as a single signal for clarity in presentation and explanation. Those skilled in the art will understand that a signal can represent a bus of signals, which can have various bit widths, and that this disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, dedicated processors, digital signal processors (DSPs), integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, separate gate or transistor logic, separate hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a dedicated computer while that general-purpose computer is executing computing instructions (e.g., software code) related to the embodiments of this disclosure.

[0012] Examples may be described in relation to processes depicted as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe actions as sequential processes, many of these actions may also occur in different sequences, concurrently, or substantially simultaneously. In addition, the order of actions may be rearranged. Processes may, but are not limited to, methods, threads, functions, procedures, subroutines, or subprograms. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or codes in a computer-readable medium. Computer-readable medium includes both computer storage media and communication media, including any media that facilitate the transfer of computer programs from one location to another.

[0013] Any reference to elements in this specification using notations such as "first," "second," etc., does not limit the number or order of those elements unless such limitation is expressly stated. Rather, these notations may be used in this specification as a convenient way to distinguish two or more elements or examples of elements. Thus, references to the first and second elements do not mean that only two elements may be used, or that in any manner the first element must precede the second element. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term “substantially” when referring to a given parameter, characteristic, or condition means and includes the extent to which a person skilled in the art would understand that the given parameter, characteristic, or condition is within a small variation, such as within an acceptable manufacturing tolerance. For example, depending on the particular parameter, characteristic, or condition to be substantially satisfied, the parameter, characteristic, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, any relative terms such as “over,” “under,” “on,” “underlying,” “upper,” and “lower” are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and do not imply, nor rely on, any specific preference, orientation, or order, unless the context clearly indicates otherwise.

[0016] In this specification, the term “combined” and its derivatives may be used to indicate that two elements cooperate with or interact with each other. When one element is described as “combined” with another, those elements may be in direct physical or electrical contact, but there may be an intervening element or layer between them. In contrast, when one element is described as “directly combined” with another, there is no intervening element or layer. The term “connected” may be used interchangeably with the term “combined” in this specification and has the same meaning unless otherwise expressly indicated or the context indicates to those skilled in the art in another way.

[0017] As used herein, the terms “assert,” “de-assert,” and their derivatives, used in reference to a pin, mean to assert or de-assert a signal associated with a pin (e.g., a signal specifically assigned to a pin, or a signal to which a pin is specifically assigned), respectively.

[0018] A system-based chip (SBC) is an integrated circuit (IC) that combines multiple functions for the operation of an electronic system. Typically, an SBC integrates various different functions onto a single chip and, in non-limited embodiments, includes power management functions such as voltage regulators, power switches, or protection circuits for managing the system's power supply; communication interfaces such as, but not limited to, a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Serial Peripheral Interface (SPI), or an Inter-Integrated Circuit (I2C); embedded systems such as a state machine or microprocessor for controlling and coordinating tasks; analog functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning circuits; and diagnostic and safety functions such as monitoring and reporting voltage levels, temperature, or fault conditions.

[0019] SBCs are found in a variety of operational contexts, including automotive and industrial applications. A non-exclusive automotive application for SBCs is in 10SPE (i.e., 10 Mbps single-pair Ethernet) networks (also known as "10BASE-T1S networks"). 10SPE is a network technology defined in sections 147 and 148 of IEEE 802.3. 10SPE is used to provide collision-free deterministic transmission in multidrop networks.

[0020] In some cases, as a non-limiting example, the transceiver (xcvr) and controller of a 10SPE physical layer device (PHY) may be located on different dies, and thus the dies may be subject to different processing conditions. Such an architecture is referred to herein as a "split PHY" architecture. The digital blocks of the PHY controller that are susceptible to damage during the high voltage temperature process are located on a first die that does not undergo the high voltage temperature process. The analog and digital blocks of the PHY transceiver that are less susceptible to damage during the high voltage temperature process or that require such a high voltage temperature process are located on a second die that undergoes such a high voltage temperature process.

[0021] The 10SPE transceiver interface standard currently under specification development by the Technology Committee 14 of the Open Alliance (hereinafter, "TC14") defines a hardware interface (specifically, a 3-pin hardware interface) for communication between the PHY transceiver and the PHY controller in the case of a split PHY architecture.

[0022] In 10SPE, a microcontroller (MCU) implements the PHY controller function and an SBC implements the PHY transceiver function. In 10SPE, the non-transceiver responsibilities of the SBC include regulated power supply (e.g., low voltage power supply), observability / control of the high voltage region (e.g., processing of high voltage signals), and a functional safety mechanism for the MCU to reach a safe state. Thus, in addition to the transceiver function, the SBC implements functions of an electronic system such as, but not limited to, power management, watchdog circuit, monitor, general purpose input / output (GPIO).

[0023] TC14 describes the low-power (sleep-wake) behavior of a PHY transceiver for partial networking. Partial networking refers to features that enable selective power management and communication capabilities within a network. Partial networking allows specific network nodes or devices to enter a low-power or sleep state while still maintaining basic communication functions. In Ethernet networks, partial networking is utilized to optimize power consumption, particularly in automotive or industrial applications. Allowing selected devices to enter a low-power or sleep state can, among other things, reduce overall power consumption, extend battery life, or improve energy efficiency.

[0024] Modern MCUs typically operate at lower voltages such as 3.3V, thereby becoming incompatible with the direct high-voltage signals typically found in automotive, industrial, and other high-voltage applications. For example, in automotive applications, the battery voltage (Vbat) can be nominally 12V, but can vary significantly under different conditions such as those specified by the LV124 standard, among others. Similarly, other applications such as fire alarm systems can operate at a nominal voltage of 24V.

[0025] One or more embodiments generally relate to a system-on-a-chip (SBC) capable of handling supply voltage signals and high-voltage signals. The SBC integrates a high-voltage (HV) GPIO function into the SBC, enabling the SBC to process high-voltage signals and interface with low-voltage devices such as a low-voltage MCU.

[0026] In one or more embodiments, the SBC is capable of level-shifting high-voltage system signals to an MCU-compatible level (e.g., from 12V to 3.3V, among others).

[0027] Additionally or alternatively, in one or more embodiments, changes in high-voltage inputs may be detected and qualified by the SBC and then communicated to the MCU via interrupts. This allows the MCU to be notified of high-voltage changes without being directly exposed to the high voltage.

[0028] Additionally or alternatively, in one or more embodiments, when the MCU writes to a register, the SBC may signal this as a high-voltage or ground (GND) output using an open-drain driver.

[0029] Additionally or alternatively, in one or more embodiments, but not limited to them, the MCU may control high-voltage domain modules via GPIO outputs and enable functions such as wake signaling.

[0030] Additionally or alternatively, in one or more embodiments, high-voltage GPIOs may be used for wake signals (e.g., WAKEIN) in the always-on region (uninterruptable voltage domain, VDDU). This allows the SBC to wake the system based on the high-voltage input and wake it from a low-power or sleep state (change its power state).

[0031] Figure 1 is a block diagram illustrating one or more embodiments, in particular, a system 100 that implements a 10SPE PHY.

[0032] System 100 includes an MCU 102 and an SBC 108. The MCU 102 includes a PHY controller 104 and an I2C bus controller 106. The PHY controller 104 and PHY transceiver 110 form a 10SPE PHY. The PHY controller 104 and PHY transceiver 110 communicate via a hardware interface 112 which includes connections for carrying signals associated with transmit signaling (TX connection), energy sense signaling (ED connection), and receive signaling (RX connection). The MCU 102 and SBC 108 communicate via the I2C bus and optionally via command connections, control connections, and management connections (represented in Figure 1 by connections INTn and RSTn, which are specific non-limiting embodiments of the command connections, control connections, and management connections) that specify actions required from the MCU. A non-limiting embodiment of communication via command connections, control connections, and management connections includes interrupt (IRQ) signaling.

[0033] The PHY controller 104 is responsible for managing the digital aspects of 10BASE-T1S PHY communication. It handles tasks such as coding, decoding, and managing the link layer protocol. The I2C bus controller 106 manages communication over the I2C bus and facilitates command, control, and data exchange between the MCU 102 and the SBC 108. In the specific embodiment depicted by Figure 1, the optional logic managing communication between command connections, control connections, and management connections (e.g., INTn and RSTn, but not limited to these) is represented by the same block representing the I2C bus controller 106, but may be in different logical partitions.

[0034] The SBC108 implements or manages the functions of the PHY transceiver 110, the functions of the MCU 102, and the internal functions of the SBC108 itself (SBC functions, which are non-transceiver functions). The SBC108 may also optionally implement the functions of sensors (sensors not depicted, but to be considered optional). Vuc is the supply voltage managed by the SBC108 and provided from the SBC108 to the MCU 102. The SBC108 may also optionally provide supply voltages to other devices such as sensors as needed (e.g., supplying Vsen, but not limited to these). Vsup is the supply voltage provided to the SBC108 and may be used, for example, directly or as a regulated version of Vsup, to generate Vuc. Vbat is the battery voltage and represents the high-voltage supply voltage provided to the system 100 and more specifically to the SBC108 (e.g., an unregulated voltage source that generates a voltage higher than the supply voltage VSup). GPIO stands for General Purpose Input / Output Connection. The transmit / receive connection, common mode choke (CMC), and connector are physical circuits that connect the SBC108 to a physical transmit medium, such as twisted pair, but are not limited to these. WAKEIN is an input connection used exclusively to receive external power management signals (e.g., wake or sleep, but are not limited to these) from an external source (e.g., outside of system 100, but are not limited to these). WAKEOUT is an output connection used exclusively to send power management signals outside of system 100.

[0035] The SBC108 is capable of high-voltage I / O processing, as discussed below. In one or more embodiments, the SBC108 includes one or both of a level shifter 116 and an IRQ signaler 118 to facilitate high-voltage I / O processing.

[0036] The level shifter 116 converts the signal from a high voltage level to a lower MCU-compatible voltage level. This allows the MCU 102 to safely read the high voltage input of the high voltage I / O 114 without being directly exposed to the high voltage.

[0037] The IRQ signaler 118 detects changes in the high-voltage input of the high-voltage I / O 114 and qualifies the changes. The IRQ signaler 118 communicates the qualified signals to the MCU 102 via interrupts (e.g., generating interrupts, but not limited to interrupts), allowing the MCU 102 to respond to high-voltage events without directly processing the high-voltage signals. The system 100 may include one or more interrupt and control lines connecting the SBC 108 and the MCU 102 to facilitate IRQ and control signaling that communicates qualified signals to the MCU 102 to notify the MCU 102 of high-voltage events.

[0038] The SBC108 may also include GPIO control 120 in the always-on region to facilitate power management functions such as wake detection and signaling, in cooperation with one or more of the level shifters 116 or IRQ signalers 118. In one or more embodiments, the GPIO control 120 may detect certain conditions, such as a high-voltage wake signal for the HV GPIO, and trigger a response by the appropriate system.

[0039] High-voltage GPIOs (HV GPIOs) are capable of handling higher voltage levels than standard GPIOs. In this context, an HV GPIO processes a signal represented by the voltage level of Vbat, while a standard GPIO processes a signal represented by the level of Vsup, where Vsup is lower than Vbat.

[0040] As part of the intended wake process, a high-voltage GPIO pin may be configured to detect a wake signal represented by a voltage change that satisfies specific conditions.

[0041] The IRQ signaler 118 of the SBC108 qualifies the detected signal, ensuring that it is a valid wake event. During qualification, the IRQ signaler 118 generates an interrupt to notify the MCU102 of the wake event. Upon receiving the interrupt, the MCU102 initiates the process of transitioning the system from a low-power or sleep state to an active state.

[0042] Figure 2 is a schematic diagram illustrating an HV I / O200 for an SBC such as the SBC108 in one or more embodiments. The HV I / O200 can connect the WAKEIN and WAKEOUT connections of the SBC (e.g., SBC108) to pads. The pads are for high-voltage connections. The pads operate at Vbat, and the SBC connections operate at Vsup, where Vsup is... <Vbatである。

[0043] HV I / O200 is a non-limiting embodiment of the level shifter 116 in Figure 1.

[0044] In one or more embodiments, the HV I / O200 may be an internal circuit of the SBC108 that couples its internal connections to connections (e.g., pads) for connecting to the outside of the SBC, or the HV I / O200 may be external to the SBC108 and function as an interface between the SBC and such external sources for connecting to external sources.

[0045] The high-voltage input stage includes a comparator with hysteresis (here, a Schmitt trigger). The output of the comparator is coupled to the SBC's internal wake signaling connection dind. This output is switchably coupled to ground by a transistor switch. This output of the comparator can be connected in series or parallel to dind depending on the state of the transistor switch. When the switch is on, the output of the comparator is coupled in parallel with dind; when the switch is off, the output of the comparator is coupled in series with dind. The gate of the switch and the reference input of the comparator are coupled to receive the signal en-ind.

[0046] The input to the comparator is coupled in parallel to the input node, which is also coupled to ground via a capacitor. The input node is switchably coupled to a high-value resistor (here, a 500K ohm resistor) via another transistor switch. The gate of this transistor switch is coupled to Vsup (here, 3.3V). This transistor is an n-channel MOSFET coupled in series with the high-value resistor. The other end of the high-value resistor is coupled to a node in parallel with several series-coupled Zener diodes and pads.

[0047] In one or more embodiments, a wake event may be indicated as a specific voltage change at a pad. A signal detector (not shown in Figure 2) may set internal bits (e.g., flags, but not limited to) in response to the detection of a valid voltage change at dind. The valid voltage change at dind may be used to infer a valid voltage change at a pad. The valid voltage change at a pad indicates a wake signal at the pad. If the voltage potential of Vbat is at the pad, Vbat (3.3V) appears at the input of the comparator. If the ground voltage potential is at the pad, the ground voltage appears at the input of the comparator.

[0048] The part of the HV I / O200 circuit above the part of the circuit including the high-voltage input stage is the high-voltage output stage. Doutd and Endb are internal signals used to control the output state of the pad. Connections to Doutd and Endb are connected to the inputs of the NOR gate. When Doutd and Endb are set to 0, the gate output (GATE_out) is set to 1. When either or both Doutd and Endb are set to 1, the gate output (GATE_out) is set to 0. If the transistor switch is an N-channel MOSFET, when doutd and endb are 0 (ground), the transistor switch is on, allowing current to flow, and therefore the pad is on ground. When either or both doutd and endb are at logic level 1, the transistor switch is off, not allowing current to flow, and therefore the pad is at VBAT.

[0049] Figure 3 is a schematic diagram of a system 300 for driving the high-voltage GPIO of an SBC, according to one or more embodiments. The system 300 includes a CSR 302, a MUX 304, and an inverter 306.

[0050] CSR302 is a command status register containing at least the bits EXT Flag, Flags1, Flags2, and Flag Select. Flags1, Flags2, and Flag Select are available for use as needed based on specific operating conditions.

[0051] MUX304 provides a MUX selection between Flag1 and Flag2, at least partially based on flag select. The output of MUX304 is coupled to high-voltage I / O by inverter 306. The EXT flag is a bit (e.g., an external wake signal, but not limited to) that can be set by GPIO via HV I / O200 in a non-limiting embodiment.

[0052] Figure 4 is a schematic diagram illustrating a system 400 for generating internal signals via the high-voltage I / O of Figure 2, according to one or more embodiments. The system 400 includes a high-voltage input / output 402, a signal detector 404, and a CSR 406.

[0053] System 300 receives an input signal (voltage signal) having a voltage range from Vbat to ground (i.e., a high-voltage region). The high-voltage input / output 402 (which may be HV I / O200 in Figure 2) converts the voltage signal into an interval voltage level signal, which is then supplied to the signal detector 404. The signal detector 404 determines, based on the output of the high-voltage input / output 402, the portion of the signal present in the pad that was a valid input signal, and indicates a valid signal at the output of the signal detector 404. The EXT_Flag of CSR is set based on the output of the signal detector 404.

[0054] Figure 5 is a state diagram illustrating the behavior of an SBC managing high-voltage GPIOs in one or more embodiments. Intersections represent states (particularly operating modes), namely SBC_sleep, SBC_reset, LPwake, LP, SBC_operative, normal, and config. Directed edges between intersections represent transitions from one state to another. The conditions or events that trigger the transitions indicated by the directed edges are also depicted.

[0055] The SBC off state (SBC_off) is the initial state where the SBC's power is completely turned off. The SBC can transition from SBC_off to SBC_reset in response to a Vuc power-on reset (POR).

[0056] The SBC reset state (SBC_reset) is the state in which the SBC initializes its components and prepares for operation. In response to a reset signal (RSTn) indicating that the reset process is complete, the SBC can transition from the SBC_off state to the SBC operating state (SBC_oper).

[0057] The SBC operating state (SBC_oper) is a state in which the SBC is fully functional and capable of performing its tasks. The SBC can transition from the SBC operating state (SBC_oper) to the SBC sleep state (SBC_sleep) in response to an SBC command for sleep and the PHY transceiver being in low power (LP) mode. The SBC can transition from the SB operating state (SBC_oper) to the low power (LP) wake state in response to an interrupt timeout. The SBC can transition from the SB operating state (SBC_oper) to SBC_reset in response to an indication that a reset signal (RSTn) has been given.

[0058] The SBC sleep state (SBC_sleep) is a low-power sleep state in which the SBC minimizes its power consumption. The SBC can transition from the SBC sleep state (SBC_sleep) to the SBC wake state (SBC_wake) in response to over-temperature shutdown (OTSD) and over-voltage shutdown (OVSD). The SBC can transition from the SBC sleep state to the SBC operating state (SBC_oper) in response to an SBC command for waking and the PHY transceiver being in LP mode.

[0059] The SBC wake state (SBC_wake) is a transition state in which the SBC transitions from the SBC sleep state to the SBC operating state.

[0060] The low-power wake state (LPwake) indicates that the PHY transceiver has woken up from a low-power state. The LPwake state is triggered by a wake signal.

[0061] The low-power (LP) state indicates a low-power state in the PHY transceiver, consuming minimal power. The LP state is triggered by a wake signal.

[0062] The normal state is the normal operating state of a PHY transceiver, in which the PHY transceiver performs its standard functions. A PHY transceiver can transition from the normal state to the transmit state, the configured state, or the low-power state. The transition to the transmit state is triggered by the need to send data. The transition to the configured state is triggered by a configuration command. The transition to the low-power state (LP) is triggered by a sleep command.

[0063] The transmit state is when the PHY transceiver is ready to receive and transmit data. The PHY transceiver can switch from the transmit state to the transmitting state, which is triggered by the start of transmission.

[0064] The transmitting state (xmiting) indicates that the PHY transceiver is in the process of transmitting data. The PHY transceiver can transition from the transmitting state to the normal state when data transmission is complete.

[0065] The configuration state is the state in which the PHY transceiver is being configured. The PHY transceiver can transition from the configuration state to the normal state when the configuration is complete.

[0066] Figure 6 is a flowchart illustrating a process 600 for processing high-voltage signals and interface those high-voltage signals with a low-voltage MCU, according to one or more embodiments. While the exemplary process 600 illustrates a specific sequence of operations, the sequence can be modified without departing from the scope of the disclosure. For example, some of the operations described may be performed in parallel or in different sequences that do not significantly affect the functionality of process 600. In other embodiments, different components of an exemplary device or system implementing process 600 may perform functions substantially simultaneously or in specific sequences.

[0067] According to some embodiments, the method includes the step of receiving signaling in a system-based chip that implements a transceiver of 10SPE PHY in block 602.

[0068] According to some embodiments, the method includes, in block 604, changing the signaling in the system base chip from a first voltage level incompatible with the voltage domain of a microcontroller (MCU) implementing a 10SPE PHY controller to a second voltage level compatible with the voltage domain of the MCU.

[0069] According to some embodiments, the method includes the step of communicating the modified signaling to the MCU in block 606.

[0070] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 7 illustrates a non-limiting embodiment of the implementation of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein can be performed by hardware capable of executing the functional elements.

[0071] Figure 7 is a block diagram of a circuit 700 that may be used in some embodiments to implement various functions, operations, actions, processes, or methods disclosed herein. The circuit 700 includes one or more processors 702 (which may be referred to herein as “processors 702”) operably coupled to one or more data storage devices 704 (which may be referred to herein as “storage devices 704”). The storage device 704 includes machine-executable code 706 stored therein, and the processors 702 include logic circuits 708. The machine-executable code 706 describes functional elements that can be implemented (e.g., performed) by the logic circuits 708. The logic circuits 708 are adapted to implement (e.g., perform) the functional elements described by the machine-executable code 706. When the circuit 700 executes the functional elements described by the machine-executable code 706, it should be considered dedicated hardware for executing the functional elements disclosed herein. In some embodiments, the processor 702 may execute the functional elements described by the machine-executable code 706 sequentially, simultaneously (for example, on one or more different hardware platforms), or in one or more parallel processing streams.

[0072] When implemented by the logic circuit 708 of the processor 702, the machine-executable code 706 adapts the processor 702 to perform the operations of the embodiments disclosed herein. In non-limiting embodiments, the machine-executable code 706 may adapt the processor 702 to perform some or all operations to facilitate high-voltage I / O processing considered herein, such as high-voltage wake signaling input / output for a 10BASE-T1S system-based chip, but not limited to these. In non-limiting embodiments, the processor machine-executable code 706 may adapt the processor 702 to perform some or all operations of state diagram 500 or process 600.

[0073] In addition, as a non-limiting embodiment, machine executable code 706 may be adapted to perform some or all of the features, functions, or operations disclosed herein for one or more of the finite state machines (FSMs) implementing System 100, HV I / O 200, System 300, System 400, System 1000, or State Diagram 500. More specifically, the features, functions, or operations disclosed herein for regulating power state changes.

[0074] The processor 702 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer while the general-purpose computer is executing functional elements corresponding to machine-executable code 706 (e.g., software code, firmware code, hardware description) related to embodiments of this disclosure. Note that the general-purpose processor (which may be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor 702 may include any conventional processor, controller, microcontroller, or state machine. The processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration.

[0075] In some embodiments, the storage device 704 includes volatile data storage devices (e.g., random-access memory (RAM), but not limited to them) and non-volatile data storage devices (e.g., flash memory, hard disk drives, solid-state drives, erasable programmable read-only memory (EPROM), but not limited to them). In some embodiments, the processor 702 and the storage device 704 may be implemented in a single device (e.g., semiconductor device products, system on chips (SOCs), but not limited to them). In some embodiments, the processor 702 and the storage device 704 may be implemented in separate devices.

[0076] In some embodiments, machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code). In a non-limiting embodiment, computer-readable instructions may be stored in a storage device 704, accessed directly by the processor 702, and executed by the processor 702 using at least a logic circuit 708. Also in a non-limiting embodiment, computer-readable instructions may be stored in the storage device 704, transferred to a memory device (not shown) for execution, and executed by the processor 702 using at least a logic circuit 708. Thus, in some embodiments, the logic circuit 708 includes an electrically configurable logic circuit 708.

[0077] In some embodiments, machine-executable code 706 may describe hardware (e.g., circuits) implemented within logic circuits 708 to implement functional elements. This hardware may be described at any of the various levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. In non-limiting embodiments, Verilog, SystemVerilog, or very large-scale integration (VLSI) hardware description languages ​​(VHDL) may be used.

[0078] The HDL description can be translated into a description at any of several other levels of abstraction, as desired. In a non-limiting embodiment, the high-level description can be translated into a logic-level description such as register-transfer language (RTL), gate-level (GL) description, layout-level description, or mask-level description. In a non-limiting embodiment, the microoperations performed by the hardware logic circuits of logic circuit 708 (e.g., gates, flip-flops, registers, etc., but not limited to these) can be described in RTL and then translated into a GL description by a synthesis tool, which can then be translated into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, separate gate or transistor logic, separate hardware components, or combinations thereof. Thus, in some embodiments, the machine-executable code 706 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0079] In embodiments where the machine-executable code 706 includes a hardware description (at any level of abstraction), the system (including a storage device 704, not shown) implements the hardware description described by the machine-executable code 706. In non-limiting embodiments, the processor 702 may include a programmable logic device (e.g., an FPGA or PLC), and the logic circuit 708 may be electrically controlled to implement circuits corresponding to the hardware description in the logic circuit 708. Also in non-limiting embodiments, the logic circuit 708 may include hardwired logic manufactured by a manufacturing system (including a storage device 704, not shown) according to the hardware description of the machine-executable code 706.

[0080] Regardless of whether the machine-executable code 706 includes computer-readable instructions or hardware descriptions, the logic circuit 708 is adapted to implement the functional elements described by the machine-executable code 706 when implementing the functional elements of the machine-executable code 706. Note that while hardware descriptions may not directly describe functional elements, they indirectly describe functional elements that the hardware elements described by the hardware description are capable of performing.

[0081] When used in this disclosure, the terms “module” or “component” may refer to a specific hardware implementation for performing actions of a module or component and / or software object or software routine that are stored in and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing devices, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored in and / or executed in general-purpose hardware), specific hardware implementations, or combinations of software and specific hardware implementations, are also possible and intended.

[0082] When used in this disclosure, the term “combination” referring to multiple elements may include any combination of all elements or any various different subcombinations of some elements. For example, the phrase “A, B, C, D, or any combination thereof” may refer to A, B, C, or D; any combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or any one of C and D.

[0083] The terms used in this disclosure, and in particular in the appended claims (e.g., the text of the appended claims, but not limited to them), are generally intended to be “open” terms (for example, “including” should be interpreted as “including, but not limited to,” “having” should be interpreted as “at least having,” and “includes” should be interpreted as “including, but not limited to,” but not limited to). As used herein, “each” means “part or whole.” As used herein, “each and all” means “whole.”

[0084] Additionally, if a specific number of introduced claim enumerations is intended, such intent will be explicitly enumerated in the claims; if there is no such enumeration, such intent does not exist. For example, to aid understanding, the following attached claims may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim enumeration. However, the use of such phrases should not be interpreted as the introduction of a claim enumeration by the indefinite article “a” or “an” limiting any particular claim containing such introduced claim enumeration to only one embodiment containing such enumeration (for example, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more,” although this is not limiting), and the same applies to the use of the definite article used to introduce a claim enumeration.

[0085] In addition, even if specific numbers are explicitly listed in the introduced claims, a person skilled in the art will recognize that such a list should be interpreted as meaning at least the number listed (for example, the explicit list of “two lists” without other modifiers means, without limitation, at least two lists or two or more lists). Furthermore, where conventions similar to “at least one of A, B, and C” or “without limitation, one or more of A, B, and C” are used, such structures are generally intended to include, without limitation, A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0086] Furthermore, any separating words or phrases that present two or more alternative terms should be understood, whether in the specification, claims, or drawings, as intended to include the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0087] Further non-limiting embodiments include: Example 1: Apparatus comprising: a pad associated with high-voltage signaling, the high-voltage signaling being represented by a voltage change between first voltage levels; a system base chip comprising: a circuit for changing a voltage signal between a first voltage level and a second corresponding voltage level, the second voltage level being lower than the first voltage level, the first voltage level being utilized in the pad, and the second voltage level being utilized by the system base chip; and a signal detector for detecting an effective voltage change in the pad in response to the changed voltage signal;

[0088] Example 2: The apparatus according to Example 1, wherein the voltage range of the first voltage level is defined between the ground voltage potential and the first voltage level, and the voltage range of the second voltage level is defined between the ground voltage potential and a second voltage level lower than the battery voltage.

[0089] Example 3: The apparatus according to Example 1 or 2, comprising a register of a system-based chip (SBC) for storing the output of a signal detector, and an input path of a circuit from pads to the register, wherein the pads are supplied by a first supply voltage that provides a first voltage level, and the input path of the circuit is supplied by a second supply voltage that provides a second voltage level.

[0090] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the input path includes a high-value series resistor to limit the current flow through the circuit when a high voltage is applied to the pad.

[0091] Example 5: The apparatus according to any one of Examples 1 to 4, further comprising an interrupt signaler for communicating events, at least partially based on information stored in the registers of the SBC.

[0092] Example 6: The system base chip is the apparatus described in any of Examples 1 to 5, which mounts a 10SPE PHY transceiver.

[0093] Example 7: The apparatus according to any one of Examples 1 to 6, comprising a register for storing an output signal and an output path of the circuit from the register to a pad, wherein the pad is supplied by a first supply voltage that provides a first voltage level, and the output path of the circuit is supplied by a second supply voltage that provides a second voltage level.

[0094] Example 8: A device comprising a microcontroller implementing a 10-speed physical layer (PHY) controller and a system base chip implementing a transceiver for the 10-speed PHY, wherein the system base chip receives and processes high-voltage external signals and interfaces the high-voltage external signals with the low-voltage region of the microcontroller (MCU).

[0095] Example 9: The apparatus as in Example 8, wherein the high-voltage external signal includes an external wake signaling, and the system base chip is for generating an internal wake signaling representing the external wake signaling, a voltage range for the high-voltage external signaling defined between the ground voltage level and a first voltage level, and a voltage range for the internal wake signaling defined between the ground voltage and a second voltage level lower than the first voltage level.

[0096] Example 10: The apparatus according to any one of Examples 8 and 9, wherein the system base chip communicates wake events to the MCU, at least in part, based on internal wake signaling.

[0097] Example 11: The apparatus described in any of Examples 8-10, wherein the system base chip provides internal wake signaling to the MCU.

[0098] Example 12: A method comprising the steps of: receiving a signaling signal on a system-based chip implementing a transceiver of a 10SPE PHY; changing the signaling signal on the system-based chip from a first voltage level incompatible with the voltage domain of a microcontroller (MCU) implementing a controller of the 10SPE PHY to a second voltage level compatible with the voltage domain of the MCU; and communicating the changed signaling signal to the MCU.

[0099] While this disclosure is described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, many additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, together with its legal equivalents. In addition, features of one embodiment can be combined with features of another embodiment, as conceived by the inventors, but still remain within the scope of this disclosure.

Claims

1. It is a device, A pad associated with a high-voltage signaling, wherein the high-voltage signaling is represented by a voltage change between first voltage levels, and the pad It is a system-based chip, A circuit for changing a voltage signal between a first voltage level and a second corresponding voltage level, wherein the second voltage level is lower than the first voltage level, the first voltage level is utilized by the pad, and the second voltage level is utilized by the system base chip, and A system base chip comprising a signal detector for detecting an effective voltage change in the pad in response to the changed voltage signal, A device equipped with the following features.

2. The voltage range of the first voltage level is defined between the ground voltage potential and the first voltage level. The apparatus according to claim 1, wherein the voltage range of the second voltage level is defined between the ground voltage potential and a second voltage level lower than the battery voltage.

3. A register of the system base chip (SBC) for storing the output of the signal detector, The input path of the circuit from the pad to the register, Equipped with, The apparatus according to claim 2, wherein the pad is supplied by a first supply voltage that provides the first voltage level, and the input path of the circuit is supplied by a second supply voltage that provides the second voltage level.

4. The apparatus according to claim 3, wherein the input path includes a high-value series resistor for limiting the current flow through the circuit when a high voltage is applied to the pad.

5. The apparatus according to claim 3, further comprising an interrupt signaler for communicating an event based at least in part on the information stored in the register of the SBC.

6. The apparatus according to claim 1, wherein the system base chip is equipped with a 10 SPE PHY transceiver.

7. A register that stores the output signal, The output path of the circuit from the register to the pad, Equipped with, The apparatus according to claim 1, wherein the pad is supplied by a first supply voltage that provides the first voltage level, and the output path of the circuit is supplied by a second supply voltage that provides the second voltage level.

8. It is a device, A microcontroller that implements a 10-SPE physical layer (PHY) controller, A system base chip that implements the aforementioned 10SPE PHY transceiver, Equipped with, The system-based chip is a device that receives and processes high-voltage external signals and interfaces the high-voltage external signals with the low-voltage region of a microcontroller (MCU).

9. The aforementioned high-voltage external signal includes external wake signaling, and the system base chip is The apparatus according to claim 8, for generating an internal wake signaling representing the external wake signaling, a voltage range of the high-voltage external signal defined between the ground voltage level and a first voltage level, and a voltage range of the internal wake signaling defined between the ground voltage and a second voltage level lower than the first voltage level.

10. The apparatus according to claim 9, wherein the system-based chip communicates wake events to the MCU, at least in part, based on the internal wake signaling.

11. The apparatus according to claim 9, wherein the system base chip provides the internal wake signaling to the MCU.

12. It is a method, A system-based chip implementing a 10-SPE PHY transceiver includes the step of receiving a signal, The system base chip includes the step of changing the signaling from a first voltage level incompatible with the voltage range of a microcontroller (MCU) on which the controller of the 10SPE PHY is mounted to a second voltage level compatible with the voltage range of the MCU, The steps include communicating the modified signaling to the MCU, Methods that include...

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