Address space management in the register bank of the system basis chip

Abstract

The embodiment includes managing the address space within the register bank of a system basis chip. The device includes a bus slave and a system basis chip. The system basis chip includes a register bank, an access controller for restricting the reach of the bus slave to a selected set of addresses in the register bank, and an address space manager for setting the selected set of addresses in the register bank.

Description

Technical Field

[0001] (Claim of Priority) This application claims the benefit of the filing date of International Application PCT / CN2023 / 107648, filed on July 17, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] (Field of the Invention) Embodiments generally relate to a 10 SPE physical layer (PHY). Some embodiments generally relate to a system basis chip implementing a transceiver of a 10 SPE PHY and a microcontroller implementing a controller of the 10 SPE PHY. Some embodiments generally relate to a system basis chip that manages an address space within a register bank of the system basis chip.

Background Art

[0003] Integrated circuits (ICs) are utilized in various operating situations and may be subject to various stresses.

Brief Description of the Drawings

[0004] To facilitate easy identification of any particular element or action, the leading digit of the reference number refers to the figure number in which that element was first introduced. [Figure 1] A block diagram showing the system and architecture of a system basis chip (SBC) designed to manage register access and expand the address space of a 10BASE-T1S transceiver, according to one or more embodiments. [Figure 2] A block diagram of a system including a system basis chip and a microcontroller, according to one or more embodiments. [Figure 3] A schematic diagram showing an exemplary format of an MDIO bit stream and an I2C bit stream, respectively received by an MDIO slave having address space management and an I2C slave, according to one or more embodiments. [Figure 4] This is a schematic diagram illustrating an example of a special-purpose register, based on one or more embodiments. [Figure 5A] This is a schematic diagram showing a register bank or a portion thereof in one or more embodiments in an exemplary environment. [Figure 5B] This is a schematic diagram further illustrating the structure of a register bank in an exemplary environment. [Figure 6] This document illustrates an exemplary process for demonstrating the behavior of access control logic to enable changes to address assignments within a system basis chip or its address controller, using one or more embodiments. [Figure 7] This flowchart illustrates the process of adding non-native register addresses to the address assignment of an MDIO slave and expanding its accessible register space, using one or more embodiments. [Figure 8] This flowchart illustrates the process of approving an address access request to ensure that the address access request falls within an authorized address allocation, as demonstrated by one or more embodiments. [Figure 9] One or more embodiments illustrate one aspect of the subject matter. [Figure 10] In some embodiments, these are block diagrams of circuits that may be used to implement various functions, operations, actions, processes, or methods disclosed herein. [Modes for carrying out the invention]

[0005] The following detailed description refers to the accompanying drawings, which form part of this specification and illustrate specific examples of embodiments in which the disclosure may be carried out. These embodiments are described in sufficient detail to enable those skilled in the art to carry out the disclosure. However, other embodiments may be utilized, and the structure, materials, and processes may be modified without departing from the scope of the disclosure.

[0006] The illustrative diagrams presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but are merely conceptual representations used to illustrate the embodiments discussed herein. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the reader's convenience. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristics.

[0007] The following description may include examples to help enable those skilled in the art to carry out the disclosed examples. The use of the terms “exemplary,” “as an example,” and “for example” means that the relevant description is illustrative, and the scope of this disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of this disclosure to specified components, steps, features, functions, etc.

[0008] It will be readily apparent that the components of the embodiments described herein and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following descriptions of various embodiments are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Various aspects of the embodiments may be presented in the drawings, which are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations illustrated and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Conversely, the specific implementations illustrated and described are merely illustrative and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic between various blocks are examples of specific implementations. It will be readily apparent to those skilled in the art that this disclosure can be implemented by numerous other partitioning solutions. For the most part, details such as timing considerations are omitted, as such details are not necessary for a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. Some drawings may illustrate a signal as a single signal for clarity in presentation and explanation. Those skilled in the art will understand that a signal can represent a bus of signals, which can have various bit widths, and that this disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, dedicated processors, digital signal processors (DSPs), integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, separate gate or transistor logic, separate hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration. A general-purpose computer, including a processor, is considered a dedicated computer while it is executing computing instructions (e.g., software code, but not limited to those) related to the embodiments discussed herein.

[0012] Examples may be described in relation to processes depicted as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe actions as sequential processes, many of these actions can also occur in different sequences, concurrently, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes may, but are not limited to, methods, threads, functions, procedures, subroutines, or subprograms. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or codes in a computer-readable medium. Computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of computer programs from one location to another.

[0013] Any reference to elements in this specification using notations such as "first," "second," etc., does not limit the number or order of those elements unless such limitation is expressly stated. Rather, these notations may be used in this specification as a convenient way to distinguish two or more elements or examples of elements. Thus, references to the first and second elements do not mean that only two elements may be used, or that in any manner the first element must precede the second element. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term “substantially” when referring to a given parameter, characteristic, or condition means and includes the extent to which a person skilled in the art would understand that the given parameter, characteristic, or condition is within a small variation, such as within an acceptable manufacturing tolerance. For example, depending on the particular parameter, characteristic, or condition to be substantially satisfied, the parameter, characteristic, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, any relative terms such as “over,” “under,” “on,” “underlying,” “upper,” and “lower” are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and do not imply, or rely on, any particular preference, orientation, or order, unless the context clearly indicates otherwise.

[0016] In this description, the term “combined” and its derivatives may be used to indicate that two elements cooperate with or interact with each other. When one element is described as “combined” with another, those elements may be in direct physical or electrical contact, but there may be an intervening element or layer between them. In contrast, when one element is described as “directly combined” with another, there is no intervening element or layer. The term “connected” may be used interchangeably with the term “combined” herein and has the same meaning unless otherwise expressly indicated or the context indicates to those skilled in the art in another way.

[0017] As used herein, the terms “assert,” “de-assert,” and their derivatives, used in reference to a pin, mean to assert or de-assert a signal associated with a pin (for example, a signal specifically assigned to a pin, or a signal to which a pin is specifically assigned), respectively.

[0018] A system basis chip (SBC) is an integrated circuit (IC) that combines multiple functions for the operation of an electronic system. The SBC typically integrates various different functions into a single chip, and non-limiting examples include, but are not limited to, power management functions such as voltage regulators, power switches, or protection circuits for managing the power of the system, communication interfaces such as, but not limited to, CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Inter-Integrated Circuit), functions for controlling and coordinating tasks by an embedded system such as, but not limited to, a state machine or a microprocessor, analog functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning circuits, and diagnostic and safety functions such as, but not limited to, monitoring and reporting of voltage levels, temperature, or fault states.

[0019] SBCs are found in a variety of operating situations, including automotive and industrial applications. Non-limiting examples of automotive applications for SBCs are those in a 10SPE (i.e., 10 Mbps single-pair Ethernet) network (also referred to as a "10BASE-T1S network"). 10SPE is a network technology defined in Articles 147 and 148 of IEEE 802.3. 10SPE can be used to provide deterministic transmission without collisions in a multi-drop network.

[0020] In some cases, by way of non-limiting example, the transceiver (xcvr) and controller of a 10SPE physical layer device (PHY) may be placed on different dies, and thus, the dies are subject to different processing conditions. Such an architecture is referred to herein as a "split PHY" architecture. The digital blocks of the PHY controller that are vulnerable to damage during high voltage temperature processes are placed on a first die that does not undergo the high voltage temperature process. The analog and digital blocks of the PHY transceiver that are either less vulnerable to damage during high voltage temperature processes or require such high voltage temperature processes are placed on a second die that undergoes such high voltage temperature processes.

[0021] The 10SPE transceiver interface standard currently under specification development by the Open Alliance Technical Committee 14 (hereinafter, "TC14") defines a hardware interface (specifically, a 3-pin hardware interface) for communication between the PHY transceiver and the PHY controller in the case of a split PHY architecture.

[0022] In 10SPE, a microcontroller (MCU) implements the PHY controller function and an SBC implements the PHY transceiver function. In 10SPE, the non-transceiver responsibilities of the SBC include regulated power supply, observability / control of the high voltage domain, and a functional safety mechanism for the MCU to reach a safe state. Thus, in addition to the transceiver function, the SBC implements functions of an electronic system, including but not limited to, for example, power management, watchdog circuits, monitors, general purpose input / output (GPIO), etc.

[0023] TC14 describes the low-power (sleep-wake) behavior of PHY transceivers for partial networking. Partial networking refers to a characteristic feature that enables selective power management and communication capabilities within a network. Partial networking allows specific network nodes or devices to enter a low-power or sleep state while still maintaining basic communication functions. In Ethernet networks, partial networking is used to optimize power consumption, particularly in automotive or industrial applications. Enabling selected devices to enter a low-power or sleep state can reduce overall power consumption, extend battery life, or improve energy efficiency, but is not limited to these possibilities.

[0024] The System Basis Chip (SBC) incorporates a 10BASE-T1S transceiver that requires an expanded register space due to the limited number of vendor-specific registers defined by the Open Alliance (OA) specification. The OA specification allows access to 32 registers via the Management Data Input / Output (MDIO) interface, of which only 15 are available for vendor-specific use. Occasionally, as a non-exclusive example, it may be desirable to have additional registers for tuning, testing, electronic fusion, and debugging, among other things.

[0025] One or more embodiments generally relate to managing the address space within the register bank of an SBC implementing a 10BASE-T1S transceiver. An SBC implementing a 10BASE-T1S transceiver can extend the register space associated with the 10BASE-T1S transceiver beyond the 32 registers defined by the OA specification and manage indirect access to other register spaces within the SBC.

[0026] In one or more embodiments, the SBC utilizes at least two of the 15 vendor-specific registers to function as control / address and data registers, enabling access to an extended register space beyond the 32 registers specified in the OA specification. One of the at least two registers is used as a control register and includes a field for read / write control and the address of an extended configuration register. The other of the at least two registers is used as a data register and holds data to be written to or read from an extended register specified by the control register.

[0027] In one or more embodiments, the SBC includes a bank of registers divided into at least two groups: a first group of registers accessible by an MDIO driver and a second, distinct group of registers accessible by an I2C driver (e.g., logically divided, physically divided, or both). The MDIO driver handles access to registers within a transceiver-specific address space, while the I2C driver manages access to registers for non-transceiver functions, such as power supply and watchdog functions, using a separate register space (e.g., a register space distinct from the transceiver-specific address space).

[0028] In some cases, the firmware for the MDIO driver and the I2C driver may each have a list of resources, including register addresses, that the firmware can utilize. However, in some cases, the firmware is customizable and therefore vulnerable to unauthorized access. In one or more embodiments, the SBC includes hardware lockout to ensure that cross-access between the MDIO-accessible register space and the I2C-accessible register space is prevented during normal operation in order to maintain security and integrity. Attempting to access an incorrect resource triggers a malfunction, and the hardware in the SBC prevents that access from being completed. In this way, SBC-specific registers are not accessible via the MDIO driver, and transceiver-specific registers are not accessible via I2C.

[0029] In one or more embodiments, hardware lockout may be temporarily disabled, in non-exclusive examples, by utilizing a specific set or sequence of cryptographic keys ("access keys"). In non-exclusive examples, it may be desirable to disable hardware lockout for debugging, testing, or programming purposes, but these are not limited to these. The access keys turn off hardware lockout and thus unlock the possibility of cross-accessing the registers by the MDIO driver and the I2C driver.

[0030] Figure 1 is a block diagram showing System 100 and its architecture, representing one or more embodiments of a system basis chip (SBC) designed to manage register access and extend the address space of a 10BASE-T1S transceiver.

[0031] System 100 includes a system basis chip (SBC) 102 and one or more bus slaves 112. The system basis chip 102 includes an address space manager 104, an access controller 106, and a register bank 110. The access controller 106 includes access control logic 108.

[0032] The bus slave 112 is a device that operates as a peripheral or subordinate device of the bus master in a computer or electronic communication system.

[0033] In a bus-based architecture, electronic communication systems, data, and control signals can be transferred using the bus between each of the bus slaves 112 (via bitstreams) and between the bus slaves 112 and the bus master. The bus slaves 112 monitor the bus (e.g., MDIO or I2C) to solicit addressed commands or requests from the bus slaves 112, process received data or instructions, provide requested information, or perform requested actions. One or more of the bus slaves 112 may be implemented in a system basis chip (SBC) 102 or another device, as required.

[0034] One or more of the bus slaves 112 may be MDIO (Management Data Input / Output) bus slaves. Non-exclusive examples of MDIO bus slaves include physical layer (PHY) transceivers, Ethernet switches (e.g., Gigabit Ethernet switches, but not limited to these), network interface cards (NICs), Ethernet media converters, and Ethernet routers and gateways.

[0035] One or more of the bus slaves 112 may be I2C (Inter-Chip) bus slaves. Non-exclusive examples of I2C bus slaves include sensors, memory chips, or peripheral devices. One or more of the bus slaves 112 may be PCI (Peripheral Component Interconnect) bus systems. Non-exclusive examples of PCI bus slaves include network cards, sound cards, or peripheral devices. The bus slaves 112 monitor the bus for commands or requests addressed to them, process received data or instructions, provide requested information, or perform requested actions.

[0036] The address space manager 104 dynamically manages the accessibility of one or more buses to the register bank 110. The address space manager 104 operates by adding or removing addresses from a selection set of addresses in the register bank 110. The selection set of addresses corresponds to a selection of the address space in the register bank that buses (e.g., MDIO buses or I2C buses, but not limited to them) can interact with. In one or more embodiments, the address space manager 104 manages the accessibility of one or more buses to the register bank 110 in response to address space extension requests 114. An address space extension request 114 may identify a bus slave (e.g., one of the bus slaves 112, but not limited to them) and include an identification of the desired address space extension (e.g., the number of additional registers or addresses, or the amount of additional memory space, but not limited to them). For example, an address space extension request 114 requesting a transceiver-specific address space extension may identify a 10BASE-T1S transceiver and indicate the number of additional registers. In some cases, it may be desirable to reduce the extended address space of a bus slave (for example, to free up space for another bus slave, but not limited to that purpose), in which case the address space extension request 114 may include identifying the bus slave and identifying the desired address space to be reduced (for example, the number of registers or addresses to reduce, or the amount of memory space to reduce, but not limited to those). In one or more embodiments, the address space manager 104 does not reduce the address space below the bus native address space (for example, the minimum number of addresses or registers in the specification, but not limited to those).

[0037] In this way, the address space manager 104 effectively controls the range of registers in register bank 110 that the bus (or bus slave) is authorized to read or write to, providing flexibility in register bank resources and ensuring efficient utilization. As a non-limiting example, the address space manager 104, in response to an address space extension request 114, adjusts the range of accessible addresses and effectively controls which parts of the register bank the bus can interact with. This ensures flexibility and efficient utilization of register bank resources.

[0038] The access controller 106 restricts the reach of the bus to selected addresses in register bank 110 that correspond to a selected portion of the address space of register bank 110. The access controller 106 enforces an interaction boundary within register bank 110 for a given bus. This is done by blocking any attempt to interact with addresses outside the selected set of addresses in the address space of register bank. This ensures that a given bus can, in non-restrictive examples, only read from or write to an assigned address range, thereby protecting the integrity of other addresses in register bank.

[0039] The access control logic 108 ("access ctrl logic 108") of the access controller 106 functions as a security mechanism for expanding the address selection set of the address space of the register bank 110. In one or more embodiments, the access control logic 108 allows the address space manager 104 to add addresses to or remove addresses from the address selection set only if the correct set of access keys is provided. This key-based authorization process ensures the secure and controlled expansion of the accessible address space and prevents unauthorized or accidental modifications. Thus, for a particular address space or portion of the register bank, the access control logic 108 is aware of a predetermined sequence or set of digital keys that respectively permit any modifications to the address space. The access control logic 108 is also aware of the current state of each address space, including which addresses are currently part of the selection set.

[0040] Bus native addresses are addresses that can be directly accessed by each bus master (for example, addresses in bus slaves, such as the addresses of registers in register bank 110, but not limited to them). As used herein, the term “directly accessed” (and its derivatives) means that an address is accessed using a single access operation (for example, a single read or write operation, but not limited to them), and the term “directly accessible” means that an address is accessible using a single access operation. An unrestricted example of a directly accessed address is one where the address is placed on an address line, decoded in the register bank, and data is read from or written to a data line. This direct approach enables uniform firmware driver operation. In contrast to native addresses, extensible addresses are addresses that require multiple access operations to be accessed (for example, addresses in registers in register bank 110, but not limited to them). Extensible addresses are not directly accessible in a single step and involve additional stages, such as using a register as a staging register.

[0041] Figure 2 is a block diagram of system 200. System 200 includes a system basis chip 202 and a microcontroller 214. The system basis chip 202 includes an MDIO slave 204 with address space management, access control logic 206, an I2C slave 208, an access controller 210, and a register bank 212. The microcontroller 214 includes an MDIO master 216 and an I2C master 218.

[0042] The MDIO slave 204, which has address space management, is an MDIO bus slave and address space manager (for example, address space manager 104 in Figure 1). The access control logic 206 is a non-limiting example of the access control logic 108 in Figure 1. The access controller 210 is a non-limiting example of the access controller 106 in Figure 1. The register bank 212 is a non-limiting example of the register bank 110 in Figure 1.

[0043] The system basis chip 202 integrates both the register bank 212 and the PHY transceiver (without depicting xcvr logic or a finite state machine) and provides a flexible address space allocation mechanism. Initially, a separate portion of the address space of register bank 212 is dedicated to the MDIO bus / PHY transceiver, and another separate portion of the address space of register bank 212 is dedicated to the I2C slave 208. The system basis chip 202 provides dynamic address space management (including, but not limited to, adding or removing address spaces within a selected address space set).

[0044] This makes part or all of the address space allocated to the I2C slave 208 (referred to as the "extended register address" or "ext reg addr" in Figure 2), which may include part or all of the SBC's address space for non-PHY transceiver-specific functions, accessible to the MDIO slave, thereby extending the range of addresses to which the MDIO can interact. The allocation process is controlled here by an address space manager integrated with the MDIO slave (e.g., address space manager 104, but not limited to these), but may be a separate logical block (e.g., a logical block not integrated with the MDIO slave, but not limited to these). The allocation process is coordinated by access control logic 206, which thereby maintains secure and controlled access to the resources of register bank 212 for the purpose of expanding or shrinking the address space. Access control logic 206 ensures secure and controlled access to the register bank by verifying the provided key and approving the address space change. A signal line for an indication of unlocking (UNLOCK) is shown between the access control logic 206 and the access controller 210. The unlock signal is used to control changes in address allocation. In one or more embodiments, as a non-limiting example, address assignments may be maintained in the address domain table or extended domain table of the MDIO slave. Access control logic 206 requires the correct set of keys to generate an unlock signal. Once authorized, the unlock signal allows an MDIO slave 204 (part of the MDIO slaves) having address space management to modify the address space, such as adding or removing addresses. In various embodiments, a first value of the unlock signal may enable a change in address assignments, and a second different value of the unlock signal (a value different from the first value) may disable a change to address assignments.

[0045] In non-exclusive embodiments, adjusting address assignments may include updating control registers or tables (e.g., extended register control & data (shown as "EXTN CTRL & DATA" in Figure 1), but not limited to these) to include new addresses within MDIO assignments. Adjusting address assignments may also include updating control registers or tables to set registers as staging registers to access one or more extended registers, as described below. Adjusting address assignments may also include updating control registers or tables (optionally including control registers or tables) to remove addresses from I2C assignments.

[0046] The MDIO slave 204, which has address space management, is responsible for managing the register space accessible via the MDIO interface. As mentioned above, this may include transceiver-specific address spaces. Address (addr) and data (data) signal lines are shown between the MDIO slave 204 with address space management and the access controller 210, and between the I2C slave 208 and the access controller 210. The signal on the address line specifies the register address in register bank 212 that is being accessed (read from or written to), and the signal on the data line carries the actual data to be written to or read from the specified register address. In the intended example, the MDIO slave 204 or I2C slave 208 with address space management receives address information from the MDIO master 216 or I2C master 218 and uses this signal to identify a specific register in register bank 110.

[0047] This structure provides a high degree of flexibility and efficiency in managing the register bank address space, allowing it to adapt to changing requirements of the system basis chip operation or the MDIO slave operation.

[0048] Register bank 212 includes several purpose-specific registers, namely command registers and lock control registers, the bits of which are used to control access to and allocation of portions of the address space of register bank 212. This setup enables flexible, controlled, and secure access to the registers within the bank and flexible, controlled, and secure operation of those registers, particularly in the case of extended or indirect access.

[0049] Figure 3 is a schematic diagram showing exemplary formats of MDIO bitstream 300 and I2C bitstream 302 received by MDIO slave 204 and I2C slave 208, respectively, which have address space management, in one or more embodiments.

[0050] MDIO and I2C each have a data line and one clock line (the clock line is not shown). Since they each have one data line, data is received as a bitstream in the format of MDIO bitstream 300 and I2C bitstream 302.

[0051] Referring to the MDIO bitstream 300, bits #1 through #8 are preamble bits, i.e., the sequence that prepares the MDIO slave for incoming data. Bit #9 is the start sequence that signals the beginning of the MDIO frame. Bits #11 and #12 specify the type of operation, such as read or write. The next four bits (bits #13 through #16) indicate the physical address that identifies which MDIO device the command is directed to. The next five bits (bits #17 through #21) are the register addresses within the target device. The remaining bits are the data payload for the operation.

[0052] Referring to I2C bitstream 302, the I2C bitstream begins with a start bit indicating the start of communication. Following the start bit is a 7-bit address field specifying the I2C slave device address. The next bit indicates the operation type (read or write). The following bit is an acknowledgment bit sent by the I2C slave to confirm receipt of the address. The next bit contains the data payload to be transferred, which is either read from or written to the I2C slave device. The last bit of I2C bitstream 302 is a stop bit indicating the end of communication.

[0053] Both the MDIO driver and the I2C driver utilize bitstreams for data transfer, ensuring synchronized communication via a single data line and an accompanying clock line (not shown). The MDIO bitstream 300 and the I2C bitstream 302, their respective formats and bit values, allow access to and management of the register space within the SBC, enabling precise control and data transfer to and from MDIO and I2C slaves.

[0054] Figure 4 is a schematic diagram showing examples of the special-purpose register 400 in one or more embodiments.

[0055] Figure 4 shows the structure and function of an exemplary special-purpose register 400 within the SBC, including control registers, extended control registers, and data staging registers. These registers are used to manage the extended address space and ensure secure and flexible access to the register bank's resources. The control registers handle key-based security mechanisms, the extended control registers manage read / write operations for extended addresses, and the data staging registers facilitate indirect data access.

[0056] Control Register 408: This register contains three key-related fields: a first key bit, a second key bit, and an enable bit. The first key bit indicates whether the first key (key 1) has been received. This is reset (or cleared) upon any write to a specific register named SFTR, except when writing to key 2. The second key bit indicates the reception of the second key (key 2). This enables any write access to the SFTR register when both key 1 and key 2 are "1". This bit is also reset when writing to another specific register, SFTRm. The enable bit functions as a control signal for firmware (FW) access to all control state register (CSR) bits in the indirect domain. When set to "1", FW access is enabled; when set to "0", FW access is disabled. Before this bit can be enabled or disabled, a specific key value must be written to the SFTR register: a non-restrictive example is SFTR key 1 (16'h4149) followed by SFTR key 2 (16'h4155). SFTR and SFTRm are not shown in the diagram.

[0057] Extended Control Register 402: This register contains several fields, including an extended address field, read control, and write control. The extended register address field is used to hold addresses that are part of a selected portion of the register bank's address space. The read control functions as a control signal. When this bit is set to "1", data stored in extended register 406, referenced by the extended register address stored in extended control register 402, can be read from data staging register 404. The read control functions similarly. When this bit is set to "1", data held in data staging register 404 is written to extended register 406 associated with the current extended address.

[0058] The data staging register 404 may be a memory-mapped register. In one or more embodiments, the system basis chip 202 or peripheral devices (not shown) map specific addresses in the register bank 212 (the extended address space of the register bank 212) to various registers, enabling direct access to these registers via standard memory read and write operations. As a non-limiting example, an address decoding mechanism is provided that maps unique addresses to specific registers in the register bank 212.

[0059] The “reserved” field is depicted to indicate that not all fields within a special-purpose register are required to be used solely for address space allocation and access control as discussed herein, but may be used for that purpose.

[0060] Figure 5A is a schematic diagram showing a register bank 502 or a portion thereof in one or more embodiments in an exemplary environment.

[0061] The register bank 502 includes an allocated MDIO native address space 512 and an expandable address 514. The MDIO native address space 512 includes various key register addresses for managing MDIO operation and secure access. In this particular embodiment, the MDIO native address space 512 includes the MDIO register address 504, the lock control register address 506, the expansion control register address 508, and the data staging register address 510.

[0062] Register bank 502 is the primary storage area for configuration and operation registers within the system basis chip (SBC). The MDIO native address space 512 is the portion of the register bank dedicated to addresses natively accessible via the MDIO interface. MDIO register addresses 504 are standard addresses used for typical MDIO operations such as configuration and status monitoring. Lock control register address 506 is used to control access permissions and to lock or unlock specific portions of the register bank. Extension control register address 508 manages the extension of the address space, including control of read and write operations to extended addresses. Data staging register address 510 acts as a medium for data transfer, staging data to be read from or written to the extended register space. Extensible addresses 514 are initially outside the native MDIO address space but can be dynamically allocated to the native MDIO address space.

[0063] After the address allocation process, the extended data register address 516 logically becomes part of the MDIO native address space 512 and is accessible via the data staging register address 510. The extended control register address 508 and the lock control register address 506 enable the management of access to and secure modification of the register bank's address space. The data staging register address 510 facilitates indirect access to extended addresses and ensures seamless data transfer between the extended address space and the native address space.

[0064] In particular, the extensible address 514 includes the extended data register address 516, and since the extended data register address 516 is accessible via the data staging register address 510, it is logically part of the MDIO native address space 512 after the address allocation process.

[0065] Figure 5B is a schematic diagram further illustrating the structure of register bank 502 in an exemplary environment. Figure 5B highlights that, once the expandable address 514 is allocated and integrated into the MDIO native address space 512, it becomes accessible as part of the entire register space managed by the system basis chip (SBC). Similar parts are denoted in the same way as in the description of Figure 5B. In particular, the expandable address 514, initially outside the native address space, can be reallocated to extend the MDIO addressable space. Furthermore, after reallocation, the extended data register addresses 516 are integrated into the MDIO native address space 512 and become accessible via the data staging register address 510.

[0066] Figure 6 shows an exemplary process 600 to represent the behavior of access control logic for enabling changes to address assignments within a system basis chip or its address controller, in one or more embodiments. While the exemplary process 600 depicts a specific sequence of operations, the sequence may be modified without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in different sequences that do not significantly affect the functionality of process 600. In other embodiments, various components of an exemplary device or system implementing process 600 may perform functions substantially simultaneously or in specific sequences. One or more operations of process 600 may, in non-limiting examples, be performed by access control logic 108, access control logic 206, access controller 106, access controller 210, system basis chip (SBC) 102, system basis chip 202, system 100, or system 200.

[0067] When hardware lockout is enabled, the system starts process 600 to prevent unauthorized changes to address assignments.

[0068] According to one or more embodiments, process 600 may include receiving keys in the unlock logic in operation 602. The SBC receives a set of keys in the unlock logic. These keys, if authorized, are for authorizing changes to the requester's address space.

[0069] In one or more embodiments, process 600 may include, in operation 604, acknowledging the received key. In one or more embodiments, the unlock logic acknowledging the received key to ensure that the key matches the expected value. Only if the key is correct and acknowledging it can process 600 proceed to activate the change.

[0070] If a key is not authorized (for example, if authorization fails, but not limited to these cases), hardware lockout remains in effect, and no changes can be made to address assignments. The SBC's address controller continues to prevent unauthorized changes and maintains the integrity and security of the register bank's address space. Optionally, in one or more embodiments, there may be an error handling mechanism to log failed attempts or trigger security alerts. This ensures that any unauthorized attempts to modify the address space are recorded and dealt with appropriately.

[0071] According to one or more embodiments, process 600 may include, in operation 606, enabling a change in address assignment in the address controller of the system basis chip. Upon successful key authorization, the unlock logic signals the address controller. The address controller is then able to change the address assignment, enabling a secure change to the address space in the register bank.

[0072] In one or more embodiments, the key may be received over one or more cycles as needed. In a particular non-limiting example, the unlock logic may proceed through two verification states, namely lock 1 and lock 2. When key 1 is written, the unlock logic transitions from lock 1 to lock 2, and when key 2 is written, it transitions from lock 2 to unlock. If the key is not written or is not written within a predetermined number of clock cycles, the finite state machine of the unlock logic transitions from lock 2 to lock 1. Process 600 may optionally perform this behavior each time a read or write is initiated, or it may perform this behavior once and then remain in the unlocked state until a reset is received.

[0073] Figure 7 is a flowchart illustrating a process in one or more embodiments for adding non-native register addresses to the address assignment of an MDIO slave and extending its accessible register space. The exemplary process 700 describes a particular sequence of operations, but the sequence may be modified without departing from the scope of the disclosure. For example, some of the operations described may be performed in parallel or in different sequences that do not significantly affect the functionality of process 700. In other embodiments, various components of an exemplary device or system implementing process 700 may perform functions substantially simultaneously or in a particular sequence. One or more operations of process 700 may, in non-limiting examples, be performed by access control logic 108, access control logic 206, address space manager 104, MDIO slave 204 with address space management, access controller 106, access controller 210, system basis chip (SBC) 102, system basis chip 202, system 100, or system 200.

[0074] According to one or more embodiments, process 700 may include in operation 702 selecting N non-native register addresses to be added to the MDIO slave address assignment. Process 700 selects a set of N non-native register addresses that need to be added to the MDIO slave address assignment in operation 702, where N is an integer greater than or equal to 1.

[0075] According to one or more embodiments, process 700 may include in operation 704 the request for the right to change the address assignment of the MDIO slave. A request is made to obtain the necessary rights to change the address assignment. This step ensures that only permitted changes are made to the address space of the MDIO slave.

[0076] In some cases, requests to change address assignments may be rejected. If a request to change address assignments is rejected, no changes are made to the address space. The integrity and security of the existing address space are preserved, and unauthorized or unintended changes are prevented. Optionally, an error handling mechanism may log failed attempts or trigger notifications. This ensures that any unauthorized or failed attempts to modify the address space are recorded and dealt with appropriately.

[0077] According to one or more embodiments, process 700 may, when granted the right to change the address assignment of an MDIO slave, include in operation 706 adding n non-native register addresses to the address assignment of the MDIO slave, so that the n non-native register addresses become the extended register addresses of the MDIO slave. When a request for the right to change the address assignment is granted, the selected non-native register addresses are added to the address assignment of the MDIO slave. These addresses become the extended register addresses of the MDIO slave, expanding its accessible register space.

[0078] In a non-limiting embodiment, changing an address assignment may include updating control registers or tables to include the new address within the MDIO assignment. Changing an address assignment may also include updating control registers or tables (optionally including control registers or tables) to remove an address from the I2C assignment.

[0079] Figure 8 is a flowchart illustrating a process 800 that approves an address access request to ensure that the address access request falls within an authorized address allocation, in one or more embodiments. While the exemplary process 800 depicts a specific sequence of operations, the sequence may be modified without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in different sequences that do not significantly affect the functionality of process 800. In other embodiments, various components of an exemplary device or system implementing process 800 may perform functions substantially simultaneously or in specific sequences. One or more operations of process 800 may, in non-limiting examples, be performed by access control logic 108, access control logic 206, address space manager 104, MDIO slave 204 with address space management, access controller 106, access controller 210, system basis chip (SBC) 102, system basis chip 202, system 100, or system 200.

[0080] According to some embodiments, the method includes, in operation 802, receiving the requested address at the address controller of the system basis chip. The address controller of the SBC receives the request, which includes the address the requester is trying to access.

[0081] According to some embodiments, the method includes determining in operation 804 whether the requested address is within the requester's address allocation. The address controller checks whether the requested address is within the address allocation assigned to the requester. This step ensures that only authorized addresses can be accessed.

[0082] According to some embodiments, the method includes blocking access in operation 806 if it is determined that the requested address is not within the requester's address allocation. Access is blocked if the requested address is not within the permitted address allocation. This prevents unauthorized access to protected registers.

[0083] According to some embodiments, the method includes blocking access in operation 808 if it is determined that the requested address is within the requester's address allocation. If the requested address is within an authorized address allocation, access is granted. The requester can then read from or write to the specified address as permitted.

[0084] Figure 9 is a block diagram showing a system that is a specific, non-exclusive example of system 200.

[0085] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 10 shows non-limiting embodiments of implementations of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein can be performed by hardware capable of executing the functional elements.

[0086] Figure 10 is a block diagram of a circuit 1000 that may be used in some embodiments to implement various functions, operations, actions, processes, or methods disclosed herein. The circuit 1000 includes one or more processors 1002 (sometimes referred to herein as “processor 1002”) operably coupled to one or more data storage devices 1004 (sometimes referred to herein as “storage device 1004”). The storage device 1004 includes machine-executable code 1006 stored in the storage device 1004, and the processor 1002 includes logic circuits 1008. The machine-executable code 1006 information includes information describing functional elements that may be implemented (e.g., performed) by the logic circuits 1008. The logic circuits 1008 are adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1006. When the circuit 1000 executes the functional elements described by the machine-executable code 1006, it should be considered dedicated hardware for executing the functional elements disclosed herein. In some embodiments, the processor 1002 may execute the functional elements described by the machine-executable code 1006 sequentially, simultaneously (for example, on one or more different hardware platforms), or in one or more parallel processing streams.

[0087] When implemented by the logic circuit 1008 of the processor 1002, the machine-executable code 1006 adapts the processor 1002 to perform the operations of the embodiments disclosed herein. In a non-limiting embodiment, the machine-executable code 1006 may adapt the processor 1002 to perform some or all of the operations of a process for managing the address space in the register bank of the system basis chip.

[0088] In addition, as a non-limiting embodiment, the machine-executable code 1006 may adapt the processor 1002 to perform some or all of the features, functions, or operations disclosed herein in order to manage or utilize the address space in the register bank of the system basis chip.

[0089] The processor 1002 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, separate gate or transistor logic, separate hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer while the general-purpose computer is executing functional elements corresponding to machine-executable code 1006 (e.g., software code, firmware code, hardware description) related to the embodiments discussed herein. Note that the general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor 1002 may include any conventional processor, controller, microcontroller, or state machine. The processor 1002 may also be implemented as a combination of computing devices such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration.

[0090] In some embodiments, the storage device 1004 includes volatile data storage devices (e.g., random-access memory (RAM), but not limited to them) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited to them). In some embodiments, the processor 1002 and the storage device 1004 may be implemented in a single device (e.g., semiconductor device product, system on chip (SOC), but not limited to them). In some embodiments, the processor 1002 and the storage device 1004 may be implemented in separate devices.

[0091] In some embodiments, the machine-executable code 1006 may include computer-readable instructions (e.g., software code, firmware code). In a non-limiting embodiment, the computer-readable instructions may be stored in the memory device 1004, directly accessed by the processor 1002, and executed by the processor 1002 using at least the logic circuit 1008. Also in a non-limiting embodiment, the computer-readable instructions may be stored in the memory device 1004, transferred to a memory device (not shown) for execution, and executed by the processor 1002 using at least the logic circuit 1008. Thus, in some embodiments, the logic circuit 1008 includes an electrically configurable logic circuit 1008.

[0092] In some embodiments, machine-executable code 1006 may describe hardware (e.g., circuits) implemented within logic circuits 1008 to execute functional elements. This hardware may be described at any of various levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. In non-limiting embodiments, Verilog, SystemVerilog, or very large-scale integration (VLSI) hardware description languages ​​(VHDL) may be used.

[0093] An HDL description can be translated into a description at any of several other levels of abstraction, as desired. In a non-limiting embodiment, a high-level description can be translated into a logic-level description such as a register-transfer language (RTL), gate-level (GL) description, layout-level description, or mask-level description. In a non-limiting embodiment, the microoperations performed by the hardware logic circuits of logic circuit 1008 (e.g., gates, flip-flops, registers, etc.) may be described in RTL and then translated into a GL description by a synthesis tool, the GL description may be translated into a layout-level description by a placement and routing tool, this layout-level description corresponding to the physical layout of an integrated circuit of programmable logic devices, separate gate or transistor logic, separate hardware components, or combinations thereof. Thus, in some embodiments, the machine-executable code 1006 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0094] In embodiments where the machine-executable code 1006 includes a hardware description (at any level of abstraction), the system (including a storage device 1004, not shown) implements the hardware description described by the machine-executable code 1006. In non-limiting embodiments, the processor 1002 may include a programmable logic device (e.g., an FPGA or PLC), and the logic circuit 1008 may be electrically controlled to implement circuits corresponding to the hardware description in the logic circuit 1008. Also in non-limiting embodiments, the logic circuit 1008 may include hardwired logic manufactured by a manufacturing system (including a storage device 1004, not shown) according to the hardware description of the machine-executable code 1006.

[0095] Regardless of whether the machine-executable code 1006 includes computer-readable instructions or hardware descriptions, the logic circuit 1008 is adapted to execute the functional elements described by the machine-executable code 1006 when implementing the functional elements of the machine-executable code 1006. Note that while hardware descriptions do not have to directly describe functional elements, they indirectly describe the functional elements that the hardware elements described by them can execute.

[0096] Where used in this disclosure, the terms “module” or “component” may refer to a specific hardware implementation for performing actions of a module or component and / or software object or software routine that are stored in and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing devices, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored in and / or executed in general-purpose hardware), specific hardware implementations, or combinations of software and specific hardware implementations, are also possible and intended.

[0097] When used in this disclosure, the term “combination” referring to multiple elements may include any combination of all elements or any various different subcombinations of some elements. For example, the phrase “A, B, C, D, or any combination thereof” may refer to A, B, C, or D; any combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or any one of C and D.

[0098] The terms used in this disclosure, and in particular in the appended claims (e.g., the text of the appended claims, but not limited to them), are generally intended to be “open” terms (for example, “including” should be interpreted as “including, but not limited to,” “having” should be interpreted as “at least having,” and “includes” should be interpreted as “including, but not limited to,” but not limited to). As used herein, “each” means “part or whole.” As used herein, “each and all” means “whole.”

[0099] Additionally, if a specific number of introduced claims is intended, such intention will be explicitly enumerated in the claims; if there is no such enumeration, such intention does not exist. For example, to aid understanding, the attached claims below may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim enumeration. However, the use of such phrases should not be interpreted as meaning that the introduction of a claim description with the indefinite article “a” or “an” means that any particular claim containing such introduced claim description is limited to only one embodiment containing such description (for example, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more,” but not as limiting). The same applies to the use of definite articles used to introduce a claim enumeration.

[0100] In addition, even if a specific number is explicitly stated in the introduced claims, a person skilled in the art will recognize that such a statement should be interpreted as meaning at least the number stated (for example, the explicit statement “two statements” without other modifiers means, but not limited to, at least two statements or two or more statements). Furthermore, where conventions similar to “but not limited to, at least one of A, B, and C” or “but not limited to, one or more of A, B, and C” are used, such structures are generally intended to include, but not limited to, A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0101] Furthermore, any separating words or phrases that present two or more alternative terms should be understood, whether in the specification, claims, or drawings, as intended to include the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0102] Further non-limiting embodiments include:

[0103] Example 1: A device comprising a bus slave and a system basis chip, the system basis chip including a register bank, an access controller for restricting the reach of the bus slave to a selected set of addresses in the register bank, and an address space manager for setting the selected set of addresses in the register bank.

[0104] Example 2: The apparatus described in Example 1, where the address space manager modifies the addresses within the selected set of addresses for the register bank in order to set a select set of addresses for the register bank.

[0105] Example 3: The apparatus according to Example 1 or Example 2, wherein the address space manager adds an address to the register bank's address selection set or removes an address from the register bank's address selection set in order to change an address in the register bank's address selection set.

[0106] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the access controller allows the bus slave to interact with registers in the register bank that correspond to the selected set of addresses in the register bank, and blocks the bus slave to interact with registers in the register bank that correspond to addresses outside the selected set of addresses in the register bank.

[0107] Example 5: The bus slave is a management data input / output bus slave, as described in any one example from Examples 1 to 4.

[0108] Example 6: The register bank address selection set includes the native addresses of the bus slaves, as described in any one example from Examples 1 to 5.

[0109] Example 7: The access controller is the apparatus described in any one example of Examples 1 to 6, wherein the address space manager allows the address space manager to change the selected set of addresses in the register bank in response to a key-based authorization process, at least partially.

[0110] Example 8: The apparatus according to any one of Examples 1 to 7, further comprising additional bus slaves, wherein the access controller restricts the reach of the additional bus slaves to a further select set of addresses in the register bank.

[0111] Example 9: The apparatus according to any one example of Examples 1 to 8, wherein the registers of the register bank include a first key field, a second key field, and an enable field, the first key field indicating whether a first key has been received and approved, the second key field indicating whether a second key has been received and approved, and the enable field indicating whether the firmware has access to all the bits of the control state register of the system basis chip.

[0112] Example 10: The apparatus according to any one example of Examples 1 to 9, wherein the registers of the register bank include an extended address field, a read field, and a write field, the extended address field holds an extended address in a selected set of addresses of the register bank that is associated with the extended register, the read field indicates whether data can be read from the extended register via the data staging register, and the read field indicates whether data can be written to the extended register via the data staging register.

[0113] Example 11: The extended register is a memory-mapped register, as described in any one example from Examples 1 to 10.

[0114] Example 12: The apparatus according to any one example of Examples 1 to 11, wherein the address space manager, in response to the debug state of the system basis chip, sets a selection set of register bank addresses to include the entire address space of the register bank.

[0115] Example 13: An apparatus as described in any one of Examples 1 to 12, comprising a physical layer transceiver, wherein the access controller restricts the reach of the physical layer transceiver to a further selected set of addresses in the register bank, and the selected set of addresses is different from the further selected set of addresses.

[0116] Example 14: A method comprising: selecting N non-native register addresses to be added to the address assignment of an MDIO slave; requesting the right to change the address assignment of the MDIO slave; and, upon being granted the right to change the address assignment of the MDIO slave, adding N non-native register addresses to the address assignment of the MDIO slave so that the N non-native register addresses become the extended register addresses of the MDIO slave.

[0117] While this disclosure is described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, together with their legal equivalents. In addition, features of one embodiment can be combined with features of another disclosed embodiment, as conceived by the inventors, but still remain within the scope of this disclosure.

Claims

1. It is a device, Bus slave and It is a system basis chip, Register Bank, An access controller for restricting the reach of the bus slave to a select set of addresses in the register bank, and An address space manager that sets the selected set of addresses for the register bank, Includes a system basis chip, A device equipped with the following features.

2. In order to set the selected set of addresses of the register bank, the address space manager, The apparatus according to claim 1, which changes the address of the register bank address within the selection set.

3. In order to change the addresses in the selected set of addresses of the register bank, the address space manager, The apparatus according to claim 2, which adds an address to the selection set of addresses of the register bank or removes an address from the selection set of addresses of the register bank.

4. In order to restrict the reach of the bus slave to the selected set of addresses in the register bank, the access controller: This enables the bus slave to interact with the registers of the register bank that correspond to the selected set of addresses of the register bank, and The apparatus according to claim 2, which blocks the interaction of the bus slave with a register in the register bank that corresponds to an address outside the selected set of addresses of the register bank.

5. The apparatus according to claim 1, wherein the bus slave is a management data input / output bus slave.

6. The apparatus according to claim 1, wherein the selected set of addresses of the register bank includes the native address of the bus slave.

7. The aforementioned access controller The apparatus according to claim 1, wherein the address space manager allows the selected set of addresses in the register bank to change in response at least partially to a key-based authorization process.

8. Equipped with additional bus slaves, The aforementioned access controller The apparatus according to claim 1, wherein the reach of the further bus slaves is limited to a further selected set of addresses of the register bank.

9. The registers in the register bank include a first key field, a second key field, and an enable field. The first key field indicates whether the first key has been received and approved. The second key field indicates whether the second key has been received and approved. The apparatus according to claim 1, wherein the enable field indicates whether the firmware has access to all the bits of the control state register of the system basis chip.

10. The registers in the aforementioned register bank include an extended address field, a read field, and a write field. The extended address field holds the extended addresses in the selected set of addresses of the register bank, which are associated with the extended registers. The read field indicates whether data from the extended register can be read via the data staging register, and The apparatus according to claim 1, wherein the read field indicates whether or not data can be written to the extended register via the data staging register.

11. The apparatus according to claim 10, wherein the extended register is a memory-mapped register.

12. The apparatus according to claim 1, wherein the address space manager sets the selected set of addresses of the register bank to include the entire address space of the register bank in response to the debug state of the system basis chip.

13. Equipped with a physical layer transceiver, The aforementioned access controller The reach of the physical layer transceiver is limited to a further selection of addresses in the register bank, The apparatus according to claim 1, wherein the selected set of addresses is different from the further selected set of addresses.

14. It is a method, The steps include selecting N non-native register addresses to add to the MDIO slave address assignment, The steps include requesting the right to change the address assignment of the MDIO slave, A method comprising the step of, when the right to change the address assignment of the MDIO slave is granted, adding the N non-native register addresses to the address assignment of the MDIO slave so that the N non-native register addresses become the extended register addresses of the MDIO slave.

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