Free layer in magnetoresistive random access memory
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2024-07-04
- Publication Date
- 2026-08-03
Smart Images
Figure 2026525731000001_ABST
Abstract
Description
Technical Field
[0001] This application relates to the manufacture of semiconductor integrated circuits. More specifically, it relates to a method for forming a free layer in a magnetic resistive random access memory and a structure formed thereby.
Background Art
[0002] Semiconductor memory devices have experienced explosive growth in recent years and are fully recognized as playing an extremely important role in the management and organization of digital information that is constantly transforming our society. Magnetic resistive random access memory (MRAM) is one type of non-volatile memory (NVM). In particular, spin transfer torque MRAM (STT-MRAM) is known as embedded NVM (eNVM) and can retain the stored digital information without loss even when the power supply to the STT-MRAM device is stopped or accidentally disconnected. The use of STT-MRAM enables a memory device with higher density, lower power consumption, and reduced manufacturing costs compared to other types of MRAM devices.
[0003] MRAM technology, including STT-MRAM, is typically based on a magnetic tunnel junction (MTJ) stack that includes a tunnel barrier layer disposed or sandwiched between a reference layer and a free layer. Conventionally, the free layer is made of a cobalt-iron-boron alloy material. The properties of the cobalt-iron-boron alloy material have a significant impact on the performance of MRAM and are being studied for further improvement.
[0004] STT-MRAM is a type of advanced eNVM device that relies on an MTJ stack for device functionality. Cobalt-iron-boron (CoFeB) alloys are typically used as the material for forming the free layer in the MTJ stack. The inventors recognize that the properties of the CoFeB alloy, along with the free layer formation process using the CoFeB alloy, significantly influence the functionality of the MTJ stack and the overall operation of the STT-MRAM. For example, when forming an STT-MRAM, particularly an MTJ stack, the free layer needs to be deposited in an amorphous state on a crystalline tunnel barrier layer, which is usually magnesium oxide (MgO). To maintain the amorphous state during and after CoFeB deposition, the CoFeB alloy is typically deposited from a target containing about 20 to 40 at.% boron (B).
[0005] A high boron content enhances the wettability of the MgO surface, resulting in improved uniformity during the formation of the CoFeB free layer. On the other hand, a high boron content causes CoFe to remain in an amorphous state, reducing the magnetoresistance (TMR) of the free layer thus formed, which is undesirable for the performance of the MTJ. To absorb the excess amount of boron, a free-layer structure has been introduced in which a refractory metal layer is placed between the first and second CoFeB layers. The refractory metal layer is usually formed thin enough not to cause magnetic separation of the first and second CoFeB layers, and thus does not lead to malfunction of the MTJ device. However, a thin refractory metal layer is not sufficient to absorb the excess boron in the free layer. [Overview of the project]
[0006] Embodiments of the present invention provide a magnetoresistive random access memory (MRAM). The MRAM comprises a reference layer; a tunnel barrier layer of magnesium oxide (MgO); and a free layer, the free layer having a first cobalt-iron-boron (CoFeB) layer on the tunnel barrier layer; a spacer layer on the first CoFeB layer; a second CoFeB layer on the spacer layer; and a capping layer of MgO on the second CoFeB layer. Furthermore, the first CoFeB layer and the second CoFeB layer are substantially boron (B) depleted and each comprises a first region adjacent to the tunnel barrier layer and the capping layer and a second region adjacent to the spacer layer, the first region of the first CoFeB layer and the second CoFeB layer comprises crystalline cobalt iron (CoFe), and the second region of the first CoFeB layer and the second CoFeB layer comprises an amorphous CoFe alloy. The local crystallinity of the first region helps to result in high tunnel magnetoresistance (TMR), high perpendicular magnetic anisotropy (PMA), and high state coercivity compared to current technologies. The local amorphous state of the second region results in a low magnetic moment, thus enabling faster write times and improved device characteristic distribution.
[0007] In one embodiment, the spacer layer comprises an alloy of a refractory metal and iron, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W).
[0008] In another embodiment, the spacer layer contains an iron concentration level ranging from about 20 atomic percent (at.%) to about 80 at.%.
[0009] In yet another embodiment, the first CoFeB layer and the second CoFeB layer contain less than 5 at.% boron.
[0010] In one embodiment, the first region of the first CoFeB layer has a thickness that is between about 20% and about 40% of the thickness of the first CoFeB layer.
[0011] In another embodiment, the thickness of the first region of the first CoFeB layer is between about 0.2 nm and about 0.5 nm, and the thickness of the second region of the first CoFeB layer is between about 0.2 nm and about 0.7 nm. In another embodiment of the present invention, a magnetoresistive random access memory (MRAM) is provided, comprising a reference layer; a tunnel barrier layer on the reference layer; and a free layer on the tunnel barrier layer, the free layer comprising a first cobalt-iron-boron (CoFeB) layer on the tunnel barrier layer; a spacer layer on the first CoFeB layer; a second CoFeB layer on the spacer layer; and a capping layer on the second CoFeB layer, the spacer layer being an alloy of a refractory metal and iron, wherein the iron has a concentration level in the range of about 20 at.% to about 80 at.%. In another embodiment of the present invention, a magnetic tunnel junction (MTJ) stack is provided, comprising a reference layer; a tunnel barrier layer on the reference layer; and a free layer on the tunnel barrier layer, wherein the free layer comprises a first cobalt-iron-boron (CoFeB) layer; a spacer layer of a refractory metal and iron-containing alloy; a second CoFeB layer; and a capping layer, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W); and the spacer layer is sandwiched between the first CoFeB layer and the second CoFeB layer. [Brief explanation of the drawing]
[0012] The present invention will be better understood and recognized from the following detailed description of embodiments of the invention, in conjunction with the accompanying drawings. [Figure 1] This figure illustrates a cross-sectional view of a semiconductor structure according to one embodiment of the present invention. [Figure 2] This figure illustrates a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. [Figure 3] This figure illustrates a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. [Figure 4]This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 5] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 6] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 7] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 8] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 9] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 10] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention. [Figure 11] This figure illustrates cross-sectional views of a semiconductor structure at various stages of manufacturing according to one embodiment of the present invention.
[0013] For the sake of brevity and clarity, please understand that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, where applicable, in various functional block diagrams, two connected devices and / or elements may not necessarily be illustrated as connected. In some other instances, certain elements in a functional block diagram may be grouped for illustrative purposes only, but this does not necessarily imply that these elements belong to or are embodied in a single physical entity. [Modes for carrying out the invention]
[0014] In the following detailed descriptions and accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings serve as both illustrative and schematic representations and are not drawn to scale. Furthermore, for the sake of clarity, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in certain descriptions or drawings. This does not imply that any of the unexpressed layers, structures, and regions are omitted from actual semiconductor structures. Moreover, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with regard to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to cover all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used to form semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of simplicity.
[0015] In this specification, the terms “about” or “substantially” used in relation to thickness, width, proportion, range, etc., should be understood to mean that they are close or approximately, and not exactly so. For example, the terms “about” or “substantially” as used herein mean that there may be a small margin of error, such as 1% or less of the stated quantity. Similarly, the terms “on,” “over,” or “on top of” used herein to describe the positional relationship between two layers or structures are intended to be interpreted broadly and should not be interpreted as excluding the presence of one or more intervening layers or structures.
[0016] Furthermore, while various reference numerals may be used throughout different drawings, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures. Therefore, to simplify the explanation, detailed descriptions of the same or similar features, elements, or structures may not be repeated in each drawing. The notation of the same or similar elements may also be omitted in some drawings to avoid making the drawings overly detailed.
[0017] Embodiments of the present invention provide a free layer structure used in MTJ stacks to improve the functionality of the formed MTJ device. The free layer includes a multilayer sandwich-type spacer positioned between first and second cobalt-iron-boron (CoFeB) layers. The multilayer sandwich-type spacer includes a plurality of non-magnetic spacers separated by and / or sandwiched between a plurality of iron interlayers. The plurality of non-magnetic spacers, such as a plurality of refractory metal layers, can absorb large amounts of boron (B), and the plurality of iron interlayers can magnetically bond the plurality of non-magnetic spacers together and ultimately bond with the first and second CoFeB layers. On the other hand, the plurality of iron interlayers can attract, disperse, and / or absorb some of the boron. Embodiments of the present invention, by using a free layer structure with a multilayer sandwich-type spacer for boron absorption, make it possible to use CoFeB targets with very high boron content, up to 50 to 60 atomic percent (at.%), in the free layer deposition process. The high boron content in the CoFeB target improves the wettability of the magnesium oxide (MgO) tunnel barrier layer, resulting in more uniform deposition of the CoFeB material.
[0018] FIG. 1 is a diagram exemplarily showing a cross-sectional view of a semiconductor structure according to one embodiment of the present invention. More specifically, an embodiment of the present invention provides a MRAM device including an MTJ stack 10. The MTJ stack 10 may include a reference layer 300, a tunnel barrier layer 401 on the reference layer 300, and a free layer 510 on the tunnel barrier layer 401. The free layer 510 may include, in one embodiment, a first CoFeB layer 511, a spacer layer 512 on the first CoFeB layer 511, a second CoFeB layer 513 on the spacer layer 512, and a capping layer 514 on the second CoFeB layer 513.
[0019] In one embodiment, the spacer layer 512 may be a multi-layer spacer such as an alloy formed from a stack of alternating layers of a non-magnetic metal such as a refractory metal and a magnetic metal such as iron (Fe). For example, the spacer layer 512 may be formed from a set of refractory metal layers 5121 and a set of iron layers 5122, and the set of refractory metal layers 5121 and the set of iron layers 5122 are arranged alternately. Hereinafter, the term "set" may include one or more. In other words, the set of refractory metal layers 5121 may be separated by the set of iron layers 5122, or the set of iron layers 5122 may be separated by the set of refractory metal layers 5121. In one embodiment, the stack of alternating layers may include at least two layers of refractory metal and one layer of iron. The refractory metal may be, for example, zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re) and / or tungsten (W).
[0020] During the formation of the spacer layer 512, each of the refractory metal layers 5121 can be formed with a thickness between about 0.05 nm and about 0.4 nm. This thickness range is important because the spacer layer 512 formed thereby can have a sufficient amount of refractory metal to provide sufficient absorption of boron, and on the other hand, to ensure that the iron layers 5122 disposed above and below the refractory metal layer 5121 are not magnetically separated from each other due to the thickness of the refractory metal layer 5121. Further, for example, each of the iron layers 5122 can be formed with a thickness between about 0.3 nm and about 1.0 nm. This thickness range is similarly important because it ensures that the iron layers 5122 have sufficient magnetic power or magnetic force to couple to each other and to the first and second CoFeB layers 511 and 513 below and above the spacer layer 512. The refractory metal layer 5121 and the iron layer 5122 can be combined together to form an alloy. The first CoFeB layer 511 and the second CoFeB layer 513 can have boron substantially depleted due to the unique multilayer structure of the spacer layer 512, particularly the plurality of boron-absorbing refractory metal layers 5121.
[0021] The tunnel barrier layer 401 can be a magnesium oxide (MgO) layer, and the capping layer 514 can also be an MgO layer. The first CoFeB layer 511 can include a first region 5111 adjacent to the tunnel barrier layer 401. The first region 5111 of the first CoFeB layer 511 contains highly crystallized cobalt iron (CoFe) by contacting the MgO of the tunnel barrier layer 401 and being relatively far from the spacer layer 512 (compared to the second region 5112 of the first CoFeB layer 511). The highly crystallized first region 5111 of the first CoFeB layer 511 provides a high tunnel magnetoresistance (TMR) and helps improve the performance of the MRAM device.
[0022] On the other hand, the capping layer 514 may also be an MgO layer. The second CoFeB layer 513 may include a first region 5131 adjacent to the capping layer 514. The first region 5131 of the second CoFeB layer 513 also contains highly crystallized CoFe, being in contact with the MgO of the capping layer 514 and relatively separated from the spacer layer 512 (compared to the second region 5132 of the second CoFeB layer 513). The highly crystallized first region 5131 of the second CoFeB layer 513 helps to provide high perpendicular magnetic anisotropy (PMA) and high state retention.
[0023] On the other hand, the first CoFeB layer 511 may include a second region 5112 adjacent to the spacer layer 512, and the second CoFeB layer 513 may also include a second region 5132 adjacent to the spacer layer 512. The second regions 5112 and 5132 contain amorphous CoFe alloy, which is kept in an almost amorphous state by being closer to the spacer layer 512 (than the first regions 5111 and 5131, respectively), and particularly closer to a refractory metal such as Nb. The amorphous CoFe alloy improves the uniformity of the first and second CoFeB layers 511 and 513, which contributes to more uniform device performance.
[0024] In one non-limiting example, the first region 5111 of the first CoFeB layer 511 may have a thickness between approximately 20% and approximately 40% of the total thickness of the first CoFeB layer 511. For example, the first region 5111 may have a thickness between approximately 0.2 nm and approximately 0.5 nm, while the second region 5112 may have a thickness between approximately 0.2 nm and approximately 0.7 nm. Similarly, the first region 5131 of the second CoFeB layer 513 may have a thickness between approximately 20% and approximately 40% of the total thickness of the second CoFeB layer 513. For example, the first region 5131 may have a thickness between approximately 0.2 nm and approximately 0.5 nm, while the second region 5132 may have a thickness between approximately 0.2 nm and approximately 0.7 nm.
[0025] As shown in Figure 1, the spacer layer 512 may be formed to begin with a refractory metal layer 5121 directly above the first CoFeB layer 511 and end with another refractory metal layer 5121 directly below the second CoFeB layer 513. In this case, the resulting spacer layer 512 may have an iron content in the range of about 20 at.% to about 80 at.% overall. However, embodiments of the present invention are not limited to this embodiment. The spacer layer 512 may also have different arrangements of refractory metal layers, i.e., non-magnetic layers, and iron layers, i.e., magnetic layers, which will be described in more detail below.
[0026] Figure 2 is a diagram illustrating an illustrative cross-sectional view of a semiconductor structure according to another embodiment of the present invention. More specifically, embodiments of the present invention provide an MRAM device including an MTJ stack 20. Similar to the MTJ stack 10 shown in Figure 1, the MTJ stack 20 may include a reference layer 300, a tunnel barrier layer 401 above the reference layer 300, and a free layer 520 above the tunnel barrier layer 401. In one embodiment, the free layer 520 may include a first CoFeB layer 521, a spacer layer 522 above the first CoFeB layer 521, a second CoFeB layer 523 above the spacer layer 522, and a capping layer 524 above the second CoFeB layer 523.
[0027] The spacer layer 522 may be formed from a stack of alternating layers, for example, a set of non-magnetic refractory metal layers 5221 and a set of magnetic iron layers 5222. However, embodiments of the present invention are not limited to this form. In one embodiment, the spacer layer 522 may be formed by sputtering from an alloy target containing a refractory metal such as Nb and a magnetic metal such as Fe, instead of forming a multilayer structure of refractory metal layers and magnetic metal layers.
[0028] Unlike the spacer layer 512 in Figure 1, the spacer layer 522 may begin with an iron layer 5222 directly above the first CoFeB layer 521 and end with another iron layer 5222 directly below the second CoFeB layer 523. In this case, the spacer layer 522 thus formed may have an iron content in the range of approximately 20 at.% to approximately 80 at.% in total. Starting with an iron layer 5222 helps prevent refractory metals such as niobium (Nb) forming the refractory metal layer 5221 from migrating to the MgO layer at the interface between the first CoFeB layer 521 and the tunnel barrier layer 401. This migration may occur if the heavy iron atoms of the iron layer 5222 are not present, because the first CoFeB layer 521 is usually very thin, on the order of 1 nm. Since niobium atoms do not retain spin polarization, preventing niobium atoms from migrating to the interface with the MgO layer helps prevent a decrease in the overall TMR potential. On the other hand, controlling the amount of iron is also important, because excessive amounts of iron can cause a decrease in PMA.
[0029] The first CoFeB layer 521 and the second CoFeB layer 523 are substantially boron-depleted due to the unique multilayer structure of the spacer layer 522, which contains a sufficient amount of boron-absorbing niobium atoms. The first CoFeB layer 521 may include a first region 5211 consisting mostly of highly crystallized CoFe and a second region 5212 consisting of an amorphous CoFe alloy. Similarly, the second CoFeB layer 523 may include a first region 5231 consisting mostly of highly crystallized CoFe and a second region 5232 consisting of an amorphous CoFe alloy. The local crystallinity of the highly crystallized CoFe near the MgO, and the amorphous CoFe alloy in the remainder of the first CoFeB layer 521 and the second CoFeB layer 523, help to create the structure of the free layer 520, which helps to achieve higher TMR, higher PMA, and improved state retention while maintaining the low write current used during MRAM fabrication compared to MRAM using a conventional free layer.
[0030] Figure 3 is a diagram illustrating an illustrative cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention. More specifically, embodiments of the present invention provide an MRAM device including an MTJ stack 30. Similar to the MTJ stack 10 shown in Figure 1, the MTJ stack 30 may include a reference layer 300, a tunnel barrier layer 401 above the reference layer 300, and a free layer 530 above the tunnel barrier layer 401. In one embodiment, the free layer 530 may include a first CoFeB layer 531, a spacer layer 532 above the first CoFeB layer 531, a second CoFeB layer 533 above the spacer layer 532, and a capping layer 534 above the second CoFeB layer 533.
[0031] The spacer layer 532 may be a multilayer spacer and may be formed from a stack of alternating layers including a set of non-magnetic metal refractory metal layers 5321 and a set of magnetic metal iron layers 5322. In this case, the spacer layer 522 formed thereby may have an iron content in the range of about 20 at.% to about 80 at.% overall. Unlike the spacer layer 512 in Figure 1 and the spacer layer 522 in Figure 2, the spacer layer 532 may begin with an iron layer 5322 (or refractory metal layer) directly above the first CoFeB layer 531 and end with a refractory metal layer 5321 (or iron layer) directly below the second CoFeB layer 533.
[0032] The first CoFeB layer 531 may comprise a first region 5311 made of almost highly crystalline CoFe and a second region 5312 made of an amorphous CoFe alloy. Similarly, the second CoFeB layer 533 may comprise a first region 5331 made of almost highly crystalline CoFe and a second region 5332 made of an amorphous CoFe alloy. Both the first CoFeB layer 531 and the second CoFeB layer 533 are substantially boron-depleted due to the unique multilayer structure of the spacer layer 532. Unlike conventional spacer layers, the spacer layer 532 contains a sufficient amount of boron-absorbing niobium atoms.
[0033] Figures 4 to 11 illustrate cross-sectional views of semiconductor structures at various stages of manufacturing according to multiple embodiments of the present invention. More specifically, embodiments of the present invention provide receiving or providing a semiconductor substrate 101, such as a silicon (Si) substrate, and forming an MTJ stack 40 by forming a diffusion barrier layer 201 on the semiconductor substrate 101, which may be an amorphous tantalum (Ta) and / or tantalum nitride (TaN) layer, as shown in Figure 4. Subsequently, a CoFeB layer 202 may be deposited in an amorphous state on the diffusion barrier layer 201 of an amorphous Ta / TaN layer, as shown in Figure 5.
[0034] In further embodiments of the present invention, as shown in Figure 6, a seed layer 203, such as a ruthenium (Ru) layer and / or a platinum (Pt) layer, can be formed on the amorphous CoFeB layer 202, the seed layer 203 can remain in an amorphous state, a reference layer 300 can be formed on the seed layer 203, and a tunnel barrier layer 401 can be formed on the reference layer 300.
[0035] In one embodiment, the base layer 300 may have a multilayer structure. For example, the base layer 300 may include a first stack of alternating cobalt and platinum layers 301; a second stack of alternating cobalt and iridium layers 302 provided on top of the alternating layers 301 of the first stack; a tungsten (W) layer 303 provided on top of the alternating layers 302 of the second stack; and another amorphous CoFeB layer 304 provided on top of the tungsten layer 303.
[0036] Embodiments of the present invention may further provide forming a free layer structure on the tunnel barrier layer 401. Thus, embodiments of the present invention provide forming a first CoFeB layer 501 in an amorphous state on the tunnel barrier layer 401, as shown in Figure 7; forming a spacer layer 502 on the first CoFeB layer 501, as shown in Figure 8; forming a second CoFeB layer 503 on the spacer layer 502, as shown in Figure 9; and forming a capping layer 504 on the second CoFeB layer 503. The spacer layer 502 may have a structure similar to any of the spacer layers 512, 522, and 532 shown in Figures 1, 2, and 3, respectively, the structures and material composites thereof are described in detail above with respect to the respective drawings. The capping layer 504 may be an MgO layer that helps increase the PMA of the free layer 500, thereby reducing the write voltage of the MRAM device.
[0037] After forming a free layer according to an embodiment of the present invention, another CoFeB layer 601 is deposited in an amorphous state on the free layer 500, and a capping layer 602 is further deposited on the CoFeB layer 601. Both of these can further improve or enhance the PMA of the free layer 500.
[0038] According to one embodiment of the present invention, the MTJ stack 40 can be subjected to one or more annealing processes at temperatures ranging from about 300°C to about 435°C, typically between about 380°C and 420°C, and the annealing process, in conjunction with thermal cycling of other CMOS devices, can have a total duration of approximately several tens of minutes to several hours. During the annealing process, boron atoms, particularly those present in the first CoFeB layer 501 and the second CoFeB layer 503, are attracted to and / or absorbed by refractory metal layers such as the niobium metal layer and iron layers in the spacer layer 502, and possibly diffuse into the nearby MgO layer of the tunnel barrier layer 401 and the capping layer 504, resulting in a substantially depleted boron state in the first CoFeB layer 501 and the second CoFeB layer 503. For example, the first CoFeB layer 501 and the second CoFeB layer 503 may have a boron content or boron concentration level lower than 5 at.%.
[0039] On the one hand, because they are in contact with MgO, the first regions 5011 and 5031 may contain crystallized CoFe, which may result in higher TMR and PMA of the free layer 500. On the other hand, because they are close to the niobium in the spacer layer 502, the second regions 5012 and 5032 may contain amorphous CoFe alloy, which improves wettability and the overall uniformity of the MRAM device.
[0040] The exemplary methods discussed herein should be understood to be readily integrable with other semiconductor processing flows, semiconductor devices, and integrated circuits comprising various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be manufactured with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention may be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. With respect to the teachings of the present invention provided herein, those skilled in the art will be able to apply the methods of the present invention to other implementation examples and applications.
[0041] Therefore, at least a portion of one or more of the semiconductor structures described herein can be realized as integrated circuits. The resulting integrated circuit chips may be sold by manufacturers as bare dies in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chips may be mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher carrier) or in a multi-chip package (such as a ceramic carrier with surface interconnects and / or embedded interconnects). In either case, the chips may then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product such as a motherboard. The final product can be anything containing integrated circuit chips, ranging from toys and other low-cost applications to input devices such as displays and keyboards, and advanced computer products with central processing units.
[0042] While the above description has provided illustrative examples of various embodiments of the present invention, these embodiments are not intended to be exhaustive, and the present invention is not limited to the embodiments disclosed herein. The terminology used herein has been selected to best describe the principles of the embodiments, the practical applications or technical improvements that surpass existing technologies, and to enable those skilled in the art to understand the embodiments disclosed herein. Many modifications, substitutions, alterations, and equivalents will likely come to mind for those skilled in the art. Such modifications, alterations, and / or alternative embodiments may be made without departing from the scope of the present invention, and all such modifications and alterations have been conceived and considered within the scope of the present invention. Accordingly, the appended claims should be understood to encompass all such modifications and alterations within the scope of the present invention.
Claims
1. Reference layer; Magnesium oxide (MgO) tunnel barrier layer; and free layer The free layer includes, The first cobalt-iron-boron (CoFeB) layer above the tunnel barrier layer; Spacer layer on the first CoFeB layer; A second CoFeB layer on the spacer layer; and MgO capping layer on the second CoFeB layer Includes, The first and second CoFeB layers are substantially depleted of boron (B) and each includes a first region adjacent to the tunnel barrier layer and the capping layer and a second region adjacent to the spacer layer, respectively, the first region of the first and second CoFeB layers contains crystalline cobalt iron (CoFe), and the second region of the first and second CoFeB layers contains amorphous CoFe alloy. Magnetoresistive Random Access Memory (MRAM).
2. The MRAM according to claim 1, wherein the spacer layer comprises an alloy of a refractory metal and iron, and the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W).
3. The MRAM according to claim 1, wherein the spacer layer includes an iron concentration level in the range of about 20 at.% to about 80 at.%.
4. The MRAM according to claim 1, wherein the first CoFeB layer and the second CoFeB layer contain less than 5 at.% of boron.
5. The MRAM according to claim 1, wherein the first region of the first CoFeB layer has a thickness between approximately 20% and approximately 40% of the thickness of the first CoFeB layer.
6. The MRAM according to claim 1, wherein the thickness of the first region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.5 nm, and the thickness of the second region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.7 nm.
7. Reference layer; The tunnel barrier layer above the aforementioned reference layer; and Free layer above the tunnel barrier layer The free layer includes, The first cobalt-iron-boron (CoFeB) layer above the tunnel barrier layer; Spacer layer on the first CoFeB layer; A second CoFeB layer on the spacer layer; and Capping layer on the second CoFeB layer Includes, The spacer layer is an alloy of a refractory metal and iron, where the iron has a concentration level in the range of approximately 20 at.% to approximately 80 at.%. Magnetoresistive Random Access Memory (MRAM).
8. The MRAM according to claim 7, wherein the refractory metal is selected from the group consisting of zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), and tungsten (W).
9. The MRAM according to claim 7, wherein the tunnel barrier layer is a magnesium oxide (MgO) layer, the first CoFeB layer is located directly above the tunnel barrier layer, the first CoFeB layer is substantially boron (B) depleted, and includes a first region adjacent to the tunnel barrier layer and a second region adjacent to the spacer layer; the first region includes crystalline cobalt iron (CoFe), and the second region includes an amorphous CoFe alloy.
10. The MRAM according to claim 7, wherein the capping layer is a magnesium oxide (MgO) layer located directly above the second CoFeB layer, the second CoFeB layer being substantially boron (B) depleted and comprising a first region adjacent to the capping layer and a second region adjacent to the spacer layer; the first region comprising crystalline cobalt iron (CoFe) and the second region comprising an amorphous CoFe alloy.
11. The MRAM according to claim 7, wherein the first region of the first CoFeB layer has a thickness between approximately 20% and approximately 40% of the thickness of the first CoFeB layer.
12. The MRAM according to claim 7, wherein the thickness of the first region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.5 nm, and the thickness of the second region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.7 nm.
13. The MRAM according to claim 7, wherein the spacer layer is formed from a stack of alternating layers of the refractory metal and iron, and each of the alternating layers has a thickness between approximately 0.3 nm and approximately 1.0 nm.
14. The MRAM according to claim 7, wherein the spacer layer is formed by sputtering deposition using an alloy target, the alloy target comprises the refractory metal and iron, and the iron has a concentration level in the range of about 20 at.% to about 80 at.%.
15. Reference layer; The tunnel barrier layer above the aforementioned reference layer; and Free layer above the tunnel barrier layer Includes, The free layer comprises a first cobalt-iron-boron (CoFeB) layer; a spacer layer of a refractory metal and iron-containing alloy; a second CoFeB layer; and a capping layer, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W), and the spacer layer is sandwiched between the first and second CoFeB layers. Magnetic tunnel junction (MTJ) stack.
16. The MTJ stack according to claim 15, wherein the tunnel barrier layer is a magnesium oxide (MgO) layer, the first CoFeB layer is directly above the tunnel barrier layer and includes a first region adjacent to the tunnel barrier layer and a second region adjacent to the spacer layer; the first region is substantially boron (B) depleted and contains crystalline cobalt iron (CoFe), and the second region is substantially boron (B) depleted and contains amorphous CoFe alloy.
17. The MTJ stack according to claim 16, wherein both the first region and the second region of the first CoFeB layer contain less than 5 at.% boron.
18. The MTJ stack according to claim 16, wherein the thickness of the first region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.5 nm, and the thickness of the second region of the first CoFeB layer is between approximately 0.2 nm and approximately 0.7 nm.
19. The MTJ stack according to claim 16, wherein the spacer layer is formed from a stack of alternating layers of the refractory metal and iron, and each of the alternating layers has a thickness between approximately 0.3 nm and approximately 1.0 nm.
20. The MTJ stack according to claim 15, wherein the spacer layer contains iron at a concentration level in the range of about 20 at.% to about 80 at.%.