Shared source / drain contacts for stacked transistors

Abstract

A semiconductor structure having a shared source / drain contact for stacked transistors is provided. The semiconductor structure includes a first transistor having a first source / drain (S / D) region; a second transistor having a second S / D region, the second transistor stacked on top of the first transistor; and a first S / D contact shared by the first S / D region of the first transistor and the second S / D region of the second transistor, wherein the first S / D contact has a first portion and a second portion, the first portion being in direct contact with the top surface of the first S / D region of the first transistor and in direct contact with the bottom surface of the second S / D region, and the second portion being in direct contact with the inner wall of the second S / D region of the second transistor. A method for manufacturing the semiconductor structure is also provided.

Description

Technical Field

[0004] , , , ,

[0001] The present invention relates to the manufacture of semiconductor integrated circuits. More specifically, it relates to shared source / drain contacts for vertically stacked transistors, and methods of forming the same.

Background Art

[0005] According to one embodiment, the semiconductor structure further includes a trench anchor just above the top of the first S / D region of the first transistor, where the first portion of the first S / D contact is saddled over the trench anchor so as to contact the top and sidewall surfaces of the trench anchor. The trench anchor of epitaxial SiGe provides an additional contact area between the first S / D contact and the first S / D region of the first transistor, thereby further helping to reduce contact resistance.

[0006] In one embodiment, the trench anchor comprises epitaxially grown silicon germanium (SiGe) and is partially embedded in the first S / D region of the first transistor.

[0007] In another embodiment, the second portion of the first S / D contact is located just above the top of a portion of the first portion of the first S / D contact.

[0008] In yet another embodiment, the second S / D region of the second transistor includes an opening extending from its top surface to its bottom surface, the opening having an inner wall, the inner wall being in direct contact with the second portion of the first S / D contact.

[0009] In one embodiment, the first and second transistors are first and second nanosheet transistors, and the semiconductor structure further includes a dielectric insulating layer that separates the first transistor from the second transistor.

[0010] In one embodiment, the top surface of the first S / D region of the first transistor has a V-shape, and the bottom surface of the first S / D region of the first transistor has an inverted V-shape.

[0011] According to one embodiment, the semiconductor structure further includes a second S / D contact in contact with the top surface of the fourth S / D region of the second transistor, and a first back-side S / D contact in contact with the bottom surface of the third S / D region of the first transistor.

[0012] Embodiments of the present invention also provide a method for forming a semiconductor structure. The method comprises the steps of forming a first source / drain (S / D) region of a first transistor on a substrate; and forming a first interlevel dielectric (interlevel) on the top of the first S / D region. The steps include: forming a dielectric (ILD) layer; forming a second S / D region of a second transistor on the top of the first ILD layer; exposing the top surface of the first S / D region of the first transistor by creating an opening in the second S / D region of the second transistor and the first ILD layer; removing the first ILD layer through the opening, thereby horizontally expanding a portion of the opening between the first S / D region of the first transistor and the second S / D region of the second transistor, thereby exposing the top surface of the first S / D region and the bottom surface of the second S / D region; and filling the opening with a conductive material to form a first S / D contact, the first S / D contact being shared by the first S / D region of the first transistor and the second S / D region of the second transistor.

[0013] According to one embodiment, the method further includes the step of forming the trench anchor in the opening by epitaxially growing the trench anchor from the exposed top surface of the first S / D region of the first transistor, before removing the first ILD layer through the opening.

[0014] In one embodiment, the height of the trench anchor is below the bottom surface of the second S / D region of the second transistor.

[0015] In another embodiment, the first S / D contact has a first portion and a second portion, the second portion being just above the top of the first portion, and the first portion of the first S / D contact fills the expanded portion of the opening and is positioned over the trench anchor.

[0016] In yet another embodiment, the step of forming the first S / D region includes the step of epitaxially growing the first S / D region so that the top surface is formed in a V-shape.

[0017] According to another embodiment, the method further includes the steps of forming a second S / D contact in contact with the top surface of the fourth S / D region of the second transistor, and forming a first backside S / D contact in contact with the bottom surface of the third S / D region of the first transistor. [Brief explanation of the drawing]

[0018] The present invention will be more fully understood and recognized from the following detailed description of embodiments of the invention, which will be interpreted in conjunction with the accompanying drawings.

[0019] [Figure 1] Figures 1A, 1B, and 1C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 2] Figures 2A, 2B, and 2C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 3] Figures 3A, 3B, and 3C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 4] Figures 4A, 4B, and 4C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 5] Figures 5A, 5B, and 5C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 6] Figures 6A, 6B, and 6C are cross-sectional and / or simplified top views illustrating different cross-sections of a semiconductor structure during the manufacturing stage of an embodiment of the present invention. [Figure 7] Figures 7A, 7B, and 7C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 8] Figures 8A, 8B, and 8C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 9] Figures 9A, 9B, and 9C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 10] Figures 10A, 10B, and 10C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 11] Figures 11A, 11B, and 11C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 12] Figures 12A, 12B, and 12C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 13] Figures 13A, 13B, and 13C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 14] Figures 14A, 14B, and 14C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 15] Figures 15A, 15B, and 15C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 16] Figures 16A, 16B, and 16C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of an embodiment of the present invention. [Figure 17] FIGS. 17A, 17B and 17C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of a semiconductor structure according to an embodiment of the present invention. [Figure 18] FIGS. 18A, 18B and 18C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of a semiconductor structure according to an embodiment of the present invention. [Figure 19] FIGS. 19A, 19B and 19C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of a semiconductor structure according to an embodiment of the present invention. [[ID=X]] [Figure 20] FIGS. 20A, 20B and 20C are cross-sectional views and / or simplified top views illustrating different cross-sections of a semiconductor structure in the manufacturing stages of a semiconductor structure according to an embodiment of the present invention.

[0020] [[ID=X]] [[ID=X]] [Figure 21] A flowchart illustrating a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [[ID=X]]

[0021] [[ID=X]] For the purposes of simplicity and clarity, it will be understood that the elements shown in the drawings are not necessarily drawn to scale. Further, in the various functional block diagrams, two connected devices and / or elements may not necessarily be shown as being connected. In some other instances, the grouping of some elements within a functional block diagram may be for illustrative purposes only and may not necessarily imply that they are within a single physical entity or that they are embodied within a single physical entity. DETAILED DESCRIPTION OF THE INVENTION [[ID=X]] [[ID=X]]

[0022] In the following detailed description and accompanying drawings, please understand that the various layers, structures, and regions shown in the drawings are illustrative and schematic representations, not drawn to scale. Furthermore, for the sake of simplicity, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given illustrations or drawings. This does not imply that any unexpressed layers, structures, and regions are omitted from actual semiconductor structures. Additionally, please understand that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with regard to semiconductor processing steps, we want to emphasize that the description provided herein is not intended to encompass all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, some processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, may be intentionally omitted herein for the sake of brevity.

[0023] It should be understood that the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., are intended to mean close or approximate, not exactly. For example, the terms “about” or “substantially” used herein suggest, merely as an example, that there may be a small margin of error, such as 1% or less of the stated quantity. Similarly, the terms “on,” “over,” or “on top of” used herein to describe the positional relationship between two layers or structures are intended to be interpreted broadly and should not be interpreted as excluding the existence of one or more intervening layers or structures.

[0024] Furthermore, while various reference numerals may be used across different drawings, the same or similar reference numerals may be used throughout the drawings to refer to the same or similar features, elements, or structures. Therefore, for the sake of brevity, detailed descriptions of the same or similar features, elements, or structures may not be repeated in each drawing. Labeling of the same or similar elements in some drawings may also be omitted to avoid cluttering the drawings.

[0025] Figures 1A and 1B are examples of different cross-sectional views, and Figure 1C is a simplified top view thereof during the manufacturing stage of a semiconductor structure according to one embodiment of the present invention. More specifically, Figure 1A shows a cross-sectional view of a semiconductor structure along the dashed line X, as shown in Figure 1C. In other words, the cross-sectional view in Figure 1A crosses the gate in a direction along the length of the gate. Figure 1B shows a cross-sectional view of a semiconductor structure along the dashed line Y, as shown in Figure 1C. In other words, the cross-sectional view in Figure 1B crosses the S / D region in a direction along the width of the gate. Figure 1C selectively shows key elements such as nanosheets, gates, S / D regions, and elements that are not yet formed or covered by other elements. On the other hand, elements such as dielectric cap layers and sidewall spacers are not necessarily shown to avoid drawing clutter, and similarly, even if some of these elements are present, they may not necessarily be shown, to the extent that it does not hinder the description of embodiments of the present invention, such as by omitting them from Figure 1C.

[0026] Similarly, Figures 2A, 2B, and 2C through 20A, 20B, and 20C show cross-sectional and simplified top views of semiconductor structures at various manufacturing stages, corresponding to Figures 1A, 1B, and 1C.

[0027] Embodiments of the present invention provide a step of forming a semiconductor structure 10 exemplified to include a plurality of stacked nanosheet transistors. However, embodiments of the present invention are not limited to this form and may be applied to other types of transistors and / or active devices. Specifically, the semiconductor structure 10 may include a semiconductor substrate 101 and an insulating layer such as an oxide layer 102 on top of the substrate 101. One or more sets of stacked nanosheet transistors may be formed on top of the oxide layer 102. For example, one of the one or more sets of stacked nanosheet transistors may include a lower nanosheet transistor 210 and an upper nanosheet transistor 310. The lower nanosheet transistor 210 includes a set of nanosheets 211, which may be silicon (Si) nanosheets, separated by a set of sacrificial sheets 212, which may be silicon germanium (SiGe) nanosheets. An inner spacer 213 of a dielectric material such as silicon nitride (SiN) or silicon oxide (SiO2) may be formed in a recess created in the set of sacrificial sheets 212. Similarly, the upper nanosheet transistor 310 includes a set of nanosheets 311, for example, of Si nanosheets, separated by a set of sacrificial sheets 312, for example, of SiGe nanosheets. An inner spacer 313 of dielectric material, for example, SiN or SiO2, may be formed in a recess created in the set of sacrificial sheets 312. The lower nanosheet transistor 210 may be insulated or separated from the upper nanosheet transistor 310 by a spacer layer, for example, a middle dielectric isolation (MDI) layer 301.

[0028] One or more sacrificial gate structures may be formed on the top of one or more sets of nanosheet transistor structures. For example, one sacrificial gate structure includes a sacrificial gate 401 that is patterned by a directional and / or selective etching process and by applying a hard mask 409 formed on its top during the etching process. Sidewall spacers 410 may be formed on the sidewalls of the sacrificial gate 401. One or more sacrificial gate structures may subsequently be used in etching or recess processes to pattern a stack of raw nanosheets into one or more sets of stacked nanosheets to form one or more sets of stacked nanosheet transistors.

[0029] Embodiments of the present invention further provide a step of etching the oxide layer 102 through openings between sacrificial gate structures to form one or more placeholders for forming back contacts during the back processing step. For example, the first and second placeholders 111 and 112 may be formed to be embedded in the oxide layer 102, for example, by a selective etching process and a subsequent epitaxial growth process. In one embodiment, the first and second placeholders 111 and 112 may be SiGe epitaxially grown from a semiconductor substrate 101 which may be a Si substrate.

[0030] Figures 2A and 2B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 2C is a simplified top view thereof. More specifically, an embodiment of the present invention, following the steps shown in Figures 1A, 1B and 1C, provides a step of forming a sacrificial layer 201 to protect the sidewalls of the set of nanosheets 211 of the lower nanosheet transistor 210. For example, an organic planarization layer (OPL) may be formed between one or more sacrificial gate structures and at openings thereon. The OPL between the sacrificial gate structures may then be recessed. For example, the OPL may be recessed to below the level of the MDI layer 301, as a result of which the sidewalls of the set of nanosheets 311 of the upper nanosheet transistor 310 may be exposed. Meanwhile, the remaining OPL may form a sacrificial layer 201 that covers the sidewalls of the set of nanosheets 211 of the lower nanosheet transistor 210.

[0031] Figures 3A and 3B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 3C is a simplified top view thereof. More specifically, following the steps shown in Figures 2A, 2B, and 2C, embodiments of the present invention provide a step of forming a protective liner 411 that lines the sidewalls and sacrificial gate structures at the tops of the set of nanosheets 311 of the upper nanosheet transistor 310. The protective liner 411 may be formed, for example, by depositing a conformal layer of protective material covering the semiconductor structure 10, followed by applying a directional etching process to remove the horizontal portion of the conformal layer, thereby forming the protective liner 411 on the sidewalls of the set of nanosheets 311 of the upper nanosheet transistor 310.

[0032] Figures 4A and 4B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 4C is a simplified top view thereof. More specifically, following the steps shown in Figures 3A, 3B, and 3C, embodiments of the present invention provide a step of removing the sacrificial layer 201, for example by an ashing process, to expose the sidewalls of the set of nanosheets 211 of the lower nanosheet transistor 210 and the first and second placeholders 111 and 112 in the oxide layer 102. Embodiments of the present invention then provide a step of forming the source / drain region of the lower nanosheet transistor 210 by epitaxial growth from the sidewalls of the set of nanosheets 211, which are Si in the material, and from the first and second placeholders 111 and 112, which are epitaxially grown SiGe.

[0033] For example, the first source / drain (S / D) region 221 can be epitaxially grown from the sidewalls of the set of nanosheets 211. Since nucleation occurs only at the sidewalls of the set of nanosheets 211 and not at the oxide layer 102, the growth of the first S / D region 221 does not have to start from the oxide layer 102, and therefore a gap can be formed between the first S / D region 221 and the oxide layer 102 below it. On the other hand, the third S / D region 223 can be epitaxially grown from both sidewalls of the set of nanosheets 211 and from the first placeholder 111, and the fifth S / D region 225 can be epitaxially grown from both sidewalls of the set of nanosheets and from the second placeholder 112.

[0034] In one embodiment, the epitaxial growth of the first S / D region 221 can be controlled and stopped or terminated in a timely manner when the epitaxial growth from the left set of nanosheets 211 and the right set of nanosheets 211 begin to merge, resulting in a V-shaped apex in the cross-section made in the direction along the gate length, as shown in Figure 4A, which helps to increase the contact area with the S / D contact to be formed thereon. At the bottom of the first S / D region 221, an inverted V-shaped bottom surface can be formed because there is no epitaxial growth from the oxide layer 102. On the other hand, the third and fifth S / D regions 223 and 225 have only V-shaped apex surfaces, because the third and fifth S / D regions 223 and 225 are also epitaxially grown from the first and second placeholders 111 and 112. Therefore, unlike the first S / D area 221, the bottom surfaces of the third S / D area 223 and the fifth S / D area 225 are in complete contact with the first and second placeholders 111 and 112, respectively.

[0035] Figures 5A and 5B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 5C is a simplified top view thereof. More specifically, following the steps shown in Figures 4A, 4B, and 4C, embodiments of the present invention provide the steps of selectively removing the liner 411 to expose the MDI layer 301, and depositing a first interlayer dielectric (ILD) layer 302 covering the formed S / D region including first, third, and fifth S / D regions 221, 223, and 225. The first ILD layer 302 may be formed, for example, by first depositing dielectric material between and above the sacrificial gate structure; applying a CMP process to planarize the top surface of the deposited dielectric material; and recessing the dielectric material until the sidewalls of the set of nanosheets 311 of the upper nanosheet transistor 310 are exposed. The remaining dielectric material forms the first ILD layer 302 covering the sidewalls of the MDI layer 301.

[0036] Figures 6A and 6B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 6C is a simplified top view thereof. More specifically, following the steps shown in Figures 5A, 5B, and 5C, embodiments of the present invention provide a step of epitaxially growing S / D regions from the sidewalls of a set of nanosheets 311 of an upper nanosheet transistor 310 above a first ILD layer 302.

[0037] For example, the second S / D region 222 and the fourth S / D region 224 of the upper nanosheet transistor 310 may be formed on the tops of the first S / D region 221 and the third S / D region 223 of the lower nanosheet transistor 210, respectively, by epitaxial growth from the sidewalls of the set of nanosheets 311 via the first ILD layer 302. In addition, the sixth S / D region 226 may be epitaxially formed on the top of the fifth S / D region 225. In one embodiment, and unlike the first S / D region 221, the second, fourth, and sixth S / D regions 222, 224, and 226 may be overgrown so that their bottom surfaces are in full contact with the bottom of the first ILD layer 302.

[0038] Figures 7A and 7B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 7C is a simplified top view thereof. More specifically, following the steps shown in Figures 6A, 6B, and 6C, embodiments of the present invention provide a step of depositing a second interlayer dielectric (ILD) layer 303 covering second and fourth S / D regions 222 and 224, and a sixth S / D region 226 of the upper nanosheet transistor 310. The second ILD layer 303 may be formed, for example, by first depositing dielectric material between and above sacrificial gate structures, and then applying a CMP process to planarize the top surface of the deposited dielectric material. In one embodiment, the dielectric material of the second ILD layer 303 may differ from the dielectric material of the first ILD layer 302. In addition, the CMP process may remove a hard mask 409 at the top of the sacrificial gate 401, and optionally a portion of the sacrificial gate 401.

[0039] Figures 8A and 8B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 8C is a simplified top view thereof. More specifically, following the steps shown in Figures 7A, 7B, and 7C, embodiments of the present invention provide a step of selectively removing a sacrificial gate 401; a step of selectively removing a sacrificial sheet 312 surrounding a set of nanosheets 311 of an upper nanosheet transistor 310; and a step of selectively removing a sacrificial sheet 212 surrounding a set of nanosheets 211 of a lower nanosheet transistor 210. Next, a metal gate 402 may be formed in a replacement-metal-gate (RMG) process, where the material for the metal gate 402 may be used to fill the space remaining after the removal of the sacrificial gate 401, sacrificial sheet 312, and sacrificial sheet 212. The metal gate 402 may include a layer of gate dielectric, one or more layers of work function metal, and gate metal at the top of one or more work function metals. The gate metal may include, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and / or other suitable conductive materials.

[0040] Figures 9A and 9B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 9C is a simplified top view thereof. More specifically, following the steps shown in Figures 8A, 8B, and 8C, embodiments of the present invention provide a step of forming one or more source / drain contacts, such as a first S / D contact 621 (see Figures 16A, 16B) that is in contact with both the lower nanosheet transistor 210 and the upper nanosheet transistor 310. In the step of forming the first S / D contact 621, embodiments of the present invention provide a step of creating an opening 501 in a second S / D region 222 of the upper nanosheet transistor 310. The opening 501 may be formed by first forming a hard mask 509 that extends from the top to the bottom of the second S / D region 222 and has an opening at the top of the second ILD layer 303, and then transferring the opening in the hard mask 509 to the second ILD layer 303 and the second S / D region 222 by a selective and / or directional etching process. The selective etching process may etch through the second S / D region 222, exposing the first ILD layer 302 below it. The opening 501 may include the sidewall of the epitaxial SiGe of the second S / D region 222.

[0041] Figures 10A and 10B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 10C is a simplified top view thereof. More specifically, following the steps shown in Figures 9A, 9B, and 9C, embodiments of the present invention provide a step of performing ion implantation on the exposed sidewall of an opening 501 which is part of a second S / D region 222. In other words, ions can be implanted on the inner wall of the second S / D region 222. By implanting suitable dopants such as boron (B) for p-type nanosheet transistors or phosphorus (P) for n-type nanosheet transistors, embodiments of the present invention can further enhance the conductivity of the second S / D region 222.

[0042] Figures 11A and 11B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 11C is a simplified top view thereof. More specifically, following the steps shown in Figures 10A, 10B, and 10C, embodiments of the present invention provide a step of forming a protective liner 511 that lines the sidewalls of the opening 501. The protective liner 511 provides protection for the second S / D drain region 222 of the upper nanosheet transistor 310 during a subsequent etching process that continues to create an opening to expose the first S / D region 221 of the lower nanosheet transistor 210. The protective liner 511 may be formed, for example, by depositing a conformal layer of protective material covering the semiconductor structure 10, and then applying a directional etching process to remove the horizontal portion of the conformal layer, thereby forming the protective liner 511 on the sidewalls of the opening 501 and, in particular, on the inner sidewalls of the second S / D region 222.

[0043] Figures 12A and 12B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 12C is a simplified top view thereof. More specifically, following the steps shown in Figures 11A, 11B, and 11C, embodiments of the present invention provide a step of selectively etching a first ILD layer 302, exposed by an opening 501 until at least the top surface of the first S / D region 221 of the lower nanosheet transistor 210 is exposed, for example by a reactive-ion-etching (RIE) process. The selective etching further creates an opening 521 below the opening 501 in the first ILD layer 302, and in one embodiment, the opening 521 may partially etch the first S / D region 221 of the lower nanosheet transistor 210. During the selective etching process in creating the opening 521, the epitaxially grown SiGe of the second S / D region 222 of the upper nanosheet transistor 310 is protected by a protective liner 511.

[0044] Figures 13A and 13B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 13C is a simplified top view thereof. More specifically, following the steps shown in Figures 12A, 12B, and 12C, embodiments of the present invention provide a step of forming a trench epitaxial trench anchor 601 in the opening 521 by performing trench epitaxial growth of, for example, boron-doped SiGe for a PFET or phosphorus-doped Si for an NFET in the opening 521. The trench anchor 601 grows from the exposed first S / D region 221 of the lower nanosheet transistor 210 and has a height below the bottom surface of the second S / D region 222 of the upper nanosheet transistor 310. In other words, the top surface of the trench anchor 601 may be below the top surface of the first ILD layer 302. This is important for achieving low contact resistance by later forming a partially wrap-around contact for the bottom S / D epitaxial with trench epitaxial.

[0045] Figures 14A and 14B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 14C is a simplified top view thereof. More specifically, following the steps shown in Figures 13A, 13B, and 13C, embodiments of the present invention provide a step of selectively etching the first ILD layer 302 through openings 501 and 521 with respect to surrounding material including trench anchors 601, the top surface of the first S / D region 221 of the lower nanosheet transistor 210, and the bottom surface of the second S / D region 222 of the upper nanosheet transistor 310. For example, the etching step of the first ILD layer 302 expands a portion of the openings 501 and 521 by horizontally expanding the opening 521 until substantially both the bottom surface of the second S / D region 222 of the upper nanosheet transistor 310 and the top surface of the first S / D region 221 of the lower nanosheet transistor 210 are exposed, thereby creating an opening 611. The opening 611 may be positioned across the trench anchor 601 of the trench epi. In other words, the opening 611 may have an upside-down inverted U shape in a cross section that crosses the gate in the direction along the length of the gate, as shown in Figure 14A, and in a cross section that crosses the S / D region in the direction along the width of the gate, as shown in Figure 14B.

[0046] Figures 15A and 15B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 15C is a simplified top view thereof. More specifically, following the steps shown in Figures 14A, 14B, and 14C, embodiments of the present invention provide a step of removing the protective liner 511 in a selective etching process to expose the inner wall of the second S / D region 222 of the upper nanosheet transistor 310. For example, the protective liner 511 is removed using an etching process that provides etching selectivity between silicon nitride (SiN), such as the protective liner 511, and epitaxially grown SiGe, such as the trench anchor 601, the first S / D region 221 of the lower nanosheet transistor 210, and the second S / D region 222 of the upper nanosheet transistor 310.

[0047] Figures 16A and 16B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 16C is a simplified top view thereof. More specifically, following the steps shown in Figures 15A, 15B, and 15C, embodiments of the present invention provide a step of creating n additional openings in the second ILD layer 303 through the hard mask 509 to expose selective S / D regions of the upper nanosheet transistor. For example, in addition to the opening 611, a second opening may be created to expose the top surface of a fourth S / D region 224 of the upper nanosheet transistor 310, and a third opening may be created to expose the top surface of a sixth S / D region 226. Conductive materials, including silicide liners such as Ti, metal adhesive liners such as TiN, and low-resistance metal fillers such as tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), and / or other suitable materials, can subsequently be deposited in the openings to form S / D contacts such as a first S / D contact 621, a second S / D contact 622, and a third S / D contact 623.

[0048] Specifically, the first S / D contact 621 may be formed to be a shared S / D contact of the upper nanosheet transistor 310 and the lower nanosheet transistor 210, shared by the second S / D region 222 and the first S / D region 221. The first S / D contact 621 includes an upper portion 6211 and a lower portion 6212 immediately below the upper portion 6211. The upper portion 6211 of the first S / D contact 621 may be in contact with a portion of the lower portion 6212 of the first S / D contact 621, and is in full contact with the inner wall of the second S / D region 222 of the upper nanosheet transistor 310. On the other hand, the lower part 6212 of the first S / D contact 621 is in contact with both the bottom surface of the second S / D region 222 of the upper nanosheet transistor 310 and the top surface of the first S / D region 221 of the lower nanosheet transistor 210, resulting in a substantial increase in the contact surface of the first S / D contact 621 having the second S / D region 222 of the upper nanosheet transistor 310 and the first S / D region 221 of the lower nanosheet transistor 210. Furthermore, the lower part 6212 of the first S / D contact 621 is placed over the trench anchor 601, which further increases the contact surface between the first S / D contact 621 and the first S / D region 221 of the lower nanosheet transistor 210, thereby resulting in a substantial improvement in conductivity and reduced resistance, which is a difficult problem faced by current technology.

[0049] A second S / D contact 622 may be formed to contact a fourth S / D region 224 of the semiconductor structure 10, and a third S / D contact 623 may be formed to contact a sixth S / D region of the semiconductor structure 10. After forming various metal contacts by depositing conductive material in the openings, a CMP process is applied to flatten the top surface of the conductive material, thereby completing the formation of the first, second, and third metal contacts 621, 622, and 623.

[0050] Figures 17A and 17B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 17C is a simplified top view thereof. More specifically, following the steps shown in Figures 16A, 16B, and 16C, embodiments of the present invention provide a step of continuing to form a back-end-of-line (BEOL) structure 710 on the top of the second ILD layer 303 and the tops of the first, second, and third S / D contacts 621, 622, and 623. The BEOL structure 710 may be used, for example, below a front-end-of-line (FEOL) device including an upper nanosheet transistor 310 and a lower nanosheet transistor 210 to provide signal routing and / or power distribution functions. Embodiments of the present invention further provide a step of bonding a carrier wafer 720 onto the BEOL structure 710 so that the semiconductor structure 10 can be inverted upside down for further processing from the back side of the semiconductor structure 10 or the back side of the substrate 101.

[0051] For the sake of simplicity, please note that, from Figures 18A and 18B through 20A and 20B, the drawings will continue to be used in their original orientation (instead of being upside down). However, the drawings may be described in a manner consistent with the process from the back side of the substrate 101.

[0052] Figures 18A and 18B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 18C is a simplified top view thereof. More specifically, following the steps shown in Figures 17A, 17B, and 17C, embodiments of the present invention provide a step of removing the substrate 101 from the back side of the semiconductor structure 10 by, for example, a grinding process, a CMP process, and / or other selective etching processes. Removal of the substrate 101 may stop at the oxide layer 102, exposing the first and second placeholders 111 and 112.

[0053] Figures 19A and 19B are examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 19C is a simplified top view thereof. More specifically, following the steps shown in Figures 18A, 18B, and 18C, embodiments of the present invention provide a step of selectively removing first and second placeholders 111 and 112 to expose the bottom surfaces of the third S / D region 223 and the fifth S / D region 225 of the first nanosheet transistor 210. The removal of the first and second placeholders 111 and 112 creates corresponding openings 801 and 802.

[0054] Figures 20A and 20B are illustrative examples of different cross-sectional views in the process of manufacturing a semiconductor structure according to one embodiment of the present invention, and Figure 20C is a simplified top view thereof. More specifically, following the steps shown in Figures 19A, 19B, and 19C, embodiments of the present invention provide a step of filling openings 801 and 802 with conductive materials including a silicide liner such as Ti, a metal adhesive liner such as TiN, and a low-resistance metal filler such as W, Cu, Co, Ru, and / or other suitable materials in order to form first and second backside S / D contacts 811 and 812. Subsequently, a CMP process is applied to flatten the top surfaces of the backside S / D contacts. Then, a backside interconnect structure 820 is formed at the tops of the first and second backside S / D contacts, providing power and / or signal routing functions.

[0055] Figure 21 is an example flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. The method is as follows: (910) forming a first source / drain (S / D) region of a first transistor on a substrate; (920) forming a first interlevel dielectric (ILD) layer on the top of the first S / D region; (930) forming a second S / D region of a second transistor on the top of the first ILD layer; (940) exposing the top surface of the first S / D region of the first transistor by creating an opening in the second S / D region of the second transistor and the first ILD layer; (950) forming a trench epitaxial in the opening by epitaxially growing the trench epitaxial from the exposed top surface of the first S / D region of the first transistor; (960) forming the first ILD through the opening (970) The steps include removing the LD layer, thereby horizontally expanding a portion of the opening between the first S / D region of the first transistor and the second S / D region of the second transistor, to expose the top surface of the first S / D region and the bottom surface of the second S / D region; and (970) filling the opening with a conductive material to form a first S / D contact, wherein the first S / D contact is shared by the first S / D region of the first transistor and the second S / D region of the second transistor.

[0056] It should be understood that the exemplary methods discussed herein can be readily incorporated into other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be manufactured from a variety of devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention can be employed in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered to be part of the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art may contemplate other implementations and applications of the techniques of the present invention.

[0057] Therefore, at least a portion of one or more of the semiconductor structures described herein can be implemented in an integrated circuit. The resulting integrated circuit chip can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip can be mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other high-level carrier) or in a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or embedded interconnects). In either case, the chip can then be integrated together with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate product such as a motherboard, or a final product. The final product can be any product containing an integrated circuit chip, ranging from toys and other low-cost applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0058] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive; the present invention is not limited to the embodiments disclosed herein. The terminology used herein has been selected to best describe the principles, practical applications, or technological improvements over the technologies available on the market of the embodiments, and to enable other persons skilled in the art to understand the embodiments disclosed herein. Many modifications, substitutions, alterations, and equivalents will now come to mind for those skilled in the art. Such modifications, alterations, and / or alternative embodiments may be made without departing from the scope of the present invention and are therefore intended and considered to be all included within the scope of the present invention. Accordingly, it should be understood that the appended claims are intended to encompass all such modifications and alterations that fall within the scope of the present invention.

[0059] In a preferred embodiment of the present invention as described herein, a semiconductor structure is provided comprising: a first transistor having first and third source / drain (S / D) regions; a second transistor having second and fourth S / D regions, wherein the second transistor is stacked on top of the first transistor and has a second S / D region above the first S / D region of the first transistor and a fourth S / D region above the third S / D region of the first transistor; a trench anchor just above the top of the first S / D region; and a first S / D contact shared by the first S / D region and the second S / D region, wherein the first S / D contact has a first portion and a second portion, the first portion being in direct contact with the top surface of the first S / D region, spanning over the trench anchor, and in direct contact with the bottom surface of the second S / D region, the second portion being just above the top of a portion of the first portion. The trench anchor comprises epitaxially grown silicon germanium (SiGe) and is partially embedded in the first S / D region of the first transistor. The second S / D region of the second transistor may include an opening extending from its top surface to its bottom surface, the opening having an inner wall, the inner wall of which is in direct contact with the second portion of the first S / D contact. The first and second transistors may be first and second nanosheet transistors and further include a dielectric insulating layer between the first and second transistors. The top surface of the first S / D region of the first transistor may have a V-shape, and the bottom surface of the first S / D region of the first transistor may have an inverted V-shape. The semiconductor structure may further include a second S / D contact in contact with the top surface of the fourth S / D region of the second transistor, and a first backside S / D contact in contact with the bottom surface of the third S / D region of the first transistor.

Claims

1. A first transistor having a first source / drain (S / D) region; A second transistor having a second S / D region, the second transistor being stacked on top of the first transistor; and A first S / D contact shared by the first S / D region of the first transistor and the second S / D region of the second transistor. Includes, Herein, the first S / D contact comprises a first portion and a second portion, wherein the first portion is in direct contact with the top surface of the first S / D region of the first transistor and in direct contact with the bottom surface of the second S / D region, and the second portion is in direct contact with the inner wall of the second S / D region of the second transistor, in a semiconductor structure.

2. The semiconductor structure according to claim 1, further comprising a trench anchor just above the top of the first S / D region of the first transistor, wherein the first portion of the first S / D contact is positioned across the trench anchor so as to be in contact with the top and sidewall surfaces of the trench anchor.

3. The semiconductor structure according to claim 2, wherein the trench anchor comprises epitaxially grown silicon germanium (SiGe) and is partially embedded in the first S / D region of the first transistor.

4. The semiconductor structure according to claim 1, wherein the second portion of the first S / D contact is located immediately above the top of a portion of the first portion of the first S / D contact.

5. The semiconductor structure according to claim 1, wherein the second S / D region of the second transistor includes an opening extending from its top surface to its bottom surface, the opening having an inner wall, the inner wall being in direct contact with the second portion of the first S / D contact.

6. The semiconductor structure according to claim 1, wherein the first and second transistors are first and second nanosheet transistors, and further comprises a dielectric insulating layer separating the first transistor from the second transistor.

7. The semiconductor structure according to claim 1, wherein the top surface of the first S / D region of the first transistor has a V-shape, and the bottom surface of the first S / D region of the first transistor has an inverted V-shape.

8. The semiconductor structure according to claim 1, further comprising a second S / D contact in contact with the top surface of the fourth S / D region of the second transistor, and a first back-side S / D contact in contact with the bottom surface of the third S / D region of the first transistor.

9. A step of forming the first source / drain (S / D) region of the first transistor on the substrate; A step of forming a first interlayer dielectric (ILD) layer at the top of the first S / D region; A step of forming a second S / D region of the second transistor on the top of the first ILD layer; A step of exposing the top surface of the first S / D region of the first transistor by creating an opening in the second S / D region and the first ILD layer of the second transistor; The steps of removing the first ILD layer through the opening, thereby horizontally expanding a portion of the opening between the first S / D region of the first transistor and the second S / D region of the second transistor, thereby exposing the top surface of the first S / D region and the bottom surface of the second S / D region; and In the step of filling the opening with a conductive material to form a first S / D contact, the first S / D contact is shared by the first S / D region of the first transistor and the second S / D region of the second transistor. A method for forming a semiconductor structure, including [a specific component].

10. The method according to claim 9, further comprising the step of forming the trench anchor in the opening by epitaxially growing the trench anchor from the exposed top surface of the first S / D region of the first transistor before removing the first ILD layer through the opening.

11. The method according to claim 10, wherein the height of the trench anchor is below the bottom surface of the second S / D region of the second transistor.

12. The method according to claim 11, wherein the first S / D contact has a first portion and a second portion, the second portion being just above the top of the first portion, and the first portion of the first S / D contact fills the expanded portion of the opening and is positioned over the trench anchor.

13. The method according to claim 9, wherein the step of forming the first S / D region includes the step of epitaxially growing the first S / D region so that the top surface is formed in a V-shape.

14. The steps include forming a second S / D contact that is in contact with the top surface of the fourth S / D region of the second transistor, and Step of forming a first back-side S / D contact that is in contact with the bottom surface of the third S / D region of the first transistor. The method according to claim 9, further comprising:

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