Data processors, data processing methods, electronic devices, and storage media

Abstract

The present invention provides a data processor, a data processing method, an electronic device, and a non-temporary computer-readable storage medium. [Solution] The data processor includes an N-level cache, memory, and an N-level data proxy module. Here, each level data proxy module within the N-level data proxy module corresponds one-to-one with each level cache within the N-level cache. The N-level data proxy module is configured to acquire the data access instruction sequence in the task currently being executed by the data processor, adjust the instruction transmission order of the data access instruction sequence based on the storage location of the destination data for each data access instruction within the data access instruction sequence, transmit each data access instruction in order according to the instruction transmission order, and cache the destination data returned by each data access instruction in the corresponding first-level data proxy module. The data processor significantly improves data access efficiency by reducing register occupancy time and preventing data access instructions in distant storage locations from consuming bandwidth for data access instructions in nearby storage locations.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202410420140.8 filed on April 9, 2024, the entire content of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to a data processor, a data processing method, an electronic device, and a non - transient computer - readable storage medium.

Background Art

[0003] A data access instruction (e.g., a load instruction) is a kind of basic instruction in the computer architecture principle and is used to load data from a storage unit such as a memory into a register. Its function is to read the data in a storage unit such as a memory into a specified register to facilitate subsequent operations and processing.

Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a data processor including an N-level cache and memory. The i-th level cache in the N-level cache includes at least one i-th level cache node, at least some of the i-th level cache nodes in the at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1 and i is any positive integer from 1 to N-1. The N-th level cache in the N-level cache is electrically connected to the memory, and each first level cache node is electrically connected to a corresponding compute core. The data processor further includes an N-level data proxy module, where each level data proxy module in the N-level data proxy module corresponds one-to-one with each level cache in the N-level cache. The N-level data proxy module is configured to acquire a data access instruction sequence in a task currently being executed by the data processor, adjust the instruction transmission order of the data access instruction sequence based on the memory location of the destination data for each data access instruction in the sequence, transmit each data access instruction in order according to the instruction transmission order, and cache the destination data returned by each data access instruction in the corresponding first-level data proxy module. Here, the corresponding first-level data proxy module corresponds to the first-level cache.

[0005] For example, in a data processor provided by at least one embodiment of the present disclosure, when the N-level data proxy module adjusts the instruction transmission order of the data access instruction sequence based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence, it includes performing the following operations: obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the distance between the memory storage location of the destination data for each data access instruction and the computing core in the data processor; and adjusting the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, where data access instructions with smaller corresponding physical distances have earlier transmission times.

[0006] For example, in a data processor provided by at least one embodiment of the present disclosure, when the N-level data proxy module performs the operation of adjusting the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, it includes performing the following operations: Classifying each data access instruction into different channels based on the physical distance corresponding to each data access instruction, where the physical distances corresponding to data access instructions in different channels are different. Arranging the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to the data access instructions in different channels, and obtaining the instruction transmission order, where in the instruction transmission order, data access instructions belonging to the first channel are transmitted first, data access instructions belonging to the second channel are transmitted last, data access instructions belonging to the same channel are transmitted serially according to the relative order relationship in the data access instruction sequence, the physical distance corresponding to the data access instruction in the first channel is the smallest, and the physical distance corresponding to the data access instruction in the second channel is the largest.

[0007] For example, in a data processor provided by at least one embodiment of the present disclosure, the N-level data proxy module performing the operation of adjusting the instruction transmission order of the data access instruction sequence based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence includes performing the following operations: obtaining the priority of each data access instruction; obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the distance between the memory storage location of the destination data for each data access instruction and the computing core in the data processor; and adjusting the instruction transmission order of the data access instruction sequence based on the priority of each data access instruction and the corresponding physical distance, where higher priority data access instructions are transmitted faster, and for the same priority, data access instructions with a smaller corresponding physical distance are transmitted faster.

[0008] For example, in a data processor provided by at least one embodiment of the present disclosure, the N-level data proxy module performing the task of obtaining the priority of each data access instruction includes performing the following operations: determining the priority of each data access instruction based on the time it takes for each data access instruction to return destination data when the task is pre-executed. Here, when the task is pre-executed, each data access instruction is sent in order according to the order in the data access instruction sequence, and the time it takes for each data access instruction to return destination data is collected.

[0009] For example, in a data processor provided by at least one embodiment of the present disclosure, when the N-level data proxy module performs the operation of caching destination data returned by each data access instruction in a corresponding first-level data proxy module, it includes performing the following operations: For each data access instruction, cache the destination data returned by the data access instruction in a first-level cache node or shared memory electrically connected to a compute core that uses the destination data. Here, the corresponding first-level data proxy module includes a plurality of cache blocks, the plurality of cache blocks are mapped to the first-level cache node or the shared memory, and the plurality of cache blocks are used to cache the received destination data.

[0010] For example, in a data processor provided by at least one embodiment of the present disclosure, the at least one i-th level cache node corresponds one-to-one with at least one i-th level data proxy module, the i-th level data proxy modules corresponding to at least some of the i-th level cache nodes are electrically connected to the i+1-th level data proxy module corresponding to one i+1-th level cache node, and the first level data proxy module corresponding to each first level cache node is electrically connected to at least one compute core, where the at least one compute core is electrically connected to the first level cache node. The n-th level data proxy module corresponding to the N-th level cache is electrically connected to the memory.

[0011] For example, in a data processor provided by at least one embodiment of the present disclosure, each data proxy module includes a scheduler, a request state list, a data request list, and a plurality of cache blocks, wherein the data proxy module includes any i-th level data proxy module or the N-th level data proxy module, the data request list is used to cache data access instructions awaiting transmission, the scheduler is used to sequentially transmit the data access instructions cached in the data request list according to the instruction transmission order, and to transmit the received destination data to a cache block in the corresponding compute core or an electrically connected higher-level data proxy module, and the request state list includes a plurality of state items, where each state item in the plurality of state items is used to indicate a cache block associated with the data access instruction corresponding to the state item, the position of the data access instruction in the instruction transmission order, and the plurality of cache blocks is used to cache the received destination data.

[0012] For example, in a data processor provided by at least one embodiment of the present disclosure, multiple channels are provided in the data request list of the data proxy module and are used to cache the data access instructions awaiting transmission. The physical distances corresponding to data access instructions in different channels are different. The scheduler is configured to arrange the data access instructions in each channel in order from the smallest to the largest physical distance corresponding to the data access instructions in different channels, to obtain the instruction transmission order of the data access instructions cached in the data request list, and to transmit the data access instructions awaiting transmission in order according to the instruction transmission order. Here, the physical distance corresponding to each data access instruction is the distance between the memory storage location of the destination data of each data access instruction and the computing core in the data processor, and the physical distance corresponding to each data access instruction is determined by the read address of the destination data as an input parameter in each data access instruction.

[0013] For example, in a data processor provided by at least one embodiment of the present disclosure, the data proxy module is configured to associate the unassociated cache blocks with a data access instruction selected from the data request list of the data proxy module in accordance with the instruction transmission order, in response to the presence of unassociated cache blocks within the data proxy module.

[0014] For example, in a data processor provided by at least one embodiment of the present disclosure, each cache block has a unique corresponding cache block number, and each data access instruction in the data request list has a unique corresponding request number, and when the data proxy module performs the operation of associating the unassociated cache block with a data access instruction selected from the data request list of the data proxy module in the order of instruction transmission, the operation includes: setting the request number of the data access instruction and the cache block number of the unassociated cache block in a state item corresponding to the data access instruction, and associating the unassociated cache block with the data access instruction.

[0015] For example, in a data processor provided by at least one embodiment of the present disclosure, the i+1 level data proxy module is further configured to remove a data access instruction associated with any one of the cache blocks from the data request list of the i+1 level data proxy module and to clear the state item in the request state list of the i+1 level data proxy module corresponding to the removed data access instruction in response to destination data cached in any one of the cache blocks of the i+1 level data proxy module having already been sent to the i-th level data proxy module.

[0016] For example, in a data processor provided by at least one embodiment of the present disclosure, the scheduler of the N-level data proxy module is configured to sequentially send the cached data access instructions to the memory in accordance with the instruction transmission order of the data access instructions cached in the data request list of the N-level data proxy module, receive the destination data returned sequentially from the memory, and store each returned destination data in a cache block associated with the corresponding data access instruction.

[0017] For example, in a data processor provided by at least one embodiment of the present disclosure, the scheduler of the i-level data proxy module is configured to transmit a data request signal to the electrically connected i+1-level data proxy module and to cache the received return data in a cache block associated with a data access instruction corresponding to the transmitted data request signal. The scheduler of the i+1-level data proxy module is configured to transmit destination data for a data access instruction corresponding to the data request signal to the i-level data proxy module in response to receiving the data request signal.

[0018] For example, in a data processor provided by at least one embodiment of the present disclosure, the first-level data proxy module is further configured to select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence and to perform an initialization operation on the at least one data access instruction before executing the task. Here, the at least one data access instruction is executed by a computing core electrically connected to the first-level data proxy module.

[0019] For example, in a data processor provided by at least one embodiment of the present disclosure, when the first level data proxy module performs an initialization operation for the at least one data access instruction, it includes performing the following operations: caching the at least one data access instruction in the data request list of the first level data proxy module; initializing a state item corresponding to the at least one data access instruction and storing it in the request state list of the first level data proxy module; and synchronizing the at least one data access instruction and the corresponding state item with other level data proxy modules that have a direct or indirect electrical connection relationship with the first level data proxy module.

[0020] For example, in a data processor provided by at least one embodiment of the present disclosure, the first-level data proxy module is further configured to: receive a data access instruction transmitted by a computing core electrically connected to the first-level data proxy module, determine the cache block associated with the transmitted data access instruction, and transmit the data in the associated cache block to a target register indicated by the data access instruction; delete the data access instruction associated with the associated cache block from the data request list of the first-level data proxy module, and clear the state item corresponding to the deleted data access instruction in the request state list of the first-level data proxy module; and select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence, and perform an initialization operation on the at least one data access instruction.

[0021] For example, in a data processor provided by at least one embodiment of the present disclosure, the state item includes a cache block number and a request number used to indicate a data access instruction corresponding to the state item and a cache block associated with the data access instruction; the state item further includes a channel number of the channel to which the data access instruction belongs and a priority of the data access instruction, the channel number and the priority being used to indicate the position of the data access instruction in the instruction transmission sequence; the state item further includes request received state information and request sent state information used to indicate the current state of the data access instruction; and the state item further includes data state information used to indicate the current state of destination data returned by the data access instruction.

[0022] For example, in a data processor provided by at least one embodiment of the present disclosure, before performing the task, the data processor is further configured to select a plurality of cache lines from among the cache nodes corresponding to each data proxy module and to map the plurality of cache blocks within the data proxy module.

[0023] For example, in a data processor provided by at least one embodiment of the present disclosure, the data access instruction sequence is obtained by arranging all data access instructions within a task according to their relative positions in the program corresponding to the task.

[0024] For example, in a data processor provided by at least one embodiment of the present disclosure, the data processor is a general-purpose graphics processor or graphics processor, and the data processor includes a plurality of computing units. When N=2, the first level cache in the N-level cache includes a plurality of first-level cache nodes, and the second level cache in the N-level cache includes one second-level cache node. Each first-level cache node is used for data sharing within one computing unit, and the second-level cache node is used for data sharing between the plurality of computing units. Each first-level cache node corresponds to one first-level data proxy module, and the second-level cache node corresponds to one second-level data proxy module.

[0025] At least one embodiment of the present disclosure further provides a data processing method for use in a data processor including an N-level cache and memory. The i-th level cache in the N-level cache includes at least one i-th level cache node, at least some of the i-th level cache nodes in the at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1 and i is any positive integer from 1 to N-1. The N-th level cache in the N-level cache is electrically connected to the memory, and each first level cache node is electrically connected to a corresponding computing core. The data processing method includes: obtaining a sequence of data access instructions in a task currently being executed by the data processor; adjusting the instruction transmission order of the data access instruction sequence based on the memory location of the destination data for each data access instruction in the sequence; transmitting each data access instruction sequentially according to the instruction transmission order; and caching the destination data returned by each data access instruction in a first-level cache node or shared memory electrically connected to a computing core that uses the destination data.

[0026] For example, in the data processing method provided by at least one embodiment of the present disclosure, adjusting the instruction transmission order of the data access instruction sequence based on the storage location in the memory of the destination data of each data access instruction in the data access instruction sequence includes obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the physical distance between the storage location in the memory of the destination data of each data access instruction and the computing core in the data processor, and adjusting the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, such that the data access instruction with a smaller corresponding physical distance has an earlier transmission time.

[0027] For example, in the data processing method provided by at least one embodiment of the present disclosure, adjusting the instruction transmission order of the data access instruction sequence based on the storage location in the memory of the destination data of each data access instruction in the data access instruction sequence includes obtaining the priority of each data access instruction, obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the physical distance between the storage location in the memory of the destination data of each data access instruction and the computing core in the data processor, and adjusting the instruction transmission order of the data access instruction sequence based on the priority and the corresponding physical distance of each data access instruction, such that the data access instruction with a higher priority has an earlier transmission time, and when the priorities are the same, the data access instruction with a smaller corresponding physical distance has an earlier transmission time.

[0028] At least one embodiment of the present disclosure further provides an electronic device. The electronic device includes a memory that non-temporarily stores computer-executable instructions, and a processor configured to execute the computer-executable instructions. Here, when the computer-executable instructions are executed by the processor, the data processing method according to any one of the embodiments of the present disclosure is realized.

[0029] At least one embodiment of the present disclosure further provides a non - transitory computer - readable storage medium. Here, the non - transitory computer - readable storage medium stores computer - executable instructions, and when the computer - executable instructions are executed by a processor, the data processing method according to any one of the embodiments of the present disclosure is realized.

[0030] At least one embodiment of the present disclosure further provides an electronic device including a data processor according to any one of the embodiments of the present disclosure.

Brief Description of the Drawings

[0031] To more clearly illustrate the embodiments of the present disclosure, the drawings necessary for use in the embodiments are briefly introduced below. Obviously, the drawings in the following description are merely embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on the provided drawings without creative labor.

[0032] [Figure 1] It is a schematic structural diagram of a multi - core chip system. [Figure 2] It is a schematic structural diagram of a general - purpose graphics processor. [Figure 3] It is a schematic diagram of data access instructions flowing between a cache and a memory. [Figure 4A] It is a timing diagram of data access instructions. [Figure 4B] It is a timing diagram of data access instructions. [Figure 4C] It is a timing diagram of data access instructions. [Figure 4D] It is a timing diagram of data access instructions. [Figure 5] It is a schematic structural diagram of a data processor provided by at least one embodiment of the present disclosure. [Figure 6] It is a schematic block diagram of a data proxy module provided by at least one embodiment of the present disclosure. [Figure 7] This is a schematic block diagram of a data processor provided by at least one embodiment of the present disclosure. [Figure 8A] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8B] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8C] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8D] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8E] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8F] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 8G] This is a schematic diagram of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure. [Figure 9A] This is a timing diagram of a data processor provided by at least one embodiment of the present disclosure. [Figure 9B] This is a timing diagram of a data processor provided by at least one embodiment of the present disclosure. [Figure 10] This is a schematic flowchart of a data processing method provided by at least one embodiment of the present disclosure. [Figure 11] This is a schematic block diagram of an electronic device provided by one embodiment of the present disclosure. [Figure 12] This is a schematic diagram of a non-temporary computer-readable storage medium provided by at least one embodiment of the present disclosure. [Figure 13] This is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0033] To further clarify the purpose, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described clearly and completely below, in conjunction with the accompanying drawings of the embodiments of this disclosure. Clearly, the embodiments described are some, but not all, embodiments of this disclosure. All other embodiments that a person skilled in the art could obtain without creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by a person of general skill in the art to which this disclosure belongs. The terms “First,” “Second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are used simply to distinguish different components. Terms similar to “include” or “contain” mean that the element or component listed before the term includes, but does not exclude, other elements or components. Terms similar to “connected” or “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up,” “down,” “left,” “right,” etc., are used simply to describe relative positions, and such relative positions may change accordingly after the absolute position of the object being described changes.

[0035] To make the following descriptions of embodiments of this disclosure clear and concise, this disclosure omits detailed descriptions of some known features and components.

[0036] While processors operate much faster than memory, directly accessing memory to read or write data requires a certain waiting period. Therefore, a cache is typically used during the memory access process to improve system efficiency and processor memory access speed. Processors usually prioritize searching for data in the cache. For example, if the data requested by an application or software exists in the cache, it's called a cache hit; otherwise, it's called a cache miss.

[0037] Figure 1 is a schematic diagram of a multicore chip system. As shown in Figure 1, the system is a typical 4-core on-chip system and includes four cores, three levels of cache corresponding to each of the four cores (L1 cache, L2 cache, and L3 cache), an on-chip interconnect network, memory, and other intellectual property cores. I-L1$ is the private instruction L1 cache for each core, D-L1$ is the private data L1 cache for each core, every two cores share an L2 cache, and the four cores share an L3 cache. The L3 cache and other intellectual property cores (e.g., direct memory access / video / display, etc.) access memory via the on-chip interconnect network.

[0038] The L1 cache is closest to the core, has the smallest capacity, and is the fastest.

[0039] The L2 cache has a larger capacity, for example, 256K, and is slightly slower than the L1 cache. The L2 cache can be thought of as a buffer for the L1 cache, which has limited capacity due to its very high manufacturing cost. The function of the L2 cache is to store data that the processor needs to process but the L1 cache cannot store.

[0040] The L3 cache is the largest level of the three-level cache, for example, 12MB. At the same time, it is also the slowest level in terms of access speed. The L3 cache and memory can be considered a buffer for the L2 cache. While the capacity gradually increases from the L1 cache to the L3 cache, the unit manufacturing cost gradually decreases.

[0041] When the processor operates, it first searches the L1 cache for the necessary data, then the L2 cache if it fails to find the data there, and finally the L3 cache if it still fails to find the data there. If the processor cannot find the data it needs in any of the three levels of cache, it retrieves the data from memory. The longer the search path, the longer the process takes.

[0042] Similarly, the caches of general-purpose graphics processing units (GPGPUs) or graphics processing units (GPUs) also have cache structures similar to those of the multi-core on-chip system shown in Figure 1, including, for example, hierarchical multi-level cache structures.

[0043] Figure 2 is a schematic diagram of a general-purpose graphics processor.

[0044] As shown in Figure 2, a general-purpose graphics processor is actually an array of streaming processor clusters (SPCs), including, for example, streaming processor cluster 1, ..., streaming processor cluster M shown in Figure 2, where M is a positive integer greater than 1. In a general-purpose graphics processor, one streaming processor cluster handles one computation task, or multiple streaming processor clusters handle one computation task. Data is shared between multiple streaming processor clusters via a global cache (L2 cache) or global memory.

[0045] As shown in Figure 2, taking Streaming Processor Cluster 1 as an example, one Streaming Processor Cluster includes multiple compute units, for example, compute unit 1, compute unit 2, ..., compute unit N in Figure 1, where N is a positive integer. Each compute unit (abbreviated as CU) is used to perform operations such as cumulative addition, regular addition, subtraction, multiplication, division, etc. Within one compute unit, there are multiple cores (also called compute cores), each compute core includes an arithmetic logic unit (ALU), a floating-point arithmetic unit, etc., and the compute cores are used to perform specific computation tasks. In addition, a compute unit includes a register file, shared memory, and an L1 cache, which are used to hierarchically store source and destination data associated with computation tasks. Shared memory within a compute unit is used to share data between the cores of that compute unit, and the L1 cache is used to cache data from the memory or L2 cache used by that compute unit. Of course, in some general-purpose graphics processors, the computing unit may store data using only the L1 cache and register files.

[0046] As shown in Figure 2, a general-purpose graphics processor may further include an L2 cache (also called a global cache) and memory. The L2 cache can be used for data sharing between each streaming processor cluster, and the memory may be, for example, high-bandwidth memory (HBM).

[0047] In parallel computing, computation tasks are generally executed through multiple threads. These threads are divided into multiple thread blocks before execution on a general-purpose graphics processor (or parallel computing processor), and then a thread block dispatch module (not shown in Figure 2) distributes these thread blocks to each computing unit. All threads within a single thread block must be assigned to run on the same computing unit. Simultaneously, a thread block is divided into minimum execution thread bundles (or, abbreviated, warps), each containing a fixed number (or fewer) threads, for example, 32 threads. Multiple thread blocks may run within the same computing unit or in different computing units.

[0048] In each computing unit, a thread bundle scheduling / dispatch module (not shown in Figure 1) schedules and assigns thread bundles, enabling multiple computing cores in that unit to execute the thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a single thread block may be executed simultaneously or in a time-sharing manner. Multiple threads in each thread bundle execute the same instruction. Data access instructions are sent to the L1 cache (or shared memory) within the computing unit, or further to the L2 cache or global memory, where read / write operations are performed.

[0049] When executing a data access instruction, you need to specify the address you want to read and store the read data in a target register. For example, if the read data is in memory, a data access instruction typically involves several steps:

[0050] 1. Load the memory address into the memory address register (MAR).

[0051] 2. Load the data from memory into the data register (MDR).

[0052] 3. Transfer data from the MDR to the target register. Figure 3 is a schematic diagram of the data access instruction flowing between the cache and memory. Figure 3 shows a two-level cache structure, but of course, more level cache structures have similar flow logic, so they will not be described in detail here.

[0053] In the multi-level cache structure described above, when executing a data access instruction, the computing core (core) preferentially queries the L1 cache for a cache hit according to the data address, as shown by the solid black line in Figure 3. If a hit occurs, the data is returned to the corresponding computing core. If the data is missed in the L1 cache, the search continues in the L2 cache, as shown by the dashed black line in Figure 3. If the data is found in the L2 cache, it is returned to both the L1 cache and the computing core. If the data is also missed in the L2 cache, the data must be loaded from memory and returned to the L2 cache, L1 cache, and the corresponding computing core, as shown by the dashed black line in Figure 3.

[0054] A data access instruction includes the read address of the destination data as an input parameter and the address of the destination register as an output parameter, where the read address is, for example, a memory address, and the data access instruction is used to read the destination data from the read address in memory and load it into the destination register.

[0055] Current data access instructions are not sufficiently efficient, and the demands on sending data access instructions are high. This is because the time it takes for a data access instruction to return data is not fixed. For example, the time it takes for data to be returned varies depending on the distance between the memory location where the destination data resides and the computing core. For instance, memory is usually composed of multiple memory blocks, and different memory blocks are at different distances from the computing core. Therefore, data may be stored in far memory (memory blocks relatively far from the computing core) or near memory (memory blocks relatively close to the computing core). Furthermore, it takes time to return data from memory, and it is not possible to receive the returned data immediately. As a result, when using data returned by a data access instruction, there is a waiting period, and there is a very high probability that the data will not have arrived when it is needed.

[0056] Figure 4A is a timing diagram of data access instructions.

[0057] As shown in Figure 4A, data access instructions are sent only when the data is needed (indicated by the dashed line in Figure 4A), and the destination data resides in memory. Since the instruction must be transmitted from the computing core through the L1 cache and L2 cache to memory, and the data read from memory is returned to the computing core again through the L2 cache and L1 cache, executing another instruction (e.g., instruction 2) after sending a data access instruction still results in a relatively long data wait time.

[0058] To avoid the problems mentioned above, methods are typically employed to send data access instructions earlier so that the data is already returned before use, thus minimizing data waiting. However, this method occupies the target register after the data access instruction is issued until the data is returned, resulting in the register resource being occupied for a long period, making it unavailable for other instructions and leading to the waste of register resources.

[0059] Figures 4B and 4C are timing diagrams for another data access instruction.

[0060] As shown in Figure 4B, although the data arrives immediately before use (at the time indicated by the dashed line in Figure 4B), register resources are still wasted because the target register must be occupied from the time the data access instruction is sent. Therefore, even if the data waiting time is relatively short, register resources are still being wasted.

[0061] As shown in Figure 4C, if the time when the data will be returned is not fixed and there is a high probability that the data will arrive earlier, and the data has already arrived at the time of use (the time indicated by the dashed line in Figure 4C), there is no need to wait for the data, but the register will occupy the register for an even longer time, resulting in a waste of register resources.

[0062] While users can set different data access instruction issuance times based on experience, they still cannot guarantee that data will be returned in the expected order because it is difficult for them to reliably determine the actual storage location of data within the processor. Furthermore, the time it takes for multiple data access instructions to return data can be disrupted, and if multiple threads issue many data access instructions simultaneously, the time required for data to be returned will differ, making it highly likely that the data will not be returned in the order in which the instructions were sent. For example, unnecessary data for a short period may occupy bandwidth, blocking the data that is needed now and causing it to arrive later.

[0063] Figure 4D is a timing diagram for another data access instruction.

[0064] As shown in Figure 4D, the user, through experience, recognizes that the data returned by data access instruction 2 will arrive at the expected time (thick black dashed line in Figure 4D). However, it is highly likely that the bandwidth for this returned data is occupied by other data that is not needed for a short period. For example, as shown in Figure 4D, the data returned by data access instruction 1 (data 1) occupies bandwidth, preventing the data returned by data access instruction 2 from being returned at the expected time. As a result, the actual return time of the data returned by data access instruction 2 is delayed, causing repeated data waits of varying lengths. For example, after waiting for a certain period, another instruction (e.g., instruction 1 or instruction 2 in Figure 4D) is executed first, and then the wait continues. Such methods can increase the total waiting time.

[0065] At least one embodiment of the present disclosure provides a data processor, a data processing method, an electronic device, and a non-temporary computer-readable storage medium. The data processor includes an N-level cache and memory, wherein the i-th level cache within the N-level cache includes at least one i-th level cache node, and at least some of the i-th level cache nodes within the at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1 and i is any positive integer from 1 to N-1. The N-th level cache within the N-level cache is electrically connected to memory, and each first level cache node is electrically connected to a corresponding computing core. The data processor further includes an N-level data proxy module, where each level data proxy module within the N-level data proxy module corresponds one-to-one with each level cache within the N-level cache. The N-level data proxy module is configured to obtain the data access instruction sequence in the task currently being executed by the data processor, adjust the instruction transmission order of the data access instruction sequence based on the memory location of the destination data for each data access instruction in the sequence, transmit each data access instruction sequentially according to the instruction transmission order, and cache the destination data returned by each data access instruction in the corresponding first-level data proxy module. Here, the corresponding first-level data proxy module corresponds to the first-level cache.

[0066] In a data processor provided by at least one embodiment of the present disclosure, data access instructions are transmitted in bulk using an N-level data proxy module. For data access operations, by decoupling between the computing core and memory, the computing core does not need to consider the transmission, reception, and scheduling of data access instructions, and only needs to extract the data from the corresponding first-level data proxy module when it is needed.

[0067] Since the data is extracted in advance into the first-level data proxy module and not directly loaded into the target register, data access instructions can be sent early to cache the data in the first-level data proxy module beforehand. Furthermore, it is not necessary to constantly occupy the target register before using the data; the register only needs to be occupied and the destination data loaded into the target register when the destination data is needed. This significantly reduces register occupancy time and decreases the consumption of register resources.

[0068] Furthermore, by adjusting the instruction transmission order based on the storage location of destination data for different instructions, and by preventing data access instructions located in distant storage locations from overwhelming the bandwidth of data access instructions located in nearby storage locations, the data return time is matched to user expectations, improving data access efficiency.

[0069] The embodiments of this disclosure will be described in detail below in conjunction with the attached drawings, but this disclosure is not limited to these specific embodiments.

[0070] Figure 5 is a schematic diagram of a data processor provided by at least one embodiment of the present disclosure.

[0071] As shown in Figure 5, the data processor 100 includes memory, an N-level cache, and an N-level data proxy module.

[0072] Figure 5 shows the specific structures of the first-level cache, the second-level cache, and the Nth-level cache, but other level caches are not shown redundantly because their structures are similar. Of course, in some embodiments, there may be a two-level cache structure, i.e., N=2, but this will not be described in detail here as it can be seen, for example, in Figure 7.

[0073] For example, the i-th level cache in an N-level cache includes at least one i-th level cache node, and at least some of the i-th level cache nodes within that at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1 and i is any positive integer between 1 and N-1.

[0074] For example, as shown in Figure 5, when i=1, the first-level cache includes multiple first-level cache nodes. When i=2, the second-level cache includes multiple second-level cache nodes.

[0075] For example, as shown in Figure 5, the Nth level cache within an N-level cache contains one Nth level cache node.

[0076] For example, multiple i-th level cache nodes can share one i+1-th level cache node, and all N-1 level cache nodes can share an N-th level cache node. Here, sharing means that the multiple (e.g., M, where M is a positive integer) i-th level cache nodes and the i+1-th level cache node are electrically connected, and each of the M i-th level cache nodes can exchange data with the i+1-th level cache node, for example, by obtaining the necessary data from the i+1-th level cache node.

[0077] For example, referring to Figure 5, multiple first-level cache nodes share one second-level cache node, and for example, several first-level cache nodes share one second-level cache node, and several other first-level cache nodes share another second-level cache node. For example, all N-1 level cache nodes share an N-level cache node.

[0078] For example, the number of cache nodes that share one higher-level cache node at each level can be configured as needed, and each level may be different, so this disclosure does not specifically limit this. For example, in response to N=4, each of the four first-level cache nodes can be configured to share one second-level cache node, each of the eight second-level cache nodes can share one third-level cache node, and all third-level cache nodes can share a fourth-level cache node.

[0079] For example, as shown in Figure 5, the Nth-level cache is electrically connected to memory, and the memory may be, for example, high-bandwidth memory.

[0080] For example, as shown in Figure 5, each first-level cache node is electrically connected to a corresponding computing core. For example, referring to the processor architecture shown in Figure 1, one first-level cache node can be electrically connected to one computing core, and the first-level cache node may be an L1 cache, and the first-level cache node can be electrically connected to one computing core. Alternatively, for example, referring to the processor structure shown in Figure 2, one first-level cache node can be electrically connected to multiple computing cores, and the first-level cache node may be an L1 cache, and in one computing unit, the first-level cache node can be electrically connected to four computing cores.

[0081] As shown in Figure 5, each level data proxy module within the N-level data proxy module included in the data processor corresponds one-to-one with each level cache within the N-level cache.

[0082] For example, an N-level data proxy module includes a first-level data proxy module corresponding to a first-level cache, a second-level data proxy module corresponding to a second-level cache, ... an N-level data proxy module corresponding to an N-level cache.

[0083] For example, with respect to the first to N-1 level data proxy modules, in some embodiments, each level cache corresponds to one data proxy module, and for example, all first-level cache nodes in the first-level cache correspond to one first-level data proxy module.

[0084] For example, in some other embodiments, as shown in Figure 5, a single cache node in each level cache corresponds to one data proxy module, and for example, a data processor includes a plurality of first-level data proxy modules, the plurality of first-level data proxy modules correspond one-to-one with a plurality of first-level cache nodes included in the first-level cache.

[0085] For example, a level N cache includes one level N cache node, and that level N cache node corresponds to one level N data proxy module.

[0086] For example, the same electrical connection relationships exist between data proxy modules as between corresponding cache nodes. For instance, if M i-th level cache nodes share one i+1-th level cache node, then each of these M i-th level cache nodes has an electrical connection relationship with its corresponding M i-th level data proxy modules and the i+1-th level data proxy module corresponding to that i+1-th level cache node. For i-th level data proxy modules corresponding to other i-th level cache nodes, there may be no electrical connection relationships between those i+1-th level data proxy modules.

[0087] Furthermore, each first-level data proxy module is electrically connected to several computing cores to exchange data, and these computing cores are those that have an electrical connection relationship with the first-level cache node corresponding to the first-level data proxy module. In other words, these computing cores share the first-level cache node.

[0088] Similar to the Nth-level cache node, the Nth-level data proxy module also has an electrical connection to memory, and therefore the Nth-level data proxy module can exchange data with memory.

[0089] For example, an N-level data proxy module is configured to obtain a data access instruction sequence from the data processor within the currently executing task, adjust the instruction transmission order of the data access instruction sequence based on the storage location of the destination data for each data access instruction in the sequence, transmit each data access instruction in order according to the instruction transmission order, and cache the destination data returned by each data access instruction in the corresponding first-level data proxy module.

[0090] Here, a first-level data proxy module corresponds to a first-level cache. For example, if only one first-level data proxy module is provided within a data processor, all returned destination data is cached in that first-level data proxy module. For example, if multiple first-level data proxy modules are provided within a data processor, the multiple first-level data proxy modules correspond one-to-one with multiple first-level cache nodes, and the returned destination data is cached in the first-level data proxy module corresponding to the target first-level cache node, and the compute core electrically connected to the first-level target cache node uses the returned destination data. For different data access instructions, the returned destination data may be cached in different first-level data proxy modules.

[0091] For example, a data access instruction sequence is the original instruction sequence, and it is obtained by arranging all data access instructions within a task according to their relative positions in the program corresponding to that task. In other words, the data access instruction sequence represents the original transmission order within the task program, and this transmission order is arranged according to the order the user wishes to use.

[0092] For example, a data access instruction sequence can be obtained by scanning the program code corresponding to a task, or by pre-executing that task.

[0093] For example, in some embodiments, the N-level data proxy module performing the task of adjusting the instruction transmission order of a data access instruction sequence based on the storage location of the destination data for each data access instruction in the sequence includes the following operations: Obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data for each data access instruction in memory and the computing core in the data processor. Adjusting the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, where data access instructions with smaller corresponding physical distances have earlier transmission times.

[0094] For example, the destination data that a data access instruction wants to load is located in memory, and memory has multiple memory blocks. As mentioned above, different memory blocks are at different distances from the computing core, so destination data located on the same memory block can be considered to be at the same distance, while destination data on different memory blocks can be considered to be at different distances. Alternatively, several adjacent memory blocks may be considered to be at the same distance from the computing core, and a person skilled in the art can set this as needed.

[0095] Based on the differences in physical distance corresponding to each data access instruction, the instruction transmission order of the data access instruction sequence can be adjusted. For example, the transmission order can be adjusted according to the physical distance corresponding to each data access instruction, based on the original data access instruction sequence.

[0096] For example, data access instructions with a smaller corresponding physical distance are transmitted earlier, meaning they are placed earlier in the instruction transmission sequence, while data access instructions with a larger corresponding physical distance are transmitted later, meaning they are placed later in the instruction transmission sequence. For example, data access instructions with the same corresponding physical distance are transmitted in order according to their relative order within the data access instruction sequence.

[0097] In at least one embodiment of this disclosure, the physical distance corresponding to a data access instruction does not necessarily have to be a true spatial distance value, but can be represented by any method that can distinguish the distance from the computing core. For example, the physical distance corresponding to a data access instruction can be designated as a first value when the read address of the data access instruction is located in far memory, and as a second value when the read address is located in near memory, thereby distinguishing the physical distances corresponding to different access instructions.

[0098] For example, when an N-level data proxy module adjusts the instruction transmission order of a data access instruction sequence based on the physical distance corresponding to each data access instruction, it performs the following operations: Classify each data access instruction into different channels based on the physical distance corresponding to each data access instruction. Here, the physical distances corresponding to data access instructions in different channels are different. Arrange the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to the data access instructions in different channels, and obtain the instruction transmission order. Here, in the instruction transmission order, data access instructions belonging to the first channel are transmitted first, data access instructions belonging to the second channel are transmitted last, data access instructions belonging to the same channel are transmitted serially according to their relative order within the data access instruction sequence, the physical distance corresponding to the data access instruction in the first channel is the smallest, and the physical distance corresponding to the data access instruction in the second channel is the largest.

[0099] For example, multiple channels can be set up within a data proxy module, and data access instructions can be classified into different channels based on their corresponding physical distance. For instance, data access instructions whose destination data is in the same memory block may be classified into one channel, or data access instructions whose destination data is in several memory blocks that are relatively close to each other may be classified into one channel.

[0100] For example, a first channel, a second channel, a third channel, etc., can be installed. For example, the first channel is a high-speed channel, so the physical distance corresponding to data access instructions within the first channel is relatively small, and for example, the destination data for data access instructions within the first channel is located in near memory. For example, the second channel is a low-speed channel, so the physical distance corresponding to data access instructions within the second channel is relatively large, and for example, the destination data for data access instructions within the second channel is located in far memory. For example, a third channel, etc., may also be installed, and the physical distance corresponding to data access addresses within these channels is smaller than the physical distance corresponding to data access addresses within the second channel, but larger than the physical distance corresponding to data access addresses within the first channel.

[0101] For example, when arranging the instruction transmission order, data access instructions are arranged on a channel-by-channel basis. For example, assuming that three channels are installed in a data proxy module, with the first channel being a high-speed channel, the second channel being a low-speed channel, and the third channel being an intermediate channel, the physical distance corresponding to data access instructions classified as channel 1 is the minimum, the physical distance corresponding to data access instructions classified as channel 3 is greater than the physical distance corresponding to data access instructions classified as channel 1, and the physical distance corresponding to data access instructions classified as channel 2 is the maximum, i.e., greater than the physical distance corresponding to data access instructions classified as channel 3. It should be noted that more channels may be installed depending on the actual situation, or only two channels may be installed to classify different data access instructions, and this disclosure does not specifically limit this.

[0102] All data access commands in the first channel are placed at the very beginning of the command transmission order and transmitted first, all data access commands in the third channel are placed after the data access commands in the first channel and transmitted, and all data access commands in the second channel are transmitted after the data access commands in the third channel.

[0103] If a channel contains multiple data access instructions, these instructions can be transmitted serially in any order. Alternatively, they may be transmitted sequentially according to their relative order within the data access instruction sequence. That is, for these data access instructions, those earlier in the sequence are transmitted preferentially, and those later are transmitted later. In this case, the instruction transmission order further satisfies the instruction transmission order expected by the program itself, and destination data that is expected to be loaded quickly can be returned even faster.

[0104] In the embodiment described above, channels are introduced to classify and manage data access instructions. Based on the difference in distance between the storage location where the destination data to be loaded resides and the computing core, data access instructions are classified into different channels. Instructions corresponding to shorter physical distances are sent preferentially, and those corresponding to longer physical distances are sent later. By sending data access instructions corresponding to different physical distances separately, and by minimizing the burden of bandwidth consumption on shorter requests, the return time of destination data is brought as close as possible to the user's expectations.

[0105] For example, in some embodiments, the instruction transmission order may further take into account the priority of data access instructions. For instance, the physical distance corresponding to some data access instructions may be relatively large, but these instructions may be relatively important to the user, and the user may expect to use the data returned by these instructions sooner. Therefore, by setting these instructions to a higher priority, they can be transmitted sooner.

[0106] For example, an N-level data proxy module adjusting the instruction transmission order of a data access instruction sequence based on the memory location of the destination data for each data access instruction in the sequence includes the following operations: obtaining the priority of each data access instruction; obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the distance between the memory location of the destination data for each data access instruction and the computing core in the data processor; and adjusting the instruction transmission order of the data access instruction sequence based on the priority and corresponding physical distance of each data access instruction, where higher priority data access instructions are transmitted faster, and for the same priority, data access instructions with a smaller corresponding physical distance are transmitted faster.

[0107] For example, an N-level data proxy module performing the task of obtaining the priority of each data access instruction includes the following operations: determining the priority of each data access instruction based on the time it takes for each instruction to return the destination data when the task is pre-executed. Here, when the task is pre-executed, each data access instruction is sent in order according to the order in the data access instruction sequence, and the time it takes for each instruction to return the destination data is collected.

[0108] For example, in a process that pre-executes tasks, the time it takes for each data access command collected to return destination data can be used to determine which data access commands should be set to be sent in advance. For instance, if some data access commands return destination data relatively slowly, but that destination data needs to be used sooner, these data access commands can be set to a higher priority.

[0109] In the adjusted instruction transmission order, the priority of data access instructions is given priority, followed by the channel to which they belong. For example, data access instructions with higher priority are transmitted earlier, so they are transmitted preferentially even if they belong to a slow channel, while other data access instructions (e.g., those with lower priority but on a fast channel) are transmitted after a delay in their corresponding clock period. If the priorities are the same, data access instructions are transmitted in order from the one with the smallest physical distance to the other to the one with the largest physical distance. Specifically, this can be described as classifying data access instructions into different channels, and the instruction transmission order is obtained by arranging the data access instructions within each channel in order from the one with the smallest physical distance to the other to the one with the largest physical distance to the other.

[0110] In this embodiment, a priority is set for each data access command, and high-priority commands are issued as quickly as possible to match the user's expectations for return time. Furthermore, by using multi-channel transmission and separating the transmission of data access commands within high and low-speed channels, slow requests from the slow channel with longer processing times do not put excessive strain on the bandwidth of fast requests from the high-speed channel with shorter processing times.

[0111] For example, when an N-level data proxy module performs the operation of caching destination data returned by each data access instruction in a corresponding first-level data proxy module, it includes performing the following operations: For each data access instruction, it caches the destination data returned by the data access instruction in a first-level cache node or shared memory connected to the compute core that uses the destination data. For example, the corresponding first-level data proxy module includes multiple cache blocks, the multiple cache blocks are mapped to the first-level cache node or shared memory, and the multiple cache blocks are used to cache the received destination data.

[0112] For example, assuming that data access instruction 1 is sent by a computing core in Figure 5, the computing core must use the destination data 1 returned by data access instruction 1 to read the destination data 1 from memory via an N-level data proxy module and cache it in a first-level cache node or shared memory connected to the computing core. Specifically, the first-level data proxy module may contain multiple cache blocks, and these cache blocks are mapped to the first-level cache node or shared memory. That is, the cache blocks actually use the first-level cache node or shared memory to cache the received destination data. For example, as shown in Figures 1 and 2, the first-level cache node may be an L1 cache, and as shown in Figure 2, the shared memory may be shared memory connected to the computing core.

[0113] As a result, the destination data returned by each data access instruction is cached in a first-level cache node or shared memory that is very close to the compute core. When the compute core needs the destination data, it can send a data access instruction to the corresponding first-level data proxy module, which then returns the destination data cached in the first-level cache node or shared memory directly to the target register. Because the first-level cache node or shared memory is closest to the compute core, has high bandwidth and fast data transfer rates, and does not need to retrieve data from memory, data latency is significantly reduced. In addition, since the register is only occupied when the destination data is used, data latency is short, which in turn significantly reduces register occupancy time, conserves register resources, reduces resource consumption, and improves data access efficiency.

[0114] For example, as described above, each data proxy module has an electrical connection relationship similar to that of its corresponding cache node. That is, the electrical connections between corresponding data proxy modules follow the same relationship as the electrical connections between cache nodes. Taking the i-th level data proxy module within an N-level data proxy module as an example, at least one i-th level cache node corresponds one-to-one with at least one i-th level data proxy module, and at least some of the i-th level data proxy modules corresponding to i-th level cache nodes are electrically connected to the i+1-th level data proxy module corresponding to one i+1-th level cache node.

[0115] For example, the electrical connection relationship between a Level 1 data proxy module and a compute core is the same as the electrical connection relationship between the corresponding Level 1 cache node and the compute core. That is, depending on which compute core a Level 1 cache node is electrically connected to, the corresponding Level 1 data proxy module will also be electrically connected to those compute cores.

[0116] For example, the Nth-level data proxy module is further electrically connected to memory.

[0117] Figure 6 is a schematic block diagram of a data proxy module provided by at least one embodiment of the present disclosure.

[0118] For example, the data proxy module may be any i-th level data proxy module or an N-th level data proxy module. That is, each data proxy module has the same structure as shown in Figure 6.

[0119] As shown in Figure 6, the data proxy module 200 includes a scheduler 201, a request status list 202, and a data request list 203.

[0120] The data request list 203 is used to cache data access instructions awaiting transmission and contains instruction information for the data access instructions. For example, the instruction information includes the input and output parameters of the data access instruction, where the input parameter includes the address to read the destination data and the output parameter includes the address of the target register. Furthermore, a unique corresponding request number may be assigned to each data access instruction, and the instruction information may further include that request number.

[0121] For example, if P data access instructions can be cached in the data request list 203, and P is less than the total number of data access instructions in the data access instruction sequence, then, in accordance with the order in the data access instruction sequence, the first P data access instructions are first cached in the data request list 203, and after the processing of the data access instructions is complete, the (P+1)th data access instruction is retrieved from the data access instruction sequence and cached in the data request list 203, and so on. Here, P is a positive integer.

[0122] For example, as shown in Figure 6, the data request list 203 has multiple channels (multiple rectangular boxes in the data request list 203), including, for example, the first channel, the second channel, etc., and each channel is used to cache at least one data access instruction. The physical distances corresponding to data access instructions in different channels are different.

[0123] For example, the physical distance corresponding to a data access instruction can be determined by the read address within the data access instruction. For instance, when caching data access instructions in the data request list 203, the corresponding physical distance is determined based on the read addresses of different data access instructions, and the data access instructions are cached in different channels based on the corresponding physical distances. For example, data access instructions whose read addresses are in near memory are placed in the first channel, and data access instructions whose read addresses are in far memory are placed in the second channel. A detailed explanation of channels can be found in the relevant sections above, so it will not be elaborated here.

[0124] The scheduler 201 is used to sequentially send data access instructions cached in the data request list 203 according to the instruction transmission order, and to send the received destination data to the corresponding compute core or cache block in an electrically connected higher-level data proxy module.

[0125] For example, a first-level data proxy module, in response to receiving a data access instruction sent by a computing core electrically connected to the first-level data proxy module, determines the cache block associated with the transmitted data access instruction and sends the data in the associated cache block to the target register indicated by the data access instruction.

[0126] For data proxy modules at levels other than the first level, for example, the i+1th level data proxy module, when the scheduler 201 of the i+1th level data proxy module receives a data request signal from a higher level data proxy module (for example, the i-th level data proxy module), it sends the destination data of the data access command corresponding to the data request signal to the i-th level data proxy module.

[0127] The request state list 202 contains multiple state items. Here, each state item within the multiple state items is used to indicate the cache block associated with the data access instruction corresponding to the state item, the position of the data access instruction corresponding to the state item in the instruction transmission sequence, and so on.

[0128] As shown in Figure 6, the data proxy module further includes a plurality of cache blocks, for example, cache blocks 0 to N, used to cache destination data received by the data proxy module.

[0129] For example, the destination data received by the Nth-level data proxy module may come from memory, and the destination data received by the i-th-level data proxy module may come from a lower-level data proxy module, i.e., the i+1th-level data proxy module.

[0130] For example, before executing a task, the data processor is further configured to select at least one cache line from the cache nodes corresponding to each data proxy module and map it to the cache blocks within the data proxy module.

[0131] For example, as shown in Figure 6, a cache node contains multiple cache lines, and a cache line is the basic unit of the cache. Each cache line is mapped to one cache tag according to one of the following mapping relationships: direct mapping, set associative, or full associative. That is, each cache tag has a one-to-one fixed mapping relationship or static mapping relationship with one cache line. For example, each cache tag contains a virtual address (VA), access information (age count), and reference information (reference count / ref_cnt), etc.

[0132] As shown in Figure 6, several cache lines are selected from the cache nodes corresponding to the data proxy module 200 to generate a mapping relationship with the cache blocks. In other words, the destination data actually cached in the cache blocks is stored in the mapped cache lines.

[0133] Of course, as mentioned above, cache blocks within the data proxy module may be mapped to shared memory within the compute unit. For example, on-chip memory may be used to map the cache blocks.

[0134] When cache blocks are mapped using first-level cache nodes and shared memory, the distance between them and the computing cores is shortest, data transfer bandwidth is high, and speed is fast, which reduces data wait latency, shortens register occupancy time, reduces resource consumption, and improves data access efficiency.

[0135] For example, received destination data needs to be stored in the corresponding cache block, and the data access instruction associated with that corresponding cache block is used to load that destination data.

[0136] For example, each cache block has a unique corresponding cache block number, and as shown in Figure 6, the status item includes the cache block number and request number used to indicate the data access instruction corresponding to the status item and the cache block associated with that data access instruction. For example, by setting the cache block number and request number within the status item, one data access instruction can be associated with one cache block, and the destination data returned by that data access instruction is stored in the associated cache block.

[0137] For example, in some embodiments, as shown in Figure 6, the status item further includes a channel number representing the channel to which the data access instruction (identified by the request number) corresponding to the status item belongs. For example, the first channel is designated with channel number 0, the second channel with channel number 1, and so on. For example, the channel number is used to indicate the position of the data access instruction in the instruction transmission sequence, and the channel to which the data access instruction belongs can be determined by the channel number, and the instruction is transmitted according to the process described above.

[0138] For example, when the scheduler 201 sends a data access instruction cached in the data request list 203, it arranges the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to the data access instructions in different channels, obtains the instruction transmission order of the data access instructions cached in the data request list 203, and transmits these data access instructions in order according to this instruction transmission order. For example, assuming that there are two channels in the data request list 203, with the first channel being a high-speed channel and the second channel being a low-speed channel, the scheduler first transmits the data access instructions belonging to the first channel, and then transmits the data access instructions belonging to the second channel. Data access instructions belonging to the same channel are transmitted serially according to the relative order relationship within the data access instruction sequence.

[0139] For example, in some embodiments, as shown in Figure 6, the status item may further include priority, and the channel number and priority together indicate the position of the data access command in the command transmission order.

[0140] For example, when a status item includes priority, as described above, when the scheduler 201 sends data access instructions cached in the data request list 203, it first considers the priority and sends the data access instructions with the highest priority first. Then, for the other data access instructions with lower priority, it still uses the channel as a unit and sends them in order from the one with the smallest physical distance corresponding to the data access instructions in different channels to the one with the largest physical distance. The specific process of determining priority and sending instructions using channel numbers and priority can be found in the content described above, so it will not be described in detail here.

[0141] For example, the status item may include only the channel number and not the priority, in which case the channel number is used to determine the position of the data access instruction in the instruction transmission order. For example, the status item may include both the channel number and the priority, in which case the channel number and the priority are used to determine the position of the data access instruction in the instruction transmission order.

[0142] For example, as shown in Figure 6, the status item further includes request reception status information and request transmission status information used to indicate the current state of the data access command, and the user can perform status monitoring of the data access command based on the request reception status information and request transmission status information.

[0143] For example, request reception status information includes the following three types of states: The first state is a state in which no request has been received, for example, a state in which there is no binding to any data access instruction after the initialization of the status item. The second state is a state in which a request is being received, for example, a state in which a higher-level data proxy module is synchronizing a data access instruction. The third state is a state in which a request already exists, for example, a state in which the status item already has a corresponding data access instruction, and for example, the request number of that data access instruction has already been entered in the corresponding position of the status item.

[0144] For example, request transmission status information includes the following three states: The first state is when no request has been received, for example, when there is no binding to any data access instructions after the initialization of the status item. The second state is when a request is being transmitted, for example, when data access instructions are being synchronized or transmitted to memory or a lower-level data proxy module. The third state is when the request has already been sent, for example, when the request has already completed transmission.

[0145] For example, as shown in Figure 6, the status item further includes data status information used to indicate the current state of the destination data returned by the data access command.

[0146] For example, data state information includes the following four states: The first state is empty, for example, a state where there is no binding to any data access instructions after the state item has been initialized. The second state is waiting for data, for example, a state where a data access instruction or data request signal has already been sent and the system is waiting for the data to be returned. The third state is receiving data, indicating that the data has already been returned from memory or a lower-level data proxy module. The fourth state is that the data already exists, for example, a state where the data has already been cached in the corresponding cache block.

[0147] The specific settings for the requested reception status information, requested transmission status information, and data status information can be adjusted as needed, and therefore this disclosure does not specifically limit them.

[0148] For example, initialize each data proxy module before executing a task.

[0149] For example, the first-level data proxy module is configured to select at least one data access instruction from the data access instruction sequence in the order of the sequence and to perform an initialization operation on at least one data access instruction before executing a task. Here, the at least one data access instruction is executed by a computing core electrically connected to the first-level data proxy module.

[0150] For example, a first-level data proxy module selects at least one data access instruction from among the data access instructions executed by a computing core electrically connected to a first-level cache node corresponding to the first-level data proxy module, in accordance with the order of these data access instructions in the data access instruction sequence. This order refers to the original order of the data access instruction sequence, i.e., the order in which the data access instructions appear in the program code corresponding to the task. In the initialization phase before executing the task, P data access instructions are selected and cached in the data request list, and initialization operations are performed. When task execution begins, after the destination data of the data access instructions is sent to the target register, one or more data access instructions that have not yet been sent are selected from the data access instruction sequence in order, cached in the data request list, and initialization operations are performed.

[0151] For example, when a first-level data proxy module performs an initialization operation for at least one data access instruction, it includes performing the following operations: caching at least one data access instruction in the first-level data proxy module's data request list; initializing the state item corresponding to at least one data access instruction and storing it in the first-level data proxy module's request state list; and synchronizing at least one data access instruction and the corresponding state item with other level data proxy modules that have a direct or indirect electrical connection relationship with the first-level data proxy module.

[0152] For example, when a first-level data proxy module caches at least one data access instruction in its data request list, it caches at least one data access instruction on the corresponding channel based on the physical distance corresponding to the at least one data access instruction.

[0153] For example, when the first-level data proxy module initializes a state item corresponding to at least one data access instruction, it sets the cache block number and request number within the state item and determines the data access instruction and associated cache block corresponding to that state item. The specific process will be described later and will not be detailed here.

[0154] Based on the read address within the data access instruction, the physical distance corresponding to the data access instruction can be determined, and the channel number can be set within the status item. If the status item includes a priority, the priority within the status item may also be set based on the priority of the acquired data access instruction.

[0155] Additionally, the request reception status information, request transmission status information, and data status information are set as initial values, but these will not be described in detail here.

[0156] Subsequently, the first level data proxy module synchronizes these data access commands and their corresponding state items with other level data proxy modules with which it has a direct or indirect electrical connection.

[0157] For example, other level data proxy modules include second-level data proxy modules to the Nth-level data proxy modules, and electrical connection relationships are determined based on the electrical connection relationships between the corresponding cache nodes. For example, the information to be synchronized includes instruction information and status items of data access commands. For example, after synchronization, the data access commands awaiting transmission are also stored in the data request lists of other level data proxy modules, and the corresponding status items are stored in the request status lists. For example, for the Nth-level data proxy module, the data access commands and their status items selected by all first-level data proxy modules are stored.

[0158] For example, for any data proxy module, in response to the existence of unassociated cache blocks within the data proxy module, the unassociated cache blocks are associated with one data access instruction selected from the data request list of the data proxy module in the order of instruction transmission. For example, an unassociated cache block refers to a cache block that has not yet established an association with any data access instruction, and an unassociated cache block can be identified by the request number and cache block number in the status item.

[0159] For example, when a data proxy module associates an unassociated cache block with a data access instruction selected from the data proxy module's data request list in the order of instruction transmission, it performs the following operations: set the request number of the data access instruction and the cache block number of the unassociated cache block in the state item corresponding to the data access instruction, and associate the unassociated cache block with the data access instruction.

[0160] For example, the Nth-level data proxy module is configured to sequentially send cached data access instructions to memory according to the instruction transmission order of the data access instructions cached in the Nth-level data proxy module's data request list, and to receive the destination data returned sequentially from memory and store each returned destination data in the cache block associated with the corresponding data access instruction.

[0161] In other words, when transporting data from the first block begins, the Nth-level data proxy module sends the first data access instruction that needs to be sent, determined based on the instruction transmission order, to memory, and stores the received destination data in the cache block associated with that data access instruction. If there are still available cache blocks, it sends the second data access instruction that needs to be sent, determined based on the instruction transmission order, to memory, stores the received destination data in the cache block associated with that data access instruction, and so on.

[0162] For first-level data proxies to the (N-1)-level data proxy modules, i.e., the i-th level data proxy module, it is configured to send a data request signal to the electrically connected i+1-th level data proxy module in response to the existence of free cache blocks within the i-th level data proxy module, and to cache the received return data in the cache block associated with the data access instruction corresponding to the transmitted data request signal. For example, the i+1-th level data proxy module is configured to send the destination data of the data access instruction corresponding to the data request signal to the i-th level data proxy module that transmitted the data request signal in response to receiving the data request signal.

[0163] For example, an empty cache block refers to a cache block that already has a data access instruction associated with it, but does not store any data, and has not sent any data access instructions associated with that cache block. An empty cache block can be determined by data status information and request transmission status information.

[0164] For example, when the i-th level data proxy module discovers that there is an empty cache block, it sends a data request signal NEED_DATA to the i+1-th level data proxy module. When the i+1-th level data proxy module receives the NEED_DATA signal, it determines the destination data for the data access instruction corresponding to the NEED_DATA signal from the cache block and sends the destination data to the i-th level data proxy module. The i-th level data proxy module then caches the received return data in a cache block, and that cache block is associated with the data access instruction corresponding to the transmitted data request signal.

[0165] Through the process described above, the Nth-level data proxy module caches the destination data read from memory in its own cache block. The (N-1)th-level data proxy module then retrieves the destination data from the Nth-level data proxy module and caches it in its own cache block. This process continues until the destination data is cached in the cache block of the first-level data proxy module. Furthermore, each data proxy module retrieves the destination data according to the same command transmission sequence.

[0166] This allows data access instructions to be sent earlier, and by pre-caching memory data in the first-level data proxy module, data can be read directly from the first-level data proxy module when the destination data is used, eliminating the need to read data from memory and reducing data waiting time. Furthermore, since the data is cached in the cache block of the first-level data proxy module, even if data access instructions are sent early, there is no need to occupy the target register in advance, thus reducing the occupancy time of the target register, lowering resource consumption, and improving data access efficiency.

[0167] For example, the first-level data proxy module is configured to, in response to receiving a data access instruction sent by a computing core electrically connected to a first-level cache node corresponding to the first-level data proxy module, determine the cache block associated with the transmitted data access instruction and send the data in the associated cache block to the target register indicated by the data access instruction; delete the data access instruction associated with the associated cache block from the data request list of the first-level data proxy module and clear the state item corresponding to the deleted data access instruction in the request state list of the first-level data proxy module; and select at least one data access instruction in order from the data access instruction sequence and perform an initialization operation on that at least one data access instruction.

[0168] For example, after the first-level data proxy module sends data to the computing core, it removes the data access instruction from the data request list and clears the state item corresponding to the removed data access instruction in the request state list, which can then be reused for other data access instructions. Subsequently, it selects one data access instruction from the data access instruction sequence and caches it in the data request list, while performing initialization operations according to the process described above. This includes, for example, setting state items, caching to the corresponding channel in the data request list based on the physical distance corresponding to the data access instruction, and synchronization with other level data proxy modules, but these will not be described in detail here.

[0169] For other level data proxy modules, taking the i+1 level data proxy module as an example, the i+1 level data proxy module is further configured to remove a data access instruction associated with one of the cache blocks from the data request list of the i+1 level data proxy module and to clear the state entry corresponding to the removed data access instruction in the request state list of the i+1 level data proxy module in response to destination data cached in any one of the cache blocks within the i+1 level data proxy module already being sent to the i level data proxy module.

[0170] For example, after deleting and erasing information related to the data access instruction, the i+1 level data proxy module can associate the cache block with other unassociated data access instructions in the data request list.

[0171] Figure 7 is a schematic block diagram of a data processor provided by at least one embodiment of the present disclosure.

[0172] For example, the data processor shown in Figure 7 may be a general-purpose graphics processor or a graphics processor. The data processor includes multiple computing units. The structure of Figure 7 will not be described in detail here, as it can be found in the related explanation in Figure 2.

[0173] For example, if N=2, the first level cache within the N-level cache includes multiple first-level cache nodes, each used for data sharing within a single computing unit, and each first-level cache node may be the L1 cache or shared memory in Figure 7. The second level cache within the N-level cache includes one second-level cache node, which is used for data sharing between all computing units, and the second-level cache node may be the L2 cache in Figure 7, i.e., the global cache.

[0174] For example, each first-level cache node corresponds to one first-level data proxy module, and each second-level cache node corresponds to one second-level data proxy module. For example, in Figure 7, one first-level data proxy module is provided within each computing unit in Figure 7, and this first-level data proxy module is electrically connected to all computing cores within the computing unit. One second-level data proxy module is provided that corresponds to the L2 cache, and this second-level data proxy module is electrically connected to memory and all first-level data proxy modules.

[0175] For example, using the data processor shown in Figure 7 as an example, we will specifically explain the process by which the multilevel data proxy module performs data access instruction scheduling and data caching.

[0176] Figures 8A to 8G are schematic diagrams of the processing steps of a multilevel data proxy module provided by at least one embodiment of the present disclosure.

[0177] First, as shown in Figure 8A, the computing core initializes each level data proxy module before starting task execution.

[0178] For example, initializing each level data proxy module involves allocating cache blocks to each data proxy module, for instance, by selecting several cache lines or memory lines from a first-level cache node or shared memory to map cache blocks within the first-level data proxy module, and by selecting several cache lines from a second-level cache node to map cache blocks within the second-level data proxy module. The first-level data proxy module also selects several data access instructions in order from a data access instruction sequence and performs initialization operations on these instructions. For example, the initialization operation includes caching these data access instructions in the corresponding channels in the data request list of the first-level data proxy module, initializing the state items corresponding to these data access instructions and saving them in the request state list of the first-level data proxy module, and synchronizing these data access instructions and corresponding state items with other level data proxy modules (i.e., second-level data proxy modules) that have a direct or indirect electrical connection relationship with the first-level data proxy module. The specific process is as described above and will not be detailed here.

[0179] After initializing each level data proxy module, the data request list of each data proxy module caches data access commands awaiting transmission, and these cached data access commands are already categorized according to the channel. In addition, the status items corresponding to the data access commands have been initialized and are stored in the request status list of each data proxy module.

[0180] For example, as shown in Figure 8A, the first channel caches five data access instructions, which are data access instructions Req#0, Req#1, Req#2, Req#3, and Req#4, respectively. For example, the first-level data proxy module includes multiple channels, each capable of caching up to five data access instructions, and selects data access instructions according to their order from front to back within the data access instruction sequence. If the physical distance corresponding to the first data access instruction Req#0 in the data access instruction sequence is very small, for example, assuming that the read address of that data access instruction Req#0 is in near memory, it is cached in the first channel, and so on. For example, the first channel is a high-speed channel, and the order of data access instructions Req#0 to Req#4 is the same as the relative order within the data access instruction sequence.

[0181] For example, as shown in Figure 8A, each data proxy module provides two cache blocks, which are cache block 0 and cache block 1. In each data proxy module, for example, during the initialization phase, settings are made to associate data access instruction Req#0 with cache block 0 and data access instruction Req#1 with cache block 1.

[0182] Subsequently, as shown in Figure 8B, when transporting data from the first block begins, the second-level data proxy module selects one data access instruction from the data request list according to the instruction transmission order and sends it to memory. For example, it selects the first data access instruction Req#0 on the first channel (high-speed channel) and sends it to memory. It then receives the destination data Data#0 of the data access instruction Req#0 returned from memory and stores it in cache block 0 of the second-level data proxy module associated with the data access instruction Req#0.

[0183] Subsequently, as shown in Figure 8C, the transport of the second block of data is initiated, and the destination data Data#0 is returned to the first-level data proxy module.

[0184] For example, since cache block 1 in the second-level data proxy module is free, the scheduler of the second-level data proxy module sends data access instruction Req#1 to memory, receives the destination data Data#1 of data access instruction Req#1 returned from memory, and stores it in cache block 1 of the second-level data proxy module associated with data access instruction Req#1.

[0185] For example, since cache block 0 in the first-level data proxy module is free, the scheduler of the first-level data proxy module sends a data request signal to the second-level data proxy module, indicating that destination data for data access instruction Req#0 is required. After receiving the data request signal, the second-level data proxy module sends destination data Data#0 to the first-level data proxy module, removes data access instruction Req#0 from the data request list of the second-level data proxy module, and clears the status item corresponding to data access instruction Req#0 in the request status list. That is, at this time, cache block 0 of the second-level data proxy module can also be associated with other data access instructions, for example, it can be associated with data access instruction Req#2. After receiving destination data Data#0, the first-level data proxy module stores it in cache block 0 associated with data access instruction Req#0.

[0186] For example, as shown in Figure 8D, when the computing core sends data access instruction Req#0 to the first-level data proxy module, the first-level data proxy module returns the data Data#0 in cache block 0 associated with data access instruction Req#0 to the target register. Subsequently, it removes data access instruction Req#0 from the data request list of the first-level data proxy module and clears the state item corresponding to data access instruction Req#0 in the request state list of the first-level data proxy module. That is, at this time, cache block 0 can be associated with other data access instructions, for example, with data access instruction Req#2.

[0187] Subsequently, as shown in Figure 8E, the first-level data proxy module selects data access instruction Req#5 from the data access instruction sequence in order and caches it in the data request list of the first-level data proxy module. For example, the physical distance corresponding to data access instruction Req#5 is relatively small and therefore classified as the first channel. At the same time, the state item corresponding to data access instruction Req#5 is initialized and stored in the request state list of the first-level data proxy module. Furthermore, data access instruction Req#5 and the corresponding state item are synchronized with the second-level data proxy module.

[0188] For example, as shown in Figure 8E, since cache block 1 in the first-level data proxy module is free, the scheduler of the first-level data proxy module sends a data request signal to the second-level data proxy module, which indicates that destination data for data access instruction Req#1 is required. After receiving the data request signal, the second-level data proxy module sends destination data Data#1 to the first-level data proxy module, removes data access instruction Req#1 from the data request list of the second-level data proxy module, and clears the status item corresponding to data access instruction Req#1 in the request status list. That is, at this time, cache block 1 of the second-level data proxy module can also be associated with other data access instructions, for example, it can be associated with data access instruction Req#3. After receiving destination data Data#1, the first-level data proxy module stores it in cache block 1 associated with data access instruction Req#1.

[0189] As shown in Figure 8E, since cache block 0 in the second-level data proxy module is also free, the scheduler of the second-level data proxy module sends data access instruction Req#2 to memory, receives the destination data Data#2 of data access instruction Req#2 returned from memory, and stores it in cache block 0 of the second-level data proxy module associated with data access instruction Req#2.

[0190] For example, as shown in Figure 8F, when the computing core sends data access instruction Req#1 to the first-level data proxy module, the first-level data proxy module returns the data Data#1 in cache block 1 associated with data access instruction Req#1 to the target register. Subsequently, it removes data access instruction Req#1 from the data request list of the first-level data proxy module and clears the state item corresponding to data access instruction Req#1 in the request state list of the first-level data proxy module. That is, at this time, cache block 1 can also be associated with other data access instructions, for example, it can be associated with data access instruction Req#3.

[0191] Subsequently, as shown in Figure 8G, the first-level data proxy module selects data access instruction Req#6 from the data access instruction sequence in order and caches it in the data request list of the first-level data proxy module. For example, the physical distance corresponding to data access instruction Req#6 is relatively small and therefore classified as the first channel. At the same time, the state item corresponding to data access instruction Req#6 is initialized and stored in the request state list of the first-level data proxy module. Furthermore, data access instruction Req#6 and the corresponding state item are synchronized with the second-level data proxy module.

[0192] For example, as shown in Figure 8G, since cache block 0 in the first-level data proxy module is free, the scheduler of the first-level data proxy module sends a data request signal to the second-level data proxy module, which indicates that destination data for data access instruction Req#2 is required. After receiving the data request signal, the second-level data proxy module sends destination data Data#2 to the first-level data proxy module, removes data access instruction Req#2 from the data request list of the second-level data proxy module, and clears the status item corresponding to data access instruction Req#2 in the request status list. That is, at this time, cache block 0 of the second-level data proxy module can also be associated with other data access instructions, for example, it can be associated with data access instruction Req#4. After receiving destination data Data#2, the first-level data proxy module stores it in cache block 0 associated with data access instruction Req#2.

[0193] For example, as shown in Figure 8G, since cache block 1 in the second-level data proxy module is also free, the scheduler of the second-level data proxy module sends data access instruction Req#3 to memory, receives the destination data Data#3 of data access instruction Req#3 returned from memory, and stores it in cache block 1 of the second-level data proxy module associated with data access instruction Req#3.

[0194] By repeatedly executing the process described above, each data access instruction is sent sequentially according to the instruction transmission order, and the destination data returned from each data access instruction is cached in the corresponding first-level data proxy module, for example, the first-level cache node corresponding to the first-level data proxy module. As a result, even if data access instructions are sent relatively early, there is no need to occupy registers early, thus reducing register occupancy time. Furthermore, even if the transmission time of data access instructions is relatively late, for example, if they are sent only after the destination data is needed, the data only needs to be read from within the first-level data proxy module, thus reducing overall waiting time and improving data access efficiency.

[0195] Furthermore, the instruction transmission order is determined based on the original order of the data access instruction sequence and the distance between the storage location of the destination data for each data access instruction and the computing core. Instructions that are closer are sent first, and those that are farther away are sent later, so that slower requests do not burden the bandwidth of faster requests as much as possible. In some embodiments, the instruction transmission order is determined based on the original order of the data access instruction sequence, the distance between the storage location of the destination data for each data access instruction and the computing core, and the priority of each data access instruction, so that return times meet user expectations by issuing high-priority data access instructions as early as possible.

[0196] Figure 9A is a timing diagram of a data processor provided by at least one embodiment of the present disclosure.

[0197] As shown in Figure 9A, the computing core caches destination data from memory in the L1 cache relatively early based on the process described above. Therefore, even if the transmission time of data access instructions is relatively late, the overall waiting time is relatively short compared to the timing shown in Figure 4A, as it only needs to read the destination data from the first-level data proxy module.

[0198] Furthermore, since it is only necessary to read the destination data from the first-level data proxy module, as shown in Figure 9A, the register occupancy time is significantly reduced, resource consumption is reduced, and data access efficiency is improved compared to the timing shown in Figures 4B and 4C.

[0199] Figure 9B is a timing diagram of a data processor provided by at least one embodiment of the present disclosure.

[0200] As shown in Figure 9B, the computing core caches destination data from memory in the L1 cache relatively early according to the process described above, resulting in a relatively shorter register occupancy time compared to the timing shown in Figure 4D. Furthermore, this disclosure transmits data access instructions on a channel-by-channel basis, sending data access instructions closer to the computing core first and sending data access instructions further away from the computing core later, thereby minimizing the bandwidth burden on faster requests by slower requests. In addition, data access requests can be prioritized, and the time it takes to return data can be matched to user expectations by issuing high-priority data access instructions as early as possible.

[0201] It should be noted that the components and structure of the data processor 100 shown in Figure 5, etc., are merely illustrative and not limiting; therefore, the data processor 100 may have other components and structures as needed.

[0202] For example, these modules can be implemented as hardware (e.g., circuit) modules, software modules, or any combination thereof, and the following embodiments are similar and will not be described again here.

[0203] For example, such a data processor can be implemented using a central processing unit (CPU), a graphics processor, a general-purpose graphics processor, a digital signal processor, or other general-purpose processors, or a dedicated processor such as a tensor processing unit (TPU), a neural network processing unit (NPU), or other types of processing units having data processing capabilities and / or instruction execution capabilities, along with corresponding computer instructions.

[0204] It should be noted that in embodiments of this disclosure, the data processor 100 may include more or fewer circuits or units, and the connections between each circuit or unit are not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and may consist of analog devices based on circuit principles, digital chips, or other applicable configurations.

[0205] At least one embodiment of the present disclosure further provides a data processing method. Figure 10 is a schematic flowchart of the data processing method provided by at least one embodiment of the present disclosure.

[0206] For example, this data processing method is used in a data processor that includes an N-level cache and memory.

[0207] For example, the data processor may be a central processing unit (CPU), a graphics processor, a general-purpose graphics processor, a tensor processing unit (TPU), a neural network processor (NPU), etc., and this disclosure does not specifically limit it.

[0208] For example, a data processor can employ an architecture similar to that shown in Figure 1 or Figure 2 above.

[0209] The i-th level cache in an N-level cache contains at least one i-th level cache node, and at least some of the i-th level cache nodes in at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1 and i is any positive integer from 1 to N-1.

[0210] The Nth level cache within the N-level cache is electrically connected to memory, and each first level cache node is electrically connected to the corresponding computing core.

[0211] For details regarding N-level caches, memory, and computing cores, please refer to the relevant explanations for the data processor described above; therefore, any overlapping sections will not be elaborated upon.

[0212] As shown in Figure 10, the data processing method provided by at least one embodiment of the present disclosure includes at least steps S10 to S40.

[0213] In step S10, the data processor obtains the data access instruction sequence within the currently executing task.

[0214] For example, a data access instruction sequence is obtained by arranging all data access instructions within a task according to their relative positions in the program corresponding to that task.

[0215] For specific details regarding obtaining data access instruction sequences, please refer to the explanation of the relevant parts in the data processor described above; therefore, we will not elaborate on any overlapping sections.

[0216] In step S20, the instruction transmission order of the data access instruction sequence is adjusted based on the storage location of the destination data for each data access instruction in the data access instruction sequence.

[0217] For example, in some embodiments, step S20 includes obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the physical distance between the memory storage location of the destination data for each data access instruction and the computing core in the data processor, and adjusting the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, where data access instructions with smaller corresponding physical distances are transmitted earlier.

[0218] For example, the physical distance corresponding to each data access instruction can be obtained from the read address within that instruction.

[0219] The instruction transmission order of a data access instruction sequence is adjusted based on the differences in the physical distances corresponding to each data access instruction. For example, the transmission order is adjusted according to the physical distance corresponding to each data access instruction, based on the original data access instruction sequence. For instance, data access instructions with smaller physical distances are transmitted earlier, meaning they are placed earlier in the instruction transmission order, while data access instructions with larger physical distances are transmitted later, meaning they are placed later in the instruction transmission order. For example, data access instructions with the same physical distance are transmitted in order according to their relative order within the data access instruction sequence.

[0220] For example, adjusting the instruction transmission order of a data access instruction sequence based on the physical distance corresponding to each data access instruction includes classifying each data access instruction into different channels based on the physical distance corresponding to each data access instruction, acknowledging that the physical distances corresponding to data access instructions within different channels are different, and arranging the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to data access instructions within different channels, thereby obtaining the instruction transmission order. Here, in the instruction transmission order, data access instructions belonging to the first channel are transmitted first, data access instructions belonging to the second channel are transmitted last, data access instructions belonging to the same channel are transmitted serially according to their relative order within the data access instruction sequence, the physical distance corresponding to data access instructions in the first channel is the smallest, and the physical distance corresponding to data access instructions in the second channel is the largest.

[0221] For example, multiple channels can be configured within a data proxy module, and data access instructions can be classified into different channels based on their corresponding physical distance. For instance, data access instructions whose destination data is in the same memory block may be classified into one channel, or data access instructions whose destination data is in multiple memory blocks that are relatively close to each other may be placed in a single channel.

[0222] Further details regarding the adjustment of the instruction transmission order of data access instruction sequences based on the physical distance corresponding to each data access instruction can be found in the relevant explanations in the data processor described above, and therefore, any overlapping sections will not be elaborated upon.

[0223] In the embodiment described above, channels are introduced to classify and manage data access instructions. Based on the difference in distance between the storage location where the destination data to be loaded resides and the computing core, data access instructions are classified into different channels, with instructions sent to the closer channel being given priority and instructions sent to the farther channel being sent later. By sending data access instructions corresponding to different physical distances separately, requests from farther distances are prevented from overwhelming the bandwidth of requests from nearby, and the return time of destination data is brought as close as possible to the user's expectations.

[0224] For example, in some other embodiments, step S20 may include obtaining the priority of each data access instruction, obtaining the physical distance corresponding to each data access instruction, where the physical distance corresponding to each data access instruction is the physical distance between the memory storage location of the destination data of each data access instruction and the computing core in the data processor, and adjusting the instruction transmission order of the data access instruction sequence based on the priority of each data access instruction and the corresponding physical distance, where data access instructions with higher priority are transmitted faster, and in the case of the same priority, data access instructions with a smaller corresponding physical distance are transmitted faster.

[0225] For example, obtaining the priority of each data access instruction could involve determining the priority of each data access instruction based on the time it takes for each instruction to return the destination data when the task is pre-executed. Here, when the task is pre-executed, each data access instruction is sent in order according to the order in the data access instruction sequence, and the time it takes for each instruction to return the destination data is collected.

[0226] Further details regarding obtaining the priority of each data access instruction can be found in the relevant explanations for the data processor described above; therefore, we will not elaborate on any overlapping sections.

[0227] In the adjusted instruction transmission order, the priority of data access instructions is given priority, followed by the channel to which they belong. For example, data access instructions with higher priority are transmitted earlier, so even if they belong to a slow channel, they are transmitted preferentially, while other data access instructions (e.g., those with lower priority but located on a fast channel) are transmitted after a delay in their corresponding clock cycle. If the priorities are the same, data access instructions are transmitted in order from the one with the smallest physical distance to the other to the one with the largest physical distance. Specifically, this can be described as classifying data access instructions into different channels, and the instruction transmission order is obtained by arranging the data access instructions within each channel in order from the one with the smallest physical distance to the other to the one with the largest physical distance to the other.

[0228] In this embodiment, a priority is set for each data access command, and high-priority commands are issued as quickly as possible to match the user's expectations for return time. Furthermore, by using multi-channel transmission and separating the transmission of data access commands within high and low-speed channels, slow requests from slow channels with long processing times do not put excessive strain on the bandwidth of high-speed requests from high-speed channels with short processing times.

[0229] Specific details regarding the adjustment of the instruction transmission order of data access instruction sequences based on priority and physical distance can be found in the relevant explanations for the data processor described above; therefore, any overlapping details will not be elaborated here.

[0230] In step S30, each data access command is sent sequentially according to the command transmission order.

[0231] For example, each data access instruction is sent to memory in order according to the instruction transmission sequence.

[0232] In step S40, the destination data returned by each data access instruction is cached in a first-level cache node connected to the compute core that uses the destination data, or in shared memory.

[0233] For example, the first level cache node may be an L1 cache, and the shared memory may be the shared memory within the computing unit shown in Figure 2.

[0234] A data processing method provided by at least one embodiment of this disclosure can cache destination data in advance in a storage unit closest to the computing core, such as a first-level cache node or shared memory, for example, in an L1 cache or shared memory. As a result, even if the transmission time of data access instructions is relatively slow, it is only necessary to read the destination data from the first-level cache node or shared memory, thus shortening the overall waiting time, significantly reducing register occupancy time, reducing resource consumption, and improving data access efficiency. Furthermore, in this data processing method, data access instructions are transmitted channel by channel, with data access instructions closer to the computing core transmitted first and data access instructions further away from the computing core transmitted later, so that slow requests do not burden the bandwidth of fast requests as much as possible. In addition, data access requests can be prioritized, and high-priority data access instructions can be issued as early as possible to match the data return time to the user's expectations.

[0235] For example, the data processor further includes an N-level data proxy module. Here, each level data proxy module within the N-level data proxy module corresponds one-to-one with each level cache within the N-level cache. For example, the N-level data proxy module can be used to implement steps S10 to S40 described above. The specific process for implementing steps S10 to S40 using the N-level data proxy module can be found in the related description of the data processor described above, so any overlapping parts will not be detailed here.

[0236] Of course, this disclosure is not limited thereto, and steps S10 to S40 described above may be implemented by other methods. For example, the data processing method described in at least one embodiment of this disclosure may be implemented by other hardware methods such as modular structures or software methods such as program code. Therefore, this disclosure is not specifically limited thereto.

[0237] Figure 11 is a schematic block diagram of an electronic device provided by one embodiment of the present disclosure. As shown in Figure 11, the electronic device 300 is suitable for use, for example, to implement a data processing method provided by an embodiment of the present disclosure. It should be noted that the components of the electronic device 300 shown in Figure 11 are illustrative and not limiting, and the electronic device 300 may have other components depending on the actual application needs.

[0238] As shown in Figure 11, the electronic device 300 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various functions by executing various appropriate operations and processes in accordance with non-temporary computer-readable instructions stored in memory.

[0239] For example, when a computer-readable instruction is executed by the processing unit 301, one or more steps of the data processing method described in any of the embodiments described above can be executed. For the purposes of this explanation, a detailed explanation of the processing steps of the data processing method can be found in the relevant descriptions in the embodiments of the data processing method described above; therefore, any overlapping details will not be elaborated here.

[0240] For example, memory can include any combination of one or more computer program products, and computer program products can include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) 303 and / or cache, and for example, computer-readable instructions can be executed by loading them from storage device 308 into random access memory (RAM) 303. Non-volatile memory can include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB storage device, flash memory, etc. The computer-readable storage media can further store various application programs and various data, such as style images and various data used and / or generated by the application programs.

[0241] For example, the processing unit 301, the read-only memory 302, and the random access memory 303 are connected to each other via the bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0242] Typically, the following devices can be connected to an input / output interface 305, an input device 306 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 308 including, for example, magnetic tape, hard disk, flash memory, etc.; and a communication device 309. The communication device 309 can enable the electronic device 300 to exchange data with other electronic devices by wireless or wired communication. Figure 11 shows an electronic device 300 with various devices, but it should be understood that it is not necessary to implement or have all the devices shown, and the electronic device 300 may alternatively implement or have more or fewer devices. For example, a processor 301 can perform a desired function by controlling other components within the electronic device 300. The processor 301 may be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit, tensor processing unit, or graphics processing unit. The central processing unit may be an x86 or ARM architecture, etc. The graphics processing unit may be directly integrated on the motherboard, or it may be built into the motherboard's northbridge chip. The graphics processing unit may also be built into the central processing unit.

[0243] The technical effects of the electronic device 300 shown in Figure 11 are the same as those of the data processing method provided in this disclosure, and therefore will not be described in detail here.

[0244] Figure 12 is a schematic diagram of a non-temporary computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as shown in Figure 12, the storage medium 400 may be a non-temporary computer-readable storage medium, and one or more computer-readable instructions 401 can be stored non-temporarily on the storage medium 400. For example, when a computer-readable instruction 401 is executed by a processor, it can be executed according to the data processing method described above.

[0245] For example, the storage medium 400 can be applied to the electronic device described above, and for instance, the storage medium 400 may include memory within the electronic device 300.

[0246] For example, the storage medium may include a smartphone memory card, a tablet computer memory unit, a personal computer hard disk, random access memory, read-only memory, erasable programmable read-only memory, portable compact disk read-only memory, flash memory, or any combination of the above-mentioned storage mediums, or other applicable storage mediums.

[0247] For example, the description of the storage medium 400 can be found in the description of memory in the embodiment of the electronic device, so any overlapping sections will not be described in detail.

[0248] Some embodiments of this disclosure further provide other electronic devices. Figure 13 is a schematic block diagram of another electronic device provided by at least one embodiment of this disclosure.

[0249] For example, as shown in Figure 13, the electronic device 500 may include a data processor 501 described in any embodiment of this disclosure. For example, the data processor 501 may be the data processor 100 described above, so overlapping parts will not be described in detail.

[0250] It should be noted that the components of the electronic device 500 shown in Figure 13 are illustrative and not limiting, and the electronic device 500 may have other components depending on the actual application needs. For example, it may include more or fewer circuits or units, and may further include other circuits or units that support the operation of the data processor 501, and this disclosure is not specifically limiting.

[0251] The connections between each circuit or unit are not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and may consist of analog devices based on circuit principles, digital chips, or other applicable configurations.

[0252] As any engineer in the art will understand, the information disclosed herein is subject to various modifications and changes. For example, the various devices or components described above may be implemented by hardware, software, firmware, or a combination of some or all of these.

[0253] Furthermore, while this disclosure makes various references to specific units in a system based on embodiments of this disclosure, any number of different units may be used to operate on the client and / or server. The units are illustrative only, and different aspects of the system and method may use different units.

[0254] This disclosure uses flowcharts to illustrate the steps of a method based on embodiments of this disclosure. It should be understood that the preceding or succeeding steps do not necessarily proceed in exact order. Conversely, the various steps may be performed in reverse order or simultaneously. At the same time, other operations may be added to these processes.

[0255] As can be understood by an ordinary artist in the art, all or some of the steps in the above-described method can be completed by instructing the relevant hardware via a computer program, which can be stored in a computer-readable storage medium such as read-only memory, magnetic disk, or optical disk. Optionally, all or some of the steps in the above-described embodiments may be implemented using one or more integrated circuits. Correspondingly, each module / unit in the above-described embodiments may be implemented in hardware form or in software function module form. This disclosure is not limited to any particular form of hardware and software combination.

[0256] Unless otherwise defined, all terms used herein have the same meaning as that commonly understood by ordinary articulators in the art to which this disclosure pertains. Furthermore, terms defined in general dictionaries should be interpreted as having the same meaning as their meanings in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0257] The above is a description of the Disclosure and should not be considered an limitation thereto. While several exemplary embodiments of the Disclosure have been described as much as possible, many modifications can be made to the exemplary embodiments without departing from the novel teachings and merits of the Disclosure, as will be understandable to those skilled in the Art. Therefore, all such modifications are intended to be included within the scope of the Disclosure as limited by the appended claims. It should be understood that the above is a description of the Disclosure and should not be considered an limitation to any particular embodiment disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The Disclosure is limited by the claims and their equivalents. [Explanation of symbols]

[0258] S10~S40: Process 300:Electronic equipment 301: Processing Unit 302:ROM 303:RAM 304: Bus 305: I / O Interface 306: Input device 307: Output device 308: Storage device 309: Communication equipment 400:Storage medium 401: Computer-readable instruction 500: Electronic devices 501: Data Processor

Claims

1. A data processor including an N-level cache and memory, wherein the i-th level cache in the N-level cache includes at least one i-th level cache node, at least some of the i-th level cache nodes in the at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1, and i is any positive integer from 1 to N-1. The Nth level cache within the N-level cache is electrically connected to the memory, and each first level cache node is electrically connected to the corresponding computing core. The data processor further includes an N-level data proxy module, where each level data proxy module within the N-level data proxy module corresponds one-to-one with each level cache within the N-level cache. The N-level data proxy module is configured to acquire a data access instruction sequence in a task currently being executed by the data processor, adjust the instruction transmission order of the data access instruction sequence based on the memory location of the destination data for each data access instruction in the sequence, transmit each data access instruction in order according to the instruction transmission order, and cache the destination data returned by each data access instruction in the corresponding first-level data proxy module, the corresponding first-level data proxy module being a data processor corresponding to the first-level cache.

2. When the N-level data proxy module adjusts the instruction transmission order of the data access instruction sequence based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence, An operation to obtain the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in memory and the computing core in the data processor, Based on the physical distance corresponding to each data access command, the command transmission order is adjusted, and data access commands with smaller physical distances are transmitted faster. The data processor according to claim 1, which includes performing the following:

3. When the N-level data proxy module adjusts the instruction transmission order of the data access instruction sequence based on the physical distance corresponding to each data access instruction, Based on the physical distance corresponding to each of the aforementioned data access instructions, each of the aforementioned data access instructions is classified into different channels, and the physical distances corresponding to data access instructions within different channels are different operations. An operation to obtain the instruction transmission order by arranging the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to the data access instructions within each channel, with the channel as the unit; The data processor according to claim 2, comprising the execution of, in the instruction transmission order, data access instructions belonging to the first channel are transmitted first, data access instructions belonging to the second channel are transmitted last, data access instructions belonging to the same channel are transmitted serially according to the relative order relationship in the data access instruction sequence, the physical distance corresponding to the data access instructions in the first channel is the minimum, and the physical distance corresponding to the data access instructions in the second channel is the maximum.

4. The N-level data proxy module performs the operation of adjusting the instruction transmission order of the data access instruction sequence based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence. The operation to obtain the priority of each data access instruction, An operation to obtain the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in memory and the computing core in the data processor, Based on the priority and corresponding physical distance of each data access instruction, the instruction transmission order is adjusted, and in the instruction transmission order, data access instructions with higher priority are transmitted faster, and in the case of the same priority, data access instructions with a smaller corresponding physical distance are transmitted faster. The data processor according to claim 2, which includes performing the following:

5. The aforementioned N-level data proxy module performs the task of obtaining the priority of each data access instruction. The data processor according to claim 4, which includes performing an operation to determine the priority of each data access instruction based on the time it takes for each data access instruction to return destination data when the task is pre-executed, and when the task is pre-executed, it transmits each data access instruction in order according to the order in the data access instruction sequence and collects the time it takes for each data access instruction to return destination data.

6. When the N-level data proxy module performs the operation of caching the destination data returned by each data access command in the corresponding first-level data proxy module, A data processor according to any one of claims 1 to 5, comprising, for each data access instruction, performing an operation to cache the destination data returned by the data access instruction in a first-level cache node or shared memory connected to a compute core that uses the destination data, wherein the corresponding first-level data proxy module includes a plurality of cache blocks, the plurality of cache blocks are mapped to the first-level cache node or the shared memory, and the plurality of cache blocks are used to cache the received destination data.

7. The at least one i-th level cache node corresponds one-to-one with at least one i-th level data proxy module, and the i-th level data proxy modules corresponding to at least some of the i-th level cache nodes are electrically connected to the i+1-th level data proxy module corresponding to one i+1-th level cache node. A first-level data proxy module corresponding to each first-level cache node is electrically connected to at least one computing core, and the at least one computing core is electrically connected to the first-level cache node. The data processor according to any one of claims 1 to 6, wherein an Nth level data proxy module corresponding to the Nth level cache is electrically connected to the memory.

8. Each data proxy module includes a scheduler, a request state list, a data request list, and multiple cache blocks, and the data proxy module includes any i-th level data proxy module or the N-th level data proxy module. The aforementioned data request list is used to cache data access commands awaiting transmission. The scheduler is used to sequentially transmit the pending data access commands cached in the data request list according to the command transmission order, and to transmit the destination data received by the data proxy module to a cache block in the corresponding compute core or an electrically connected higher-level data proxy module. The request state list includes a plurality of state items, each state item in the plurality of state items is used to indicate the cache block associated with the data access instruction corresponding to the state item, and the position of the data access instruction corresponding to the state item in the instruction transmission sequence. The data processor according to claim 7, wherein the plurality of cache blocks are used to cache destination data received by the data proxy module.

9. Within the aforementioned data request list, multiple channels are configured to cache the data access commands awaiting transmission, and the physical distances corresponding to data access commands in different channels differ. The scheduler is configured to arrange the data access instructions within each channel in order from the smallest to the largest physical distance corresponding to the data access instructions within each channel, to obtain the instruction transmission order, and to transmit the data access instructions awaiting transmission in order according to the instruction transmission order. The data processor according to claim 8, wherein the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in the memory and the computing core in the data processor, and the physical distance corresponding to each data access instruction is determined by the read address of the destination data as an input parameter in each data access instruction.

10. The aforementioned data proxy module The data processor according to claim 8, configured to associate an unassociated cache block with a data access instruction selected from the data request list in accordance with the instruction transmission order, in response to the presence of an unassociated cache block in the data proxy module.

11. Each cache block has a unique corresponding cache block number, and each data access instruction in the data request list has a unique corresponding request number. When the data proxy module performs the operation of associating the unassociated cache block with one data access instruction selected from the data request list in accordance with the instruction transmission order, The data processor according to claim 10, comprising setting the request number of the data access instruction and the cache block number of the unassociated cache block in a state item corresponding to the one data access instruction, and performing an operation to associate the unassociated cache block with the one data access instruction.

12. The i+1 level data proxy module further, The data processor according to claim 8, configured to delete a data access instruction associated with any one cache block from the data request list of the i+1 level data proxy module and to clear the state item corresponding to the deleted data access instruction in the request state list of the i+1 level data proxy module in response to destination data cached in any one cache block within the i+1 level data proxy module having already been sent to the i-th level data proxy module.

13. The scheduler of the aforementioned N-level data proxy module, The data access instructions cached in the data request list of the N-level data proxy module are sent sequentially to the memory according to the instruction transmission order, The system receives the destination data returned sequentially from the memory and stores each returned destination data in the cache block associated with the corresponding data access instruction. A data processor according to claim 8, configured to perform the following:

14. The scheduler of the i-level data proxy module corresponding to any one i-level cache node in at least some of the i-level cache nodes, It is configured to transmit a data request signal to the electrically connected i+1 level data proxy module and to cache the received return data in a cache block associated with the data access instruction corresponding to the data request signal. The scheduler of the i+1 level data proxy module, The data processor according to claim 8, configured to transmit destination data for a data access command corresponding to the data request signal to the i-level data proxy module in response to receiving the data request signal.

15. The first level data proxy module further, The data processor according to claim 8, configured to select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence and to perform an initialization operation on the at least one data access instruction, wherein the at least one data access instruction is executed by a computing core electrically connected to the first level data proxy module.

16. When the first level data proxy module performs an initialization operation for the at least one data access command, The operation of caching at least one data access command in the data request list of the first-level data proxy module, An operation to initialize a state item corresponding to at least one data access command and save it to the request state list of the first level data proxy module, An operation to synchronize the at least one data access command and the corresponding state item with another level data proxy module having a direct or indirect electrical connection relationship with the first level data proxy module, The data processor according to claim 15, which includes performing the following:

17. The first level data proxy module further, In response to receiving a data access instruction transmitted by a computing core electrically connected to the first level data proxy module, the cache block associated with the transmitted data access instruction is determined, and the data in the associated cache block is transmitted to the target register indicated by the transmitted data access instruction. The transmitted data access command is removed from the data request list of the first level data proxy module, and the status item corresponding to the transmitted data access command in the request status list of the first level data proxy module is erased. Selecting at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence, and performing an initialization operation on the at least one data access instruction, A data processor according to claim 8, configured to perform the following:

18. The state item includes a data access instruction corresponding to the state item and a cache block number and a request number used to indicate the cache block associated with the data access instruction corresponding to the state item, The status item further includes the channel number of the channel to which the data access instruction corresponding to the status item belongs, and the priority of the data access instruction corresponding to the status item, wherein the channel number and the priority are used to indicate the position of the data access instruction corresponding to the status item in the instruction transmission order. The state item further includes request received state information and request transmitted state information used to indicate the current state of the data access command corresponding to the state item, The data processor according to claim 8, wherein the state item further includes data state information used to indicate the current state of destination data returned by a data access command corresponding to the state item.

19. Before performing the aforementioned task, the data processor further: The data processor according to claim 8, configured to select a plurality of cache lines from among the cache nodes corresponding to each data proxy module and map the plurality of cache blocks within the data proxy module.

20. The data processor according to any one of claims 1 to 6, obtained by arranging all data access instructions within a task according to their relative positions in the program corresponding to the task.

21. The data processor is a general-purpose graphics processor or a graphics processor, and the data processor includes a plurality of computing units. In response to N=2, the first level cache within the N-level cache includes a plurality of first level cache nodes, and the second level cache within the N-level cache includes one second level cache node. Each first-level cache node is used for data sharing within a single computing unit, and the second-level cache nodes are used for data sharing between the multiple computing units. The data processor according to claim 7, wherein each first-level cache node corresponds to one first-level data proxy module, and the second-level cache node corresponds to one second-level data proxy module.

22. Data processing used in a data processor including an N-level cache and memory, The i-th level cache within the N-level cache includes at least one i-th level cache node, and at least some of the i-th level cache nodes within the at least one i-th level cache node share one i+1-th level cache node, where N is a positive integer greater than 1, and i is any positive integer from 1 to N-1. The Nth level cache within the N-level cache is electrically connected to the memory, and each first level cache node is electrically connected to the corresponding computing core. The aforementioned data processing method The data processor obtains the data access instruction sequence within the currently executing task, The instruction transmission order of the data access instruction sequence is adjusted based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence. The data access commands are transmitted in order according to the command transmission sequence, The destination data returned by each data access instruction is cached in a first-level cache node or shared memory electrically connected to the computing core that uses the destination data. A method that includes this.

23. The instruction transmission order of the data access instruction sequence is adjusted based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence. The physical distance corresponding to each data access instruction is obtained, and the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in memory and the computing core in the data processor. Based on the physical distance corresponding to each data access instruction, the instruction transmission order is adjusted, and in the instruction transmission order, data access instructions with smaller corresponding physical distances are transmitted earlier. The data processing method according to claim 22, which includes the following:

24. The instruction transmission order of the data access instruction sequence is adjusted based on the memory storage location of the destination data for each data access instruction in the data access instruction sequence. Obtaining the priority of each data access instruction, The physical distance corresponding to each data access instruction is obtained, and the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in memory and the computing core in the data processor. Based on the priority and corresponding physical distance of each data access instruction, the instruction transmission order is adjusted so that data access instructions with higher priority are transmitted faster, and in the case of the same priority, data access instructions with a smaller corresponding physical distance are transmitted faster. The data processing method according to claim 22, which includes the following:

25. A memory device that stores computer executable instructions non-temporarily, A processor configured to execute the aforementioned computer executable instructions, An electronic device that includes, when the computer executable instruction is executed by the processor, realizes the data processing method according to any one of claims 22 to 24.

26. Computer executable instructions are stored in the aforementioned non-temporary computer-readable storage medium. A non-temporary computer-readable storage medium that realizes the data processing method according to any one of claims 22 to 24 when the computer-executable instruction is executed by the processor.

27. An electronic device comprising a data processor according to any one of claims 1 to 21.

Images