Wafers, and methods, apparatus, devices, and media for predicting surface nanotopography thereof.

Abstract

This disclosure provides wafers, as well as methods, apparatus, devices, and media for predicting their surface nanotopography, and belongs to the technical field of semiconductor manufacturing. The method includes filtering and processing the acquired surface topography measurement data of the wafer using a stepped impedance design filter during the wafer processing process to obtain a measured nanotopography value nt of the wafer, and predicting a predicted nanotopography value NT of the wafer after a subsequent processing step from the measured nanotopography value nt of the wafer based on a prediction function f(nt)=NT.

Description

[Technical Field]

[0001] This disclosure relates to the technology of semiconductor manufacturing, and more particularly to wafers, and methods, apparatus, devices, and media for predicting their surface nanotopography. [Background technology]

[0002] In the wafer manufacturing process, single-crystal silicon rods are fabricated using the Czochralski method, and then processed sequentially with wire cutting, polishing, etching, grinding, and chemical mechanical polishing (CMP) to finally obtain single-crystal silicon wafers. For single-crystal silicon wafers, their surface topography is a crucial parameter for evaluating their quality. Nanotopography (NT) of the wafer surface is one of the important quality parameters among the wafer surface topography parameters.

[0003] In the relevant embodiments, wafer NT detection is typically performed after the final surface treatment step, i.e., the chemical polishing (CMP) step. However, short-wave related quality parameters, such as nanotopography, are heavily influenced by the processing steps prior to chemical polishing. In other words, in the implementation of the relevant embodiments, if a problem occurs in the processing steps prior to CMP, it can only be detected after the CMP step. Thus, since the entire wafer manufacturing process is carried out even for wafers with problems in the pre-CMP processing, it results in a waste of production resources. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In view of this, this disclosure aims to provide a wafer capable of predicting the nanotopography value after the completion of a subsequent process of the wafer from the measured nanotopography value after the completion of the current processing process of the wafer, as well as a method, apparatus, device, and medium for predicting the surface nanotopography thereof. This makes it possible to monitor the product performance of the front-end processing process using the predicted nanotopography data, preventing defective wafers obtained in the front-end processing process from flowing into subsequent processing processes, and thus avoiding the waste of production resources. [Means for solving the problem]

[0005] The technical aspects of this disclosure are implemented as follows:

[0006] In the first phase, this disclosure relates to a method for predicting the surface nanotopography of a wafer, During the wafer processing process, a stepped impedance design filter is used to filter and process the acquired surface topography measurement data of the wafer to obtain the measured nanotopography value nt of the wafer. The present invention provides a method for predicting the surface nanotopography of a wafer, which includes predicting the predicted nanotopography value NT of the wafer after a subsequent processing step from the measured nanotopography value nt of the wafer, based on a prediction function f(nt)=NT.

[0007] In the second aspect, the present disclosure relates to a wafer surface nanotopography prediction apparatus, the apparatus comprising a filtering portion and a prediction portion, The filtering section is configured to perform filtering and data processing on the surface topography measurement data of the wafer acquired during the wafer processing process using a stepped impedance design filter, in order to obtain the measured nanotopography value nt of the wafer. The prediction portion is configured to predict the predicted nanotopography value NT of the wafer after a subsequent processing step from the measured nanotopography value nt of the wafer, based on the prediction function f(nt)=NT, and provides a wafer surface nanotopography prediction device.

[0008] In a third aspect, the Disclosure provides a computing device including a processor and memory, wherein the processor is for executing instructions stored in the memory so that the wafer surface nanotopography prediction method described in the first aspect is realized.

[0009] In the fourth aspect, the Disclosure provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is to be executed by a processor so that the wafer surface nanotopography prediction method described in the first aspect is realized.

[0010] In the fifth aspect, the present disclosure provides a wafer in which, if the predicted nanotopography value of the wafer is less than 5 nm in a 2 mm * 2 mm standard and / or less than 10 nm in a 10 mm * 10 mm standard, the nanotopography value of the final obtained wafer is less than 5 nm in a 2 mm * 2 mm standard and less than 10 nm in a 10 mm * 10 mm standard. [Effects of the Invention]

[0011] This disclosure provides a wafer, a method, apparatus, equipment, and medium for predicting the predicted nanotopography value of the wafer after the completion of a subsequent process, using a prediction function and measured nanotopography values ​​of the wafer after the completion of the current processing process. The predicted nanotopography value allows for monitoring each processing process to ensure the stability and consistency of the processing equipment used in the processing process, as well as monitoring the products of each processing process to ensure that acceptable products proceed to the next processing process, improving the microtopography quality of the wafer surface and preventing products with a low probability of future acceptance from being processed in subsequent processing processes. This reduces processing costs and also allows for determining whether there are problems with the process of a completed process and assisting in process adjustments. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a flowchart of the wafer surface nanotopography prediction method according to this disclosure. [Figure 2] Figure 2 is a schematic diagram of the linear correlation between predicted NT values ​​and measured NT values ​​obtained based on sampling data from 100 wafers according to this disclosure. [Figure 3] Figure 3 is a schematic diagram of the configuration of the wafer surface nanotopography prediction apparatus according to this disclosure. [Figure 4] Figure 4 is a schematic diagram of the configuration of a prediction apparatus for surface nanotopography of another wafer according to this disclosure. [Figure 5] Figure 5 is a schematic diagram of the structure of the computing device according to this disclosure. [Modes for carrying out the invention]

[0013] Hereinafter, the technical aspects of the embodiments of this disclosure will be described clearly and completely with reference to the drawings of the embodiments of this disclosure.

[0014] In a related aspect, for the surface of a wafer that has undergone a CMP process, after dividing the analysis region according to the set dimensions, the peak-to-valley values in the filtered measurement data at each sampling point within each analysis region are arranged in ascending order, and the value at the corresponding position within the ascending order array is selected as the nano-topography (NT) value of the wafer according to the set percentile (for example, 99.5%).

[0015] When viewed from the surface of the wafer, the filtered measurement data at each sampling point within each region shows the overall fluctuation phenomenon of the measurement data of each sampling point. From the perspective of waves, the present disclosure regards such a fluctuation phenomenon as being due to the superposition of wave signals of different wavelengths, and different wavelengths can correspond to the dimensions of the region where the waveform phenomenon occurs. That is, the smaller the wavelength of the wave signal, the smaller the dimension of the region where the fluctuation phenomenon of the measurement data represented thereby occurs, and the larger the wavelength of the wave signal, the larger the dimension of the region where the fluctuation phenomenon of the measurement data represented thereby occurs. In the fluctuation phenomenon appearing in the measurement data, the signal data with a long wavelength may include parameters such as bow and warp. These parameters become generally constant after the wire cutting process, and the subsequent processing steps have little influence on them. In contrast, for the signal data with a short wavelength, such as the nano-topography value, all the front-end processing steps before the CMP process will affect it. The NT value of the wafer obtained in the related aspect becomes the NT value of the wafer after undergoing the CMP process, and this data can only represent the performance of the entire wafer processing process and cannot evaluate the performance of each processing step in the processing process. Furthermore, as the requirements for the surface micro-topography of wafers by advanced processes become increasingly strict, it is necessary to monitor each processing step to ensure the stability and consistency of the processing equipment employed in the processing step, and to monitor the products of each processing step to ensure that qualified products can proceed to the next processing step, so as to improve the micro-topography quality of the surface of the wafer.

[0016] Based on this, the present disclosure provides a method for predicting the surface nanotopography of a wafer, and the method includes steps S101 to S102.

[0017] In step S101, during the wafer processing, using a step - impedance design filter, filtering and data processing are performed on the obtained surface topography measurement data of the wafer to obtain the measured nanotopography value nt of the wafer.

[0018] In the present disclosure, the measured nanotopography value of the wafer is obtained after any process in the wafer processing is completed. In some examples, after completing any processing step (such as wire cutting), by measuring the surface height at the sampling points on the surface of the wafer after wire cutting in a single - point measurement mode, the surface topography measurement data of the wafer may be obtained.

[0019] In the above example, the single - point measurement mode is a mode in which only the measurement data at one sampling point can be measured in one measurement process. As an example, a contact - type measurement mode may be adopted. For example, a probe is used to contact the surface of the wafer to be measured and horizontally move on the surface of the wafer. Due to the difference in the surface height of the wafer to be measured during the horizontal movement, a vertical displacement occurs in the probe, and the vertical displacement is sensed by a displacement sensor. The sensed vertical displacement value is converted into the surface height data of the wafer to be measured, that is, it is converted into the historical measurement data about the surface height of the wafer. For example, a non - contact measurement mode such as measurement by the capacitance method or laser focus measurement may also be adopted.

[0020] Of course, in some examples, the surface topography measurement data of the wafer after the current processing step is completed may be obtained in only one measurement process. For example, a measurement mode using optical means (such as Fizeau interference, differential interference, etc.) may also be used. In the present disclosure, no further elaboration is made on this.

[0021] Specifically, the sampling interval used during measurement may be determined by the accuracy of the measuring instrument and the specific recipe. For example, in the case of optical measuring instruments, the sampling interval may be as low as 0.2 mm, while in the case of some less accurate capacitive measuring instruments, the sampling interval may be as high as 4 mm.

[0022] In this disclosure, surface topography measurement data for all sampling points may be considered as a single three-dimensional wave phenomenon when viewed from the entire surface of the wafer. This wave phenomenon may consist of superimposed wave signals of different wavelengths, and for the NT value, the corresponding wavelength range is 22 microns to 20 millimeters. In some examples, the surface topography measurement data is filtered to filter out wavelengths in the range of 22 microns to 20 millimeters.

[0023] In some examples, the Disclosure does not employ a fixed-size filter to filter surface topography measurement data for all sampling points on the wafer surface. The dimensions of the filter vary depending on the location of the sampling points. For example, the filter may be a stepped-impedance design filter, the dimensions of which may be designed according to the target wavelength range, sampling interval, and sampling point locations of the wafer surface topography measurement data.

[0024] In this disclosure, taking a target wavelength range of 22 microns to 20 millimeters as an example, after obtaining filtering values ​​for the wavelength range of 22 microns to 20 millimeters, the wafer surface may be divided into multiple regions to be analyzed, peak-to-valley (PV) values ​​for the filtering values ​​within each region to be analyzed may be obtained, and after arranging all the PV values ​​of the regions to be analyzed in ascending order, the PV values ​​may be selected as the measured nanotopography values ​​after the completion of wire cutting of the wafer according to the set percentile.

[0025] In step S102, based on the prediction function f(nt)=NT, the predicted nanotopography value NT of the wafer after the subsequent processing step is predicted from the measured nanotopography value nt of the wafer.

[0026] In this disclosure, a subsequent processing step refers to a processing step in the wafer processing process that occurs after the step of obtaining wafer surface topography measurement data as described in step S101. For example, if the wafer surface topography measurement data after the wire cutting step is set to be obtained in step S101, the subsequent processing step described in step S102 may be a step in the wafer processing process that occurs after the wire cutting step, such as a polishing step, etching step, grinding step, CMP step, etc.

[0027] Taking the wire-cutting process as an example, if a normal distribution for the NT value of the wafer is formed by the processing steps after the wire-cutting process, then based on this setting, it is considered that there is a fixed functional relationship between the nanotopography value of the wafer after the wire-cutting process is completed and the nanotopography value of the wafer after the subsequent processing steps are completed. In this disclosure, this is represented as NT = f(nt), where NT represents the predicted nanotopography value of the wafer after the subsequent processing steps are completed, nt represents the measured nanotopography value of the wafer obtained via step S101, and f() represents the expression of the prediction function.

[0028] In this disclosure, after obtaining the predicted nanotopography values ​​of the wafer, it becomes possible to evaluate the processing steps that have been completed so far.

[0029] In some cases, the operational status of the equipment performing the currently completed processing steps can be determined from the statistical data of the predicted nanotopography values ​​of the wafer, thereby ensuring the stability and consistency of the equipment and avoiding machine-specific differences. For example, by monitoring the predicted NT values ​​of all products processed daily by each piece of equipment, if the predicted NT values ​​are discrete, have too many outliers, or have an excessively large average value, it means that the equipment is unstable and needs to be shut down for maintenance.

[0030] In some cases, the decision of whether to continue the subsequent processing of the wafer may be made based on a comparison between the predicted nanotopography value of the wafer and a set evaluation index. This allows for the selection of acceptable products and their subsequent processing, preventing products with a low probability of future acceptance from being processed in subsequent processes, thereby reducing processing costs.

[0031] In some examples, the process parameters of the currently completed processing step are adjusted according to the predicted nanotopography values ​​of the wafer. For example, the predicted nanotopography values ​​of the product in each processing step are used to determine whether there are problems with the process in the completed step. This helps to adjust the process and enables more accurate responses. Furthermore, in process adjustment, the process parameters of the processing step may also be fed back and adjusted by referring to these predicted nanotopography values.

[0032] According to the technology shown in Figure 1, a prediction function and the measured nanotopography value after the current processing step of the wafer are used to predict the predicted nanotopography value of the wafer after the completion of subsequent processes. Based on this predicted nanotopography value, it is possible to monitor each processing step and ensure the stability and consistency of the processing equipment used in the processing step, as well as monitor the products of each processing step to ensure that acceptable products proceed to the next processing step, improve the microtopography quality of the wafer surface, and avoid processing products that are unlikely to be acceptable in the future in subsequent processing steps. This reduces processing costs and also allows for determining whether there are problems with the process of a completed step and supports process adjustments.

[0033] Regarding the technical embodiment shown in Figure 1, in several possible implementations, the dimensions of the stepped impedance design filter described in step S101 may be designed according to the target wavelength range, sampling interval, and sampling point position of the wafer surface topography measurement data, and the specific design process is as follows: Based on the aforementioned target wavelength range, the filter is determined using a double Gauss low-pass filtering function, The critical dimensions of the filter are determined according to the upper wavelength limit of the target wavelength range, Perform edge shrinkage processing according to the sampling point position, If the distance between the sampling point position and the center of the wafer surface is less than or equal to the critical dimension, the radius of the stepped impedance design filter is determined to be the first radius, or If the distance between the sampling point position and the center of the wafer surface is greater than the critical dimension, the radius of the stepped impedance design filter may be determined to be a second radius smaller than the first radius.

[0034] In the above example, the target wavelength range may be 22 micron wavelengths to 20 millimeter wavelengths, corresponding to the NT value. In this disclosure, the filter may be a circular filter and may be configured with a double Gaussian low-pass filtering function. Specifically, determining the filter using a double Gaussian low-pass filtering function based on the above-mentioned target wavelength range is as follows: Determine a first Gaussian low-pass filtering function whose low-pass filtering range covers up to the upper limit of the target wavelength range, Determine a second Gaussian low-pass filtering function whose low-pass filtering range covers up to the lower limit of the target wavelength range, The first Gaussian low-pass filtering function G LP1 and the second Gaussian low-path filtering function G LP2 From, G DHP =G LP1 (1-G LP2 The function G for describing the filter follows the formula ) DHP This includes obtaining.

[0035] For example, the relationship between the cutoff wavelength and the standard deviation is: TIFF2026526159000002.tif8170 Defined as such, the Gaussian low path filtering function is TIFF2026526159000003.tif17170 In this equation, λ represents the wavelength as a parameter of the function. What needs to be explained is that for the first Gaussian low-pass filtering function and the second Gaussian low-pass filtering function, their standard deviations σ are different, allowing them to preserve signals in different wavelength ranges.

[0036] After obtaining a circular filter according to the specific embodiment described above, it is necessary to set the operating range of the filter according to the sampling point position where the filtering calculation is performed. Specifically, for the wafer surface, the topographic changes become more drastic the closer you are to the edge. Therefore, in order to accurately capture drastic topographic changes and effectively capture the characteristics of surface topography at different scales, when the sampling point is close to the edge of the wafer surface, the operating range of the corresponding circular filter must be smaller than the operating range of the circular filter corresponding to the sampling point closer to the center of the wafer surface. In other words, as the sampling point gradually moves away from the center of the wafer surface, the operating range of the corresponding filter must be reduced, or this may be called edge contraction. In this disclosure, the edge contraction method is stepwise, that is, a critical dimension is set to determine whether the sampling point is close to the center of the wafer surface or close to the edge of the wafer surface. If the sampling point is closer to the edge of the wafer surface than to the center of the wafer surface, the filter's operating range needs to be reduced (k is the edge processing coefficient during reduction). Furthermore, if the distance between the sampling point and the center of the wafer surface is greater than the critical dimension, the second radius is fixed to a value smaller than the first radius. Taking a 12-inch wafer as an example, its radius R is 150 mm, the edge exclusion amount (EE) during measurement is usually 3 mm, the upper limit w of the target wavelength range is 20 mm, and the critical dimension a can be calculated according to the following formula. a = R - EE - 0.5 * w

[0037] In this disclosure, the step radius of the filter is set according to the critical dimension, as shown in Table 1 below.

[0038] [Table 1]

[0039] In some examples, when the distance between the sampling point and the center of the wafer surface is greater than the critical dimension, the second radius is not only smaller than the first radius, but is also set to decrease as the distance between the sampling point and the center of the wafer surface increases, for example, by linear reduction, and does not need to be set to a fixed value.

[0040] Based on the above implementation, after obtaining a circular filter and the radius of its operating range according to the above embodiment, it becomes possible to use the filter to filter the surface topography measurement data of the wafer and obtain the measured nanotopography value of the wafer. Specifically, obtaining the wafer measured nanotopography value is possible. After filtering the wafer surface topography measurement data using the stepped impedance design filter, the filtered values ​​for each sampling point position are obtained. For all sampling points, divide the area to be analyzed into at least one region according to the set dimensions, For each region to be analyzed, obtain the peak-to-valley (PV) value for the maximum and minimum filtering values ​​within that region. This may include arranging the PV values ​​of all regions to be analyzed in ascending order, and then selecting the PV values ​​as the measured nanotopography values ​​of the wafer according to the set percentiles.

[0041] In the above example, if the sampling point is near the wafer edge and the filter's effective range extends beyond the wafer surface edge range, during the filtering process, the portion of the filter's effective range that extends beyond the wafer surface edge range may be interpolated or left uninterrupted. The interpolation method may be linear extrapolation, symmetric interpolation, cubic spline interpolation, etc., but this disclosure will not elaborate further.

[0042] In the above example, the division of the area to be analyzed may be determined according to the specific surface topography measurement and analysis requirements. In this disclosure, the area to be analyzed is obtained by dividing it according to a uniform grid, that is, dividing the data on the surface of the wafer into several uniform small grids, with each grid being one area to be analyzed, and the dimensions of each grid being a 10*10 micron or 20*20 micron square.

[0043] In the above example, after arranging the PV values ​​of each region to be analyzed in ascending order, the Nth PV value from the end is selected as the measured nanotopography value of the wafer according to a specific percentile, such as 99%, 99.5%, etc.

[0044] Regarding the technical embodiment shown in Figure 1, in some possible implementations, the method further includes a process for obtaining a prediction function, and specifically, this process is: The method may include obtaining the prediction function by performing mathematical modeling and fitting from the measured nanotopography values ​​of the hysteretic wafer after the completion of the current processing step and the measured nanotopography values ​​of the hysteretic wafer after the completion of the subsequent processing step, using a linear fitting or polynomial fitting method.

[0045] Regarding the above implementation configuration, in detail, whether the measured nanotopography value is obtained after the completion of the current processing step or after the completion of a subsequent processing step, it is possible to obtain the measured nanotopography value of the hysteretic wafer by filtering and processing the surface topography measurement data of the hysteretic wafer using the stepped impedance design filter. The specific implementation process is the same as the specific acquisition process for the measured nanotopography value of the wafer in the above-described embodiment, and this disclosure will not elaborate further.

[0046] In some examples of this implementation, obtaining the prediction function using a linear fitting or polynomial fitting method may include the following details in its specific implementation. First, the measured nanotopography values ​​of the hierarchical wafer after the completion of the current processing step, and the nanotopography values ​​of the same hierarchical wafer after the completion of subsequent processing steps, are organized into a dataset and stored, for example, in the form of a matrix, with each row in the matrix corresponding to one sample. Next, an appropriate prediction function f(nt)=NT is selected depending on the actual situation, such as a linear function, polynomial function, exponential function, or logarithmic function. For example, if polynomial fitting is selected, the data is usually fitted using the least square method, that is, the parameters of the prediction function f(nt) are determined by minimizing the sum of squared residuals between the actual observed value NT and the fitted value (f(nt) value), and finally a prediction function that can be applied to actual production is obtained.

[0047] Based on the aforementioned technical aspects, this disclosure will be described through one specific embodiment. In this embodiment, 100 bare wafers with a radius of 150 mm after wire cutting are used as an example. After removing the edges from each bare wafer according to an edge exclusion amount (EE) of 4 mm, the surface height data is sampled and measured using a capacitive method to obtain surface topography measurement data for each bare wafer. For example, sampling is performed uniformly according to a polar coordinate system with the center of the wafer surface as the pole, that is, one diameter direction is measured every 45°, and the sampling interval in each diameter direction is set to 4 mm. In this polar coordinate system, surface topography measurement data for 8 * 37 sampling points can be obtained, and when viewed as a whole from the entire surface of the wafer, each sampling point can be considered as a single pixel point.

[0048] Next, after filtering the surface topography measurement data for each sampling point using the filter described above, the filtered values ​​for all sampling points are divided into areas to be analyzed according to a 10mm*10mm dimension. For each area to be analyzed, the PV value of that area is determined according to the filtered value of each pixel point (sampling point). After arranging all of these PV values ​​of the areas to be analyzed in ascending order, the Nth PV value from the end is selected as the measured nanotopography value after wire cutting of the bare wafer, according to a specific percentile, such as 99%, 99.5%, etc.

[0049] Subsequently, for each of the 100 bare wafers, the predicted nanotopography values ​​were calculated using a fitting function based on the measured nanotopography values ​​after wire cutting was completed. In this embodiment, the fitting function is obtained by linear fitting using hierarchical wafer data, as shown by the dashed line in Figure 2. In this embodiment, the prediction function is NT = 1.9785 * nt + 5.9023, where nt represents the measured nanotopography value after wire cutting is completed, and NT represents the predicted nanotopography value.

[0050] Finally, using CMP as an example of a subsequent processing step, we analyze whether there is a correlation between the actual nanotopography values ​​and predicted nanotopography values ​​after CMP of these 100 bare wafers. Referring to Figure 2, using the predicted nanotopography values ​​after wire cutting and the actual nanotopography values ​​after CMP as coordinates, the predicted and actual nanotopography values ​​for the 100 wafers selected in this disclosure are as shown by the points in Figure 2. To verify whether there is a correlation between the predicted nanotopography values ​​(predicted NT values) and the actual nanotopography values ​​(actual NT values), we calculate the residual between the fitting curve and the actual data from the predicted NT values ​​and the measured NT values, or the R of the fitting curve. 2Indicators such as values ​​are calculated. For the 100 wafers selected in this embodiment, the correlation between the predicted NT value and the actual NT value is as shown in Table 2.

[0051] [Table 2]

[0052] Table 2 shows that there is a correlation between the predicted NT value and the actual NT value.

[0053] Based on the method for predicting the surface nanotopography of a wafer according to the aforementioned technical embodiment, if the predicted nanotopography value of the wafer is less than 5 nm in a 2 mm * 2 mm standard and / or less than 10 nm in a 10 mm * 10 mm standard, then the nanotopography value of the wafer is less than 5 nm in a 2 mm * 2 mm standard and less than 10 nm in a 10 mm * 10 mm standard.

[0054] It should be explained that the processing step in which the predicted nanotopography values ​​are obtained precedes the acquisition of the nanotopography values ​​of the wafer. For example, the predicted nanotopography values ​​may be obtained after the wire-cutting step, and the nanotopography values ​​in the wafer may be obtained after the CMP step. Alternatively, the predicted nanotopography values ​​may be obtained after the CMP step, and the nanotopography values ​​in the wafer may be obtained when the wafer enters the backend semiconductor manufacturing process, but this disclosure does not elaborate further.

[0055] Based on the same inventive concept as described above, with reference to Figure 3, a wafer surface nanotopography prediction device 30 according to the present disclosure is shown, and the device 30 includes a filtering section 301 and a prediction section 302. The filtering section 301 is configured to perform filtering and data processing on the surface topography measurement data of the wafer acquired during the wafer processing process using a stepped impedance design filter, in order to obtain the measured nanotopography value nt of the wafer. The prediction unit 302 is configured to predict the predicted nanotopography value NT of the wafer after a subsequent processing step from the measured nanotopography value nt of the wafer, based on the prediction function f(nt)=NT.

[0056] In some examples, the dimensions of the stepped impedance design filter are designed according to the target wavelength range, sampling interval, and sampling point location of the wafer surface topography measurement data, and accordingly, the filtering portion 301 is: Based on the aforementioned target wavelength range, the filter is determined using a double Gaussian low-pass filtering function. The critical dimensions of the filter are determined according to the upper wavelength limit of the target wavelength range. Edge shrinkage processing is performed according to the sampling point position. If the distance between the sampling point position and the center of the wafer surface is less than or equal to the critical dimension, the radius of the stepped impedance design filter is determined to be the first radius, or If the distance between the sampling point position and the center of the wafer surface is greater than the critical dimension, the radius of the stepped impedance design filter is configured to be a second radius smaller than the first radius.

[0057] In some examples, the filtering portion 301 is Determine the first Gauss low-pass filtering function whose low-pass filtering range covers up to the upper limit of the target wavelength range. Determine the second Gaussian low-pass filtering function such that the low-pass filtering range covers up to the lower limit of the target wavelength range. The first Gaussian low-pass filtering function G LP1 and the second Gaussian low-pass filtering function G LP2 are used to obtain the function G DHP =G LP1 (1-G LP2 ) according to the formula, and the function G DHP for describing the filter is configured to be obtained.

[0058] In some examples, the filtering part 301 uses the step-to-impedance design filter to filter the surface topography measurement data of the wafer, and then obtains the filtering value at each sampling point position. For all sampling points, at least one area to be analyzed is divided according to the set dimension. For the maximum filtering value and the minimum filtering value in each area to be analyzed, the peak-to-valley (PV) value of each area to be analyzed is obtained. After arranging the PV values of all areas to be analyzed in ascending order, the PV value is selected as the measured nano-topography value of the wafer according to the set percentile.

[0059] Referring to FIG. 4, the device 30 further includes a fitting part 303 configured to perform mathematical modeling and fitting on the measured nano-topography value after the completion of the current processing step of the history wafer and the measured nano-topography value after the completion of the subsequent processing step of the history wafer, so as to obtain the prediction function in the form of linear fitting or polynomial fitting.

[0060] In some examples, the filtering part 301 is further configured to obtain the measured nano-topography value of the history wafer by performing filtering and data processing on the surface topography measurement data of the history wafer using the step-to-impedance design filter.

[0061] In some examples, referring to Figure 4, the apparatus 30 is, From the statistical data of the predicted nanotopography values ​​of the wafer, the operating status of the equipment performing the currently completed front-end processing step can be determined, or Based on the comparison results between the predicted nanotopography values ​​of the wafer and the set evaluation index, it is determined whether or not to continue the subsequent processing of the wafer, or The system further includes a feedback section 304 configured to adjust process parameters of the currently completed processing step according to the predicted nanotopography values ​​of the wafer.

[0062] What needs to be explained is that the specific implementation of the functions configured in each "part" of the above-mentioned apparatus can be found by referring to the implementation forms and examples of the corresponding steps in the wafer surface nanotopography prediction method described above, and will not be elaborated upon here.

[0063] Referring to Figure 5, which shows a structural block diagram of a computing device according to one exemplary embodiment of the present disclosure. In some examples, the computing device 50 may be at least one of the following devices: a smartphone, a smartwatch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The computing device 50 has communication capabilities and is able to access a wired or wireless network. The computing device 50 generally refers to one of several terminals, but as those skilled in the art will understand, the number of such terminals may be more or less. In some examples, the computing device 50 is able to receive data based on the wired or wireless network it accesses. Understandably, the computing device 50 is responsible for, but is not limited to, the calculation and processing tasks relating to the technical embodiments of the present disclosure.

[0064] As shown in Figure 5, the computing device in this disclosure may include one or more processors 510 and memory 520.

[0065] Selectively, the processor 510 connects various parts of the computing device using various interfaces and lines, and performs various functions of the computing device and processes data by operating or executing instructions, programs, code sets or instruction sets stored in memory 520, and by retrieving data stored in memory 520. Selectively, the processor 510 may be implemented using at least one hardware form from among Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 510 may integrate one or more combinations from among a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Of these, the CPU mainly processes the operating system, user interface, and application programs, while the GPU is responsible for rendering and drawing content that needs to be displayed on the touch display screen. The NPU is for implementing artificial intelligence (AI) functions, and the baseband chip is for processing wireless communications. The baseband chip may be implemented separately on a single chip, rather than being integrated into the processor 510.

[0066] The memory 520 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 520 may include a non-transitory computer-readable storage medium. The memory 520 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 520 may include a program storage area and a data storage area, the program storage area capable of storing instructions for implementing an operating system, instructions for at least one function (e.g., touch function, audio playback function, image playback function, etc.), instructions for implementing each of the above embodiments, etc. The data storage area can store data created in accordance with the use of the computing device, etc.

[0067] Furthermore, as those skilled in the art will understand, the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than those shown, or may include combinations of some components or components in different arrangements. For example, the computing device may further include components such as a display screen, imaging components, microphone, speaker, radio frequency circuit, input unit, sensors (e.g., accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth® module, etc., but no further details are provided here.

[0068] The disclosure further provides a computer-readable storage medium having at least one instruction stored therein, the at least one instruction being to be executed by a processor so that the wafer surface nanotopography prediction method described in each of the above embodiments is realized.

[0069] This disclosure further provides a computer program product which includes computer instructions, which are stored in a computer-readable storage medium, and the computer device implements the wafer surface nanotopography prediction method described in each of the above embodiments by having the computing device execute the computer instructions, which are read from the computer-readable storage medium by the processor of the computing device and which are executed by the processor.

[0070] The Disclosure further provides a wafer in which, if the predicted nanotopography values ​​obtained via the wafer surface nanotopography prediction methods described in each of the above embodiments are less than 5 nm in a 2 mm*2 mm standard and / or less than 10 nm in a 10 mm*10 mm standard, the nanotopography values ​​of the final obtained wafer are less than 5 nm in a 2 mm*2 mm dimension and less than 10 nm in a 10 mm*10 mm dimension.

[0071] As will be apparent to those skilled in the art, in one or more of the above examples, the functions described in the embodiments of this disclosure can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions are stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable medium includes computer storage media and communication media. Communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media are any available medium accessible by a general-purpose or special-purpose computer.

[0072] It should be explained that the technical embodiments described in this disclosure can be combined in any way, as long as they do not contradict each other.

[0073] The foregoing describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Those skilled in the art will readily conceive of modifications and substitutions within the technical scope described in the Disclosure, and all such modifications and substitutions should be considered within the scope of protection of the Disclosure. Therefore, the scope of protection of the Disclosure should be in accordance with the attached claims.

[0074] [Cross-reference of related applications] This disclosure claims priority to Chinese Patent Application No. 202410895811.6, filed in China on 5 July 2024, the entirety of which is incorporated herein by reference.

Claims

1. A method for predicting the surface nanotopography of a wafer, During the wafer processing process, a stepped impedance design filter is used to filter and process the acquired surface topography measurement data of the wafer to obtain the measured nanotopography value nt of the wafer. A method for predicting the surface nanotopography of a wafer, comprising predicting a predicted nanotopography value NT of the wafer after a subsequent processing step from a measured nanotopography value nt of the wafer, based on a prediction function f(nt) = NT.

2. The dimensions of the stepped impedance design filter are designed according to the target wavelength range, sampling interval, and sampling point location of the wafer surface topography measurement data, and the method is designed accordingly. Based on the aforementioned target wavelength range, the filter is determined using a double Gauss low-pass filtering function, The critical dimensions of the filter are determined according to the upper wavelength limit of the target wavelength range, Perform edge shrinkage processing according to the sampling point position, If the distance between the sampling point position and the center of the wafer surface is less than or equal to the critical dimension, the radius of the stepped impedance design filter is determined to be the first radius, or The method according to claim 1, further comprising determining the radius of the stepped impedance design filter to a second radius smaller than the first radius if the distance between the sampling point position and the center of the wafer surface is greater than the critical dimension.

3. Based on the aforementioned target wavelength range, determining the filter using a double Gaussian low-pass filtering function is possible. Determine a first Gaussian low-pass filtering function whose low-pass filtering range covers up to the upper limit of the target wavelength range, Determine a second Gaussian low-pass filtering function whose low-pass filtering range covers up to the lower limit of the target wavelength range, The first Gaussian low-pass filtering function G ＬＰ１ and the second Gaussian low-path filtering function G ＬＰ２ From, G ＤＨＰ = G ＬＰ１ (1-G) ＬＰ２ The function G for describing the filter follows the formula ) ＤＨＰ The method according to claim 2, which includes obtaining

4. Using the stepped impedance design filter described above, filtering and data processing are performed on the acquired wafer surface topography measurement data to obtain the measured nanotopography values ​​of the wafer. After filtering the wafer surface topography measurement data using the stepped impedance design filter, the filtered values ​​for each sampling point position are obtained. For all sampling points, divide the area to be analyzed into at least one region according to the set dimensions, For each area to be analyzed, obtain the peak-to-valley (PV) value for the maximum and minimum filtering values ​​within that area. The method according to claim 2, comprising arranging the PV values ​​of all regions to be analyzed in ascending order, and then selecting the PV values ​​as the measured nanotopography values ​​of the wafer according to the set percentiles.

5. The aforementioned method, The method according to claim 1, comprising performing mathematical modeling and fitting from the measured nanotopography values ​​of the hysteretic wafer after the completion of the current processing step and the measured nanotopography values ​​of the hysteretic wafer after the completion of the subsequent processing step to obtain the prediction function in the form of linear fitting or polynomial fitting.

6. The aforementioned method, The method according to claim 5, further comprising obtaining measured nanotopography values ​​of the hysteretic wafer by filtering and processing the surface topography measurement data of the hysteretic wafer using the stepped impedance design filter.

7. A wafer surface nanotopography prediction apparatus, the apparatus comprising a filtering portion and a prediction portion, The filtering section is configured to perform filtering and data processing on the surface topography measurement data of the wafer acquired during the wafer processing process using a stepped impedance design filter, thereby obtaining the measured nanotopography value nt of the wafer. A wafer surface nanotopography prediction device, wherein the prediction portion is configured to predict the predicted nanotopography value NT of the wafer after a subsequent processing step from the measured nanotopography value nt of the wafer, based on the prediction function f(nt) = NT.

8. A computing device including a processor and memory, wherein the processor is for executing instructions stored in the memory so that a method for predicting wafer surface nanotopography according to any one of claims 1 to 6 is realized.

9. A computer-readable storage medium storing at least one instruction, wherein the at least one instruction is to be executed by a processor so as to realize the wafer surface nanotopography prediction method according to any one of claims 1 to 6.

10. A wafer wherein the predicted nanotopography value NT of the wafer is less than 5 nm in a 2 mm * 2 mm standard and / or less than 10 nm in a 10 mm * 10 mm standard, and the nanotopography value of the wafer is less than 5 nm in a 2 mm * 2 mm standard and less than 10 nm in a 10 mm * 10 mm standard.

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