Selective atomic layer etching of Si-based materials

Abstract

A method for processing a substrate, comprising: forming a photoresist layer containing metal and oxygen on a silicon-containing substrate; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithography process, wherein a portion of the substrate is exposed after patterning; and selectively etching the substrate with respect to the patterned photoresist layer by performing an atomic layer etching (ALE) process.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Non - Provisional Patent Application No. 18 / 362,652, filed Jul. 31, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present invention generally relates to a method for processing a substrate, and in certain embodiments, to selective atomic layer etching (ALE) of Si - based materials.

Background Art

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning layers of dielectric materials, conductive materials, and semiconductor materials on a substrate to form a network of electronic components and interconnecting elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated as a monolithic structure. The process flow used to form the constituent structures of a semiconductor device often involves the deposition and removal of various materials, and in some cases, patterns of several types of materials are exposed on the surface of the processed substrate. Etching is one of the important processes in such semiconductor device manufacturing. In the modern semiconductor industry, etching is typically performed by wet etching using a liquid etchant or dry etching such as reactive ion etching.

[0004] As the critical dimensions and feature sizes of ICs are shrinking below 10 nm, the semiconductor industry demands improved accuracy of dimensions (e.g., line width, etching depth, and film thickness) during the etching process. For example, controllability at the atomic scale may be required, but it is difficult to achieve with conventional etching techniques. For this reason, alternative etching techniques that meet such requirements are strongly desired.

Summary of the Invention

Means for Solving the Problems

[0005] A method for processing a substrate, according to an embodiment of the present invention, comprising: forming a photoresist layer containing metal and oxygen on a silicon-containing substrate; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithography process, wherein a portion of the substrate is exposed after patterning; and performing an atomic layer etching (ALE) process to selectively etch the substrate with respect to the patterned photoresist layer.

[0006] According to embodiments of the present invention, a method for processing a substrate, comprising etching, wherein an atomic layer etching (ALE) process is performed to selectively etch silicon in a substrate with respect to a metal oxide disposed on the substrate, the ALE process comprising: exposing the substrate to a halogen-containing gas in the absence of plasma to form a modified surface layer containing silicon; exposing the modified surface to a first plasma containing argon (Ar) to etch the modified surface layer; and repeating the two exposure steps.

[0007] According to an embodiment of the present invention, a method for processing a substrate comprising: forming a patterned tin oxide layer on a silicon (Si) substrate, wherein a portion of the Si substrate is exposed after the patterned tin oxide layer is formed; exposing the Si substrate to a first plasma containing hydrogen; forming a modified Si surface by exposing the Si substrate to a gas containing CF4 or NF3 in the absence of plasma; and selectively etching the modified Si surface with respect to the patterned tin oxide layer by exposing the modified Si surface to a second plasma containing argon (Ar).

[0008] To fully understand the present invention and its advantages, refer hereto to the following description, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1A] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and depict a substrate being fed in, which includes a metal oxide resist (MOR) layer. [Figure 1B] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the ultraviolet (UV) exposure step. [Figure 1C] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the development step. [Figure 1D] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the ALE pretreatment step. [Figure 1E] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the modification step of the ALE process. [Figure 1F] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the removal step of the ALE process. [Figure 1G] The images show cross-sectional views of a substrate during an exemplary semiconductor manufacturing process, including an atomic layer etching (ALE) process, according to various embodiments, and the substrate after the ALE process steps have been periodically repeated. [Figure 2] This shows the simulated adsorption energies of fluorine-containing adsorbates (CF4 and NF3) useful in the modification step of the ALE process on two surfaces (Si and SnO2). [Figure 3A] This is a process flow diagram of the ALE process method according to various embodiments, showing one embodiment. [Figure 3B] This is a process flow diagram of the ALE process method according to various embodiments, illustrating alternative embodiments. [Figure 3C]This is a process flow diagram of the ALE process method according to various embodiments, and further embodiments are shown. [Figure 4] A cross-sectional view of a plasma system for performing an ALE process according to one embodiment is shown. [Figure 5A] A top view is shown illustrating a spatially isolated plasma system for performing an ALE process according to a specific embodiment. [Figure 5B] A spatially isolated plasma system for performing an ALE process according to a specific embodiment is shown, with a cross-sectional view. [Modes for carrying out the invention]

[0010] This application relates to the manufacture of semiconductor devices, and more specifically, to selective atomic layer etching (ALE) of silicon (Si)-based materials. Specifically, the ALE method can be applied to selectively etch silicon against metal oxide resists (MORs) that are useful in extreme ultraviolet (EUV) lithography. EUV lithography, generally based on a wavelength of about 13.5 nm, can extend current photolithography techniques beyond their optical limits by reducing the wavelength of the imaging source to pattern small critical-size features. Metal oxide materials (including, for example, tin (Sn) metal) have been found to be particularly suitable for direct EUV photopatterning because they strongly absorb EUV light compared to conventional polymer-based resists. However, the selectivity of MOR masks in pattern transfer etching after exposure is insufficient and can suffer from pattern collapse, which presents challenges in certain applications such as technology nodes of less than 5 nm.

[0011] Embodiments of this application disclose an atomic layer etching (ALE) method that can improve the etching selectivity of silicon-based materials to metal-containing layers, such as patterned metal oxide resists (MORs). ALE is a film etching technique consisting of a series of self-limiting reactions. A first step (modification step) modifies the surface by adsorption of a modifier to form a thin layer. A second step (removal step) is the removal of at least a portion of the formed layer. The concept of ALE is similar to atomic layer deposition (ALD). The difference is that, unlike ALD where material is added, the material is removed during the second step of ALE. Each step is self-limiting, and only one thin layer (e.g., a single atomic layer) is removed in one cycle of the ALE process. To achieve the desired etching amount, the steps are usually repeated, and therefore the ALE process generally refers to a series of such steps. Various embodiments of the method may use a halogen-containing gas (e.g., CF4 or NF3) as a modifier in the first step and a plasma treatment (e.g., Ar plasma) for the second step to selectively etch silicon against MOR (e.g., SnO2). To improve etching performance (e.g., selectivity), one or more surface pretreatment steps (e.g., H2 plasma treatment) may also be performed before or during the ALE process. The ALE methods described herein can conveniently overcome the problem of MOR mask selectivity in high numerical aperture (NA) EUV lithography applications.

[0012] Hereinafter, referring to FIGS. 1A to 1G, an exemplary manufacturing process including an atomic layer etching (ALE) process according to various embodiments will be described. The selective adsorption of a modifier on an etching target surface (e.g., silicon), as demonstrated by simulation, is shown in FIG. 2. Exemplary process flow diagrams are shown in FIGS. 3A to 3C. FIGS. 4 and 5A to 5B provide an exemplary plasma system for performing an ALE process according to various embodiments. All the figures are drawn for illustrative purposes only and are not to scale, including the aspect ratio of the features. This disclosure mainly describes embodiments of an ALE method for selective silicon etching of a metal-containing EUV photoresist, but the method should not be limited to EUV lithography applications or lithography applications.

[0013] FIGS. 1A to 1G show cross-sectional views of a substrate during an exemplary process of semiconductor manufacturing including an atomic layer etching (ALE) process according to various embodiments.

[0014] FIG. 1A shows a cross-sectional view of an incoming substrate 100 including a metal oxide resist (MOR) layer 110.

[0015] In one or more embodiments, the substrate 100 can be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 100 can include a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, or other compound semiconductors. In other embodiments, the substrate comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, and a layer of silicon on a silicon substrate or an SOI substrate.

[0016] In various embodiments, the substrate 100 is or includes a part of a semiconductor device and may have undergone some steps of processing, for example, following a conventional process. For example, a semiconductor structure may include a substrate 100 in which various device regions are formed. At this stage, the substrate 100 may include isolation regions such as shallow trench isolation (STI) regions and other regions formed therein. Thus, the substrate 100 is used to collectively refer to any structures formed therein.

[0017] In various embodiments, the substrate 100 can be an etching target in an atomic layer etching (ALE) process. In other embodiments, although not specifically shown in FIG. 1A, the substrate 100 may include a layer formed therein, and the layer may be selectively etched to form concave features in the layer on the substrate 100.

[0018] As shown in FIG. 1A, a metal oxide resist (MOR) layer 110 can be formed on the substrate 100. In certain embodiments, the MOR layer 110 can be an EUV-active photoresist. In the present disclosure, MOR is used to refer to any metal oxide-based photoresist. Generally, MOR includes small metal oxide clusters having an organic part, which can undergo a photoreaction upon UV exposure to form a stable cross-linked metal oxide network structure. As will be further described below with reference to FIGS. 1B - 1C, the unreacted portion of the MOR can be selectively removed by a development step. The photoreaction can involve an increase in M - O - M bonds and the removal of the organic part. Thus, the chemical composition of the MOR before or after UV exposure may not be a stoichiometric metal oxide consisting of metal and oxygen, despite its name, and may only indicate the presence of metal and oxygen in the composition in some cases. In various embodiments, the MOR layer 110 can be a negative photoresist.

[0019] In certain embodiments, the MOR layer 110 may contain metal and oxygen. In one embodiment, the metal in the MOR layer 110 may be tin (Sn). The MOR layer 110 can be deposited on the substrate 100 using a dry process or a wet process, such as spin coating technology. In one or more embodiments using spin coating technology, a photoresist solution can be prepared by dissolving a metal oxide resist (MOR) or its precursor in a solvent, and the photoresist solution is then dispensed from a nozzle onto the central portion of the substrate 100. The photoresist solution onto the wafer can be dispensed either while the wafer is rotating (i.e., dynamic dispensing) or while it is not rotating (i.e., static dispensing). The wafer is rotated, for example, at a speed of 500 rpm to 4000 rpm, and centrifugal force acts, causing the photoresist solution to spread outward toward the edges of the substrate 100. As the solvent evaporates from the photoresist solution, the MOR layer 110 is formed on the substrate 100, uniformly coating the surface of the substrate 100. In certain embodiments, the MOR layer 110 has a thickness of 10 nm to 50 nm. The thickness of the MOR layer 110 can be selected considering the target feature size and the technique for patterning. For example, for semiconductor manufacturing of sub-5 nm nodes such as 3 nm nodes, a thin MOR layer may be desirable to achieve a feature size with sufficient patterning performance. Accordingly, in one embodiment, the MOR layer 110 has a thickness of 5 nm to 20 nm.

[0020] Process conditions for spin coating technology may include, among other things, spin speed, spin time, solvent system, and temperature. In certain embodiments, after spin coating, non-uniform features of the MOR layer 110 may be formed on the edge portions (e.g., edge beads) of the substrate 100. These non-uniform features can be removed by a conventional edge bead removal (EBR) process in which the solvent is distributed to the edge portions while the substrate 100 is rotated.

[0021] In certain embodiments, the substrate 100 may be optionally subjected to a soft bake to remove residual solvent from the MOR layer 110. The soft bake process may include heating the substrate 100 in a temperature range, for example, 75°C to 100°C.

[0022] In alternative embodiments, one or more deposition techniques may be used for deposition. Examples include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma-enhanced CVD (PECVD).

[0023] Figure 1B shows a cross-sectional view of the substrate 100 after the ultraviolet (UV) exposure step.

[0024] In Figure 1B, the UV lithography process can be performed by exposing the substrate 100 to UV radiation 120 through a photomask 125. The photomask 125 ensures that only the unmasked areas of the substrate 100 are irradiated with UV radiation 120. In various embodiments, the UV radiation 120 is extreme UV (EUV) (for example, having a wavelength of 13.5 nm).

[0025] The dose in the exposure step may be selected to balance pattern fidelity and mask selectivity during pattern transfer. In certain embodiments where EUV is used for the UV exposure step, the exposure is performed in a low-dose exposure regime, for example, 1 mJ / cm². 2 ~10mJ / cm 2Low-dose exposure can be performed in such a manner. Low-dose exposure can improve process efficiency and minimize the effects of UV irradiation on the device structure, but it can adversely affect the tonal characteristics of the photoresist, thereby impairing mask selectivity. Accordingly, improvement of the selectivity of subsequent pattern transfer etching may be necessary. Methods of the ALE process in various embodiments can improve mask selectivity and can be used to mitigate this challenge in low-dose exposure regimes. Low-dose exposure regimes in lithography can be particularly useful in applications such as low-power and high-performance metal oxide semiconductor (MOS) devices, high-resolution optical devices, and high-density memory devices with larger capacities. Furthermore, in other embodiments, methods using low-dose exposure regimes can be applied, for example, to manufacture transparent electrodes used in solar cells and touchscreens.

[0026] In the illustrated example, the MOR layer 110 functions as a negative-type photoresist. Accordingly, upon UV exposure, the exposed areas of the MOR layer 110 are converted directly or indirectly into reacted metal oxide 130. In contrast, the masked areas of the MOR layer 110 remain unreacted. The reacted metal oxide 130 may have substantially higher etching resistance compared to the MOR layer 110 due to its denser crosslinked metal oxide network structure, and the difference in material properties between the two areas (i.e., the reacted and unreacted areas) may enable the tonal characteristics of the UV photoresist.

[0027] In certain embodiments, a post-exposure bake (PEB) may be optionally performed after the UV exposure step by thermally treating the substrate 100. PEB may be beneficial in ensuring the removal of residual solvent and / or further differentiating the material properties of the reacted metal oxide 130 from those of the MOR layer 110. In one or more embodiments, PEB may be performed at 80–220°C.

[0028] Figure 1C shows a cross-sectional view of the substrate 100 after the development step.

[0029] After completing the UV exposure step and an optional post-exposure bake (PEB), a development step may be performed. In the embodiment shown in Figure 1C, any remaining unreacted portions of the MOR layer 110 can be selectively removed relative to the reacted metal oxide 130. In various embodiments, the reacted metal oxide 130 after the development step may provide a pattern that is transferred to the underlying structure for semiconductor manufacturing. In the embodiments shown in Figures 1A to 1G, the pattern can be transferred to the body of the substrate 100, while in other embodiments, a semiconductor or dielectric layer formed on the substrate 100 may be patterned accordingly. The pattern formed by the UV photolithography process (e.g., Figures 1A to 1C) may include vias, line recesses, or any concave features useful in semiconductor manufacturing. In one embodiment, the pattern of the reacted metal oxide 130 may have a pitch size of 10 nm to 40 nm.

[0030] The developing step can be a wet or dry process. Conventionally, photoresist can be removed by treating the substrate with a developer to decompose the reacted areas (in the case of positive-type resists) or unreacted areas (in the case of negative-type resists). In various embodiments, a similar wet process may be applied to remove the MOR layer 110. Alternatively, in other embodiments, a dry process may be used. A dry process may include, for example, a selective plasma etching process or a thermal process, which can conveniently eliminate the use of a developer. In certain embodiments, the dry process may be performed using a reactive ion etching (RIE) process or atomic layer etching (ALE).

[0031] Figure 1D shows a cross-sectional view of the substrate 100 after the ALE pretreatment step.

[0032] After the development step, one or more ALE pretreatment steps may be performed to prepare the exposed surface for the subsequent ALE process. In various embodiments, the ALE pretreatment step may include exposing the substrate 100 to a hydrogen-containing plasma 140 (e.g., H2 plasma). In various embodiments, after exposure to the plasma 140, the surface state of the reacted metal oxide 130 and the substrate 100 may be modified. Figure 1D shows the modified metal oxide surface 145 and the modified silicon surface 155. In one embodiment, the hydrogen plasma treatment may conveniently improve the selectivity of the modification step in the ALE process by, for example, increasing the hydroxyl groups on the modified metal oxide surface 145 and the silicon hydride on the modified silicon surface 155. In certain embodiments, another ALE pretreatment step may also be performed before the hydrogen plasma treatment. In one embodiment, before the hydrogen plasma treatment, the substrate 100 may be exposed to a fluorine-containing gas. Examples of fluorine-containing gases for the ALE pretreatment step include, but are not limited to, NF3, CF4, and C2F4. While we do not wish to be limited by any theory, these ALE pretreatment steps can conveniently help remove impurities from the surface.

[0033] In one or more embodiments, ALE pretreatment, particularly hydrogen plasma treatment, may also be useful for reducing the surface of the substrate 100. In one embodiment, native oxides (e.g., silicon oxide) formed on the substrate surface may be removed by hydrogen plasma treatment, increasing reactivity during the ALE process. Furthermore, such treatment can conveniently enable the application of the ALE process to a variety of etching target materials. For example, oxide materials such as silicon oxide can also be selectively etched against the MOR layer 110. The surface of the silicon oxide may first be reduced by hydrogen plasma treatment or other reduction steps, and then the reduced surface may be etched by ALE. Thus, each cycle of ALE may further include reduction steps for successively forming new reduced surfaces available for the next cycle of the ALE process. In one or more embodiments, the plasma 140 may be a remote plasma generated using a remote plasma source.

[0034] In various embodiments, after the ALE pretreatment step, the substrate 100 may be gradually etched using the ALE process. The ALE process may include periodically repeating a modification step (Figure 1E) and a removal step (Figure 1F) to achieve a target etching profile. Each cycle of the ALE process may remove one layer of material (e.g., silicon of the substrate 100) at a time (e.g., a single atomic layer in ALE, or several stacks of single atomic layers in pseudo-ALE).

[0035] Figure 1E shows a cross-sectional view of the substrate 100 after the modification step of the ALE process.

[0036] The reforming step can be carried out by exposing the substrate 100 to a reforming gas 160 containing a halogen. In various embodiments, the reforming gas 160 may contain CF4 or NF3. In certain embodiments, the reforming gas may further contain inert carrier gases such as helium (He), argon (Ar), and nitrogen (N2) in any proportion. In various embodiments, the chamber may first be filled with a flow of inert gas, and then a halogen-containing gas (e.g., CF4) may subsequently be supplied to the inert carrier flow as pulses.

[0037] In various embodiments, the modification step may be carried out as a non-plasma process in the absence of plasma. In certain embodiments, the substrate 100 may be kept at a temperature of 0°C to 100°C during the modification step. In other embodiments, the temperature may be maintained between -100°C and 40°C. In one embodiment, the non-plasma process for the modification step may be carried out at a pressure of 10 milliliters to 760 torr and a gas flow rate of 10 sccm to 1000 sccm.

[0038] Figure 1E shows a halogenated metal oxide surface 148 and a halogenated silicon surface 158. The inventors of this application have confirmed that the adsorption of halogen-containing gases (e.g., CF4) may be more favorable on the modified silicon surface 155 of the substrate 100 than on the reacted metal oxide 130, thereby conveniently improving the ALE selectivity of silicon-based materials to metal oxide materials. However, it should be noted that the halogen-containing gas molecules used in the modification step may or may not chemically react with the modified metal oxide surface 145 or the modified silicon surface 155 in Figure 1D. In certain embodiments, the halogenated metal oxide surface 148, the halogenated silicon surface 158, or both may primarily contain physically adsorbed molecules of halogen-containing gases.

[0039] In certain embodiments, after exposure to the reformed gas 160, the process chamber holding the substrate 100 may be purged with an inert gas. During the purging process, the substrate 100 may be exposed to a flow of an inert gas such as helium (He), argon (Ar), or nitrogen (N2). In some embodiments, the process chamber may be evacuated instead of purged. In even more specific embodiments, both purging and evacuating may be performed. In certain embodiments, the duration of the purging / evacuating process may range from 0.5 seconds to 300 seconds.

[0040] Figure 1F shows a cross-sectional view of the substrate 100 after the removal step of the ALE process.

[0041] The removal step of the ALE process may include exposing the substrate 100 to plasma 170 to form a recess 175 in the substrate 100. The depth of the recess 175 in Figure 1F has been appropriately enlarged for illustrative purposes. In various embodiments, the plasma 170 may include argon (Ar), other noble gases, dinitrogen (N2), or mixtures thereof in any mixing ratio. + The impact of ions may lead to the dissociation of halogen-containing gases adsorbed on the halogen-treated silicon surface 158 and the formation of etchant chemical species (e.g., F radicals). In contrast, etching of the halogen-treated metal oxide surface 148 may be substantially slower compared to the halogen-treated silicon surface 158. Various plasma parameters (e.g., source power and bias power) can be adjusted so that the plasma 170 can supply enough energy to enable material removal. Depending on the bias power, the impact may have strong directionality, and the ALE process may be adjusted to be anisotropic, although in other embodiments, isotropic ALE may be possible. In one or more embodiments, the plasma 170 may be formed from Ar and one or more reactive gases (e.g., H2).

[0042] In certain embodiments, the substrate 100 may be maintained at a temperature of 0°C to 100°C during the removal step. In other embodiments, the temperature may be maintained at -100°C to 40°C. In one embodiment, the plasma process for the removal step may be performed at a pressure of 10 mT to 100 mT, a gas flow rate of 50 sccm to 500 sccm, and a source power of 50 W to 1000 W.

[0043] Figure 1G shows a cross-sectional view of the substrate 100 after the ALE process steps have been periodically repeated.

[0044] In Figure 1G, the recess 175 can be extended to the target depth by periodically repeating the modification step (Figure 1E) and the removal step (Figure 1F). In certain embodiments, one or more of the ALE pretreatment steps (e.g., hydrogen plasma treatment) may also be repeated as part of the periodic ALE process. The process conditions for each step of the ALE process may be kept the same for each cycle, or they may be changed as the process progresses through multiple cycles. With appropriate conditions, the etching selectivity may be sufficient to minimize etching of the reacted metal oxide 130, allowing the recess 175 to be formed without completely consuming the reacted metal oxide 130, thereby conveniently improving the overall process efficiency of the EUV photolithography process using metal oxide resist (MOR) and subsequent pattern transfer steps. In certain embodiments, after the ALE process for forming the recess 175 is complete, any remaining reacted metal oxide 130 on the substrate 100 may be removed, for example, by a hydrogen-based plasma etching process.

[0045] Figure 2 shows the simulated adsorption energies of fluorine-containing adsorbates (CF4 and NF3) useful in the modification step of the ALE process on two surfaces (Si and SnO2).

[0046] The inventors of this application demonstrated the selective adsorption of etching agent precursors on an etching target surface by computer energy calculations. In Figure 2, the simulated adsorption energies of CF4 and NF3 as exemplary reforming gas components are plotted for Si and SnO2 surfaces. The adsorption energies are shown to be higher on the Si surface for both gases. For CF4, the adsorption energy on the Si surface is almost twice that on the SnO2 surface, and for NF3, it is more than four times. This difference in adsorption energies suggests that during the reforming step, the reforming gas may be more favorably adsorbed on the Si surface than on the metal oxide surface, meaning that more fluorine species may be formed on the silicon surface as an etching agent during the subsequent removal step. Accordingly, the combination of fluorine-containing reforming gases for ALE processes with plasma treatment (e.g., Ar plasma) can conveniently improve the etching selectivity of silicon to metal oxides.

[0047] As further shown in Figure 2, the adsorbates favored for adsorption differ for the two surfaces. On the Si surface, the adsorption energy of NF3 is greater than that of CF4, whereas on the SnO2 surface, the relationship is reversed (E ads-CF4 >E ads-NF3 In other words, when NF3 is used as the adsorbate, the difference in adsorption energy between the two surfaces (Si vs. SnO2) is greater. This demonstrates that the composition of the halogen-containing reforming gas can be selected and optimized considering the adsorption energy of the different materials being etched and protected.

[0048] The various embodiments of the ALE process described above can favorably overcome current challenges of metal oxide resists (MORs), such as tin oxide resists, in EUV photolithography applications by providing improved etching selectivity. Specifically, by using a halogen-containing modifying gas in the absence of plasma during the modification step, better control over etching selectivity and process flexibility can be achieved. At the same time, damage and consumption of the MOR can be suppressed, thus minimizing the risk of pattern collapse during pattern transfer to the underlying structure. The ability to use tin oxide resists can further improve EUV photolithography, particularly in terms of critical dimensional uniformity (CDU), yield, and process reliability. These advantages of the ALE process can be particularly useful in applications where thin photoresist layers (e.g., MOR layer 110) may be used. Generally, the thinner the photoresist layer, the better the etching selectivity required for subsequent pattern transfer etching. As a result, conventional pattern transfer techniques such as reactive ion etching (RIE) may not be sufficiently selective.

[0049] Figures 3A to 3C show process flow diagrams of the ALE process method according to various embodiments. The process flow can follow the diagrams described above (e.g., Figures 1A to 1G), and therefore will not be described again.

[0050] In Figure 3A, process flow 30 begins with forming a photoresist layer containing metal and oxygen on a silicon-containing substrate (block 310, Figure 1A), followed by patterning the photoresist layer using an extreme ultraviolet (EUV) photolithography process, after which a portion of the substrate is exposed (block 320, Figures 1B-1C). Subsequently, an atomic layer etching (ALE) process is performed so that the substrate can be selectively etched relative to the patterned photoresist layer (block 330, Figures 1E-1G).

[0051] In Figure 3B, another process flow 32 may include performing an atomic layer etching (ALE) process to selectively etch the silicon of the substrate against a metal oxide placed on the substrate (block 332). In various embodiments, the ALE process may include first exposing the substrate to a halogen-containing gas in the absence of plasma to form a modified surface layer containing silicon (block 333, Figure 1E), and then exposing the modified surface to a first plasma containing argon (Ar) to etch the modified surface layer (block 335, Figure 1F). The two exposure steps may be repeated to achieve the target etching depth (Figure 1G).

[0052] In Figure 3C, another process flow 34 may begin with forming a patterned tin oxide layer on a silicon (Si) substrate, after which a portion of the Si substrate is exposed (block 324, Figures 1A-1C). The Si substrate may then be exposed to a first plasma containing hydrogen (block 328, Figure 1D). Subsequently, a modified Si surface may be formed by exposing the Si substrate to a gas containing CF4 or NF3 in the absence of plasma (block 334, Figure 1E), followed by selective etching of the modified Si surface against the patterned tin oxide layer by exposing the modified Si surface to a second plasma containing argon (Ar) (block 336, Figure 1F).

[0053] Figure 4 shows a cross-sectional view of a plasma system for performing the ALE process according to one embodiment.

[0054] For illustrative purposes, Figure 4 shows a substrate 100 placed on a substrate holder 454 (e.g., a circular electrostatic chuck (ESC)) inside a plasma processing chamber 410 near the bottom. The substrate 100 may optionally be maintained at a desired temperature using a heater / cooler 456 surrounding the substrate holder 454. The temperature of the substrate 100 may be maintained by a temperature controller 440 connected to the substrate holder 454 and the heater / cooler 456. The ESC may be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that it can be electrically connected to the substrate holder 454.

[0055] As shown in Figure 4, the substrate holder 454 may be the bottom electrode of the plasma processing chamber 410. In the exemplary example in Figure 4, the substrate holder 454 is connected to two RF bias power supplies 470 and 480 via blocking capacitors 490 and 491. In some embodiments, a conductive circular plate near the top inside the plasma processing chamber 410 is the upper electrode 452. In Figure 4, the upper electrode 452 is connected to the DC power supply 450 of the plasma processing system 40.

[0056] The gas can be introduced into the plasma processing chamber 410 by a gas delivery system 420. The gas delivery system 420 includes multiple gas flow controllers for controlling the flow of multiple gases into the chamber. Each of the gas flow controllers of the gas delivery system 420 may be assigned to a fluorocarbon, a noble gas, or an equilibrator, respectively. In some embodiments, an optional center / edge splitter can be used to independently adjust the gas flow at the center and edges of the substrate 100.

[0057] RF bias power supplies 470 and 480 may be used to supply continuous wave (CW) power or pulsed RF power to maintain a plasma such as plasma 460. The plasma 460 shown between the upper electrode 452 and the bottom electrode (which is also the substrate holder 454) exemplifies the direct plasma generated near the substrate 100 within the plasma processing chamber 410 of the plasma processing system 40. Etching may be performed by exposing the substrate 100 to the plasma 460 while supplying power to the substrate holder 454 using the RF bias power supplies 470 and 480, and optionally supplying power to the upper electrode 452 using the DC power supply 450.

[0058] The configuration of the plasma processing system 40 described above is merely illustrative. In alternative embodiments, various alternative configurations of the plasma processing system 40 may be used. For example, inductively coupled plasma (ICP) may be used with RF source power coupled to a planar coil on the upper dielectric cover, and the gas inlet or gas outlet may be coupled to the upper wall, etc. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rate, and other plasma processing parameters may be selected according to the respective process recipe. In some embodiments, the plasma processing system 40 may be a resonator such as a helical resonator.

[0059] Figures 5A and 5B show a spatially isolated plasma system 500 for performing an ALE process according to another embodiment. Figure 5A is a top view and Figure 5B is a cross-sectional view.

[0060] In Figure 5A, the plasma system 500 may comprise four spatially separated compartments of a spatial processing chamber 540. Steps in the ALE process may be performed, for example, by moving the substrate through the four spatially separated compartments of the spatial processing chamber 540 using a rotatable stage 510.

[0061] In the top view shown in Figure 5A, the rotatable stage 510 is separated into four sections: a first purge section 545, a first processing section 550, a second purge section 555, and a second processing section 560. Both the first and second purge sections 545 and 555 function as inert gas curtains separating the two processing sections 550 and 560. An inert gas (e.g., argon, helium, or N2) is introduced through one of the gas inlets 520. Each section may have one or more gas inlets and gas outlets. In Figure 5A, the first processing section 550 has a gas inlet 552 and a gas outlet 524, the second processing section 560 has a gas inlet 523 and a gas outlet 525, and the two purge sections 545 and 555 have a gas inlet 520 and a gas outlet 526. In various embodiments, the modification step of the ALE process may be performed in a first processing section 550, and the removal step of the ALE process may be performed in a second processing section 560. Two purge sections 545 and 555 may be used to remove any residual gas or residual gas by-products from the previous step. In various embodiments, the purge gas may include a noble gas or dinitrogen (N2). By using a rotatable stage 510, these steps may be repeated periodically as a periodic etching process (pseudo-ALE or ALE) to gradually etch the target layer (e.g., a silicon substrate). In various embodiments, as described above, the modification step may be a non-plasma process, and the removal step may be a plasma process. Thus, at least one of the processing sections of the plasma system 500 (e.g., the second processing section 560) is configured to maintain the plasma and perform the plasma process. In another embodiment, a pretreatment step (e.g., H2 plasma) may also be performed within the plasma system 500, and the plasma system 500 may comprise at least two processing compartments, each of which is configured to maintain the plasma.

[0062] As further shown in Figure 5A, multiple substrates can be loaded onto the rotatable stage 510. The first substrate 502, shown loaded onto the rotatable stage 510 in the first processing compartment 550, may undergo an initial modification step (e.g., CF4 / NF3 exposure). As the rotatable stage 510 rotates, the first substrate 502 then moves to the second purging compartment 555 for purging, and then to the second processing compartment 560 for a removal step (e.g., Ar plasma exposure). Simultaneously, another substrate 504, positioned on the opposite side of the first substrate 502 on the rotatable stage 510 (e.g., initially in the second processing compartment 560 as shown in Figure 5A), is also processed as it moves from the second processing compartment 560 to the first purging compartment 545, and then to the first processing compartment 550, followed by the next rotation. Accordingly, multiple substrates can undergo different steps of the periodic deposition process simultaneously. One rotation of the rotatable stage 510 is equivalent to executing one cycle of the periodic deposition process.

[0063] In various embodiments, the first processing compartment 550 and the second processing compartment 560 may each be configured to maintain plasma for processing, but the ALE process may use only one of them for the plasma process. In other embodiments, only one of the two processing compartments may be configured to maintain plasma. The cross-sectional view shown in Figure 5B shows the processing compartments 550 and 560. In the exemplary spatial processing chamber 540, the processing compartments 550 and 560 are configured to maintain capacitively coupled plasma (CCP) using an upper electrode 512 coupled to an RF power supply 514. In the exemplary embodiment shown in Figure 5B, the rotatable stage 510 is electrically coupled to ground. The grounded rotatable stage 510 may function as a bottom electrode. Gas outlets 524, 525, and 526 are connected to a vacuum pump of the gas flow system and may be controlled to maintain a desired pressure and gas flow rate in the corresponding compartments.

[0064] The spatially separated plasma system 500 shown in Figure 5B is merely illustrative, and other plasma configurations may be used. In various alternative embodiments, the plasma system may be configured to maintain an inductively coupled plasma (ICP). In other embodiments, the periodic deposition process may be a non-plasma process and can still be performed using a spatially separated plasma system 500 or the like without colliding plasmas during deposition.

[0065] Exemplary embodiments of the present invention are described below. Other embodiments can also be understood from the entirety of this specification and the claims submitted herein. [Examples]

[0066] Example 1. A method for processing a substrate, comprising: forming a photoresist layer containing metal and oxygen on a silicon-containing substrate; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithography process, wherein a portion of the substrate is exposed after patterning; and selectively etching the substrate with respect to the patterned photoresist layer by performing an atomic layer etching (ALE) process.

[0067] Example 2. The ALE process according to Example 1, comprising exposing a substrate to a gas containing a halogen, exposing the substrate to a first plasma containing argon (Ar) to etch the substrate, and repeating the two exposure steps.

[0068] Example 3. The method according to one of Example 1 or 2, wherein the gas comprises CF4 or NF3.

[0069] Example 4. The method according to one of Examples 1 to 3, wherein the ALE process further comprises exposing the substrate to a second plasma containing hydrogen before exposure to a gas containing halogen.

[0070] Example 5. The method according to one of Examples 1 to 4, further comprising exposing the substrate to a fluorine-containing gas before the ALE process.

[0071] Example 6. The patterned photoresist layer is made of tin oxide, according to the method of one of Examples 1 to 5.

[0072] Example 7. The method according to one of Examples 1 to 6, wherein the substrate is a silicon (Si) substrate.

[0073] Example 8. The method according to one of Examples 1 to 7, wherein the substrate comprises silicon oxide, and the method further comprises a reduction step of reducing the surface of the substrate to silicon before the ALE process.

[0074] Example 9. A method for processing a substrate, comprising performing an atomic layer etching (ALE) process to selectively etch silicon on the substrate with respect to a metal oxide disposed on the substrate, wherein the ALE process includes: exposing the substrate to a halogen-containing gas in the absence of plasma to form a modified surface layer containing silicon; exposing the modified surface to a first plasma containing argon (Ar) to etch the modified surface layer; and repeating the two exposure steps.

[0075] Example 10. The method according to Example 9, wherein the metal oxide contains tin oxide and the halogen-containing gas contains CF4 or NF3.

[0076] Example 11. The ALE process according to one of Examples 9 or 10, wherein silicon is removed at a first etching rate and metal oxides are removed at a second etching rate, the first etching rate being greater than the second etching rate.

[0077] Example 12. The method according to one of Examples 9-11, wherein the ALE process further comprises exposing the substrate to a second plasma containing hydrogen in a plasma etching chamber before exposure to a halogen-containing gas.

[0078] Example 13. The method according to one of Examples 9-12, wherein the ALE process is performed in a plasma etching chamber, and the ALE process further comprises purging the etching product from the plasma etching chamber after exposure to the first plasma.

[0079] Example 14. The method according to one of Examples 9 to 13, wherein the ALE process is performed using a plasma system comprising a first process compartment and a second process compartment, the exposure to a halogen-containing gas is performed in the first process compartment and the exposure to a first plasma is performed in the second compartment.

[0080] Example 15. The method according to one of Examples 9 to 14, wherein the plasma system comprises a rotating stage configured to hold a substrate, and the ALE process further comprises transferring the substrate from a first process compartment to a second process compartment by rotating the rotating stage.

[0081] Example 16. A method for processing a substrate, comprising: forming a patterned tin oxide layer on a silicon (Si) substrate, wherein a portion of the Si substrate is exposed after the patterned tin oxide layer is formed; exposing the Si substrate to a first plasma containing hydrogen; forming a modified Si surface by exposing the Si substrate to a gas containing CF4 or NF3 in the absence of plasma; and selectively etching the modified Si surface with respect to the patterned tin oxide layer by exposing the modified Si surface to a second plasma containing argon (Ar).

[0082] Example 17. The method according to Example 16, wherein forming a patterned tin oxide layer comprises forming a photoresist layer containing tin and oxygen on a Si substrate, exposing the photoresist layer to an extreme ultraviolet (EUV) irradiation pattern such that the portion of the photoresist exposed to EUV forms tin oxide, and developing the photoresist layer to remove the unreacted portion of the photoresist layer, thereby forming a patterned tin oxide layer from the portion of the photoresist exposed to EUV.

[0083] Example 18. Exposure to the pattern for EUV irradiation was 1 mJ / cm². 2 ~30 mJ / cm² 2 The method according to one of Examples 16 or 17, performed in doses of [specify dose].

[0084] Example 19. The method according to one of Examples 16-18, wherein the patterned tin oxide layer has a pattern with a pitch size of 10 nm to 40 nm.

[0085] Example 20. The method according to any one of Examples 16 to 19, wherein exposure to the gas is performed at a temperature of 10°C to 30°C.

[0086] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. By reference to this specification, various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art. Therefore, the appended claims are intended to encompass all such modifications or embodiments.

Claims

1. A method for processing a substrate, wherein the method is Forming a photoresist layer containing metal and oxygen on a silicon-containing substrate, Patterning the photoresist layer using an extreme ultraviolet (EUV) photolithography process, wherein a portion of the substrate is exposed after the patterning. A method comprising performing an atomic layer etching (ALE) process to selectively etch the substrate with respect to the patterned photoresist layer.

2. The ALE process described above is Exposing the substrate to a gas containing halogens, The substrate is exposed to a first plasma containing argon (Ar) to etch the substrate, The method according to claim 1, comprising repeating the two exposure steps described above.

3. The aforementioned gas is CF ４ or NF ３ The method according to claim 2, including the method described in claim 2.

4. The method according to claim 2, further comprising exposing the substrate to a second plasma containing hydrogen before exposure to the gas containing the halogen.

5. The method according to claim 1, further comprising exposing the substrate to a fluorine-containing gas prior to the ALE process.

6. The method according to claim 1, wherein the patterned photoresist layer comprises tin oxide.

7. The method according to claim 1, wherein the substrate is a silicon (Si) substrate.

8. The method according to claim 1, wherein the substrate comprises a silicon oxide, and the method further comprises a reduction step of reducing the surface of the substrate to silicon before the ALE process.

9. A method for processing a substrate, wherein the method is The process involves performing an atomic layer etching (ALE) process to selectively etch silicon on a substrate with respect to a metal oxide disposed on the substrate, wherein the ALE process is: The substrate is exposed to a halogen-containing gas in the absence of plasma to form a modified surface layer containing silicon, The modified surface is exposed to a first plasma containing argon (Ar) to etch the modified surface layer. A method comprising etching, comprising repeating the two exposure steps described above.

10. The metal oxide includes tin oxide, and the halogen-containing gas is CF ４ or NF ３ The method according to claim 9, including the method described in claim 9.

11. The method according to claim 9, wherein the ALE process removes the silicon at a first etching rate and the metal oxide at a second etching rate, the first etching rate being greater than the second etching rate.

12. The method according to claim 9, further comprising exposing the substrate to a second plasma containing hydrogen in the plasma etching chamber prior to exposure to the halogen-containing gas.

13. The method according to claim 9, wherein the ALE process is performed in a plasma etching chamber, and the ALE process further comprises purging the etching product from the plasma etching chamber after exposure to the first plasma.

14. The method according to claim 9, wherein the ALE process is performed using a plasma system comprising a first process chamber and a second process chamber, the exposure to the halogen-containing gas is performed in the first process chamber, and the exposure to the first plasma is performed in the second chamber.

15. The method according to claim 14, wherein the plasma system comprises a rotating stage configured to hold the substrate, and the ALE process further comprises transferring the substrate from the first process section to the second process section by rotating the rotating stage.

16. A method for processing a substrate, wherein the method is The process involves forming a patterned tin oxide layer on a silicon (Si) substrate, wherein a portion of the Si substrate is exposed after the patterned tin oxide layer has been formed. Exposing the Si substrate to a first plasma containing hydrogen, The Si substrate is subjected to CF in the absence of plasma. ４ or NF ３ By exposing the Si surface to a gas containing the following, A method comprising selectively etching the modified Si surface with respect to the patterned tin oxide layer by exposing the modified Si surface to a second plasma containing argon (Ar).

17. Forming the aforementioned patterned tin oxide layer is A photoresist layer containing tin and oxygen is formed on the Si substrate, The photoresist layer is exposed in a pattern of extreme ultraviolet (EUV) irradiation, wherein the portion of the photoresist exposed to EUV forms tin oxide. The method according to claim 16, comprising developing the photoresist layer to remove unreacted portions of the photoresist layer, and forming the patterned tin oxide layer from the EUV-exposed portion of the photoresist.

18. The exposure in the pattern of the EUV irradiation is 1 mJ / cm ２ ~30 mJ / cm ２ The method according to claim 17, which is performed in doses of [number].

19. The method according to claim 16, wherein the patterned tin oxide layer has a pattern having a pitch size of 10 nm to 40 nm.

20. The method according to claim 16, wherein the exposure to the gas is carried out at a temperature of 10°C to 30°C.

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