Integrated circuit with vertical differential superconducting qubit loop and method for manufacturing the same

Abstract

The superconducting circuit and its fabrication method may include at least a portion of a superconducting qubit having high coherence, low noise, and low sensitivity, which can be integrated with other structures and devices of a quantum processor. The superconducting circuit may include a motion inductance layer directly superimposed on a substrate, a first dielectric layer superimposed on the motion inductance layer, and a superconducting wiring layer superimposed on the first dielectric layer. The motion inductance layer includes a first qubit conductor of a superconducting qubit loop containing a superconducting material having a relatively high inductance value, and the superconducting wiring layer includes at least a second qubit conductor containing a superconducting material having a relatively low inductance value to complete the loop. Further layers may include a shielding structure, a feedback path between the second qubit conductor and the first qubit conductor, a galvanic coupling connection interface, and a flux bias interface with conductors on different layers.

Description

[Technical Field]

[0001] Cross-reference of related applications This patent application claims priority to U.S. Patent Application No. 63 / 529,840, filed on 31 July 2023, the entire disclosure of which is incorporated herein by reference in its entirety.

[0002] Technical field This disclosure relates in general to low-noise superconducting integrated circuits for quantum processors, and more specifically to superconducting integrated circuits including vertical differential qubit loops and methods for manufacturing the same. [Background technology]

[0003] background Superconducting integrated circuits Superconductivity is a set of physical properties observed in a material in which its electrical resistance disappears and magnetic flux fields are excluded from the material. Materials exhibiting these properties are referred to as superconductors in this application. Superconductors generally have a specific critical temperature below which their electrical resistance drops to zero. Materials exhibiting these properties are also referred to as superconducting materials in this application. Superconducting materials may include, for example, superconducting metals. Niobium is a superconducting metal that becomes superconducting below 9.2 K. Current in a loop of a superconducting material can persist indefinitely without a power source.

[0004] An integrated circuit (also referred to in this application as a chip) is one or more electronic circuits on a single (or "chip") substrate. In some configurations, the substrate is silicon. In other configurations, the substrate is sapphire. By integrating a large number of devices onto a chip, circuits can be made orders of magnitude smaller, faster, and cheaper than circuits built with individual electronic components.

[0005] A superconducting integrated circuit is an integrated circuit that contains a superconducting material. A superconducting circuit (e.g., a superconducting integrated circuit) may contain one or more superconducting devices. If the superconducting integrated circuit includes a superconducting quantum processor, the superconducting devices of the superconducting integrated circuit may be, for example, superconducting qubits, coupling devices, readout devices, or magnetic flux storage devices.

[0006] Superconducting processor Quantum processors can take the form of superconducting processors. However, superconducting processors may include processors not designed for quantum computing. For example, some embodiments of superconducting processors may operate by emphasizing different principles, such as the principles governing the operation of classical computer processors, rather than focusing on quantum effects such as quantum tunneling, superposition, and entanglement. However, there may still be some advantages to implementing such superconducting "classical" processors. Due to their natural physical properties, superconducting classical processors may be capable of faster switching speeds and shorter computation times than non-superconducting processors, and therefore, solving certain problems on superconducting classical processors may be more practical in some cases.

[0007] Superconducting qubit Superconducting qubits are a type of superconducting quantum device that can be included in superconducting integrated circuits. Superconducting qubits can be classified into several categories depending on the physical properties used to encode information. For example, superconducting qubits can be classified into charge devices, flux devices, and phase devices. Charge devices store and manipulate information in the charge state of the device. Flux devices store and manipulate information in variables related to the magnetic flux passing through a part of the device. Phase devices store and manipulate information in variables related to the superconducting phase difference between two regions of the device. Superconducting qubits typically include at least one Josephson junction. A Josephson junction is a small break in a continuous superconducting current path and is generally realized by a thin insulating barrier sandwiched between two superconducting electrodes. Thus, a Josephson junction may be implemented as a three-layer (or "tri-layer") structure. Superconducting qubits are further described, for example, in U.S. Patents 7,876,248, 8,035,540, and 8,098,179.

[0008] Quantum processor Quantum processors can take the form of superconducting quantum processors. Superconducting quantum processors may include several superconducting qubits and associated local bias devices. Superconducting quantum processors may also include couplers (also known as coupling devices or qubit couplers) that selectively provide communicative coupling between qubits.

[0009] Superconducting qubits are solid-state qubits based on circuits of superconducting materials. The operation of superconducting qubits is based on the fundamental principles of flux quantization and Josephson tunneling. The superconducting effect can exist in different configurations, giving rise to different types of superconducting qubits, including flux qubits, phase qubits, charge qubits, and hybrid qubits. These different configurations can differ in the loop topology, the arrangement of Josephson junctions, and the physical parameters of the superconducting circuit elements, such as inductance, capacitance, and critical current of the Josephson junctions.

[0010] In one implementation, a superconducting qubit includes a superconducting loop separated by a Josephson junction. The inductance and critical current can be selected, adjusted, or tuned to increase the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop, and to enable the qubit to operate as a bistable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop of the qubit is approximately equal to 3.

[0011] In one implementation, the superconducting coupler includes a superconducting loop separated by a Josephson junction. The inductance and critical current can be selected, adjusted, or tuned to reduce the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop, and to enable the coupler to operate as a monostable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop of the coupler is approximately 1 or less.

[0012] Further details and embodiments of quantum processors that may be used in conjunction with this system and device are described, for example, in U.S. Patents 7,533,068, 8,008,942, 8,195,596, 8,190,548, and 8,421,053.

[0013] Noise in quantum processors A quantum processor may require a local bias to be applied to a qubit in order to implement the Hamiltonian problem. The local bias applied to a qubit is a persistent current I, as described below. p and external magnetic flux bias φ q It depends on. δh i =2|I p |δφ q

[0014] Noise is caused by the external magnetic flux bias φ q Similarly, local bias δh i This affects the problem Hamiltonian and therefore changes the specification of the qubit term. By changing the problem Hamiltonian, noise can introduce errors into the computation results from quantum annealing. However, this is only one type of erroneous specification that can result from noise. Noise can also have undesirable effects on the precision of qubit coupling, readout, and other programming of the quantum processor.

[0015] Low noise is a desirable characteristic of quantum devices. Noise can impair or degrade the functionality of individual devices, such as superconducting qubits, and the entire superconducting processor. For example, in a quantum processor performing quantum annealing, noise can negatively affect qubit coherence and reduce the effectiveness of qubit tunneling by inducing transitions from coherent to non-coherent tunneling. Since noise is a serious concern for the operation of quantum processors, measures should be taken to reduce noise as much as possible.

[0016] Impurities may be deposited on the metal surface and / or arise from the interaction of the etching / photoresist chemical system with the metal. Noise can be caused by impurities inside the quantum processor components or on the surface of the quantum processor. In some cases, noise-sensitive superconducting devices are manufactured on the top wiring layer of superconducting integrated circuits, and as a result are sensitive to post-manufacturing handling. There is a risk that noise-causing impurities will be introduced during post-manufacturing handling. One technique to reduce noise is to use a barrier passivation layer (e.g., an insulating layer) superimposed on the top wiring layer. The use of a barrier passivation layer to minimize noise from impurities on the surface of a quantum processor is described in U.S. Patent Application No. 2018 / 0219150 (granted as U.S. Patent No. 10454015).

[0017] Noise can also arise from the external environment or surrounding circuits in a superconducting processor. In a quantum processor, flux noise on a qubit can prevent proper annealing of the quantum processor due to abrupt transitions between qubit states when the flux bias is swept. Flux noise may be the result of currents flowing through the wiring of other devices included within the superconducting processor, and can particularly affect qubits at each qubit's degeneracy point. For example, flux noise can cause errors in calculations performed by the superconducting processor due to inaccuracies in setting the flux bias value and coupling strength value. Reducing or eliminating such inaccuracies can be particularly advantageous when using an integrated circuit as part of a quantum processor. Some of the static control errors can be designed out of the processor by careful layout and high-precision flux sources, and adding circuits such as on-chip shields to tune away non-ideal flux qubit behavior. However, often due to the limitations of the integrated circuit manufacturing capabilities, it can be difficult to address noise by changing the layout of the processor and adding circuits. Thus, there is a general need for materials and methods for manufacturing an integrated circuit with reduced (and thus improved coherence) flux noise without being forced to compromise the layout of the quantum processor by adding additional layers or circuits.

[0018] Shielding and Noise Magnetic fields generated by external sources can cause unwanted interactions with devices within an integrated circuit. Thus, there may be a need for a superconducting shield proximate to devices present in the integrated circuit to reduce the intensity of interference such as magnetic and electric fields.

[0019] In single flux quantum (SFQ) or rapid single flux quantum (RSFQ) technology, a superconducting shield layer may be used to isolate a device from a DC power line that may undesirably bias the device. The device is present in an integrated circuit but is isolated from the DC power line by placing a ground plane between the device and the DC power line.

[0020] In SFQ circuits, the ground plane and the shield layer are terms used synonymously. The ground plane in an SFQ integrated circuit is a metal layer that appears as an infinite ground potential for most signals within the circuit. The ground plane helps reduce noise within the integrated circuit and can be used to ensure that all components within the SFQ integrated circuit have a common potential for comparing voltage signals. Contacts can be used between wiring layers and the ground plane throughout the SFQ circuit.

[0021] The superconducting current flowing in a superconducting wire has an associated magnetic field similar to the electrons flowing in a normal metal wire. The magnetic field can inductively couple to the superconducting wire and drive a current. Quantum information processing using superconducting integrated circuits necessarily involves the movement of superconducting currents within wires and, as a result, associated magnetic fields.

[0022] The quantum properties of quantum devices are very sensitive to noise, and stray magnetic fields within superconducting quantum devices can adversely affect the quantum information processing properties of such circuits. Superconducting ground planes have been used in the art to reduce crosstalk between control lines and devices. However, such techniques are relatively robust against in-circuit noise and have only been used in superconducting integrated circuits for classical processing and sensor applications that operate at a considerably higher temperature compared to superconducting quantum processing integrated circuits.

[0023] In a superconducting quantum processing integrated circuit, it is desirable to substantially attenuate and control unwanted crosstalk between devices; otherwise, quantum information processing on a commercial scale may be impossible. The present method, system, and apparatus provide techniques for attenuating crosstalk between quantum devices in a superconducting quantum processing integrated circuit in order to support desirable quantum effects and to controllably couple quantum devices in a way that enables the exchange of coherent quantum information.

[0024] Kinetic inductance A current flowing through a metallic material stores energy in principle in both the magnetic field of that metal and the kinetic energy of the charge carriers (e.g., electrons or Cooper pairs). In a non-superconducting metal, the charge carriers collide frequently with the lattice and lose kinetic energy as Joule heating. This is also called scattering and releases energy rapidly. However, in a superconducting material, the charge carriers are Cooper pairs protected from dissipation by scattering, so scattering is substantially reduced. This enables the superconducting material to store energy in the form of kinetic inductance. This phenomenon allows kinetic inductance to efficiently store energy within the superconducting metal. Kinetic inductance is determined at least in part by the inertial mass of the charge carriers of a given material and increases as the carrier density decreases. As the carrier density decreases, a smaller number of carriers need to have proportionally higher velocities to generate the same current. A material having a high kinetic inductance for a given area (as defined below) is called a "kinetic inductance material" or "high kinetic inductance material".

[0025] A kinetic inductance material is a material having a high normal-state resistivity and / or a small superconducting energy gap, resulting in a larger kinetic inductance per unit area. Generally, the total inductance L of a superconducting material is given by L = L K + L G wherein, L G is the geometric inductance and L KThis is the kinetic inductance. The kinetic inductance of a superconducting film at near-zero temperature is equal to the effective penetration depth λ. eff It is proportional to . In particular, for a film with a given thickness t, the kinetic inductance of the film is proportional to the ratio of the film length L to the film width W (where the length is in the direction of the current and the width is perpendicular to the length) (note that both the width and length are perpendicular to the dimension in which the thickness is measured). That is, for a superconducting film with a given thickness,

number

number

[0026] In some implementations, it can be beneficial to attempt to maximize the kinetic inductance with the minimum volume. This involves attempting to minimize the film width and achieve a high effective penetration depth λ. eff This may include selecting a suitable material having the properties of and selecting the length of the film to achieve the desired kinetic inductance. Subject to manufacturing constraints, it may also be beneficial to try to minimize the thickness t of the material, such that t < 3λ. eff(bulk) In the case of (where λ eff(bulk) (This is the effective penetration depth of bulk material, not thin film), λ eff is, at least approximately

number

[0027] Manufacturing of integrated circuits Traditionally, the manufacturing of superconducting integrated circuits has not been carried out using state-of-the-art semiconductor manufacturing equipment. This may be due to the fact that some of the materials used in superconducting integrated circuits can contaminate semiconductor equipment. For example, gold is sometimes used as a resistor in superconducting circuits, but gold can contaminate the manufacturing tools used to produce CMOS wafers in semiconductor equipment. Therefore, superconducting integrated circuits containing gold are typically not processed with tools that also process CMOS wafers.

[0028] The fabrication of superconductors is generally carried out in a research environment where standard industry practices for the manufacture of superconducting circuits can be optimized. Superconducting integrated circuits are often manufactured using tools similar to those conventionally used to manufacture semiconductor chips or integrated circuits. Due to challenges specific to superconducting circuits, not all semiconductor processes and technologies are necessarily applicable to the manufacture of superconducting chips. Converting semiconductor processes and technologies for use in the manufacture of superconducting chips and circuits often requires modifications and fine-tuning. Such modifications and adjustments are generally not obvious and may require numerous experiments. The semiconductor industry faces issues and challenges that are not necessarily related to the superconducting industry. Similarly, issues and challenges of interest to the superconducting industry are often little to no relevant to standard semiconductor manufacturing.

[0029] Impurities within superconducting chips can introduce noise that can impair or degrade the functionality of individual devices, such as superconducting qubits, and the superconducting chip as a whole. Since noise is a serious concern for the operation of quantum computers, measures should be taken to reduce dielectric noise as much as possible.

[0030] The field of integrated circuit manufacturing generally involves multiple processes that can be ordered and / or combined to produce a desired effect. Exemplary systems and methods for manufacturing superconducting integrated circuits, which can be combined whole or in part with at least some embodiments of the System and Method, are described in U.S. Patents No. 8,951,808 and No. 9,768,371, which are incorporated herein by reference in their entirety.

[0031] etching Etching removes layers, such as a substrate, dielectric layer, oxide layer, electrical insulating layer, and / or metal layer, according to a desired pattern outlined by photoresist or other masking techniques. Two exemplary etching techniques are wet chemical etching and dry chemical etching.

[0032] Wet chemical etching, or "wet etching," is generally achieved by immersing wafers in an etching bath, such as an acid bath. Typically, the etching solution is contained in a temperature-controlled polypropylene bath. The bath is usually equipped with either a ring-shaped plenum exhaust or a slotted exhaust port at the rear of the etching station. A vertical laminar flow hood is commonly used to supply uniformly filtered, particulate-free air to the top surface of the etching bath.

[0033] Dry chemical etching, or "dry etching," is commonly used due to its ability to better control the etching process and reduce contamination levels. Dry etching effectively etches the desired layer by using gases through chemical reactions, such as the use of chemically reactive gases, or by physical impact, such as plasma etching using argon atoms.

[0034] For example, plasma etching systems have been developed that can effectively etch silicon, silicon dioxide, silicon nitride, aluminum, tantalum, tantalum compounds, chromium, tungsten, gold, and many other materials. Two types of plasma etching reactor systems, barrel reactor systems and parallel plate reactor systems, are commonly used. Both types of reactors operate on the same principle, differing mainly only in their configuration. A typical reactor consists of a vacuum reactor chamber, usually made of aluminum, glass, or quartz. A radio frequency or microwave energy source (collectively called an RF energy source) is used to activate a fluorine-based or chlorine-based gas that acts as the etching solution. A wafer is loaded into the chamber, a pump evacuates the chamber, and the reactive gas is introduced. The RF energy ionizes the gas and forms an etching plasma, which reacts with the wafer to form volatile products (these volatile products are pumped out).

[0035] Physical etching processes utilize physical impact. For example, argon gas atoms can be used to physically impact the layer to be etched, and a vacuum pump system is used to remove the displaced material. Sputter etching is a physical technique involving ion collisions and energy transfer. The wafer to be etched is mounted on a negative electrode or "target" in a glow discharge circuit. Positive argon ions impact the wafer surface, causing displacement of surface atoms. Power is supplied by an RF energy source. Ion beam etching and milling are physical etching processes that remove material using a low-energy ion beam. The ion beam is extracted from an ionized gas (e.g., argon or argon / oxygen) or plasma generated by a discharge.

[0036] Reactive ion etching (RIE) is a combination of chemical and physical etching. During RIE, a wafer is placed in a chamber with a low-pressure atmosphere of chemically reactive gases (e.g., CF4, CCl4, CHF3, and many other gases). The discharge generates an ion plasma with energies of several hundred electron volts. These ions strike the wafer surface perpendicularly, where they react to form volatile species that are removed by a low-pressure in-line vacuum system.

[0037] flattening Chemical-mechanical planarization (CMP) makes it possible to produce nearly flat surfaces. CMP is a standard process in the semiconductor industry. The CMP process uses an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring that are pressed by a dynamic polishing head. This tends to remove material, flatten irregular topography, and make the wafer flat or planar.

[0038] The above-mentioned examples of related technologies and their associated limitations are illustrative and not exclusive. Other limitations of related technologies will become apparent to those skilled in the art by reading this specification and examining the drawings. [Overview of the project] [Problems that the invention aims to solve]

[0039] overview Superconducting qubits used in quantum computing benefit from high coherence so that computations can be performed before quantum information is lost. The coherence of superconducting qubits can be enhanced by reducing noise and crosstalk transmitted to the qubit from the environment and other structures within the quantum processor. Integrating superconducting qubits into strategically ordered multilayer fabricated stacks, including other devices and structures within the quantum processor, can lead to improved flexibility and control of the superconducting qubits, increased scalability of quantum processors and greater complexity of solvable problems, and reduced exposure of control signals to environmental noise. [Means for solving the problem]

[0040] This specification describes a superconducting circuit comprising at least a highly coherent superconducting qubit loop of superconducting qubits that can be integrated with other structures of a quantum processor, and a method for manufacturing the superconducting circuit. The superconducting qubit loop comprises two qubit loop conductor segments having asymmetric inductance values, which may allow control of the ratio of qubit inductance between the qubit control structure and the coupler connection interface so that the qubit can be galvanically coupled to a superconducting coupler. The orientation of the qubit loop conductor segments in the superconducting circuit may be selected to limit crosstalk between the superconducting qubit loop and the structure coupled to the qubit.

[0041] In one embodiment, a superconducting circuit is provided. The superconducting circuit includes a substrate, a kinetic inductance layer directly overlapping the substrate, a first dielectric layer overlapping at least a portion of the kinetic inductance layer, and a device loop superconducting wiring layer overlapping the first dielectric layer. The kinetic inductance layer includes a material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature. At least a first portion of the kinetic inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device. The device loop superconducting wiring layer includes a relatively low inductance superconducting material having a relatively low inductance value and exhibiting superconducting behavior below a critical temperature, wherein the relatively low inductance superconducting material has a lower inductance value compared to a relatively high inductance value. At least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop.

[0042] In some implementations, the superconducting circuit further includes a second dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, and a shielding superconducting wiring layer overlapping the second dielectric layer for shielding at least the superconducting loop.

[0043] In some implementations, the superconducting loop of the main body of a superconducting controllable device is the superconducting qubit loop of the qubit body of a superconducting qubit.

[0044] In some implementations, the superconducting qubit loop of the qubit body is galvanically coupled to the Josephson junction of the superconducting qubit. The motion inductance layer includes at least one pair of coupler connection leads of the qubit body, each pair of which is positioned at a distance from the Josephson junction along the length of the first device loop conductor segment such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction. The superconducting circuit further includes at least one pair of coupler connection interfaces, each pair of which is for galvanically coupling one pair of coupler connection leads of the superconducting qubit to the corresponding one pair of coupler leads of the superconducting coupler.

[0045] In some implementations, the superconducting circuit further includes a first intermediate superconducting wiring layer directly overlapping at least a first dielectric layer, a second dielectric layer overlapping at least a portion of the first intermediate superconducting wiring layer, a third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, and a second intermediate superconducting wiring layer overlapping at least a portion of the third dielectric layer. Each pair of coupler connection interfaces includes at least a pair of first layer coupler connection portions on the first intermediate superconducting wiring layer directly overlapping a corresponding pair of coupler connection leads, a pair of device loop layer coupler connection portions on the device loop superconducting wiring layer directly overlapping a pair of first layer coupler connection portions, and a pair of second layer coupler connection portions on the second intermediate superconducting wiring layer directly overlapping a pair of device loop layer coupler connection portions.

[0046] In some implementations, for each pair of coupler connection interfaces, one pair of second-layer coupler connection portions is directly galvanically coupled to one pair of coupler lead wires.

[0047] In some implementations, the superconducting circuit further includes a fourth dielectric layer superimposed on at least a second intermediate superconducting wiring layer, and a third intermediate superconducting wiring layer directly superimposed on at least the fourth dielectric layer. For each pair of coupler connection interfaces, the first coupler connection interface of the pair of coupler connection interfaces includes a first second layer coupler connection portion of a pair of second layer coupler connection portions that are directly galvanically coupled to the first coupler lead of a pair of coupler leads, and the second coupler connection interface of the pair of coupler connection interfaces includes a third layer coupler connection portion on a third intermediate superconducting wiring layer that is directly superimposed on the second second layer coupler connection portion of a pair of second layer coupler connection portions, the third layer coupler connection portion being directly galvanically coupled to the second coupler lead of a pair of coupler leads.

[0048] In some implementations, the superconducting circuit further includes a first intermediate superconducting wiring layer overlapping a first dielectric layer, a second dielectric layer directly overlapping at least a portion of the first intermediate superconducting wiring layer, a third dielectric layer directly overlapping at least a portion of the device loop superconducting wiring layer, a second intermediate superconducting wiring layer directly overlapping at least the third dielectric layer, and a fourth dielectric layer overlapping at least the second intermediate superconducting wiring layer. The first intermediate superconducting wiring layer includes one or more first bias loop conductor segments positioned to align with and overlap the first qubit loop conductor segment along the cross-section of the superconducting circuit. The second intermediate superconducting wiring layer includes one or more second bias loop conductor segments, each of which is positioned to align with and overlap the corresponding one of the first bias loop conductor segments along the cross-section of the superconducting circuit.

[0049] In some implementations, the body of the superconducting controllable device is symmetrical with respect to a vertical centerline along the width of the superconducting circuit.

[0050] In some implementations, the superconducting circuit further includes one or more flux bias loops, each flux bias loop enclosing a portion of the length of a second device loop conductor segment, and an external superconducting wiring layer of the body of a superconducting controllable device, each having at least one pair of bias line interfaces. Each pair of bias line interfaces is directly electrically coupled to the corresponding flux bias loop.

[0051] In some implementations, each of the one or more flux bias loops includes a plurality of superconducting vias electrically coupling a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, and a plurality of superconducting vias electrically coupling the corresponding second bias loop conductor segment to a corresponding first bias loop conductor segment.

[0052] In some implementations, each of one or more flux bias loops includes a corresponding first bias loop conductor segment from one or more first bias loop conductor segments, a first bias loop portion of a first intermediate superconducting wiring layer directly overlapping the corresponding first bias loop conductor segment, a second bias loop portion of a qubit loop superconducting wiring layer directly overlapping the first bias loop portion, a corresponding second bias loop conductor segment from one or more second bias loop conductor segments, and a third bias loop portion of a second intermediate superconducting wiring layer directly overlapping the corresponding second bias loop conductor segment and located below a corresponding pair of bias line interfaces.

[0053] In some implementations, each pair of at least one bias line interface can be directly electrically coupled to the corresponding pair of analog lines such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first and second device loop conductor segments. Each pair of analog lines can be operated to transmit the corresponding bias signal to the superconducting loop of the body of the superconducting controllable device.

[0054] In some implementations, the feedback path electrically couples a second device loop conductor segment to a kinetic inductance layer. The feedback path surrounds the first device loop conductor segment, at least partially.

[0055] In some implementations, the feedback path includes multiple superconducting vias that enable communication between a second device loop conductor segment and a first device loop conductor segment.

[0056] In some implementations, the kinetic inductance layer includes a first kinetic inductance layer feedback termination and a second kinetic inductance layer feedback termination, located along the cross-section of the superconducting circuit on the first and second sides of the first device loop conductor segment, respectively. The superconducting circuit further comprises a first intermediate superconducting wiring layer overlapping at least a portion of the first dielectric layer and the kinetic inductance layer, and a second dielectric layer overlapping at least a portion of the first intermediate superconducting wiring layer and the first dielectric layer. The device loop superconducting wiring layer overlaps the second dielectric layer. The feedback path includes a first intermediate layer feedback path portion and a second intermediate layer feedback path portion on the first intermediate superconducting wiring layer, which overlap directly on the first and second kinetic inductance layer feedback terminations and the second kinetic inductance layer feedback terminations, and the second device loop conductor segment overlaps directly on the first and second intermediate feedback path portions to communicately couple the second device loop conductor segment to the kinetic inductance layer.

[0057] In some implementations, the superconducting circuit further comprises a shielding structure, the shielding structure including a shielding superconducting wiring layer on the outer surface of the body of the superconducting controllable device in the superconducting circuit, and a first shielding arm and a second shielding arm extending from the shielding superconducting wiring layer through the superconducting circuit to a first intermediate superconducting wiring layer so as to at least partially surround a second device loop conductor segment and a feedback path.

[0058] In some implementations, the first and second shield arms include superconducting vias that extend from the shield superconducting wiring layer through the superconducting circuit to the first intermediate superconducting wiring layer.

[0059] In some implementations, the superconducting circuit further includes a third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, and the shielded superconducting wiring layer overlaps the third dielectric layer and at least a portion of the device loop superconducting wiring layer. The first and second shielding arms are a first intermediate layer shielding structure portion and a second intermediate layer shielding structure portion on a first intermediate superconducting wiring layer, each of which is located at a corresponding lateral position along the width of the cross-section of the superconducting circuit, and a first device loop layer shielding structure portion and a second device loop layer shielding structure portion on a device loop superconducting wiring layer overlapping the first dielectric layer. The shielded superconducting wiring layer overlaps directly on the first device loop layer shielding structure portion and the second device loop layer shielding structure portion to communicately couple the shielded superconducting wiring layer to the first intermediate superconducting wiring layer.

[0060] In some implementations, the superconducting loop of the superconducting controllable device body is galvanically coupled to the Josephson junction of the superconducting controllable device. The kinetic inductance layer includes at least one pair of coupler connection leads of the superconducting controllable device body, each pair of coupler connection leads positioned at a distance from the Josephson junction along the length of the first device loop conductor segment such that the majority of the total inductance of the superconducting controllable device is located between each pair and the Josephson junction. The superconducting circuit further includes at least one pair of coupler connection interfaces, each pair of which is for galvanically coupling a pair of coupler connection leads of the superconducting controllable device to a corresponding pair of coupler leads of a superconducting coupler.

[0061] In some implementations, the superconducting circuit further includes a third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, and a second intermediate superconducting wiring layer overlapping at least a portion of the third dielectric layer. Each pair of coupler connection interfaces includes a pair of first layer coupler connection portions on the first intermediate superconducting wiring layer that directly overlap a corresponding pair of coupler connection leads, a pair of device loop layer coupler connection portions on the device loop superconducting wiring layer that directly overlap a pair of first layer coupler connection portions, and a pair of second layer coupler connection portions on the second intermediate superconducting wiring layer that directly overlap a pair of device loop layer coupler connection portions.

[0062] In some implementations, for each pair of coupler connection interfaces, one pair of second-layer coupler connection portions can be directly galvanically coupled to one pair of coupler lead wires.

[0063] In some implementations, the superconducting circuit further includes a fourth dielectric layer overlapping at least a portion of a second intermediate superconducting wiring layer, and a third intermediate superconducting wiring layer overlapping at least a portion of the fourth dielectric layer. For each pair of coupler connection interfaces, the first coupler connection interface of the pair of coupler connection interfaces includes a first second layer coupler connection portion of a pair of second layer coupler connection portions that can be directly galvanically coupled to the first coupler lead of a pair of coupler leads, and the second coupler connection interface of the pair of coupler connection interfaces includes a third layer coupler connection portion on a third intermediate superconducting wiring layer that overlaps directly on the second second layer coupler connection portion of the pair of second layer coupler connection portions, and the third layer coupler connection portion can be directly galvanically coupled to the second coupler lead of a pair of coupler leads.

[0064] In some implementations, the first intermediate superconducting wiring layer includes one or more first bias loop conductor segments, each of which is aligned with and overlaps a first device loop conductor segment along the cross-section of the superconducting circuit. The superconducting circuit further includes a third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, a second intermediate superconducting wiring layer overlapping the third dielectric layer, and a fourth dielectric layer overlapping at least a portion of the second intermediate superconducting wiring layer. The second intermediate superconducting wiring layer includes one or more second bias loop conductor segments, each of which is aligned with and overlaps a corresponding one of the first bias loop conductor segments along the cross-section of the superconducting circuit.

[0065] In some implementations, the body of the superconducting controllable device is symmetrical with respect to a vertical centerline along the width of the superconducting circuit.

[0066] In some implementations, the superconducting circuit further includes one or more flux bias loops, each flux bias loop enclosing a portion of the length of a second device loop conductor segment, and an external superconducting wiring layer of the body of a superconducting controllable device, each having at least one pair of bias line interfaces. Each pair of bias line interfaces is directly electrically coupled to the corresponding flux bias loop.

[0067] In some implementations, each of the one or more flux bias loops includes a plurality of superconducting vias electrically coupling a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, and a plurality of superconducting vias electrically coupling the second bias loop conductor segment to a corresponding first bias loop conductor segment.

[0068] In some implementations, each of the one or more flux bias loops includes a corresponding first bias loop conductor segment from one or more first bias loop conductor segments, a first bias loop portion of a first intermediate superconducting wiring layer directly overlapping the corresponding first bias loop conductor segment, a second bias loop portion of a device loop superconducting wiring layer directly overlapping the first bias loop portion, a corresponding second bias loop conductor segment from one or more second bias loop conductor segments, and a third bias loop portion of a second intermediate superconducting wiring layer directly overlapping the corresponding second bias loop conductor segment.

[0069] In some implementations, each pair of at least one bias line interface can be directly electrically coupled to the corresponding pair of analog lines such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first and second device loop conductor segments. Each pair of analog lines is for transmitting the corresponding bias signal to the superconducting loop of the body of the controllable device.

[0070] In some implementation configurations, materials with relatively high inductance values ​​include titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

[0071] In some implementations, the substrate contains an electrical insulating material, which is one of the following: silicon dioxide, silicon trioxide, silicon nitride, quartz, and sapphire.

[0072] In some implementations, superconducting materials with relatively low inductance include one of aluminum, niobium, and tantalum.

[0073] In some implementations, the superconducting loop of the main body of a superconducting controllable device is the superconducting coupler loop of the coupler body of a superconducting coupler.

[0074] In some implementations, the superconducting loop of the main body of a controllable superconducting device is the same superconducting loop as the main body of a quantum flex parametron (QFP).

[0075] In one embodiment, a method for manufacturing a superconducting circuit is provided. The method includes forming a kinetic inductance layer directly on a substrate, forming a first dielectric layer on top of at least a portion of the kinetic inductance layer, and forming a device loop superconducting wiring layer on top of the first dielectric layer. The kinetic inductance layer comprises a relatively high inductance superconducting material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature. At least a first portion of the kinetic inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device. The device loop superconducting wiring layer comprises a relatively low inductance superconducting material having a lower inductance value compared to a high inductance value and exhibiting superconducting behavior below a critical temperature. At least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop.

[0076] In some implementation configurations, forming a kinetic inductance layer involves depositing a relatively high-inductance superconducting material on the surface of a substrate and patterning the deposited relatively high-inductance superconducting material so as to include at least a first device loop conductor segment of a superconducting loop. Forming a first dielectric layer involves at least depositing a dielectric material on the surface of the kinetic inductance layer. Forming a device loop superconducting wiring layer involves depositing a relatively low-inductance superconducting material and patterning the relatively low-inductance superconducting material so as to include at least a second device loop conductor segment of a superconducting loop.

[0077] In some implementation configurations, the method further includes forming a second dielectric layer by depositing a dielectric material on at least a portion of the surface of a device loop superconducting wiring layer, and forming a shielded superconducting wiring layer by depositing a layer of relatively low inductance superconducting material on top of the second dielectric layer.

[0078] In some implementation configurations, forming a motion inductance layer directly on a substrate, wherein at least a first portion of the motion inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device, and forming a motion inductance layer, wherein at least a first portion of the motion inductance layer is a first qubit loop conductor segment of the superconducting qubit loop of the qubit body of a superconducting qubit. Forming a device loop superconducting wiring layer so as to overlap a first dielectric layer, wherein at least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming a device loop superconducting wiring layer, wherein the device loop superconducting wiring layer is a qubit loop superconducting wiring layer, and at least a portion of the qubit loop superconducting wiring layer is a second qubit loop conductor segment of the qubit superconducting loop.

[0079] In some implementations, the method further includes forming a Josephson junction that is galvanically coupled to the superconducting qubit loop of the qubit body, and forming one or more pairs of coupler connection interfaces. Forming the motion inductance layer includes depositing a high-inductance superconducting material and patterning the deposited high-inductance superconducting material to include a first qubit loop conductor segment and one or more pairs of coupler connection leads of the qubit body. Each pair of the one or more pairs of coupler connection leads is patterned along the length of the first qubit loop conductor segment, at a distance from the Josephson junction, such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction. The one or more pairs of coupler connection interfaces are for galvanically coupling the corresponding pair of coupler connection leads of the qubit body of the superconducting qubit to the corresponding pair of coupler leads of the superconducting coupler.

[0080] In some implementations, the method further includes forming a first intermediate superconducting wiring layer so as to overlap at least a portion of a first dielectric layer, forming a second dielectric layer so as to overlap at least a portion of the first intermediate superconducting wiring layer, forming a third dielectric layer so as to overlap at least a portion of a qubit loop conductor segment superconducting wiring layer, and forming a second intermediate superconducting wiring layer so as to overlap at least a portion of the third dielectric layer. To form each pair of one or more pairs of coupler connection interfaces, forming a first intermediate superconducting wiring layer includes depositing a second layer of relatively low inductance superconducting material and patterning the second layer of relatively low inductance superconducting material to include a pair of first layer coupler connection portions that directly overlap the corresponding pair of coupler connection leads; forming a qubit loop superconducting wiring layer further includes patterning a first layer of relatively low inductance superconducting material to include a pair of qubit loop layer coupler connection portions that directly overlap the pair of first layer coupler connection portions; and forming a second intermediate superconducting wiring layer includes depositing a third layer of relatively low inductance superconducting material and patterning the third layer of relatively low inductance superconducting material to include a pair of second layer coupler connection portions that directly overlap the pair of qubit loop layer coupler connection portions.

[0081] In some implementations, patterning a third layer of relatively low-inductance superconducting material to include a pair of second-layer coupler connection portions, wherein the second-layer coupler connection can be directly galvanically coupled to a pair of coupler leads.

[0082] In some implementations, the method further includes forming a fourth dielectric layer so as to overlap at least a portion of a second intermediate superconducting wiring layer, and forming a third intermediate superconducting wiring layer so as to overlap at least a portion of the fourth dielectric layer. For each pair of coupler connection interfaces, patterning a third layer of relatively low inductance superconducting material to include a pair of second layer coupler connection portions includes patterning the third layer of relatively low inductance superconducting material to include a first second layer coupler connection portion of a pair of second layer coupler connection portions that are directly galvanically coupled to a first coupler lead of a pair of coupler leads, and forming a third intermediate superconducting wiring layer includes depositing a fourth layer of relatively low inductance superconducting material and patterning the fourth layer of relatively low inductance superconducting material to include a third layer coupler connection portion that directly overlaps a second second layer coupler connection portion of a pair of second layer coupler connection portions, the third layer coupler connection portion being directly galvanically coupled to a second coupler lead of a pair of coupler leads.

[0083] In some implementation configurations, the method further includes forming a first intermediate superconducting wiring layer on top of a first dielectric layer, wherein the first intermediate superconducting wiring layer includes one or more first bias loop conductor segments; forming a second dielectric layer on top of at least a portion of the first intermediate superconducting wiring layer; forming a third dielectric layer on top of at least a portion of the device loop superconducting wiring layer; forming a second intermediate superconducting wiring layer on top of the third dielectric layer, wherein the formation of the second intermediate superconducting wiring layer includes the formation of one or more second bias loop conductor segments; and forming a fourth dielectric layer on top of at least a portion of the second intermediate superconducting wiring layer.

[0084] In some implementations, forming a first intermediate superconducting wiring layer includes depositing a first layer of relatively low inductance superconducting material and patterning the first layer of relatively low inductance superconducting material to align with a first device loop conductor segment along the cross-section of the superconducting circuit and to form one or more first bias loop conductor segments in positions overlapping the first device loop conductor segment. Forming a second intermediate superconducting wiring layer includes depositing a second layer of relatively low inductance superconducting material and patterning the second layer of relatively low inductance superconducting material to align with a corresponding one of the first bias loop conductor segments along the cross-section of the superconducting circuit and to form one or more second bias loop conductor segments in positions overlapping the corresponding one.

[0085] In some implementations, the method further includes forming an external superconducting wiring layer of the body of a superconducting controllable device, which includes at least one pair of bias line interfaces, and forming one or more flux bias loops, which include at least a corresponding first bias loop conductor segment and a corresponding second bias loop conductor segment, wherein each flux bias loop surrounds a portion of the length of the second device loop conductor segment. Each pair of bias line interfaces is directly electrically coupled to the corresponding flux bias loop.

[0086] In some implementations, forming each of one or more flux bias loops involves forming multiple superconducting vias to electrically couple a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, and forming multiple superconducting vias to electrically couple the second bias loop conductor segment to a corresponding first bias loop conductor segment.

[0087] In some implementations, forming a first intermediate superconducting wiring layer to form one or more flux bias loops includes depositing a first layer of relatively low inductance superconducting material and patterning the first layer of relatively low inductance superconducting material to include a corresponding first bias loop conductor segment and a first bias loop portion that directly overlaps the first bias loop conductor segment. Forming a device loop superconducting wiring layer further includes depositing a second layer of relatively low inductance superconducting material and patterning the second layer of relatively low inductance superconducting material to include a second device loop conductor segment and a second bias loop portion that directly overlaps the first bias loop portion. Forming a second intermediate superconducting wiring layer further includes depositing a third layer of a relatively low inductance superconducting material and patterning the third layer of the relatively low inductance superconducting material to include a corresponding second bias loop conductor segment and a third bias loop portion that directly overlaps the corresponding second bias loop conductor segment and is located beneath a corresponding pair of bias line interfaces.

[0088] In some implementations, the method further includes forming a feedback path that electrically couples a second device loop conductor segment of the superconducting loop to a kinetic inductance layer. The feedback path has a relatively low inductance value and at least partially surrounds the first device loop conductor segment.

[0089] In some implementations, forming a feedback path involves forming multiple superconducting vias to enable communication between a second device loop conductor segment and a first device loop conductor segment.

[0090] In some implementations, forming a motion inductance layer includes depositing a relatively high inductance superconducting material and patterning the relatively high inductance superconducting material such that it includes a first device loop conductor segment and, along the cross-section of the superconducting circuit, a first motion inductance layer feedback path termination and a second motion inductance layer feedback path termination on the first and second sides of the first device loop conductor segment, respectively. The method further includes forming a first intermediate superconducting wiring layer, which includes depositing a first layer of a relatively low inductance superconducting material and patterning the first layer of the relatively low inductance superconducting material such that it includes a first intermediate layer feedback path portion and a second intermediate layer feedback path portion that directly overlap the first motion inductance layer feedback path termination and the second motion inductance layer feedback path termination, respectively, and forming a second dielectric layer that overlaps at least a portion of the first intermediate superconducting wiring layer, wherein the device loop superconducting wiring layer overlaps the second dielectric layer. Forming a device loop superconducting wiring layer involves depositing a second layer of a relatively low inductance superconducting material and patterning the second layer of the relatively low inductance superconducting material to include a second device loop conductor segment. The second device loop conductor segment directly overlaps the first and second intermediate feedback path portions.

[0091] In some implementations, the method further includes forming a shield structure, which includes forming a shield superconducting wiring layer on the outer surface of the body of a superconducting controllable device in a superconducting circuit, and forming a first shield arm and a second shield arm that at least partially surround a second device loop conductor segment and a feedback path.

[0092] In some implementations, forming the first and second shield arms involves forming superconducting vias that extend from the shield superconducting wiring layer through the superconducting circuit to the first intermediate superconducting wiring layer.

[0093] In some implementations, the method further includes forming a third dielectric layer that overlaps at least a portion of the device loop superconducting wiring layer. To form a first shield arm and a second shield arm, forming a first intermediate superconducting wiring layer further includes patterning a first layer of relatively low inductance superconducting material such that it includes a first intermediate layer shield structure portion and a second intermediate layer shield structure portion, respectively, in corresponding lateral positions along the width of the cross-section of the superconducting circuit; forming a device loop superconducting wiring layer further includes patterning a second layer of relatively low inductance superconducting material such that it includes a first device loop layer shield structure portion and a second device loop layer shield structure portion that overlap directly on the first intermediate layer shield structure portion and the second intermediate layer shield structure portion, respectively; and forming a shield superconducting wiring layer includes depositing a shield layer of relatively low inductance superconducting material that overlaps directly on at least the first device loop layer shield structure portion and the second device loop layer shield structure portion.

[0094] In some implementations, the method further includes forming a Josephson junction that is galvanically coupled to the superconducting loop of the body of the superconducting controllable device, and forming one or more pairs of coupler connection interfaces. Forming the kinetic inductance layer involves patterning a high-inductance superconducting material to include one or more pairs of coupler connection leads of the body of the superconducting controllable device, and further includes patterning each pair of coupler connection leads on the kinetic inductance layer at a distance from the Josephson junction along the length of the first device loop conductor segment, such that the majority of the total inductance of the superconducting controllable device is located between each pair and the Josephson junction. The one or more pairs of coupler connection interfaces are for galvanically coupling a corresponding pair of coupler connection leads of the body of the superconducting controllable device to a corresponding pair of coupler leads of a superconducting coupler.

[0095] In some implementations, the method further includes forming a fourth dielectric layer so as to overlap at least a portion of the device loop superconducting wiring layer, and forming a second intermediate superconducting wiring layer so as to overlap at least a portion of the fourth dielectric layer. To form each pair of one or more pairs of coupler connection interfaces, forming a first intermediate superconducting wiring layer includes depositing a second layer of relatively low inductance superconducting material and patterning the second layer of relatively low inductance superconducting material to include a pair of first layer coupler connection portions that directly overlap the corresponding pair of coupler connection leads; forming a device loop superconducting wiring layer further includes patterning a first layer of relatively low inductance superconducting material to include a pair of device loop layer coupler connection portions that directly overlap the pair of first layer coupler connection portions; and forming a second intermediate superconducting wiring layer includes depositing a third layer of relatively low inductance superconducting material and patterning the third layer of relatively low inductance superconducting material to include a pair of second layer coupler connection portions that directly overlap the pair of device loop layer coupler connection portions.

[0096] In some implementations, patterning a third layer of relatively low-inductance superconducting material to include a pair of second-layer coupler connection portions is a method of patterning a third layer of relatively low-inductance superconducting material to include a pair of second-layer coupler connection portions that can be directly galvanically coupled to a pair of coupler leads.

[0097] In some implementations, the method further includes forming a fourth dielectric layer so as to overlap at least a portion of a second intermediate superconducting wiring layer, and forming a third intermediate superconducting wiring layer so as to overlap at least a portion of the fourth dielectric layer. To form each pair of one or more pairs of coupler connection interfaces, patterning a third layer of relatively low inductance superconducting material to include a pair of second layer coupler connection portions includes patterning the third layer of relatively low inductance superconducting material to include a first second layer coupler connection portion of a pair of second layer coupler connection portions that are directly galvanically coupled to a first coupler lead of a pair of coupler leads, and forming a third intermediate superconducting wiring layer includes depositing a fourth layer of relatively low inductance superconducting material and patterning the fourth layer of relatively low inductance superconducting material to include a third layer coupler connection portion that directly overlaps a second second layer coupler connection portion of a pair of second layer coupler connection portions, the third layer coupler connection portion being directly galvanically coupled to a second coupler lead of a pair of coupler leads.

[0098] In some implementations, forming a first intermediate superconducting wiring layer further includes patterning a first layer of a relatively low inductance superconducting material to include one or more first bias interface loop conductor segments, each of which is aligned with and overlaps a first device loop conductor segment along the cross-section of the superconducting circuit. The method further includes forming a second intermediate superconducting wiring layer so as to overlap a third dielectric layer, comprising depositing a third layer of a relatively low inductance superconducting material, and patterning the third layer of the relatively low inductance superconducting material so as to include one or more second bias loop conductor segments, wherein each of the one or more second bias loop conductor segments is patterned to align with a corresponding one of the first bias loop conductor segments along the cross-section of the superconducting circuit and to overlap the corresponding one, and forming a fourth dielectric layer so as to overlap at least a portion of the second intermediate superconducting wiring layer.

[0099] In some implementations, the method further includes forming an external superconducting wiring layer of the body of a superconducting controllable device, which includes at least one pair of bias line interfaces, and forming one or more flux bias loops, which include at least a corresponding first bias loop conductor segment and a corresponding second bias loop conductor segment, wherein each flux bias loop surrounds a portion of the length of the second device loop conductor segment. Each pair of bias line interfaces is directly galvanically coupled to the corresponding flux bias loop.

[0100] In some implementations, forming each of one or more flux bias loops involves forming multiple superconducting vias to electrically couple a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, and forming multiple superconducting vias to electrically couple the second bias loop conductor segment to a corresponding first bias loop conductor segment.

[0101] In some implementations, forming a first intermediate superconducting wiring layer to form one or more flux bias loops further includes patterning a first layer of relatively low inductance superconducting material to include a corresponding first bias loop conductor segment and a first bias loop portion directly overlapping the first bias loop conductor segment; forming a device loop superconducting wiring layer further includes patterning a second layer of relatively low inductance superconducting material to include a second bias loop portion directly overlapping the first bias loop portion; and forming a second intermediate superconducting wiring layer further includes patterning a third layer of relatively low inductance superconducting material to include a corresponding second bias loop conductor segment and a third bias loop portion directly overlapping the corresponding second bias loop conductor segment and located beneath a corresponding pair of bias line interfaces.

[0102] In some implementations, forming a kinetic inductance layer involves forming the kinetic inductance layer from one of titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

[0103] In some implementations, forming a superconducting loop layer involves forming a superconducting wiring layer from one of aluminum, niobium, and tantalum.

[0104] In some implementation configurations, forming a motion inductance layer directly on a substrate, wherein at least a first portion of the motion inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device, and forming a motion inductance layer, wherein at least a first portion of the motion inductance layer is a first coupler loop conductor segment of the superconducting coupler loop of the coupler body of a superconducting coupler. Forming a loop superconducting wiring layer so as to overlap a first dielectric layer, wherein at least a portion of the loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming a device loop superconducting wiring layer, wherein at least a portion of the coupler loop superconducting wiring layer is a second coupler loop conductor segment of the coupler superconducting loop.

[0105] In some implementation configurations, forming a kinetic inductance layer directly on a substrate, wherein at least a first portion of the kinetic inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device, and forming a kinetic inductance layer, wherein the first loop conductor segment is a portion of the superconducting body loop of a quantum flux parametron (QFP). Forming a loop superconducting wiring layer so as to overlap a first dielectric layer, wherein at least a portion of the loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming a device loop superconducting wiring layer, wherein the second device loop conductor segment is a second portion of the superconducting body loop of a QFP.

[0106] In one embodiment, a superconducting qubit is provided. The superconducting qubit includes a qubit body having a superconducting qubit loop, which includes a first qubit loop conductor segment communicatively coupled to a second qubit loop conductor segment. The first qubit loop conductor segment includes a relatively high inductance superconducting material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature, and the second qubit loop conductor segment includes a relatively low inductance superconducting material having a relatively low inductance value compared to the relatively high inductance value of the relatively high inductance superconducting material and exhibiting superconducting behavior below a critical temperature. The second qubit loop conductor segment overlaps the first qubit loop conductor segment within at least a portion of a superconducting circuit comprising the superconducting qubit. The superconducting qubit includes a Josephson junction electrically coupled to the superconducting qubit loop of the qubit body.

[0107] In some implementations, the qubit body further includes a shielding structure that at least partially surrounds the superconducting qubit loop, and includes at least a planar shielding portion on the outer surface of the qubit body that overlaps the second qubit loop conductor segment in at least a portion of the superconducting circuit. The planar shielding portion includes a superconducting material with relatively low inductance.

[0108] In some implementations, the shield structure further comprises a pair of shield arms, each of which extends from the planar shield portion to at least a portion of the superconducting circuit so as to at least partially surround the second qubit loop conductor segment. The shield arms contain a superconducting material with relatively low inductance.

[0109] In some implementations, the qubit body further includes a feedback path extending from a second qubit loop conductor segment to the feedback path termination. The feedback path termination contains a superconducting material with relatively high inductance and is positioned on at least a portion of the same superconducting circuit layer as the first qubit loop conductor segment, such that the feedback path at least partially surrounds the first qubit loop conductor segment. At least a large portion of the feedback path contains a superconducting material with relatively low inductance.

[0110] In some implementations, the first qubit loop conductor segment comprises one or more pairs of coupler connection leads, and the qubit body further comprises one or more pairs of coupler connection interfaces. Each pair of the one or more pairs of coupler connection interfaces is configured to galvanically couple one pair of the one or more pairs of coupler connection leads to the corresponding pair of coupler leads of a superconducting coupler.

[0111] In some implementations, each pair of coupler connection leads of one or more pairs is positioned at a distance from the Josephson junction along the length of the qubit body, such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction.

[0112] In some implementations, each pair of coupler connection interfaces of one or more pairs of qubit bodies includes a first coupler connection interface and a second coupler connection interface. The first and second coupler connection interfaces each extend through at least a portion of the superconducting circuit from the first and second coupler connection leads of a corresponding pair of coupler connection leads to the first and second coupler connection sites of the qubit body. The first and second coupler connection sites are located on the same layer of at least a portion of the superconducting circuit that overlaps the second qubit loop conductor segment. The first and second coupler connection interfaces include a superconducting material with relatively low inductance.

[0113] In some implementations, each pair of one or more pairs of coupler connection interfaces includes a first coupler connection interface extending through at least a portion of the superconducting circuit from a first coupler connection lead of a corresponding pair of coupler connection leads to a first coupler connection site of a qubit body that can galvanically couple to the first coupler lead of the corresponding pair of coupler leads. The first coupler connection site overlaps a second qubit loop conductor segment. Each pair of one or more pairs of coupler connection interfaces includes a second coupler connection interface extending through at least a portion of the superconducting circuit from a second coupler connection lead of a pair of coupler connection leads to a second coupler connection site of a qubit body that can galvanically couple to the second coupler lead of the pair of coupler leads. The second coupler connection site overlaps a first coupler connection site. The first and second coupler connection interfaces include a superconducting material with relatively low inductance.

[0114] In some implementations, the qubit body further includes one or more bias connection interfaces, each bias connection interface for electrically coupling the superconducting qubit loop to a corresponding pair of analog lines for transmitting bias signals. Each bias connection interface includes a first bias loop conductor segment interposed between a first qubit loop conductor segment and a second qubit loop conductor segment, wherein the first bias loop conductor segment is aligned with the first qubit loop conductor segment along the width of at least a portion of the superconducting circuit; and a second bias loop conductor segment overlapping the second qubit loop conductor segment, wherein the second bias loop conductor segment is aligned with the first bias loop conductor segment along the width of at least a portion of the superconducting circuit.

[0115] In some implementations, each of the one or more bias connection interfaces includes a pair of bias line interfaces on the outer surface of the qubit body in the superconducting circuit, overlapping the second qubit loop conductor segment, wherein the pair of bias line interfaces can be directly electrically coupled to the corresponding pair of analog lines. Each of the one or more bias connection interfaces includes a flux bias loop of the qubit body surrounding a portion of the length of the second qubit loop conductor segment. The flux bias loop includes a first bias loop conductor segment and a second bias loop conductor segment, and the flux bias loop galvanically couples the first bias loop conductor segment, the second bias loop conductor segment, and the pair of bias line interfaces. The pair of bias line interfaces and the flux bias loop include a superconducting material with relatively low inductance.

[0116] In some implementations, a pair of bias line interfaces can be coupled to a corresponding pair of analog lines so as to communicate directly with them, such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first and second qubit loop conductor segments.

[0117] In some implementations, the outer surface of the qubit body in at least a portion of the superconducting circuit further includes at least a portion of a shielding structure. The shielding structure includes a superconducting material with relatively low inductance.

[0118] In some implementations, superconducting qubits are symmetrical with respect to a vertical centerline along the width of the qubit body.

[0119] In some implementations, superconducting materials with relatively high inductance include one of titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

[0120] In some implementations, superconducting materials with relatively low inductance include one or more of aluminum, niobium, and tantalum.

[0121] In some implementations, the inductance per unit length of a relatively high-inductance superconducting material is 50 times greater than that of a relatively low-inductance superconducting material.

[0122] A brief explanation of some of the views in the drawing. In drawings, the same reference number identifies similar elements or acts. The size and relative position of elements in a drawing are not necessarily depicted to a fixed scale. For example, the shapes and angles of various elements are not necessarily depicted to a fixed scale, and some of these elements are arbitrarily enlarged and positioned to improve the readability of the drawing. Furthermore, the specific shapes of depicted elements are not necessarily intended to convey information about the actual shape of those elements, but are merely selected to facilitate recognition in the drawing. [Brief explanation of the drawing]

[0123] [Figure 1] This is a schematic diagram of a hybrid computing system, including a digital computer coupled to an analog computer, as disclosed herein. [Figure 2] This is a schematic diagram of an exemplary superconducting quantum processor circuit according to the present disclosure. [Figure 3] This is a schematic diagram of a portion of a multilayer manufacturing stack representing an exemplary packaging configuration of a superconducting integrated circuit as disclosed herein. [Figure 4] This is an upper plan view of a qubit according to the present disclosure. [Figure 5A] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5B] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5C] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5D] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5E] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5F] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 5G] This is a cross-sectional view of a superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing, as disclosed herein. [Figure 6A] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6B] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6C] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6D] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6E] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6F] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6G]This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6H] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6I] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 6J] This disclosure shows a cross-sectional view of an alternative superconducting integrated circuit including a vertical differential qubit loop conductor segment in a continuous stage of manufacturing. [Figure 7A] This is a cross-sectional view of a portion of a superconducting integrated circuit, including a vertical differential qubit loop conductor segment and a vertical differential magnetic flux bias line, as disclosed herein. [Figure 7B] This is a cross-sectional view of a portion of an alternative superconducting integrated circuit, including a vertical differential qubit loop conductor segment and a vertical differential flux bias line, as disclosed herein. [Figure 8A] This is a plan view of a portion of a superconducting integrated circuit including a vertical differential qubit loop conductor segment and a bias line interface, as disclosed herein. [Figure 8B] This is a cross-sectional view of the superconducting integrated circuit shown in Figure 8A, according to this disclosure. [Figure 9A] This disclosure is a plan view of a portion of a superconducting integrated circuit, including a vertical differential qubit loop conductor segment and a coupler connection interface, in one stage of manufacturing. [Figure 9B] This is a plan view of the superconducting integrated circuit shown in Figure 9A at a later stage of manufacturing, according to the present disclosure. [Figure 9C] This is a cross-sectional view of the superconducting integrated circuit shown in Figure 9B according to this disclosure. [Figure 9D] Figure 9A is a plan view of the superconducting integrated circuit in a post-manufacturing stage according to this disclosure. [Figure 9E] This is a cross-sectional view of the superconducting integrated circuit shown in Figure 9D, according to this disclosure. [Figure 10]This flowchart shows a method for fabricating a superconducting circuit including a vertical differential qubit loop conductor segment according to the present disclosure. [Modes for carrying out the invention]

[0124] Detailed explanation preamble The following description includes certain specific details to provide a full understanding of the various implementations and embodiments disclosed. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures relating to superconducting devices, integrated superconducting circuits, and manufacturing equipment are not illustrated or described in detail to avoid unnecessarily complicating the description of the implementations or embodiments of the Method. Throughout this specification and the appended claims, the terms “element” and “multiple elements” are used to encompass (but not limited to) all such structures, systems, and devices relating to superconducting circuits and integrated superconducting circuits.

[0125] Unless the context requires otherwise interpretation, throughout this specification and the subsequent claims, the term “comprise” is synonymous with “including,” and is inclusive or open-ended (i.e., does not exclude any additional undescribed elements or actions).

[0126] Throughout this specification, references to “one embodiment,” “a certain embodiment,” “another embodiment,” “one example,” “a certain example,” “another example,” “one implementation,” and “another implementation” mean that a particular related feature, structure, or characteristic described in relation to that embodiment, example, or implementation is included in at least one embodiment, example, or implementation. Therefore, the appearance of expressions such as “in one embodiment,” “in a certain embodiment,” and “another embodiment” in various parts of this specification does not necessarily all refer to the same embodiment, example, or implementation. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, examples, or implementations.

[0127] Note that, as used herein and in the appended claims, the singular forms “a,” “an,” and “the” refer to multiple objects unless the context explicitly states otherwise. For example, a reference to a circuit containing “a device” includes a single device or two or more devices. Also note that, unless the context explicitly states otherwise, the term “or” generally means “and / or.”

[0128] In the description of superconducting circuits herein, the term “layer” may refer to a material having thickness, where at least a portion of the material is in contact with at least a portion of a further surface. In some implementations, at least a portion of a layer may fill gaps between multiple portions of a preceding layer (e.g., by patterning of the preceding layer). Thus, even when referred to as multiple layers, two or more referred to layers may be spaced apart along the cross-section of the superconducting circuit and located on the same level or plane, or on a common level or plane.

[0129] In the description of superconducting circuits as used herein, the terms “overlie” and “overlying” mean that a layer directly or indirectly overlaps a reference layer. “Directly overlapping” a reference layer means that the layer is directly formed on at least a portion of the reference layer without an intervening layer. “Indirectly overlapping” a layer means that the layer is formed on at least a portion of the reference layer with at least one intervening layer between the reference layer and the layer. The above assumes a specific orientation of the superconducting circuit, but is not intended to be limiting. Therefore, the superconducting orientation shown in the figure can, for example, be inverted upside down.

[0130] In this specification, “galvanic” coupling may refer to an electrical coupling in which coupled structures and / or devices share a common metal length, and “direct galvanic coupling” may refer to a galvanic coupling in which there is no intervening metal layer between coupled structures and / or devices.

[0131] The headings provided herein are for convenience only and do not constitute an interpretation of the scope or meaning of the embodiments.

[0132] Exemplary computing system Figure 1 shows a computing system 100 with a digital computer 102. The exemplary digital computer 102 includes one or more digital processors 106 that may be used to perform conventional digital processing tasks. The digital computer 102 may further include at least one system memory 122 and at least one system bus 120 that connects various system components, including the system memory 122, to one or more digital processors 106. The system memory 122 may store one or more processor-executable instruction sets, sometimes referred to as modules 124.

[0133] One or more digital processors 106 may be any logic processing units or circuits (e.g., integrated circuits), such as one or more central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), application-specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers ("PLCs"), and / or combinations thereof. One or more digital processors 106 may be operated at room temperature, cooled to below room temperature, or even cooled and operated at cryogenic temperatures.

[0134] In some implementations, the computing system 100 comprises a quantum computer 104, which may include one or more quantum processors 126. The quantum processors 126 may include at least one superconducting integrated circuit manufactured using the systems and methods described herein. The digital computer 102 may communicate with the quantum computer 104, for example, via a controller 118. Certain calculations may be performed by the quantum computer 104 at the direction of the digital computer 102, as will be described in more detail herein.

[0135] The digital computer 102 may include a user input / output subsystem 108. In some implementations, the user input / output subsystem includes one or more user input / output components, such as a display 110, a mouse 112, and / or a keyboard 114.

[0136] The system bus 120 may use any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. The system memory 122 may include non-volatile memory such as read-only memory ("ROM"), static random-access memory ("SRAM"), and flash NAND, and volatile memory such as random-access memory ("RAM").

[0137] The digital computer 102 may also include other non-temporary computer or processor-readable storage media, or non-volatile memory 116. The non-volatile memory 116 can take various forms, including a hard disk drive for reading and writing to a hard disk (e.g., a magnetic disk), an optical disk drive for reading and writing to a removable optical disk, and / or a solid-state drive (SSD) for reading and writing to a solid-state medium (e.g., NAND-based flash memory). The non-volatile memory 116 can communicate with one or more digital processors via the system bus 120 and may include a suitable interface or controller 118 coupled to the system bus 120. The non-volatile memory 116 may function as long-term storage for processor or computer-readable instructions, data structures, or other data (sometimes referred to as program modules or modules 124) for the digital computer 102.

[0138] Although the digital computer 102 is described as using a hard disk, optical disk, and / or solid-state storage medium, those skilled in the art will understand that other types of non-transient and non-volatile computer-readable media may be used. Those skilled in the art will understand that some computer architectures use non-transient volatile memory and non-transient non-volatile memory. For example, data in volatile memory may be cached in non-volatile memory or in a solid-state disk that provides non-volatile memory using an integrated circuit.

[0139] Various processor-readable or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store executable instructions for communication with remote clients and for scheduling the use of resources, including resources on the digital computer 102 and the quantum computer 104. Also, for example, system memory 122 may store at least one of processor-executable instructions or data that, when executed by at least one processor, cause at least one processor to execute various algorithms in order to execute an instruction. In some implementations, system memory 122 may store processor- or computer-readable computation instructions and / or data for performing pre-processing, cooperative processing, and post-processing on the quantum computer 104. System memory 122 may store a set of analog computer interface instructions for interacting with the quantum computer 104.

[0140] The quantum computer 104 may include at least one analog processor, such as a quantum processor 126. The quantum computer 104 may be provided in an isolation environment, such as one that shields the internal elements of the quantum computer from heat, magnetic fields, and other external noise. This isolation environment may include a refrigerator, such as a dilution refrigerator, that can operate to cryogenically cool the analog processor to a temperature of, for example, below about 1K.

[0141] The quantum computer 104 may include programmable elements such as qubits, couplers, and other superconducting on-chip devices (also referred to herein as controllable devices). Qubits can be read out via a readout control system 128. The readout results can be sent to other computer or processor-readable instructions of the digital computer 102. Qubits can be controlled via a qubit control system 130. The qubit control system 130 may include an on-chip digital-to-analog converter (DAC) and analog lines that can operate to apply a bias to a target device. Couplers that connect qubits can be controlled via a coupler control system 132. The coupler control system 132 may include tuning elements such as an on-chip DAC and analog lines.

[0142] In some implementations, the qubit control system 130 and the coupler control system 132 may be used to implement a quantum annealing schedule as described herein for a quantum computer 104 using one or more quantum processors. According to some implementations of this disclosure, a quantum processor, such as a quantum processor 126, may be designed to perform quantum annealing and / or adiabatic quantum computation. An example of a quantum processor is described in U.S. Patent No. 7,533,068.

[0143] Alternatively, the quantum processor, such as quantum processor 126, may be a general-purpose quantum computer, and the qubit control system 130 and coupler control system 132 may be used to perform general-purpose adiabatic quantum computing or other forms of quantum computing, such as gate model-based quantum computing.

[0144] The programmable elements may be contained within the quantum processor 126 in the form of one or more integrated circuits. The qubits and couplers may be arranged in layers of the integrated circuit containing the first material. Other devices, such as a device with a read control system 128, may be arranged in other layers of the integrated circuit containing the second material. The programmable elements and / or devices of the quantum processor may advantageously include various superconducting integrated circuit arrangements with high-coherence devices as described herein.

[0145] Superconducting quantum processor Figure 2 is a schematic diagram of a portion of the circuit 200 of an exemplary superconducting quantum processor in at least one implementation. In some implementations, the superconducting quantum processor of circuit 200 may be the quantum computer 104 shown in Figure 1. Circuit 200 includes two qubits 201 and 202. A tunable coupling (diagonal coupling) is also shown between qubits 201 and 202 via a coupler 210 (i.e., providing two local interactions). Although the circuit 200 shown in Figure 2 includes only two qubits 201, 202 and one coupler 210, those skilled in the art will understand that a superconducting quantum processor may include any number of qubits and any number of couplers that couple information between them.

[0146] Circuit 200 includes a number of interfaces 221, 222, 223, 224, and 225 used to configure and control the state of the superconducting quantum processor. Each of interfaces 221, 222, 223, 224, and 225 may be realized by their respective inductively coupled structures as part of a programming subsystem and / or an optional time evolution subsystem (evolution subsystem), as shown in the figure. Alternatively or additionally, interfaces 221, 222, 223, 224, and 225 may be realized by galvanically coupled structures. In some implementations, one or more of interfaces 221, 222, 223, 224, and 225 may be driven by one or more flux storage devices or digital-to-analog converters (DACs). Such programming subsystems and / or optional time evolution subsystems may be separate from the superconducting quantum processor or may be included locally (i.e., on the same chip as the superconducting quantum processor). For example, referring to the computing system 100 in Figure 1, locally included programming subsystems and / or optional time evolution subsystems can be placed as part of the quantum computer 104.

[0147] In the operation of the superconducting quantum processor, interfaces 221 and 224 can be used to couple magnetic flux signals to the composite Josephson junctions (CJJs) 231 and 232, respectively, of qubits 201 and 202.

[0148] Similarly, interfaces 222 and 223 can be used to apply magnetic flux signals to the superconducting loops 226 and 227 of qubits 201 and 202, respectively.

[0149] Furthermore, interface 225 may be used to couple a magnetic flux signal to coupler 210. Throughout this specification and the accompanying claims, the term “quantum processor” is used to generally represent a group of physical qubits (e.g., qubits 201 and 202) and qubit couplers (e.g., coupler 210). The physical qubits 201 and 202 and coupler 210 are referred to as the “controllable devices” of the quantum processor, and their corresponding parameters are referred to as the “controllable parameters” of the quantum processor. In the context of a quantum processor, the term “programming subsystem” is used to generally represent interfaces (e.g., “programming interfaces” 222, 223, and 225) used to apply the controllable parameters to the controllable devices (including at least qubits 201, 202, and coupler 210) and other related control circuits of a superconducting quantum processor. In some implementations, programming interfaces 222, 223, and 225 may include DACs, which can be used to control controllable devices such as qubits, couplers, and parameter tuning devices.

[0150] As previously mentioned, the programming interface of the programming subsystem may be separate from the quantum processor or may communicate with other subsystems that may be locally included on the processor, such as being located as part of the quantum computer 104 in Figure 1. The programming subsystem may be able to receive programming instructions in machine language from the quantum processor and execute the programming instructions to program programmable and controllable devices (e.g., at least qubits 201, 202, and coupler 210) according to the programming instructions. In some implementations in which the quantum processor is implemented as the quantum computer 104 in Figure 1, the controllable devices (e.g., qubits 201, 202, and coupler 210) may be located as part of the quantum processor 126, and these other subsystems may be at least one of the read control system 128, qubit control system 130, and coupler control system 132 of the quantum computer 104. Initial programming instructions may be provided using the digital computer 102 and may also be sent to the quantum processor and its corresponding subsystems via one or more digital processors 106 or one or more controllers 118.

[0151] The circuit 200 also includes readout devices 251 and 252, where readout device 251 is associated with qubit 201 and readout device 252 is associated with qubit 202. In the exemplary implementation shown in Figure 2, each of the readout devices 251 and 252 includes a DC-SQUID inductively coupled to the corresponding qubit. In some implementations, each of the readout devices 251 and 252 may include at least a controllable storage device located on the chip that is superconducting below a critical temperature and can store qubit state information. More specifically, as shown in Figure 2, each of the readout devices 251 and 252 may be a quantum flux parametron (QFP), and each readout device comprises a superconducting loop isolated by its respective CJJ. The readout devices 251, 252 may be implemented as described in one or more of U.S. Patents 6,627,916, 8,169,231, 10,938,346, and 11,424,521, and / or U.S. Patent Application Publication 2022 / 0207404, which are incorporated by reference herein. In the context of circuit 200, the term “readout subsystem” is used to generally refer to the readout devices 251, 252 used to read the final states of qubits (e.g., qubits 201 and 202) in the superconducting quantum processor in order to generate a bit sequence. The readout subsystem may also include other elements such as routing circuits (e.g., latch elements, shift registers, or multiplexer circuits) and / or may be arranged in alternative configurations (e.g., XY addressable arrays, XYZ addressable arrays, etc.), any of which may include a DAC. One implementation of qubit readout is described in U.S. Patent No. 8,854,074. The behavior of the readout subsystem can be indicated by signals transmitted from the readout control system 128 in Figure 1. The readout control system 128 may be coupled to the readout devices 251 and 252 via a DAC, analog lines, or other suitable means.

[0152] Figure 2 shows only two physical qubits 201, 202, one coupler 210, and two readout devices 251, 252, but a quantum processor (e.g., a processor with circuit 200) may use any number of qubits, couplers, and / or readout devices, including a much larger number (e.g., hundreds, thousands or more). The application of the teachings herein to processors with a different (e.g., more) number of computing components will be readily apparent to those skilled in the art.

[0153] Superconducting quantum processors may include other types of qubits besides superconducting flux qubits. For example, superconducting quantum processors may include superconducting charge qubits, transmon qubits, and so on.

[0154] In some implementations, the superconducting processor circuit 200 may optionally be all or part of the superconducting processor used for quantum annealing and / or adiabatic quantum computing. In such implementations, a plurality of interfaces 221, 222, 223, 224, and 225 couple their respective flux signals to qubits 201 and 202 to realize the parameters of the system Hamiltonian. For example, the coupling of interfaces 221 and 224 to qubits 201 and 202 includes a tunable tunneling term (Δ i This can provide the off-diagonal σ of the Hamiltonian system. x The term can be provided. The use of interfaces 222, 223 for applying magnetic flux signals to the superconducting loops 226, 227 of qubits 201, 202 is h i This allows us to realize a term (a dimensionless local field of the qubit), and this coupling is the diagonal σ in the system Hamiltonian. z This can provide a term. Finally, the magnetic flux signal is coupled to the coupler 210, thereby providing one or more J ij Interface 225 may be used to realize the term (the dimensionless local field of the coupler), and this J ijFor a given term, the combination is the diagonal in the Hamiltonian system.

number

[0155] In implementations where the circuit is all or part of a superconducting processor used for quantum annealing and / or adiabatic quantum computing, an exemplary superconducting quantum processor may include a time evolution subsystem with “time evolution interfaces” 221 and 224 used to evolve devices and / or instructions such as qubits 201, 202 and other associated control circuits over time. For example, the time evolution subsystem may include annealing signal lines and corresponding interfaces (221, 224) to the qubits (201, 202).

[0156] In other implementations, the superconducting processor circuit 200 may optionally be all or part of a superconducting processor used for gate-model quantum computing.

[0157] In some implementations, the first qubit 201 and the second qubit 202 may be fluxonium qubits. In some implementations where circuit 200 is part of a superconducting processor used in gate-model quantum computing, the fluxonium qubits can be placed in a multilayer fabrication stack that allows multiplexing control circuits to be built around them. Fluxonium qubits can be advantageously designed to have large inductance by using a kinetic inductor as part of the superconducting loop of the qubit.

[0158] Figure 3 is a schematic diagram of an exemplary superconducting qubit 300. The superconducting qubit 300 comprises a superconducting loop 302 and a Josephson junction structure 304. At least a portion of the superconducting loop 302 includes a kinetic inductor 302a. In this exemplary implementation, the Josephson junction structure 304 includes a first Josephson junction 306a and a second Josephson junction 306b for forming a compound Josephson junction (CJJ). The first Josephson junction 306a is in series with the first inductor 308a, and the second Josephson junction 306b is in series with the second inductor 308b. Those skilled in the art will understand that the Josephson junction structure 304 may include only one Josephson junction or may include compound-compound Josephson junctions (CCJJs), and that in certain implementations, the first inductor 308a and the second inductor 308b may not be present.

[0159] In some implementations, the motion inductor 302a includes one of niobium nitride (NbN), titanium niobium nitride (NbTiN), titanium nitride (TiN), aluminum nitride (AlN), and granular aluminum. The motion inductor 302a may be included in a fabrication stack directly adjacent to or near a low-noise substrate, and the Josephson junction structure 304 may be included in a layer distal to the motion inductor 302a to improve the coherence of the superconducting qubit 300. In one exemplary implementation, the motion inductor 302a may have an inductance of 5 nH. A detailed description of a superconducting qubit with motion inductance can be found in International Publication No. 2022178130.

[0160] Superconducting qubit with vertical differential qubit loop conductor segment Coherence exists when there is a clear phase relationship between different states of qubits within a quantum processor, and coherence enables the computation of quantum information encoded in the quantum states of the qubits. When qubits interact with the environment, this quantum information can be lost as a result of the qubits undergoing decoherence in a thermodynamically irreversible manner after a decoherence time.

[0161] In implementations where a quantum processor performs computations using adiabatic quantum computing and / or quantum annealing, decoherence can decoherently decoherent the tunneling before state changes are induced by intrinsic phase transitions. This decoherence can limit the speed and / or accuracy at which the processor evolves over time to generate solutions.

[0162] In implementations where quantum processors perform gate-model computations, long decoherence times can be particularly advantageous due to the timescale of the computation using a series of logic gates acting on a qubit. Decoherence time may be interchangeable with "coherence time," which is the duration for which the quantum processor maintains a coherent state. Gate-model quantum computing typically involves a series of quantum error correction operations. Quantum error correction requires that a qubit be able to maintain quantum coherence for a period approximately 1,000 times the single-gate time.

[0163] Short decoherence times can prevent a quantum processor from performing all desired calculations before quantum information is lost. To mitigate the degradation of quantum information, it is desirable for the qubits of a quantum processor to have high coherence, with long decoherence times, low noise, and minimal crosstalk between qubits and between qubits and other devices.

[0164] The rate at which qubits undergo decoherence can be increased by exposure to charge noise in the Josephson junction layer of the superconducting processor manufacturing stack, and by magnetic flux noise generated in the dielectric layer and transmitted to the junction layer through the dielectric-metal interface. Replacing dielectric materials with rare, low-noise, and low-loss dielectrics can be costly and technically challenging due to the sensitivity of the junction manufacturing process to disturbances.

[0165] By increasing the inductance of a qubit, the amount of noise observed by the qubit can be reduced. This can be achieved, in part, using a flaxonium qubit, and in particular a superconducting qubit with a kinetic inductor, such as the superconducting qubit 300 shown in Figure 3.

[0166] The fabrication of high-coherence qubits has been demonstrated by patterning a single layer of low-loss superconducting metal containing the qubit circuit on a low-noise, low-loss substrate. For example, the qubit may be arranged to directly overlap on a sapphire wafer. The absence of coupling interfaces and the use of low-loss materials in the resulting circuit can significantly reduce noise affecting the behavior of the qubit and its interaction with the environment (both of which reduce the coherence of the qubit). However, the resulting single-layer circuit may also have limited functionality. In the case of only a single layer of low-noise superconducting metal and a low-noise substrate, the quantum processor may not have the resources available to accommodate, program, and read out several qubits and couplers that can be used to represent the variables and relationships between variables of the problem to be solved on the quantum processor. Such a quantum processor may not be scalable and may not be able to solve complex problems.

[0167] The complexity of a problem that can be solved on a quantum processor, such as quantum processor 126 or the quantum processor of circuit 200 in Figure 2, can be proportional to the number of qubits, couplers, and associated devices it has. Therefore, a quantum processor for solving complex problems can ideally be scaled up to accommodate a large number of devices.

[0168] To address size and scalability issues, it may be advantageous to implement superconducting circuits, including quantum processors, using multilayer fabricated stacks. Multilayer fabricated stacks enable on-chip integration of control structures, such as a readout control system 128, a qubit control system 130, and a coupler control system 132, with the qubits of a quantum processor, such as a quantum processor 126. On-chip inclusion of these structures may enable at least one or more of the following: parameter tuning of controllable devices; improved speed and / or accuracy of readout and addressing of controllable devices due to proximity of circuit elements; improved structures for controlling qubits, couplers, and other programmable devices due to noise reduction; and shielding to prevent degradation of signals transmitted between components within the superconducting circuit. The use of multilayer fabricated stacks can reduce signal degradation between qubits and other structures of the quantum processor due to signal transmission via internal wiring not exposed to the external environment and shorter travel distances. As a result, it may be possible to reduce the intrusion of environmental noise into the signal that could interfere with the operation of the quantum processor.

[0169] To reduce the exposure of qubits and couplers to potential noise sources, the layers of a multilayer fabricated stack of superconducting circuits can be strategically ordered based on the noise sensitivity of the devices formed in each layer. For example, qubits and couplers may be placed in low-noise wiring regions adjacent to a low-noise substrate, while dielectric layers and control circuits may be placed in regions further away from the substrate. Multilayer fabricated stacks with wiring layers of different superconducting materials are further described in International Publication No. 2022178130.

[0170] In some exemplary implementations, the qubit may include a motion inductor, such as the motion inductor 302a of the superconducting qubit 300, as a noise reduction measure. The majority of the qubit's superconducting loop may include a high-inductance material, such as titanium nitride (TiN), in the motion inductance layer of the fabrication stack. In some implementations, each of the qubit's superconducting loops in a multilayer fabrication stack may include two conductors within the motion inductance layer. At least some of the electric field energy in the superconducting integrated circuit may be contained within the dielectric layers of the fabrication stack, including the substrate. In a superconducting circuit with at least the qubit body, the ratio of electric field energy between a pair of qubit loop conductor segments contained within each dielectric layer can be calculated based on the material properties of the layers. Placing the qubit loop conductor segments within a motion inductance layer adjacent to the substrate and having a larger proportion of electric field energy contained within the substrate compared to other dielectric layers may be advantageous in order to reduce the amount of charge noise observed by the qubit body.

[0171] In this specification, “conductor” may mean a conductive line, wire, or trace that transmits a signal. A portion of the conductor of a superconducting qubit loop (also referred to herein as a “qubit loop conductor segment”) may be a superconducting line, wire, or trace that forms at least a portion of the superconducting qubit loop. In an implementation where the superconducting qubit loop includes two or more conductor segments, the conductor segments are communicatively coupled to each other to form a closed body loop of the qubit.

[0172] For example, the superconducting loop 302 (i.e., the main loop) of a superconducting qubit 300 can be implemented in the fabrication stack by one or more qubit loop conductor segments. In examples where two or more qubit loop conductor segments exist, the qubit loop conductor segments may be electrically coupled via one or more of inductive, magnetic, or galvanic interfaces to provide the closed superconducting loop 302 shown in Figure 3. In implementations where the superconducting loop of a qubit in a multilayer fabrication includes two conductors within a kinetic inductance layer, the entire superconducting loop 302, including the kinetic inductor 302a, may be two communicably coupled superconducting lines, wires, or traces containing a material with a high kinetic inductance value.

[0173] Figure 3 includes dashed outlines to show two qubit loop conductor segments of the superconducting loop 302. The first qubit loop conductor segment 303a may include a portion of the superconducting loop 302 provided by the kinetic inductor 302a, and the second qubit loop conductor segment 303b may include the rest of the superconducting loop 302 (excluding the Josephson junction structure 304). However, this arrangement is merely an example and is not intended to be limiting. The superconducting loop 302 can be realized by any number of qubit loop conductor segments forming a closed loop, and those segments may be arranged in any way relative to the Josephson junction structure 304.

[0174] One technique for mitigating some of the noise at the dielectric-metal interface on a qubit may involve the implementation of a quantum processor having a flip-chip configuration. The quantum processor may include an individually fabricated main chip containing qubits and couplers adjacent to a low-noise substrate, and an individually fabricated flip chip containing other structures and devices of the quantum processor. The outer layers of the two superconducting circuits are arranged to communicate with each other via a gap or vacuum layer between them. In some implementation forms, the quantum processor having a flip-chip configuration may include qubits such as a superconducting qubit 300, each containing two qubit loop conductor segments within the same layer of the fabrication stack. For example, in an implementation form of a superconducting qubit 300 as a fabrication stack, a single layer may contain two qubit loop conductor segments constituting a superconducting loop 302. The first qubit loop conductor segment 303a on the single layer may contain a superconducting material having a high kinetic inductance value, which can provide the kinetic inductor 302a in the circuit diagram of Figure 3. The second qubit loop conductor segment 303b on a single layer may include a superconducting material having a lower inductance value compared to the inductance value of a material having a high kinetic inductance value (also referred to herein as a material having a relatively high inductance value), which can provide the rest of the superconducting loop 302 in the circuit diagram of Figure 3.

[0175] In some implementations, bump bonding may be used to electrically connect a main chip containing qubits and couplers to a flip chip containing control circuits. The footprint and crosstalk associated with bump bands may limit the processor's scalability and qubit density, which can reduce the operating speed to a rate slower than the qubit's decoherence time.

[0176] In other implementations, the qubits and couplers of the main chip are electrically coupled inductively and / or magnetically to the control circuit on the flip chip, so that there is no direct physical electrical communication between the chips. For further details on quantum processors with a flip-chip configuration, see International Publication No. 2024102504. Although electrical and / or magnetic shielding may be included in the manufacturing stack, the inductive communication interface between the main chip and the flip-chip devices is prone to generating undesirable amounts of crosstalk that can adversely affect the operation of the processor.

[0177] Some of the crosstalks that affect qubits can be communication between other devices, including other qubits, or communication between different interfaces and the qubit itself. For example, the superconducting loop 226 of qubit 201 (Figure 2) is coupled to interface 222 for biasing the superconducting loop 226, to coupler 210 via the interface, and to readout device 251 via the interface. In some implementations, the superconducting loop of a qubit may be coupled to additional structures via additional interfaces, for example, the qubit may be coupled to two or more couplers. Crosstalk between the various interfaces of the superconducting loop of a qubit can be reduced by arranging the lines coupled to the superconducting loop so that they are perpendicular to the principal axes of the two qubit loop conductor segments in the fabrication stack, as will be described in more detail below.

[0178] As mentioned earlier, crosstalk can also be reduced by forming the majority of the superconducting loop from a material with high kinetic inductance; however, high kinetic inductance can also reduce desirable signal transmission between the qubit and the coupler. To provide sufficient coupling strength, a galvanic interface can be used between the qubit and the coupler instead of an inductive interface. The design of the qubit should increase the impedance between the control structure and the qubit loop conductor segment to mitigate problems caused by uncontrolled superconducting loops. Uncontrolled superconducting loops may refer to superconducting loops formed by unintended galvanic coupling, magnetic coupling, and / or inductive coupling between structures inside the qubit, and / or between structures inside the qubit and structures, lines, and / or devices adjacent to the qubit.

[0179] Therefore, there is a need for superconducting circuits with qubits that have high coherence, low noise, and low sensitivity to crosstalk, and can be easily incorporated into quantum processors that include other control circuits. To achieve this, the superconducting loop of a qubit can be fabricated to include two qubit loop conductor segments arranged in different layers of a multilayer fabricated stack. The first qubit loop conductor segment can be placed in a motion inductance layer directly adjacent to a low-noise substrate, and the second qubit loop conductor segment can be placed in a superconducting wiring layer elsewhere in the stack. This arrangement is sometimes referred to herein as a qubit with a “vertically differential” qubit loop conductor segment. The main axis of the vertically differential qubit loop conductor segment can be positioned perpendicular to the line coupled to the interface, which is either vertically differential or horizontally differential (i.e., a conductor segment in the same layer), for crosstalk reduction, and different material compositions of the qubit loop conductor segment can support galvanic coupling.

[0180] Figure 4 is a top plan view of the qubit 400. The plane of the top view of the qubit 400 is sometimes referred to herein as the XY plane, according to a set of axes. The qubit 400 resides within a multilayer fabrication stack, the layers of which will be described in detail later herein. The qubit 400 includes a qubit body 402 and a Josephson junction 404. The qubit body 402 includes four coupler connection interfaces 406a, 406b, 406c, and 406d located longitudinally along the qubit body 402 from the Josephson junction 404. The qubit body 402 also includes five bias connection interfaces 408a, 408b, 408c, 408d, and 408e located along the qubit body 402; bias connection interfaces 408a, 408b, 408c, and 408d located between the Josephson junction 404 and the coupler connection interfaces 406a and 406b; and a bias connection interface 408e located between the Josephson junction 404 and the coupler connection interfaces 406c and 406d.

[0181] In some implementations, qubit 400 is one of several qubits in the quantum processor 126 of the computing system 100 in Figure 1. In some implementations, qubit 400 is one of qubits 201 and 202 in the circuit 200 in Figure 2, and the qubit body 402 is one of the superconducting loops 226 and 227, respectively. In some implementations, qubit 400 may also be the superconducting qubit 300 in Figure 3, and the qubit body 402 may include the superconducting loop 302. Although not visible in Figure 4, the qubit body 402 extends across multiple layers of the multilayer fabricated stack. In some implementations, the superconducting qubit loop of the qubit body 402 includes vertical differential qubit loop conductor segments such that a first qubit loop conductor segment exists in a kinetic inductance layer, and a second qubit loop conductor segment exists in a superconducting wiring layer at another location in the multilayer fabricated stack. For example, in an implementation where the qubit 400 is a superconducting qubit 300, the first qubit loop conductor segment may be a first qubit loop conductor segment 303a provided by the kinetic inductor 302a of the superconducting loop 302 as a superconducting line, lead, or wire within the kinetic inductance layer of the multilayer fabricated stack. The second qubit loop conductor segment may be a second qubit loop conductor segment 303b provided by the rest of the superconducting loop as a superconducting line, lead, or wire within a relatively low-inductance superconducting wiring layer of the multilayer fabricated stack.

[0182] Figure 4 is a top view, so the shielding layer 402a of the qubit body 402 can be seen. The shielding layer 402a may also be an outer layer of the qubit body 402 in a multilayer fabrication stack, and can shield other structures and devices of the qubit body 402 on lower layers from undesirable electric and / or magnetic fields. For example, the shielding layer 402a can shield at least a portion of one or more of the superconducting qubit loop, coupler connection interfaces 406a, 406b, 406c, 406d, and bias connection interfaces 408a, 408b, 408c, 408d, 408e of the qubit body 402, thereby reducing the amount of noise transmitted to them and improving the quality of operation.

[0183] The Josephson junction 404 may be a composite Josephson junction (CJJ) or a composite-composite Josephson junction (CCJJ), where a CCJJ is a CJJ in which at least one of the parallel paths is itself a CJJ. In an implementation where the qubit 400 is a superconducting qubit 300, the Josephson junction 404 may be a Josephson junction structure 304. In an implementation where the qubit 400 is one of the first qubit 201 and the second qubit 202, the Josephson junction 404 may be the corresponding one of the first CJJ231 or the second CJJ232.

[0184] In each of the coupler connection interfaces 406a, 406b, 406c, and 406d, the qubit 400 can be coupled to the corresponding coupler. In an implementation where the qubit 400 is one of the first qubit 201 and the second qubit 202, the coupler connection interface (one of 406a, 406b, 406c, and 406d) may be an interface in which one of the qubits 201 and 202 is coupled to the coupler 210. Each of the coupler connection interfaces 406a, 406b, 406c, and 406d provides galvanic coupling between the qubit body 402 of the qubit 400 and the corresponding coupler among the multiple couplers. Although four coupler connection interfaces 406a, 406b, 406c, and 406d are shown in Figure 4, this is not intended to be limiting, and the qubit 400 may include any appropriate number of coupler connection interfaces according to the architecture of the quantum processor.

[0185] Each of the bias connection interfaces 408a, 408b, 408c, 408d, and 408e couples the qubit body 402 to a bias signal source. In one embodiment, the bias signal source may be a digital-to-analog converter (DAC) of the quantum processor that generates a bias signal based on a control signal transmitted from a digital computer, such as the digital computer 102 of the computing system 100 (Figure 1). In an implementation where the qubit 400 is one of the qubits 201 and 202, the bias line interface (one of 406a, 406b, 406c, and 406d) may be an interface in which one of the first qubit 201 and the second qubit 202 is coupled to the corresponding one of interface 222 or interface 223. Each of the bias connection interfaces 408a, 408b, 408c, 408d, and 408e may be galvanically coupled to an analog line that transmits its respective flux bias signal. In some implementations, each bias connection interface (408a, 408b, 408c, 408d, 408e) may include two conductors, which may be configured as a vertical differential conductor segment or portion, or a horizontal differential conductor segment or portion.

[0186] Figures 5A, 5B, 5C, 5D, 5E, 5F, and 5G are cross-sectional views in the XZ plane of a superconducting circuit in a series of manufacturing stages. The final illustrated manufacturing stage of the superconducting circuit (i.e., superconducting circuit 500g shown in Figure 5G) includes the superconducting loop of a superconducting qubit with a vertical differential qubit loop conductor segment. The circuit of superconducting circuit 500g may also be a qubit body, such as the qubit body 402 of qubit 400 in Figure 4, and Figure 5G may be a cross-sectional view in the XZ plane of a portion of the qubit body 402. In some implementations, superconducting circuit 500g may include superconducting loops 226, 227 and interfaces shown to block the superconducting loops 226, 227 of qubits 201, 202 in Figure 2 and / or the superconducting loop 302 of superconducting qubit 300 in Figure 3.

[0187] Figure 5A shows the superconducting circuit 500a in the first stage of manufacturing. The superconducting circuit 500a includes a substrate 502 and a kinetic inductance layer 504 superimposed on the substrate 502. The kinetic inductance layer 504 may be deposited so as to superimpose on part or all of the surface of the substrate 502. In some mounting configurations, the kinetic inductance layer 504 superimposes directly on the substrate 502. In alternative mounting configurations, other layers may be interposed between the substrate 502 and the kinetic inductance layer 504.

[0188] The substrate 502 includes a low-noise electrical insulating material. In some configurations, the electrical insulating material of the substrate 502 includes one of sapphire, quartz, silicon trioxide (SiO3), silicon dioxide (SiO2), and silicon nitride (SiN). It should be understood that the substrate 502 does not have to be a wafer made of a single material. In some configurations, the substrate 502 may include a wafer and a low-noise electrical insulating material disposed on or grown on the surface of the wafer.

[0189] The kinetic inductance layer 504 can be formed from a superconducting material having a high kinetic inductance value, which in some implementations may include one of titanium nitride (TiN), niobium nitride (NbN), titanium niobium nitride (NiTiN), aluminum nitride (AlN), and granular aluminum. The material having a high kinetic inductance value may also have a relatively high inductance value compared to other materials in the superconducting circuit 500g, at least due to its ability to store a large amount of energy in the form of kinetic energy, and possibly due to its ability to store a large amount of energy in a magnetic field. The superconducting material having a high kinetic inductance value may exhibit superconducting behavior below the critical temperature. At least a portion of the kinetic inductance layer 504 may include a first qubit loop conductor segment having a vertical differential qubit loop conductor segment. In some implementations, the kinetic inductance layer 504 may form the kinetic inductor 302a of the superconducting qubit 300 (Figure 3).

[0190] Figure 5B shows the superconducting circuit 500b in a manufacturing stage following the manufacturing stage shown in Figure 5A. The superconducting circuit 500b also includes a kinetic inductance layer 504 that overlaps the substrate 502 of the superconducting circuit 500a, but in the superconducting circuit 500b, the kinetic inductance layer 504 is patterned such that the kinetic inductance layer 504 overlaps only a portion of the substrate 502, and at least a portion of the kinetic inductance layer 504 forms or includes the first qubit loop conductor segment 504a.

[0191] The arrangement of the first qubit loop conductor segment 504a directly overlapping the substrate 502 limits its exposure to environmental noise and charge noise formed at the dielectric-metal interface of the manufacturing stack. In some implementation configurations, the first qubit loop conductor segment 504a can constitute a large portion of the superconducting loop of the qubit and a large portion of the qubit's inductance. Forming the first qubit loop conductor segment 504a of a material with high kinetic inductance and therefore high inductance can increase the impedance of the superconducting loop, thereby reducing noise and crosstalk by limiting signal transmission. Furthermore, the material of the first qubit loop conductor segment 504a may exhibit superconducting behavior below its critical temperature.

[0192] Figure 5C shows the superconducting circuit 500c in a manufacturing stage following the manufacturing stage shown in Figure 5B. The superconducting circuit 500c includes a patterned kinetic inductance layer 504 and a first dielectric layer 506, which are superimposed on the substrate 502. The first dielectric layer is deposited so as to completely superimpose on the kinetic inductance layer 504 and so as to fill the etched-out areas with a material having a high kinetic inductance value and superimpose on a portion of the substrate 502. In some configurations, the dielectric layer 506 may be composed of silicon dioxide (SiO2) or silicon nitride (SiN).

[0193] Figure 5D shows the superconducting circuit 500d in a manufacturing stage following the manufacturing stage shown in Figure 5C. The superconducting circuit 500d includes a first dielectric layer 506 that is superimposed on a patterned kinetic inductance layer 504, which is superimposed on a substrate 502. The superconducting circuit 500d also includes a first superconducting wiring layer 508 that is directly superimposed on the entire first dielectric layer 506. The first superconducting wiring layer 508 may be made of a material that exhibits superconducting behavior below a critical temperature. The material of the first superconducting wiring layer 508 may be a material having a lower kinetic inductance value and a lower inductance value compared to a material having a high kinetic inductance value and a high inductance value for the kinetic inductance layer 504.

[0194] In this specification, a material with low kinetic inductance may refer to a material in which less than 10% of its internal energy is stored as kinetic inductance. In this specification, a material with relatively low inductance may refer to a material that can store only a small amount of energy, both in the form of kinetic energy and in magnetic fields, compared to a material with relatively high inductance. In some implementation configurations, the inductance per unit length of a material with relatively high inductance may be approximately 50 times that of a material with relatively low inductance.

[0195] In some implementation configurations, the material of the first superconducting wiring layer 508 may be a metal such as aluminum, niobium, tantalum, or any other metal having suitable superconducting properties.

[0196] Figure 5E shows the superconducting circuit 500e in a manufacturing stage following the manufacturing stage shown in Figure 5D. The superconducting circuit 500e includes the first superconducting wiring layer 508, the first dielectric layer 506, the motion inductance layer 504, and the substrate 502 of the superconducting circuit 500d. However, in this manufacturing stage, the first superconducting wiring layer 508 is patterned. In some implementations, the first superconducting wiring layer 508 is etched such that the remaining portion of the first superconducting wiring layer 508 (the second qubit loop conductor segment 508a) overlaps, at least partially, preferably completely, the patterned motion inductance layer 504 in the horizontal dimension (i.e., the X-direction dimension) of the cross-section of the superconducting circuit 500e, as shown in Figure 5E. Therefore, the remaining portion (second qubit loop conductor segment 508a) may preferably have a profile that matches the profile of the patterned motion inductance layer 504 (first qubit loop conductor segment 504a) in shape and dimensions, and may be aligned with it.

[0197] At least a portion of the patterned first superconducting wiring layer 508 includes a second qubit loop conductor segment 508a of a qubit having a vertical differential qubit loop conductor segment. Since the first qubit loop conductor segment 504a is positioned as part of the motion inductance layer 504, the two qubit loop conductor segments (504a, 508a) are located on different vertical layers of the multilayer fabrication stack and can be used to distinguish the electric field energies observed in the two qubit loop conductor segments 504a, 508a via the first dielectric layer 506.

[0198] Figure 5F shows the superconducting circuit 500f in a manufacturing step following the manufacturing step shown in Figure 5E. The superconducting circuit 500f includes a patterned first superconducting wiring layer 508, a first dielectric layer 506, a kinetic inductance layer 504, and a substrate 502 of the superconducting circuit 500e. The superconducting circuit 500f also includes a second dielectric layer 510 deposited on top of at least a portion of the first superconducting wiring layer 508 and the first dielectric layer 506. The second dielectric layer 510 may contain the same or a different dielectric material as the first dielectric layer 506, and may contain silicon dioxide (SiO2) or silicon nitride (SiN).

[0199] Figure 5G shows the superconducting circuit 500g in a manufacturing stage following the manufacturing stage shown in Figure 5F. The superconducting circuit 500g includes all the elements of the superconducting circuit 500f (i.e., the patterned first superconducting wiring layer 508, the first dielectric layer 506, the motion inductance layer 504, and the substrate 502), as well as a second superconducting wiring layer 512 overlapping the second dielectric layer 510. The second superconducting wiring layer 512 may include the same or different superconducting material with relatively low inductance as the first superconducting wiring layer 508, for example, one of aluminum, niobium, and tantalum.

[0200] In some implementations, the second superconducting wiring layer 512 is a shielding layer. The shielding layer may extend indirectly or directly along and cover at least one surface of one or more superconducting devices, one or more superconducting metal layers, or portions thereof, to provide electrical and / or magnetic shielding. The shielding layer may reduce crosstalk and noise between devices or between signals transmitted by superconducting layers in a multilayer fabricated stack. Further information regarding superconducting shields used in superconducting circuits can be found in U.S. Patent No. 7,687,938.

[0201] In the superconducting circuit 500g, the second superconducting wiring layer 512 may also be a shielding layer 402a of the qubit body 402, which can at least partially shield the superconducting qubit loop of the qubit body 402, which includes the motion inductance layer 504 and at least a portion of the first superconducting wiring layer 508.

[0202] While only one qubit is illustrated as part of the superconducting circuit 500g, it should be understood that the superconducting circuit can include any number of vertical differential qubits and other structures, including (but not limited to) control structures such as couplers, bias interfaces, and DACs and superconducting quantum interference devices (SQUIDs). Similarly, it should be understood that the fabrication stack of such a superconducting circuit can include any appropriate number of layers, and may include more layers than shown in Figure 5G. For example, the superconducting circuit may include additional superconducting wiring layers, additional dielectric layers, and additional kinetic inductance layers. In some implementations, additional layers may form regions within the fabrication stack that, for example, form specific control circuits.

[0203] By placing the first qubit loop conductor segment 504a on a motion inductance layer 504 directly adjacent to the substrate 502, the amount of charge noise transmitted to the first qubit loop conductor segment 504a via the material interface between the two layers is beneficially limited. This is due to the low-noise and low-loss material properties of the substrate 502, which allows the substrate 502 to retain a portion of the electric field energy within the superconducting circuit 500g without leaking into other layers and / or the environment.

[0204] The arrangement of the first qubit loop conductor segment 504a within the motion inductance layer 504 results in the first qubit loop conductor segment 504a having a desirable relatively high inductance value that can advantageously limit crosstalk with other devices and / or structures; however, this arrangement may also reduce the effectiveness of desirable communication between them. Herein, by arranging the second qubit loop conductor segment 508a at a different vertical position within the multilayer fabrication stack, the second qubit loop conductor segment 508a is placed within the first superconducting wiring layer 508, and the second qubit loop conductor segment 508a contains a different material from the first qubit loop conductor segment 504a. In contrast to the first qubit loop conductor segment 504a, the second qubit loop conductor segment 508a contains a material having a relatively low inductance value. The relatively low inductance value of the first superconducting wiring layer 508, including the second qubit loop conductor segment 508a, can be used for effective communication between the qubit 400 (Figure 4) and the Josephson junction 404 or the qubit's CJJ.

[0205] In this specification, the difference in inductance values ​​between two qubit loop conductor segments is sometimes referred to as "asymmetrical." The asymmetrical inductance values ​​of the qubit loop conductor segments allow a portion of the superconducting qubit loop with relatively high inductance to be positioned between the qubit control structure and the interfaces where the superconducting qubit loop connects to the coupler (e.g., coupler connection interfaces 406a, 406b, 406c, 406d of qubit 400 (Figure 4)). Thus, the aforementioned portion of the superconducting qubit loop with relatively high inductance has a relatively high impedance per unit length, thereby advantageously reducing undesirable crosstalk between the Josephson junction and the coupler. However, the kinetic inductance material of this portion of the superconducting qubit loop does not generate a magnetic field strong enough to support magnetic coupling between itself and one or more couplers. The arrangement of vertical differential qubit loop conductor segments in the superconducting circuit 500g provides a portion of the superconducting qubit loop with relatively low inductance between the interfaces where the superconducting qubit loop connects to the coupler. This supports galvanic coupling between superconducting qubit loops and one or more couplers. Galvanic coupling can be more efficient than magnetic coupling, and the arrangement of the relatively high-inductance portion of the superconducting qubit loops compared to the coupling interface mitigates the qubit control problems associated with galvanic coupling of multiple superconducting loops.

[0206] Because superconducting qubits have an operating bandwidth, the qubit (including its superconducting qubit loop) must have frequencies within this range. Consequently, an overall inductance budget exists when designing a qubit to meet this criterion. A superconducting qubit loop of a 500g superconducting circuit with an asymmetric qubit loop conductor segment can be designed to realize the advantages of materials with high kinetic inductance values ​​without exceeding the inductance budget and without impairing the operation of the qubit due to the relatively low inductance value of a portion of the superconducting loop.

[0207] Superconducting circuits, including superconducting loops of qubits having vertical differential qubit loop conductor segments, can advantageously increase the design flexibility of integrated quantum processor circuits because there are more ways in which superconducting lines of other structures and / or devices within the quantum processor can be communicatively coupled to the qubits within them without further increasing crosstalk. By aligning these other lines perpendicular to the principal axes of the qubit loop conductor segments (such as the first and second device loop conductor segments on the motion inductance layer 504 and the first superconducting wiring layer 508, respectively), undesirable crosstalk between the lines and the qubit loop conductor segments is significantly limited. In a configuration where the qubit loop conductor segment is vertically differential, each additional pair of superconducting lines can be either horizontally differential (i.e., both lines are coupled to or can be coupled to the superconducting circuit via an interface located on the same layer, which may be any layer containing the superconducting material, or an additional interleaved layer containing the superconducting material or a layer superimposed on it), while still being perpendicular to the principal axis of the qubit loop conductor segment, or vertically differential (i.e., the first and second analog lines are coupled to the superconducting circuit via first and second interfaces, respectively, with the first and second interfaces located on different layers of the superconducting circuit). Conversely, in a superconducting circuit where the qubit loop conductor segment is horizontally differential, the geometry of the arrangement may cause only the vertically differential pair of additional superconducting lines to be perpendicular to the principal axis of the qubit loop conductor segment.

[0208] While some aspects of the design of the 500g superconducting circuit reduce the amount of crosstalk affecting its superconducting qubit loop, a vertical differential qubit loop conductor segment configuration may be more susceptible to charge noise than a superconducting qubit loop having a horizontal differential qubit loop conductor segment configuration where all qubit loop conductor segments are located on one layer of the fabricated stack adjacent to the substrate. In a multilayer fabricated stack with a vertical differential qubit loop conductor segment configuration, a dielectric layer (e.g., a first dielectric layer 506) is inserted between the layers containing the qubit loop conductor segments (e.g., a motion inductance layer 504 and a first superconducting wiring layer 508). A large portion of the electric field energy within the fabricated stack may be undesirably drawn from the substrate into the relatively lossy and noisy dielectric layer. Subsequently, there may be even greater dissipation of electric field energy from the dielectric layer into the layers containing the qubit loop conductor segments.

[0209] To mitigate the effects of noise from the dielectric layer of a qubit having a vertical differential qubit loop conductor segment configuration on the superconducting qubit loop, the superconducting circuit may include a feedback path between the second qubit loop conductor segment and the layer of the fabrication stack containing the first qubit loop conductor segment. The feedback path can favorably redirect some of the electric field energy back to a low-noise substrate, thereby reducing its impact on the superconducting qubit loop conductor segment.

[0210] Figures 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, and 6J are cross-sectional views in the XZ plane of a superconducting circuit in a series of manufacturing stages. The final illustrated manufacturing stage of the superconducting circuit (i.e., the superconducting circuit 600j shown in Figure 6J) includes the superconducting loop of a superconducting qubit with a vertical differential qubit loop conductor segment. The completed circuit of superconducting circuit 600j may include a qubit body such as the qubit body 402 of qubit 400 in Figure 4, and Figure 6J may be a cross-sectional view in the XZ plane of a portion of the qubit body 402. In some implementations, the completed circuit of superconducting circuit 600j may include the superconducting loops 226, 227 of qubits 201, 202 in Figure 2 and / or the superconducting loop 302 of superconducting qubit 300 in Figure 3.

[0211] Figure 6A shows the superconducting circuit 600a in the first stage of manufacturing. The superconducting circuit includes a substrate 602 and a kinetic inductance layer 604 superimposed on the substrate 602. In some configurations, the kinetic inductance layer 604 is superimposed directly on the substrate 602. In alternative configurations, other layers may be interposed between the substrate 602 and the kinetic inductance layer 604.

[0212] In some configurations, the substrate 602 includes one of sapphire, quartz, silicon, silicon dioxide, silicon trioxide, and silicon nitride. It should be understood that the substrate 602 does not need to be a wafer composed of a single material. In some configurations, the substrate 602 may include a wafer and a low-noise electrical insulating material disposed on or grown on the surface of the wafer.

[0213] The kinetic inductance layer 604 can be formed from a material having a higher kinetic inductance value and a higher inductance value compared to other materials in the completed superconducting circuit 600j. In some implementation configurations, this material may include one of titanium nitride, niobium nitride, titanium niobium nitride, aluminum nitride, and granular aluminum. Furthermore, materials having a high kinetic inductance value may exhibit superconducting behavior below the critical temperature. The kinetic inductance layer 604 may be deposited so as to overlap part or all of the surface of the substrate 602. In some implementation configurations, the kinetic inductance layer 604 may form the kinetic inductor 302a of the superconducting qubit 300 (Figure 3).

[0214] Figure 6B shows the superconducting circuit 600b in a manufacturing stage following the manufacturing stage shown in Figure 6A, where the motion inductance layer 604 is patterned to overlap only a portion of the substrate 602. The portion of the patterned motion inductance layer 604 forms or includes the first qubit loop conductor segment 604a of the superconducting loop of the qubit in the superconducting circuit 600j. The other portion of the patterned motion inductance layer 604 is the motion inductance layer feedback path termination 604b, located on either side of the first qubit loop conductor segment 604a along the cross-section of the superconducting circuit 600b.

[0215] Figure 6C shows the superconducting circuit 600c in a manufacturing step following the manufacturing step shown in Figure 6B. The superconducting circuit 600c further includes a first dielectric layer 606 overlapping at least a portion of the substrate 602. In some configurations, the first dielectric layer 606 may be composed of silicon dioxide or silicon nitride.

[0216] Figure 6D shows the superconducting circuit 600d in a manufacturing step following the manufacturing step shown in Figure 6C, and also includes a first superconducting wiring layer 608 overlapping at least a portion of the first dielectric layer 606 and at least a portion of the kinetic inductance layer 604. A mask or photoresist may be applied to the first qubit loop conductor segment 604a of the kinetic inductance layer 604 so that the material for the first superconducting wiring layer 608 is not deposited directly on it. The first superconducting wiring layer 608 may be made of a material that exhibits superconducting behavior below a critical temperature, such as aluminum, niobium, tantalum, and any other metal having suitable superconducting properties and a relatively low inductance value.

[0217] Figure 6E shows the superconducting circuit 600e in a manufacturing stage following the manufacturing stage shown in Figure 6D, where the first superconducting wiring layer 608 is patterned. The first layer feedback path portions 608a (two are shown, only one indicated by a leader) overlap directly on the kinetic inductance layer feedback path terminations 604b (two are shown, only one indicated by a leader). The intermediate dielectric layer 607 may be deposited so as to occupy the same layer as the first layer feedback path portion 608a, overlapping on the first dielectric layer 606 and directly overlapping on the first qubit loop conductor segment 604a. Additional relatively low inductance superconducting material may be deposited as part of the first superconducting wiring layer 608, overlapping on the intermediate dielectric layer 607. This additional material may include a first layer feedback path portion 608b that overlaps directly on the first layer feedback path portion 608a, and a first layer shield structure portion 608c. Each first layer shield structure portion 608c is located laterally from each first layer feedback path portion (608a, 608b) along the cross-section of the superconducting circuit 600e and directly overlaps the intermediate dielectric layer 607.

[0218] Figure 6F shows the superconducting circuit 600f in a manufacturing step following the manufacturing step shown in Figure 6E, the superconducting circuit 600f further includes a second dielectric layer 610 that overlaps the intermediate dielectric layer 607 and is at the same height as the upper surfaces of the first layer feedback path portion 608b and the first layer shield structure portion 608c. The second dielectric layer 610 may be the same or a different dielectric material as the first dielectric layer 606 and / or the intermediate dielectric layer 607, and may include silicon dioxide (SiO2) or silicon nitride (SiN).

[0219] Figure 6G shows the superconducting circuit 600g in a manufacturing step following the manufacturing step shown in Figure 6F, the superconducting circuit 600g further includes a second superconducting wiring layer 612 that directly overlaps a portion of the second dielectric layer 610 and a portion of the first superconducting wiring layer 608. The second superconducting wiring layer 612 may contain the same or different superconducting material with relatively low inductance as the first superconducting wiring layer 608, and may include one of aluminum, niobium, and tantalum.

[0220] Figure 6H shows the superconducting circuit 600h in a manufacturing step following the manufacturing step shown in Figure 6G, where the second superconducting wiring layer 612 is patterned to include a second qubit loop conductor segment 612a and a second layer shield structure portion 612b.

[0221] The second qubit loop conductor segment 612a is the second conductor of the superconducting loop of the superconducting qubit, is located on a different layer from the first qubit loop conductor segment 604a, and contains a different material from the first qubit loop conductor segment 604a. The second qubit loop conductor segment 612a directly overlaps the first layer feedback path portion 608b, forming a superconducting feedback path in which the second qubit loop conductor segment 612a is electrically coupled to the motion inductance layer feedback path termination 604b of the motion inductance layer 604.

[0222] The structure, which includes the second qubit loop conductor segment 612a, the first layer feedback path portions 608a and 608b, and the motion inductance layer feedback path termination 604b, partially surrounds or is arranged around the first qubit loop conductor segment 604a of the superconducting loop.

[0223] Hereinafter, a structure that can "partially surround" or "partially surround" one or more superconducting devices or one or more superconducting metal layers may mean a structure that indirectly or directly covers a portion of a superconducting device and / or metal layer such that the structure extends along at least two surfaces of the superconducting device and / or metal layer.

[0224] The second layer shield structure portion 612b directly overlaps the first layer shield structure portion 608c and is superconductively electrically coupled to the first layer shield structure portion 608c.

[0225] Figure 6I shows the superconducting circuit 600i in a manufacturing step following the manufacturing step shown in Figure 6H, the superconducting circuit 600i further includes a third dielectric layer 614. The third dielectric layer 614 overlaps the second dielectric layer 610 and is at the same height as the upper surface of the second layer shielding structure portion 612b. The third dielectric layer 614 may be the same or a different dielectric material as the first dielectric layer 606 and / or the second dielectric layer 610, and may include silicon dioxide or silicon nitride.

[0226] Figure 6J shows the superconducting circuit 600j in a manufacturing step following the manufacturing step shown in Figure 6I, the superconducting circuit 600j further includes a third superconducting wiring layer 616 that directly overlaps the third dielectric layer 614 and at least a portion of the second superconducting wiring layer 612. The third superconducting wiring layer 616 may contain the same or different superconducting material with relatively low inductance as the first superconducting wiring layer 608 and / or the second superconducting wiring layer 612, and may contain one of aluminum, niobium, and tantalum.

[0227] The superconducting circuit 600j includes a shield structure 620 (outlined with thick lines), which includes a shield layer 620a on the outer surface of the superconducting circuit 600j (i.e., the outer surface of a qubit body such as the outer surface of a qubit body 402), and two shield arms 620b projecting from the shield layer 620a along the cross-section of the superconducting circuit 600j to the first superconducting wiring layer 608 on both sides of the return path. In the superconducting circuit 600j, the third superconducting wiring layer 616 is the shield layer 620a of the shield structure 620. Each shield arm 620b includes one of the second layer shield structure portions 612b and one of the first layer shield structure portions 608c. In the superconducting circuit 600j, in order to shield the superconducting qubit loop, the third superconducting wiring layer 616 overlaps the second layer shielding structure portion 612b and the first layer shielding structure portion 608c, and is superconductively electrically coupled to them.

[0228] The shield structure 620 of the superconducting circuit 600j can further reduce crosstalk affecting the superconducting qubit loop compared to the crosstalk resulting in the superconducting qubit loop in the superconducting circuit 500g (which includes only a planar shield structure provided by the second superconducting wiring layer 512 as the outer surface of the superconducting circuit 500g). The multilayer arrangement of the shield structure 620 of the superconducting circuit 600j surrounds at least a portion of the superconducting loop comprising the first and second superconducting wiring layers 608, 612 to more effectively prevent the second qubit loop conductor segment 612a from being exposed to undesirable electric and / or magnetic fields.

[0229] The superconducting circuit 600j achieves the advantageous properties of the asymmetric inductance vertical differential qubit loop conductor segment of the superconducting circuit 500g (Figure 5G), including reduced crosstalk resulting from the fact that most of the superconducting qubit loop is formed from a material with relatively high inductance values, and support for galvanic coupling to one or more couplers.

[0230] The superconducting circuit 600j can further improve the coherence of the superconducting qubit by including a feedback path from the second qubit loop conductor segment 612a to the motion inductance layer 604 where the first qubit loop conductor segment 604a is located. The feedback path partially surrounding the first qubit loop conductor segment 604a (including the first layer feedback path portions 608a and 608b) can beneficially reduce the susceptibility of the superconducting qubit loop to crosstalk and increase the electric field energy density within the substrate 602.

[0231] In addition to the return path, partial encirclement of the first qubit loop conductor segment 604a and the second qubit loop conductor segment 612a by the shielding structure 620 (including 608c, 612b, and 616) of the superconducting circuit 600j can limit exposure to undesirable electric and / or magnetic fields.

[0232] The feedback path and shield arm 620b are described as being formed by an overlapping layer of a relatively low-inductance superconducting material, which in some implementations may be superconducting stud vias containing a relatively low-inductance superconducting material. In alternative implementations, the feedback path and shield arm may be superconducting vias formed by drilling holes between layers and coating the holes with a relatively low-inductance superconducting material. For example, the first layer feedback path portions 608a, 608b may be superconducting vias that galvanically couple the second qubit loop conductor segment 612a and the motion inductance layer feedback path termination 604b. The shield arm 620b, including the first layer shield structure portion 608c and the second layer shield structure portion 612b, may also be implemented as superconducting vias extending from the third superconducting wiring layer 616 into the superconducting circuit 600j.

[0233] As mentioned above, crosstalk affecting the superconducting qubit loop can be significantly reduced by aligning the principal axes of the superconducting lines of other structures and / or devices within the quantum processor perpendicular to the principal axes of the pair of vertical differential qubit loop conductor segments of the superconducting qubit loop. However, significant reduction in crosstalk may be conditional on maintaining symmetry with respect to a vertical centerline along the width of the entire qubit body. For example, the qubit body 402 of qubit 400 (Figure 4) may have vertical differential qubit loop conductor segments of superconducting circuit 500g or superconducting circuit 600j. To limit crosstalk between the first and second qubit loop conductor segments (504a, 508a, or 604a, 612a) and additional superconducting lines (coupled to bias connection interfaces 408a, 408b, 408c, 408d, 408e), the additional superconducting lines can be positioned perpendicular to the principal axis of the vertical differential qubit loop conductor segment, and each bias connection interface (408a, 408b, 408c, 408d, 408e) can be symmetrical with respect to the z axis at the central position along the x axis of the qubit body 402.

[0234] To satisfy the above criteria for reducing crosstalk between vertically differential qubit loop conductor segments and superconducting lines within the quantum processor, each bias connection interface (408a, 408b, 408c, 408d, 408e) may include a pair of bias loop conductor segments configured to be vertically differential.

[0235] Figure 7A is a cross-sectional view in the XZ plane of a superconducting circuit 700a, which includes a vertical differential qubit loop conductor segment and a vertical differential magnetic flux bias loop conductor segment providing a bias connection interface. In some implementations, the superconducting circuit 700a may be a partial cross-sectional view in the XZ plane of the qubit body 402 in Figure 4, which includes one of the bias connection interfaces 408a, 408b, 408c, 408d, and 408e.

[0236] The superconducting circuit 700a includes several elements equivalent to or similar to those of the superconducting circuit 500g. Specifically, the substrate 702 of the conduction circuit 700a may be equivalent to or similar to the substrate 502; the motion inductance layer 704 including the first qubit loop conductor segment 704a may be equivalent to or similar to the motion inductance layer 504; the first dielectric layer 706 may be equivalent to or similar to the first dielectric layer 506; the qubit loop superconducting wiring layer 712 including the second qubit loop conductor segment 712a may be equivalent to or similar to the first superconducting wiring layer 508; the third dielectric layer 714 may be equivalent to or similar to the second dielectric layer 510; and the external superconducting wiring layer 720 may be equivalent to or similar to the second superconducting wiring layer 512 for shielding the superconducting qubit loop.

[0237] Furthermore, the superconducting circuit 700a includes additional layers that form the structure of the bias connection interface. Between the first dielectric layer 706 and the qubit loop superconducting wiring layer 712, a first intermediate wiring layer 708 and a second dielectric layer 710 overlapping the first intermediate wiring layer 708 are inserted. Between the third dielectric layer 714 and the outer superconducting wiring layer 720, a second intermediate wiring layer 716 and a fourth dielectric layer 718 overlapping the second intermediate wiring layer 716 are inserted.

[0238] At least a portion of the first intermediate wiring layer 708 and at least a portion of the second intermediate wiring layer 716 form or include the first bias loop conductor segment 708a and the second bias loop conductor segment 716a, respectively. The first bias loop conductor segment 708a on the first intermediate wiring layer 708 is interposed between the first qubit loop conductor segment 704a in the motion inductance layer 704 and the second qubit loop conductor segment 712a in the qubit loop superconducting wiring layer 712. The second bias loop conductor segment 716a on the second intermediate wiring layer 716 overlaps the second qubit loop conductor segment 712a. The first bias loop conductor segment 708a and the second bias loop conductor segment 716a are aligned with the first qubit loop conductor segment 704a and the second qubit loop conductor segment 712a along the x-axis of the cross-section of the superconducting circuit 700a. Therefore, the first and second bias loop conductor segments 708a and 716a have a vertical differential configuration, with their center position along the x-axis of the cross-section (line Z in Figure 7A). sym It has advantageous symmetry with respect to the z-axis (labeled as such). This limits crosstalk between the superconducting qubit loop and the analog lines that are communicatively coupled to the bias loop conductor segments (708a, 716a).

[0239] Figure 7B is a cross-sectional view in the XZ plane of an alternative superconducting circuit 700b, which includes a vertical differential qubit loop conductor segment and a vertical differential magnetic flux bias loop conductor segment providing a bias connection interface. In some implementations, the superconducting circuit 700b may be a partial cross-sectional view in the XZ plane of the qubit body 402 in Figure 4, which includes one of the bias connection interfaces 408a, 408b, 408c, 408d, and 408e.

[0240] In some implementations, the superconducting circuit 700b may include vertical differential qubit loop conductor segments (724a, 732a) equivalent to or similar to those of the superconducting circuit 600j, a feedback path, and a shield structure 750, as well as bias connection interfaces provided by a first bias loop conductor segment 728a and a second bias loop conductor segment 736a. More specifically, the substrate 722 of the superconducting circuit 700b may be equivalent to or similar to the substrate 602; the motion inductance layer 724 including the first qubit loop conductor segment may be equivalent to or similar to the motion inductance layer 604; the first dielectric layer 726 may be equivalent to or similar to the first dielectric layer 606; the first intermediate wiring layer 728 may be equivalent to or similar to the first superconducting wiring layer 608; the second dielectric layer 730 may be equivalent to or similar to the intermediate dielectric layer 607 and the second dielectric layer 610; the qubit loop superconducting wiring layer 732 may be equivalent to or similar to the second superconducting wiring layer 612; the third dielectric layer 734 may be equivalent to or similar to the third dielectric layer 614; and the external superconducting wiring layer 740 may be equivalent to or similar to the third superconducting wiring layer 616.

[0241] In addition to the elements of the superconducting circuit 600j, the first intermediate wiring layer 728 of the superconducting circuit 700b has a first bias loop conductor segment 728a. The superconducting circuit 700b also includes a second intermediate wiring layer 736 and a fourth dielectric layer 738 overlapping the second intermediate wiring layer 736, both of which are interposed between the third dielectric layer 734 and the outer superconducting wiring layer 740. The second intermediate wiring layer 736 includes a second bias loop conductor segment 736a and a second intermediate layer shield structure portion 736b (only one is labeled in Figure 7B for clarity). The second intermediate layer shield structure portion 736b forms part of the shield arm 750b of the shield structure 750 (outlined with a thick line), and communicates with the shield surface 750a of the outer superconducting wiring layer 740 to the portion of the shield structure 750 on the qubit loop superconducting wiring layer 732 and the first intermediate wiring layer 728.

[0242] In the superconducting circuit 700b, the first bias loop conductor segment 728a is positioned along the z-axis between the first qubit loop conductor segment 724a and the second qubit loop conductor segment 732a, and the second bias loop conductor segment 736a overlaps the second qubit loop conductor segment 732a. Both the first and second bias loop conductor segments 728a and 736a are aligned with the first qubit loop conductor segment 724a along the x-axis of the cross-section of the superconducting circuit 700b, thereby creating a line Z for reducing crosstalk, as described with respect to the superconducting circuit 700a in Figure 7A. sym The symmetry criteria along these lines are satisfied.

[0243] In an alternative implementation, the shield structure 750 and a portion of the return path in Figure 7B can be implemented as superconducting vias, as previously mentioned with respect to Figure 6J.

[0244] Figure 8A is a plan view of a portion of the superconducting circuit 800. The portion of the superconducting circuit 800 may be either the superconducting circuit 700a or 700b (Figures 7A and 7B). Figure 8A may show an upper plan view of the superconducting circuit 700a or 700b in the XY plane, with the visual representation of dielectric layers (such as dielectric layers 706, 710, 714, and 718 of the superconducting circuit 700a, or dielectric layers 726, 730, 734, and 738 of the superconducting circuit 700b) excluded. Figure 8A may be a region of the qubit 400 in Figure 4, including one of the bias connection interfaces 408a, 408b, 408c, 408d, and 408e.

[0245] Figure 8A includes a substrate 802; a motion inductance layer 804 superimposed on the substate 802; a qubit loop wiring layer 812 superimposed on the motion inductance layer 804; a second intermediate wiring layer 816 superimposed on the qubit loop wiring layer 812; and an external wiring layer 820 superimposed on the qubit loop wiring layer 812. In Figure 8A, a pair of analog lines, including the first and second analog lines 830a and 830b, are coupled to the first and second bias line interfaces 820a and 820b of the external wiring layer 820, respectively.

[0246] Figure 8B is a cross-sectional view of a portion of the superconducting circuit 800 in the YZ plane. This cross-section shows a flux bias loop 840 (outlined with a thick line) extending over multiple superconducting layers in a portion of the superconducting circuit 800. In Figure 8B, the flux bias loop 840 is not shown as a closed loop and terminates at first and second bias line interfaces 820a, 820b, which are communicatively coupled to first and second analog lines 830a, 830b (Figure 8A), respectively. In some implementations, the flux bias loop 840 can perform the function of interface 222 or 223 of circuit 200 for coupling a bias signal to the superconducting loop 226 or 227 of the first qubit 201 or the second qubit 202 (see Figure 2). In the cross-sectional view of the superconducting circuit 800 in Figure 8B, the flux bias loop 840 encloses and communicatively couples only a small portion of the length of the superconducting qubit loop.

[0247] As shown in the cross-sectional view of Figure 8B, a portion of the superconducting circuit 800 includes a first intermediate wiring layer 808, which is visually obscured in the plan view of Figure 8A. The first intermediate wiring layer 808 indirectly overlaps the motion inductance layer 804 and includes a first bias loop conductor segment 808a, which may be the bias loop conductor segment of the first intermediate wiring layer 708 in Figure 7A, or the first bias loop conductor segment 728a in Figure 7B. The first bias loop conductor segment 808a is interposed between the first qubit loop conductor segment 804a of the motion inductance layer 804 and the second qubit loop conductor segment 812a of the qubit loop wiring layer 812.

[0248] A cross-sectional view of a portion of the superconducting circuit 800 also shows the dielectric layers of the superconducting circuit 800, which are not shown in Figure 8A. More specifically, the first dielectric layer 806 is directly superimposed on the motion inductance layer 804 and may be the first dielectric layer 706 in Figure 7A or the first dielectric layer 726 in Figure 7B; the second dielectric layer 810 is directly superimposed on the first intermediate wiring layer 808 and may be the second dielectric layer 710 in Figure 7A or the second dielectric layer 730 in Figure 7B; the third dielectric layer 814 is directly superimposed on the qubit loop wiring layer 812 and may be the third dielectric layer 714 in Figure 7A or the third dielectric layer 734 in Figure 7B; and the fourth dielectric layer 818 is directly superimposed on the second intermediate wiring layer 816 and may be the fourth dielectric layer 718 in Figure 7A or the fourth dielectric layer 738 in Figure 7B.

[0249] The flux bias loop 840 also includes a second bias loop conductor segment 816a (two are shown, but only one is indicated by a leader line for visual clarity), which is part of the second intermediate wiring layer 816. In the cross-sectional view of a portion of the superconducting circuit 800 in Figure 8B, it can be seen that the bias loop portion 808b of the first intermediate wiring layer 808 and the bias loop portion 812b of the qubit loop wiring layer 812 communicate with the first bias loop conductor segment 808a and the second bias loop conductor segment 816a, such that the flux bias loop 840 substantially surrounds a portion of the second qubit loop conductor segment 812a. The flux bias loop 840 also includes the bias loop portion 816b of the second intermediate wiring layer 816 (two are shown, but only one is indicated by a leader line for visual clarity), and the bias loop portion 816b is located directly beneath the first and second bias line interfaces 820a, 820b, respectively. Thus, the signal for biasing the superconducting qubit loop is transmitted to the flux bias loop 840 via the first and second analog lines 830a, 830b in Figure 8A through the first and second bias line interfaces 820a, 820b and coupled to the superconducting qubit loop via the second qubit loop conductor segment 812a.

[0250] In alternative implementations, the bias loop portions 808b and 812b may be superconducting vias extending between the first bias loop conductor segment 808a and the second bias loop conductor segment 816a. The first and second bias line interfaces 820a and 820b may also be electrically coupled to the second bias loop conductor segment 816a by superconducting vias.

[0251] The magnetic field strength generated by the first qubit loop conductor segment on a moving inductance layer such as the moving inductance layer 504 or 604 is disproportionately small compared to the impedance per unit length, so the magnetic coupling of the qubit to the coupler may be inappropriate. Instead, the qubit and the coupler can be galvanically coupled with a high coupling strength to ensure proper communication between them. Uncontrolled galvanic coupling between multiple superconducting loops can be detrimental to the operation of the qubit, but careful design of the superconducting qubit loop and placement of the coupler connection interface leads can limit the undesirable effects. As used herein, a "lead" or "segment" can refer to a conductive line, wire, or trace, or a portion of a conductive line, wire, or trace, that can electrically couple two or more devices, structures, or conductors.

[0252] Figures 9A, 9B, and 9D are plan views of portions of superconducting circuits 900a, 900b, 900d at various manufacturing stages. Figures 9A, 9B, and 9D show cross-sectional views of portions of the superconducting qubit body in the X-Y plane, and visual representations of dielectric layers (such as the first and second dielectric layers 506, 510 of superconducting circuit 500g or the first, second, and third dielectric layers 606, 610, 614 of superconducting circuit 600j) are omitted. However, those skilled in the art will understand that portions of the superconducting circuits 900a, 900b, 900d include dielectric layers disposed between the layers illustrated in the manner described above. Figures 9A, 9B, and 9D can be regions of the qubit 400 of FIG. 4 that include one of the coupler connection interfaces 406a, 406b, 406c, 406d.

[0253] A portion of the superconducting circuit 900a in Figure 9A shows a plan view of the circuit at the first intermediate stage of manufacturing, along the cross-section AA in Figure 9C or Figure 9E. The portion of the superconducting circuit 900a includes a substrate 902 and a kinetic inductance layer 904. In some configurations, the substrate 902 may be one of substrates 502, 602, and 702. In some configurations, the kinetic inductance layer 904 may be one of kinetic inductance layers 504, 604, and 704, and the illustrated portion of the kinetic inductance layer 904 in Figure 9A may be a portion of the first qubit loop conductor segment of the superconducting qubit loop. The main axis of the superconducting qubit loop is labeled as the dashed line QQ in Figure 9A. The kinetic inductance layer 904 overlaps directly on the substrate 902. The motion inductance layer 904 includes a first coupler connection lead wire 904a and a second coupler connection lead wire 904b arranged in a horizontal differential configuration (either in the same plane or spaced apart within the same layer in the manufacturing stack).

[0254] A portion of the superconducting circuit 900b in Figure 9B shows a plan view of a portion of the superconducting circuit 900a in a later stage of manufacturing, along the cross-section BB in Figure 9C, in one implementation configuration where a pair of coupler connection interfaces are vertically differential. Figure 9B includes all the elements of Figure 9A and further includes the qubit loop wiring layer 912. In some implementation configurations, the qubit loop wiring layer 912 may be the second superconducting wiring layer 612 in Figure 6J, the qubit loop superconducting wiring layer 712 in Figure 7A, or the qubit loop superconducting wiring layer 732 in Figure 7B. The illustrated portion of the qubit loop wiring layer 912 in Figure 9B may be a portion of the second qubit loop conductor segment of the superconducting qubit loop.

[0255] In FIG. 9B, the first and second coupler connection interfaces 930a, 930b (shown in thick lines in FIGS. 9B and 9C) extend through a portion of the superconducting circuit 900b to galvanically couple the first and second coupler connection leads 904a, 904b to the first and second coupler leads 940a, 940b, respectively. As shown in FIG. 9B, the first and second coupler leads 940a, 940b extend in a direction perpendicular to the major axis (labeled as dashed line Q-Q in FIG. 9B) of the first qubit loop conductor segment in the kinetic inductance layer 904 and the second qubit loop conductor segment in the qubit loop wiring layer 912. As a result, the symmetry of the qubit body with respect to the line along the z-axis at the center of the x-axis is maintained, and unwanted crosstalk from the couplers connected to the first and second coupler leads 940a, 940b is restricted.

[0256] FIG. 9C is a cross-sectional view of the superconducting circuit 900c in the Y-Z plane including a pair of vertical differential coupler connection interfaces of the qubit. In some implementations, a portion of the superconducting circuit 900c is a portion of the qubit 400 including one of the coupler connection interfaces 406a, 406b, 406c, 406d. The superconducting circuit 900c can be a view of a portion of the superconducting circuit 900b in the Y-Z plane that also includes a layer overlapping the dielectric layer and the qubit loop wiring layer 912.

[0257] The superconducting circuit 900c includes a substate 902; a motion inductance layer 904; a first dielectric layer 906 overlapping the motion inductance layer 904; a first intermediate wiring layer 908 overlapping at least the motion inductance layer 904; a second dielectric layer 910 overlapping at least the first dielectric layer 906; a qubit loop wiring layer 912 overlapping at least the second dielectric layer 910; a third dielectric layer 914 overlapping at least the qubit loop wiring layer 912; a second intermediate wiring layer 916 overlapping at least the third dielectric layer 914; a fourth dielectric layer 918 overlapping at least the second intermediate wiring layer 916; a third intermediate wiring layer 920 overlapping at least the fourth dielectric layer 918; a fifth dielectric layer 922 overlapping at least the third intermediate wiring layer 920; and a shield wiring layer 924 overlapping at least the fifth dielectric layer 922. The first intermediate wiring layer 908, the qubit loop wiring layer 912, the second intermediate wiring layer 916, the third intermediate wiring layer 920, and the shield wiring layer 924 may all contain at least one material having relatively low inductance and kinetic inductance values ​​that exhibit superconducting behavior below their respective critical temperatures. The kinetic inductance layer 904 may contain a material having relatively high kinetic inductance values ​​that exhibit superconducting behavior below its critical temperature.

[0258] In Figure 9C, it can be seen that the first and second coupler connection interfaces 930a, 930b (outlined with thick lines) that are coupled to the first and second coupler connection leads 940a, 940b shown in Figure 9B extend through the superconducting circuit 900c to the first and second coupler connection leads 904a, 904b of the motion inductance layer 904. The first and second coupler connection interfaces 930a, 930b include the first layer coupler connection portions 908a, 908b of the first intermediate wiring layer 908; the qubit loop wiring layer coupler connection portions 912a, 912b of the qubit loop wiring layer 912; and the second layer coupler connection portions 916a, 916b of the second intermediate wiring layer 916. Referring again to Figure 9B, the first coupler lead wire 940a is directly galvanically coupled to the second layer coupler connection portion 916a of the first coupler connection interface 930a for communicative coupling of the first coupler lead wire 940a to the first coupler connection lead wire 904a. The second coupler connection interface 930b also includes the third layer coupler connection portion 920b of the third intermediate wiring layer 920. The second coupler lead wire 940b is directly galvanically coupled to the third layer coupler connection portion 920b of the second coupler connection interface 930b for communicative coupling of the second coupler lead wire 940b to the second coupler connection lead wire 904b.

[0259] Referring to Figure 9C, within the qubit body, the second layer coupler connection portion 916a is sometimes called the "first coupler connection site," and the third layer coupler connection portion 920b is sometimes called the "second coupler connection site." The first and second coupler connection interfaces 930a and 930b extend between the first and second coupler connection leads 904a and 904b and the first and second coupler connection sites (916a and 920b), respectively. At the first coupler connection site (916a) located on the second intermediate wiring layer 916, the first coupler connection interface 930a is directly galvanically coupled to the first coupler lead 940a. At a second coupler connection site (920b) located on the third intermediate wiring layer 920 and overlapping the first coupler connection site (916a), the second coupler connection interface 930b directly galvanically couples with the second coupler lead wire 940b.

[0260] The dashed line AA in Figure 9C indicates a mark on the outer surface of the motion inductance layer 904 and shows the z-axis cross-section of the superconducting circuit 900c, which corresponds to the uppermost layer in the plan view of a portion of the superconducting circuit 900a. The dashed line BB in Figure 9C indicates the z-axis cross-section of the superconducting circuit 900c, which corresponds to a portion of the superconducting circuit 900c (i.e., a portion of the superconducting circuit 900b) as seen in the plan view of Figure 9B.

[0261] A portion of the superconducting circuit 900d in Figure 9D shows a plan view of a portion of the superconducting circuit 900a in a later stage of manufacturing, along the cross-section DD in Figure 9E, in an implementation configuration where a pair of coupler connection interfaces are horizontally differential. Figure 9D includes all the elements of Figure 9A and the qubit loop wiring layer 912. Figure 9D also includes first and second coupler connection interfaces 930c, 930d extending through the superconducting circuit 900d to galvanically couple the first and second coupler connection leads 904a, 904b to the first and second coupler lead leads 940c, 940d, respectively. Unlike the first and second coupler connection interfaces 930a, 930b in Figure 9B, the first and second coupler connection interfaces 930c, 930d are located on the same layer of the manufacturing stack such that one does not overlap the other.

[0262] In Figures 9B and 9D, the principal axes of the first and second coupler leads (940a, 940b, and 940c, 940d) are shown to be perpendicular to the principal axes of the first qubit loop conductor segment on the motion inductance layer 904 and the second qubit loop conductor segment on the qubit loop wiring layer 912 (labeled as dashed QQ in Figure 9D), but these are merely examples and not intended to be limiting. In alternative implementations, the coupler leads may intersect the principal axes of the qubit loop conductor segments at other angles (e.g., angles other than perpendicular or parallel to the principal axes of the coupler leads).

[0263] Figure 9E is a cross-sectional view of the superconducting circuit 900e in the YZ plane, including a pair of horizontal differential coupler connection interfaces. The superconducting circuit 900e may be a YZ plane view of a portion of the superconducting circuit 900d in Figure 9D, which also includes layers overlapping the dielectric layer and the qubit loop wiring layer 912.

[0264] Figure 9E shows that the first and second coupler connection interfaces 930c, 930d (outlined with thick lines), which are coupled to the first and second coupler leads 940c, 940d as shown in Figure 9D, extend through the superconducting circuit 900e to the first and second coupler connection leads 904a, 904b of the motion inductance layer 904. The first and second coupler connection interfaces 930c, 930d include the first layer coupler connection portions 908a, 908b; the qubit loop wiring layer coupler connection portions 912a, 912b; and the second layer coupler connection portions 916c, 916d. The first and second coupler leads 940c, 940d are directly galvanically coupled to the second layer coupler connection portions 916c, 916d of the first coupler connection interfaces 930c, 930d. Since the galvanic coupling of the first and second coupler lead wires 940c and 940d to the first and second coupler connection lead wires 904a and 904b occurs in the second intermediate wiring layer 916, the third intermediate wiring layer 920 and the fifth dielectric layer 922 in Figure 9C are not included within the superconducting circuit 900e, and the shield wiring layer 924b overlaps the fourth dielectric layer 918.

[0265] Referring to Figure 9E, the second layer coupler connection portion 916c is sometimes referred to as the "first coupler connection site" within the qubit body, and the second layer coupler connection portion 916d is sometimes referred to as the "second coupler connection site". The first and second coupler connection interfaces 930c, 930d extend between the first and second coupler connection leads 904a, 904b and the first and second coupler connection sites (916c, 916d), respectively. The first and second coupler leads 940c, 940d are directly galvanically coupled to the first and second coupler connection interfaces 930c, 930d at the first and second coupler connection sites (916c, 916d), respectively. Both the first and second coupler connection sites (916c, 916d) are located on a second intermediate wiring layer 916 that overlaps the qubit loop wiring layer 912.

[0266] Line AA in Figure 9E marks the outer surface of the motion inductance layer 904 and shows the z-axis cross-section of superconducting circuit 900e, which corresponds to the top layer in the plan view of a portion of superconducting circuit 900a. The dashed line DD in Figure 9E shows the z-axis cross-section of superconducting circuit 900e, which corresponds to a portion of superconducting circuit 900e (i.e., a portion of superconducting circuit 900d) as seen in the plan view of Figure 9D.

[0267] Returning to Figure 4, we can see that the coupler connection interfaces 406a, 406b, 406c, and 406d are located away from the Josephson junction 404 along the qubit body 402. Due to the large inductance per unit length of the motion inductance material of the first qubit loop conductor segment, this results in a significant proportion of the total qubit inductance being between the Josephson junction 404 and the coupler connection interfaces 406a, 406b, 406c, and 406d. In Figures 9A, 9B, and 9D, high-inductance paths can be realized along the motion inductance layer 904 and through the coupler connection leads 904a and 904b. High-inductance paths may have impedances that beneficially provide sufficient electrical isolation between the Josephson junction 404 and the coupler connection interfaces 406a, 406b, 406c, and 406d to prevent adverse effects. A low-inductance feedback path that completes the superconducting qubit loop of the qubit body 402 can be realized along the qubit loop wiring layer 912. For example, in the case of qubit 400, a relatively low-inductance feedback path may extend between coupler connection interface 406a and coupler connection interface 406d on a superconducting wiring layer such as the qubit loop wiring layer 912. The inductance asymmetry of the qubit loop conductor segments allows for finer control over the proportion of total qubit inductance distributed between the qubit structures.

[0268] method Figure 10 is a flowchart of Method 1000 for fabricating a superconducting circuit including a superconducting qubit loop with a vertical differential qubit loop conductor segment by the objects and methods of this specification. Method 1000 provides an exemplary method for fabricating any one of the superconducting circuits 500g, 600j, 700a, 700b, 800, 900b, 900c, 900d, 900e, and any other superconducting circuits described above.

[0269] In some implementations, the superconducting circuit fabricated by Method 1000 may include at least a portion of a superconducting qubit, such as qubit 400 in Figure 4, in which the qubit body 402 includes a superconducting qubit loop having a pair of vertical differential qubit loop conductor segments. In some implementations, the superconducting circuit fabricated by Method 1000 may include at least a portion of the superconducting qubit 300 in Figure 3, or at least a portion of either the first qubit 201 or the second qubit 202 in Figure 2. In some implementations, the superconducting circuit fabricated by Method 1000 may include at least a portion of a superconducting qubit in the quantum processor 126 in the computing system 100 in Figure 1.

[0270] Method 1000 includes acts 1002 to 1022, but in other implementations, certain acts may be omitted and / or further acts may be added. Method 1000 may be performed, for example, by integrated circuit manufacturing equipment in response to the start of a manufacturing process.

[0271] In 1002, a kinetic inductance layer is formed on the substrate, that is, directly on top of the substrate. The kinetic inductance layer includes a material having high kinetic inductance and relatively high inductance values. The formation of the kinetic inductance layer includes forming a first device loop conductor segment of the superconducting loop of the body of the superconducting controllable device. In some implementations, the material having relatively high inductance values ​​is one of niobium nitride, titanium niobium nitride, titanium nitride, aluminum nitride, and granular aluminum. In some implementations, the substrate may include a low-noise electrical insulating material.

[0272] The formation of the kinetic inductance layer may include forming a layer that includes at least a first qubit loop conductor segment of the superconducting qubit loop of the qubit body. In some implementations, the kinetic inductance layer may include only the first qubit loop conductor segment, such as in superconducting circuits 500g and 700a. In other implementations, the formation of the kinetic inductance layer may also include forming a portion of the feedback path of a second qubit loop conductor segment. For example, superconducting circuit 600j includes a kinetic inductance layer feedback path termination 604b (Figures 6B and 6J).

[0273] In other implementations, the formation of the motion inductance layer may involve forming a layer that includes at least a first device loop conductor segment of the superconducting coupler loop of the coupler body of the superconducting coupler.

[0274] In other implementations, the formation of the kinetic inductance layer may involve forming a layer that includes at least a first device loop conductor segment of the superconducting body loop of the quantum flux parametron (QFP).

[0275] In some embodiments, forming the motion inductance layer includes depositing a superconducting material having a high motion inductance and a relatively high inductance value on a low-noise electrical insulating material of the substrate. For example, this can be depositing the motion inductance layer 504 on the substrate 502 as shown in FIG. 5A, or depositing the motion inductance layer 604 on the substrate 602 as shown in FIG. 6A. Depositing the superconducting material having a relatively high inductance value can be performed using various deposition techniques.

[0276] Forming the motion inductance layer may also include patterning the superconducting material having a relatively high inductance value after deposition. For example, the superconducting circuit after patterning the motion inductance layer can be the superconducting circuit 500b of FIG. 5B or the superconducting circuit 600b of FIG. 6B. Patterning the motion inductance layer may include masking, etching, and / or planarizing at least a portion of the motion inductance layer. In some embodiments, masking may include applying a photoresist to a portion of the high motion inductance layer, and etching may include using chemical and / or physical etching techniques.

[0277] As used herein, "deposition and patterning" may include both an initial formation step in which a uniform layer of material is deposited on a lower layer surface and subsequent patterning steps (e.g., planarizing, masking, etching) performed on the material to form wiring, devices, and other structures. It will be understood that similar deposition techniques may be used in other deposition acts described herein.

[0278] At 1004, a first dielectric layer is formed overlapping at least a portion of the motion inductance layer. In some embodiments, the first dielectric layer is composed of a dielectric material such as silicon dioxide or silicon nitride. Forming the first dielectric layer may include depositing a dielectric material on the motion inductance layer and planarizing the outer surface of the deposited dielectric material.

[0279] In some configurations, the formation of the first dielectric layer may involve forming the first dielectric layer so as to directly overlap a portion of the substrate and the motion inductance layer. For example, in Figure 5C, the first dielectric layer 506 directly overlaps the substrate 502 and the motion inductance layer 504. In such configurations, the deposited material of the first dielectric layer 506 may be deposited and planarized to have a fixed height (i.e., a dimension along the z-axis of the cross-section of the multilayer fabrication stack) that exceeds the height of the motion inductance layer 504.

[0280] In other implementations, the formation of the first dielectric layer may involve forming the first dielectric layer so as to directly overlap a portion of the substrate and a portion of the motion inductance layer containing the first qubit loop conductor segment. For example, in Figure 6C, the first dielectric layer 606 directly overlaps a portion of the substrate 602 and the first qubit loop conductor segment 604a on the motion inductance layer 604. However, the first dielectric layer 606 does not overlap the motion inductance layer feedback path termination 604b so that the deposited material of the first dielectric layer 606 can be deposited and planarized to have the same height.

[0281] In 1006, a device loop superconducting wiring layer is formed. The device loop superconducting wiring layer overlaps at least a portion of the first dielectric layer. The device loop superconducting wiring layer contains a material that has a relatively low inductance value compared to the material of the kinetic inductance layer and exhibits superconducting behavior below the critical temperature. In some implementations, the device loop superconducting wiring layer contains at least one of aluminum, niobium, and tantalum. At least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop of the body of the superconducting controllable device.

[0282] In an implementation where the first device loop conductor segment is the first qubit loop conductor segment of a superconducting qubit loop, the device loop superconducting wiring layer is a qubit loop superconducting wiring layer, and the formation of at least the second device loop conductor segment includes forming at least the second qubit loop conductor segment.

[0283] In an implementation where the first device loop conductor segment is the first coupler loop conductor segment of a superconducting coupler loop, the device loop superconducting wiring layer includes the formation of at least a second coupler loop conductor segment.

[0284] In an implementation where the first device loop conductor segment is the first device loop conductor segment of the superconducting body loop of the QFP, the device loop superconducting wiring layer includes the formation of at least a second device loop conductor segment of the QFP.

[0285] In some implementations where the device loop superconducting wiring layer is a qubit loop superconducting wiring layer, the qubit loop superconducting wiring layer directly overlaps at least a portion of the first dielectric layer in superconducting circuits 500g and 600j, etc. In other implementations, the qubit loop superconducting wiring layer overlaps one or more further layers interleaving the first dielectric layer and the qubit loop superconducting wiring layer. For example, the second dielectric layers 710, 730 and the first intermediate wiring layers 708, 728 of superconducting circuits 700a, 700b are interposed between the first dielectric layers 706, 726 and the qubit loop superconducting wiring layers 712, 732.

[0286] The formation of a device loop superconducting wiring layer involves the formation of a layer containing at least a second device loop conductor segment. In some implementations, the loop superconducting wiring layer may contain only the second device loop conductor segment, such as in the first superconducting wiring layer 508 of the superconducting circuit 500g and the qubit loop superconducting wiring layer 712 of the superconducting circuit 700a. In other implementations, the formation of a device loop superconducting wiring layer may also include the formation of a portion of a shield structure. For example, the superconducting circuit 600j includes a second layer shield structure portion 612b of the shield structure 620 (Figures 6E and 6J).

[0287] In some implementations, the formation of a device loop superconducting wiring layer involves depositing a superconducting material with relatively low inductance on at least a dielectric layer of the superconducting circuit. For example, this could be depositing a first superconducting wiring layer 508 on a first dielectric layer 506, as shown in Figure 5D, or depositing a first superconducting wiring layer 608 on a first dielectric layer 608, as shown in Figure 6D. In some implementations, the formation of a device loop superconducting wiring layer also involves patterning the deposited material using masking, etching, and / or planarization techniques. For example, the superconducting circuit after patterning the device loop superconducting wiring layer could be the superconducting circuit 500e in Figure 5E or the superconducting circuit 600e in Figure 6E.

[0288] In some implementations, further acts may be included within Method 1000. Some or all of the optional acts 1008, 1010, 1012, and 1014, 1016, 1018, 1020, and 1022, indicated by the dashed outline in Figure 10, may be performed as part of Method 1000.

[0289] Optional acts 1008 and 1010 may be executed after act 1004 and optionally before act 1006.

[0290] In 1008, the first intermediate superconducting wiring layer may be formed so as to directly overlap at least the first dielectric layer. The formation of the first intermediate superconducting wiring layer may involve the deposition and patterning of layers of relatively low inductance material that exhibit superconductivity below the critical temperature. In some implementations, the formation of the first intermediate superconducting wiring layer may include the formation of first layer return path portions 608a, 608b and first layer shield structure portion 608c of the first superconducting wiring layer 608 in Figure 6E, as well as portions of the device loop conductor segment return path and shield structure, as shown in Figure 7B. The first superconducting wiring layer 608 in Figure 6E and the first intermediate wiring layer 728 in Figure 7B are formed so as to directly overlap portions of the first dielectric layers 606, 726 and portions of the return path terminations of the kinetic inductance layers 604, 724.

[0291] In some implementations, the formation of the first intermediate superconducting wiring layer may additionally or alternatively include forming a first conductor segment of a pair of bias loop conductor segments, such as the first bias loop conductor segment on the first intermediate wiring layers 708, 728 in Figures 7A and 7B.

[0292] In 1010, a second dielectric layer may be formed so as to overlap at least the first intermediate superconducting wiring layer. Formation of the second dielectric layer may include depositing the same or a different dielectric material as the first dielectric layer, and planarizing the deposited dielectric material. In some configurations, the second dielectric layer may be formed so as to directly overlap a portion of the first dielectric layer and a portion of the first intermediate superconducting wiring layer, as shown in Figures 6F and 7B.

[0293] In implementations including optional acts 1008 and 1010, optional acts 1012 and 1014 may be performed after act 1006. In 1012, a third dielectric layer may be formed so as to directly overlap at least a portion of the device loop superconducting wiring layer. In some implementations, the formation of the third dielectric layer includes depositing the same or a different dielectric material as the first and second dielectric layers, and planarizing the deposited dielectric material. In some implementations, the third dielectric layer may be formed so as to directly overlap a portion of the second dielectric layer and a portion of the device (e.g., qubit) loop superconducting wiring layer, as shown in Figures 6I and 7B, etc.

[0294] In 1014, a second intermediate superconducting wiring layer may be formed so as to directly overlap at least a third dielectric layer. The formation of the second intermediate superconducting wiring layer may involve the deposition and patterning of a relatively low inductance material that exhibits superconductivity below a critical temperature. This material may be the same as or different from the first intermediate superconducting wiring layer and the device loop superconducting wiring layer. The formation of the second intermediate superconducting wiring layer may involve the formation of a second bias loop conductor segment of a pair of bias loop conductor segments, such as the second bias loop conductor segments 716a, 736a on the second intermediate wiring layers 716, 736 in Figures 7A and 7B.

[0295] In some implementations, the formation of the second intermediate superconducting wiring layer may also include the formation of a shielding structure portion. For example, this may include the formation of a second intermediate layer shielding structure portion 736b of the second intermediate wiring layer 736, which is part of the shielding structure 750 of the superconducting circuit 700b (the second intermediate layer shielding structure portion 736b is formed to directly overlap the portion of the third dielectric layer 734 and the shielding structure portion of the qubit loop superconducting wiring layer 732 (Figure 7B)).

[0296] In some implementations, method 1000 includes forming coupler connection interfaces such as coupler connection interfaces 406a, 406b, 406c, and 406d in Figure 4, or the first and second coupler connection interfaces 930c, 930c in Figures 9D and 9E. In such implementations, act 1002 includes forming the first and second coupler connection leads 904a, 904b as part of the motion inductance layer 904 (Figure 9D); act 1008 includes forming the first layer coupler connection portions 908a, 908b; act 1006 includes forming the qubit loop wiring layer coupler connection portions 912a, 912b; and act 1014 includes forming the second layer coupler connection portions 916c, 916d. The second layer coupler connection portion 916c of the first coupler connection interface 930c and the second layer coupler connection portion 916d of the second coupler connection interface 930d can each communicately connect a pair of coupler lead wires (940c, 940d) to the first and second coupler connection lead wires 904a, 904b.

[0297] In implementations that include optional acts 1012 and 1014, optional act 1016 may be executed after act 1014. In implementations that do not include optional acts 1012 and 1014, optional act 1016 may be executed after act 1006.

[0298] In 1016, a fourth dielectric layer is formed. The formation of the fourth dielectric may include depositing a dielectric material which may be the same as or different from the dielectric material of the first dielectric layer, the second dielectric layer, and the third dielectric layer, and planarizing the deposited dielectric material.

[0299] In implementations including optional acts 1012 and 1014, the formation of the fourth dielectric layer may include forming the fourth dielectric layer so as to overlap at least the third dielectric layer. For example, the fourth dielectric layer 718 of the superconducting circuit 700a directly overlaps the third dielectric layer 714 (Figure 7A), and the fourth dielectric layer 738 of the superconducting circuit 700b directly overlaps the third dielectric layer 734 and the second intermediate wiring layer 736.

[0300] In implementations that do not include the optional acts 1012 and 1014, the formation of the fourth dielectric layer may include forming the fourth dielectric layer so as to overlap at least the first dielectric layer and the loop superconducting wiring layer. For example, the second dielectric layer 510 in the superconducting circuit 500f is formed so as to directly overlap at least a portion of the first superconducting wiring layer 508 and the first dielectric layer 506 (Figure 5F). In another embodiment, the third dielectric layer 614 in the superconducting circuit 600i is formed so as to directly overlap at least a portion of the second superconducting wiring layer 612 and the second dielectric layer 610 (Figure 6I).

[0301] Some implementations, including optional acts 1012, 1014, and 1016, may also include optional acts 1018 and 1020 in examples where the method involves forming a coupler connection interface such as the coupler connection interfaces 406a, 406b, 406c, and 406d in Figure 4, or the first and second coupler connection interfaces 930a, 930b in Figures 9A and 9B. In this implementation, Act 1002 includes forming first and second coupler connection leads 904a, 904b as part of the motion inductance layer 904 (Figure 9B); Act 1008 includes forming first layer coupler connection portions 908a, 908b; Act 1006 includes forming qubit loop wiring layer coupler connection portions 912a, 912b; and Act 1014 includes forming second layer coupler connection portions 916a, 916b, of which the second layer coupler connection portion 916a of the first coupler connection interface 930a can communicately couple one of a pair of coupler leads to the first coupler connection lead 904a.

[0302] In Act 1018, a third intermediate superconducting wiring layer is formed directly on top of at least a portion of the fourth dielectric layer. The formation of the third intermediate superconducting wiring layer may involve the deposition and patterning of a relatively low inductance material that exhibits superconductivity below a critical temperature. This material may be the same as or different from one or more of the second intermediate superconducting wiring layer, the first intermediate superconducting wiring layer, and the device loop superconducting wiring layer. The formation of the third intermediate superconducting wiring layer may include forming a third layer coupler connection portion 920b of the second coupler connection interface 930b (Figure 9B) that galvanically couples the second coupler lead of a pair of coupler leads to the second coupler connection lead 904b. In some implementations, the formation of the third intermediate superconducting wiring layer includes forming a third layer shield structure portion of a shield structure that directly on top of the second layer shield structure portion of the second intermediate wiring portion.

[0303] In Act 1020, a fifth dielectric layer is formed that directly overlaps at least a portion of the third intermediate superconducting wiring layer. The formation of the fifth dielectric layer may include depositing a dielectric material and planarizing the deposited dielectric material. The dielectric material may be the same as or different from one or more dielectric materials among the first, second, third, and fourth dielectric layers.

[0304] In 1022, the shielded superconducting wiring layer is formed so as to directly overlap at least a portion of the dielectric layer located directly beneath it. The formation of the shielded superconducting wiring layer may involve the deposition and planarization of a layer of material that exhibits superconducting behavior below a critical temperature. This material may be the same as or different from the material contained in other superconducting wiring layers of the superconducting circuit, and may be one of aluminum, niobium, and tantalum.

[0305] The formation of the shielded superconducting wiring layer provides a planar portion of the shielding structure on the outer layer of the superconducting circuit. In some implementations, excluding the optional acts 1018 and 1020, the shielded superconducting wiring layer is formed to directly overlap only the fourth dielectric layer. In other implementations, the shielding structure includes a pair of shielding arms that at least partially surround the second device loop conductor segment and, in some implementations, the feedback path (see, for example, the shielding structure 750 in Figure 7B includes a shielding surface 750a and a shielding arm 750b that partially surrounds the second qubit loop conductor segment 732a). The shielding arms extend from the shielded superconducting wiring layer into the multilayer fabrication stack of the superconducting circuit, and the shielding structure portion is included in all other superconducting wiring portions of the superconducting circuit.

[0306] In the implementation configuration excluding the optional acts 1018 and 1020, the shielded superconducting wiring layer is formed to directly overlap at least a portion of the fourth dielectric layer, where the shielded superconducting wiring layer directly overlaps the shielding structure portion of the device loop superconducting wiring layer (such as the shielding layer 620a composed of the third superconducting wiring layer 616 in Figure 6J) or the shielding structure portion of the second intermediate superconducting wiring layer (for example, the shielding surface 750a in Figure 7B, which includes an external superconducting wiring layer 740 that directly overlaps the second intermediate layer shielding structure portion 736b of the shield arm 750b). In the implementation configuration including the optional acts 1018 and 1020, the shielded superconducting wiring layer is formed to directly overlap at least a portion of the fifth dielectric layer, where the shielded superconducting wiring layer may directly overlap the shielding structure portion of the third intermediate wiring layer (such as the shielding wiring layer 924 in Figure 9B).

[0307] Afterword One or more of the above methods, processes, or techniques may be implemented by a series of processor-readable instructions stored in one or more non-temporary processor-readable media. Some examples of the above methods, processes, or techniques may be partially implemented by a dedicated device such as an adiabatic quantum computer or quantum annealing apparatus, or by a system (e.g., a computer including at least one digital processor) for programming or otherwise controlling the operation of an adiabatic quantum computer or quantum annealing apparatus. One or more of the above methods, processes, or techniques may include various acts, but those skilled in the art will recognize that in alternative embodiments certain acts may be omitted and / or additional acts may be added. Those skilled in the art will recognize that the illustrated order of acts is for illustrative purposes only and may be changed in alternative embodiments. Some of the exemplary acts or operations of one or more of the above methods, processes, or techniques may be performed iteratively. Some of the acts of one or more of the above methods, processes, or techniques may be performed at each iteration, after multiple iterations, or at the end of all iterations.

[0308] The above description of the illustrated implementations, including the contents described in the abstract, is not intended to be exhaustive or to limit the implementations to the exact forms disclosed. While certain implementations and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of this disclosure, as will be recognized by those skilled in the art. The teachings provided herein for various implementations may be applied to other methods of quantum computation, not necessarily the exemplary methods of quantum computation generally described above.

[0309] Further implementation forms can be provided by combining the various implementation forms described above. U.S. Patents No. 6,627,916, No. 7,533,068, No. 7,687,938, No. 7,876,248, No. 8,008,942, No. 8,035,540, No. 8,098,179, No. 8,169,231, No. 8,190,548, No. 8,195,596, No. 8,421,053, No. 8,854,074, No. 8,951,808, No. 9,424,526, No. 9,768,371, No. 10454015, No. 10,938,346, and No. 11,424,521 All U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications by the same applicant, including (but not limited to) U.S. Patent Application Publication No. 2018 / 0219150 (granted as U.S. Patent No. 10454015) and No. 2022 / 0207404; U.S. Provisional Patent Application No. 63 / 396,340 (published as International Publication No. 2024102504); and International Publication No. 2022178130, which are referred to herein and / or listed in the application data sheets, are incorporated herein by reference in their entirety.

[0310] In light of the above description, these and other modifications may be made to the implementation. In general, the terms used in the following claims should not be construed as limiting the claims to any specific implementation disclosed herein and in the claims, but rather as encompassing all possible implementations, along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. circuit board and A kinetic inductance layer comprising a material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature, wherein the kinetic inductance layer directly overlaps the substrate, and at least a first portion of the kinetic inductance layer is a first device loop conductor segment of a superconducting loop of the body of a superconducting controllable device, A first dielectric layer overlapping at least a portion of the motion inductance layer, A device loop superconducting wiring layer overlapping the first dielectric layer, wherein the device loop superconducting wiring layer includes a relatively low inductance superconducting material having a relatively low inductance value and exhibiting superconducting behavior below a critical temperature, the relatively low inductance superconducting material having a lower inductance value compared to the relatively high inductance value, and at least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, A superconducting circuit equipped with this feature.

2. A second dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, A shielding superconducting wiring layer overlapping the second dielectric layer for shielding at least the superconducting loop, The superconducting circuit according to claim 1, further comprising the above.

3. The superconducting circuit according to claim 1, wherein the superconducting loop of the main body of the superconducting controllable device is the superconducting qubit loop of the qubit body of a superconducting qubit.

4. The superconducting qubit loop of the qubit body is galvanically coupled to the Josephson junction of the superconducting qubit, The motion inductance layer comprises at least one pair of coupler connection leads of the qubit body, and each pair of the at least one pair of coupler connection leads is positioned at a distance from the Josephson junction along the length of the first device loop conductor segment, such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction, and The superconducting circuit according to claim 3, further comprising at least one pair of coupler connection interfaces, each pair of coupler connection interfaces for galvanically coupling a pair of coupler connection leads of the superconducting qubit to a corresponding pair of coupler leads of the superconducting coupler.

5. A first intermediate superconducting wiring layer directly overlapping at least the first dielectric layer, A second dielectric layer overlapping at least a portion of the first intermediate superconducting wiring layer, A third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, A second intermediate superconducting wiring layer overlapping at least a portion of the third dielectric layer, Furthermore, Each pair of the aforementioned coupler connection interfaces comprises at least, A pair of first layer coupler connection portions on the first intermediate superconducting wiring layer directly overlaps the corresponding pair of coupler connection lead wires, A pair of device loop layer coupler connection portions on the device loop superconducting wiring layer directly overlaps the pair of first layer coupler connection portions, A pair of second layer coupler connection portions on the second intermediate superconducting wiring layer directly overlaps the pair of device loop layer coupler connection portions, The superconducting circuit according to claim 4, including the above.

6. The superconducting circuit according to claim 5, wherein for each pair of the coupler connection interfaces, the pair of second layer coupler connection portions can be directly galvanically coupled to the pair of coupler lead wires.

7. A fourth dielectric layer overlapping at least the second intermediate superconducting wiring layer, A third intermediate superconducting wiring layer directly overlapping at least the fourth dielectric layer, Furthermore, For each pair of the aforementioned coupler connection interfaces, The first coupler connection interface of the pair of coupler connection interfaces includes a first second layer coupler connection portion of the pair of second layer coupler connection portions that can be directly galvanically coupled to the first coupler lead of the pair of coupler lead wires, and The superconducting circuit according to claim 5, wherein the second coupler connection interface of the pair of coupler connection interfaces includes a third layer coupler connection portion on the third intermediate superconducting wiring layer that directly overlaps the second second layer coupler connection portion of the pair of second layer coupler connection portions, and the third layer coupler connection portion is directly galvanically coupled to the second coupler lead of the pair of coupler lead wires.

8. A first intermediate superconducting wiring layer overlapping the first dielectric layer, wherein the first intermediate superconducting wiring layer includes one or more first bias loop conductor segments, and the one or more first bias loop conductor segments are positioned to align with the first device loop conductor segments along the cross-section of the superconducting circuit and to overlap the first device loop conductor segments, A second dielectric layer directly overlapping at least a portion of the first intermediate superconducting wiring layer, A third dielectric layer directly overlapping at least a portion of the device loop superconducting wiring layer, A second intermediate superconducting wiring layer directly overlapping at least the third dielectric layer, wherein the second intermediate superconducting wiring layer includes one or more second bias loop conductor segments, each of which is positioned to align with and overlap one of the corresponding first bias loop conductor segments along the cross-section of the superconducting circuit, A fourth dielectric layer overlapping at least the second intermediate superconducting wiring layer, The superconducting circuit according to claim 1, further comprising the above.

9. The superconducting circuit according to claim 8, wherein the body of the superconducting controllable device is symmetrical with respect to a vertical center line along the width of the superconducting circuit.

10. One or more flux bias loops, each flux bias loop surrounding a portion of the length of the second device loop conductor segment, An external superconducting wiring layer of the body of the superconducting controllable device, comprising at least one pair of bias line interfaces, wherein each pair of bias line interfaces is directly electrically coupled to the corresponding magnetic flux bias loop, The superconducting circuit according to claim 8, further comprising the above.

11. Each of the one or more magnetic flux bias loops is Multiple superconducting vias electrically coupling a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, A plurality of superconducting vias electrically coupling the corresponding second bias loop conductor segment to the corresponding first bias loop conductor segment, A superconducting circuit according to claim 10, comprising:

12. Each of the one or more magnetic flux bias loops is A corresponding first bias loop conductor segment among the one or more first bias loop conductor segments, The first bias loop portion of the first intermediate superconducting wiring layer directly overlaps the corresponding first bias loop conductor segment, A second bias loop portion of the device loop superconducting wiring layer directly overlaps the first bias loop portion, A corresponding second bias loop conductor segment among the one or more second bias loop conductor segments, The third bias loop portion of the second intermediate superconducting wiring layer directly overlaps the corresponding second bias loop conductor segment and is located below the corresponding pair of bias line interfaces, The superconducting circuit according to claim 10, including the above.

13. The superconducting circuit according to claim 10, wherein each pair of the at least one pair of bias line interfaces can be directly electrically coupled to the corresponding pair of analog lines such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first and second device loop conductor segments, and each pair of analog lines can be operated to transmit the corresponding bias signal to the superconducting loop of the body of the superconducting controllable device.

14. The superconducting circuit according to claim 1, wherein the return path electrically couples the second device loop conductor segment to the motion inductance layer, and the return path at least partially surrounds the first device loop conductor segment.

15. The superconducting circuit according to claim 14, wherein the feedback path includes a plurality of superconducting vias that communicately connect the second device loop conductor segment to the first device loop conductor segment.

16. The motion inductance layer includes a first motion inductance layer feedback path termination and a second motion inductance layer feedback path termination located on the first and second sides of the first device loop conductor segment, respectively, along the cross-section of the superconducting circuit. The superconducting circuit, A first intermediate superconducting wiring layer overlapping at least a portion of the first dielectric layer and the motion inductance layer, At least a portion of the first intermediate superconducting wiring layer and a second dielectric layer overlapping the first dielectric layer, wherein the device loop superconducting wiring layer overlaps the second dielectric layer, Furthermore, The superconducting circuit according to claim 14, wherein the feedback path includes a first intermediate layer feedback path portion and a second intermediate layer feedback path portion on the first intermediate superconducting wiring layer, which overlap directly on the first motion inductance layer feedback path termination and the second motion inductance layer feedback path termination, and the second device loop conductor segment overlaps directly on the first intermediate feedback path portion and the second intermediate feedback path portion to communicately couple the second device loop conductor segment to the motion inductance layer.

17. The shield structure further comprises, A shield superconducting wiring layer on the outer surface of the main body of the superconducting controllable device in the superconducting circuit, A first shield arm and a second shield arm extending from the shield superconducting wiring layer through the superconducting circuit to the first intermediate superconducting wiring layer so as to at least partially surround the second device loop conductor segment and the feedback path, The superconducting circuit according to claim 16, including the above.

18. The superconducting circuit according to claim 17, wherein the first shield arm and the second shield arm include superconducting vias extending from the shield superconducting wiring layer through the superconducting circuit to the first intermediate superconducting wiring layer.

19. The superconducting circuit further comprises a third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, and the shield superconducting wiring layer overlapping at least a portion of the third dielectric layer and the device loop superconducting wiring layer. The first shield arm and the second shield arm are A first intermediate layer shielding structure portion and a second intermediate layer shielding structure portion on the first intermediate superconducting wiring layer, wherein each of the first intermediate layer shielding structure portion and the second intermediate layer shielding structure portion is located at a corresponding lateral position along the width of the cross-section of the superconducting circuit, A first device loop layer shielding structure portion and a second device loop layer shielding structure portion on the device loop superconducting wiring layer, overlapping the first dielectric layer, Equipped with, The superconducting circuit according to claim 17, wherein the shielded superconducting wiring layer directly overlaps the first device loop layer shielding structure portion and the second device loop layer shielding structure portion in order to connect the shielded superconducting wiring layer to the first intermediate superconducting wiring layer in a communicative manner.

20. The superconducting loop of the main body of the superconducting controllable device is galvanically coupled to the Josephson junction of the superconducting controllable device. The motion inductance layer includes at least one pair of coupler connection leads of the body of the superconducting controllable device, and each pair of the at least one pair of coupler connection leads is positioned along the length of the first device loop conductor segment at a distance from the Josephson junction such that the majority of the total superconducting controllable device inductance of the superconducting controllable device is located between each pair and the Josephson junction, and The superconducting circuit according to claim 16, further comprising at least one pair of coupler connection interfaces, each pair of coupler connection interfaces for galvanically coupling a pair of coupler connection leads of the superconducting controllable device with a corresponding pair of coupler leads of the superconducting coupler.

21. A third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, A second intermediate superconducting wiring layer overlapping at least a portion of the third dielectric layer, Furthermore, Each pair of the aforementioned coupler connection interfaces A pair of first layer coupler connection portions on the first intermediate superconducting wiring layer directly overlaps the corresponding pair of coupler connection lead wires, A pair of device loop layer coupler connection portions on the device loop superconducting wiring layer directly overlaps the pair of first layer coupler connection portions, A pair of second layer coupler connection portions on the second intermediate superconducting wiring layer directly overlaps the pair of device loop layer coupler connection portions, The superconducting circuit according to claim 20, including the above.

22. The superconducting circuit according to claim 21, wherein for each pair of the coupler connection interfaces, the pair of second layer coupler connection portions can be directly galvanically coupled to the pair of coupler lead wires.

23. A fourth dielectric layer overlapping at least a portion of the second intermediate superconducting wiring layer, A third intermediate superconducting wiring layer overlapping at least a portion of the fourth dielectric layer, Furthermore, For each pair of the aforementioned coupler connection interfaces, The first coupler connection interface of the pair of coupler connection interfaces includes a first second layer coupler connection portion of the pair of second layer coupler connection portions that can be directly galvanically coupled to the first coupler lead of the pair of coupler lead wires, The superconducting circuit according to claim 21, wherein the second coupler connection interface of the pair of coupler connection interfaces includes a third layer coupler connection portion on the third intermediate superconducting wiring layer that directly overlaps the second second layer coupler connection portion of the pair of second layer coupler connection portions, and the third layer coupler connection portion is directly galvanically coupled to the second coupler lead of the pair of coupler lead wires.

24. The first intermediate superconducting wiring layer includes one or more first bias loop conductor segments, the one or more first bias loop conductor segments are positioned to align with and overlap the first device loop conductor segments along the cross-section of the superconducting circuit, and The superconducting circuit, A third dielectric layer overlapping at least a portion of the device loop superconducting wiring layer, A second intermediate superconducting wiring layer overlapping the third dielectric layer, wherein the second intermediate superconducting wiring layer includes one or more second bias loop conductor segments, each of which is positioned to align with and overlap one of the corresponding first bias loop conductor segments along the cross-section of the superconducting circuit. A fourth dielectric layer overlapping at least a portion of the second intermediate superconducting wiring layer, The superconducting circuit according to claim 16, further comprising the above.

25. The superconducting circuit according to claim 24, wherein the body of the superconducting controllable device is symmetrical with respect to a vertical center line along the width of the superconducting circuit.

26. One or more flux bias loops, each flux bias loop surrounding a portion of the length of the second device loop conductor segment, An external superconducting wiring layer of the body of the superconducting controllable device, comprising at least one pair of bias line interfaces, wherein each pair of bias line interfaces is directly electrically coupled to the corresponding magnetic flux bias loop, The superconducting circuit according to claim 24, further comprising the above.

27. Each of the one or more magnetic flux bias loops is Multiple superconducting vias electrically coupling a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, A plurality of superconducting vias electrically coupling the second bias loop conductor segment to the corresponding first bias loop conductor segment, A superconducting circuit according to claim 26, comprising the features described above.

28. Each of the one or more magnetic flux bias loops is A corresponding first bias loop conductor segment among the one or more first bias loop conductor segments, The first bias loop portion of the first intermediate superconducting wiring layer directly overlaps the corresponding first bias loop conductor segment, A second bias loop portion of the device loop superconducting wiring layer directly overlaps the first bias loop portion, A corresponding second bias loop conductor segment among the one or more second bias loop conductor segments, A third bias loop portion of the second intermediate superconducting wiring layer directly overlaps the corresponding second bias loop conductor segment, The superconducting circuit according to claim 26, including the above.

29. The superconducting circuit according to claim 26, wherein each pair of the at least one pair of bias line interfaces can be directly electrically coupled to the corresponding pair of analog lines such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first device loop conductor segment and the second device loop conductor segment, and each pair of analog lines is for transmitting the corresponding bias signal to the superconducting loop of the body of the superconducting controllable device.

30. The superconducting circuit according to claim 1, wherein the material having a relatively high inductance value is one of titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

31. The superconducting circuit according to claim 1, wherein the substrate includes an electrical insulating material, and the electrical insulating material is one of silicon dioxide, silicon trioxide, silicon nitride, quartz, and sapphire.

32. The superconducting circuit according to claim 1, wherein the superconducting material having relatively low inductance includes one of aluminum, niobium, and tantalum.

33. The superconducting circuit according to claim 1, wherein the superconducting loop of the body of the superconducting controllable device is a superconducting coupler loop of the coupler body of a superconducting coupler.

34. The superconducting circuit according to claim 1, wherein the superconducting loop of the body of the superconducting controllable device is the superconducting loop of the body of a quantum flex parametron (QFP).

35. The method involves forming a kinetic inductance layer directly on a substrate, wherein the kinetic inductance layer contains a relatively high inductance superconducting material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature, and at least a first portion of the kinetic inductance layer is a first device loop conductor segment of the superconducting loop of the body of a superconducting controllable device. A first dielectric layer is formed so as to overlap at least a portion of the motion inductance layer, The invention involves forming a device loop superconducting wiring layer on top of the first dielectric layer, wherein the device loop superconducting wiring layer includes a superconducting material with relatively low inductance, the relatively low inductance superconducting material has a lower inductance value compared to the high inductance value, and exhibits superconducting behavior below a critical temperature, and at least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop. A method for manufacturing a superconducting circuit, including [the specified element].

36. Forming the motion inductance layer includes depositing the relatively high inductance superconducting material on the surface of the substrate and patterning the deposited relatively high inductance superconducting material so as to include at least the first device loop conductor segment of the superconducting loop. Forming the first dielectric layer includes at least depositing a dielectric material on the surface of the motion inductance layer, and Forming the device loop superconducting wiring layer is The method according to claim 35, comprising depositing the relatively low inductance superconducting material and patterning the relatively low inductance superconducting material so as to include at least the second device loop conductor segment of the superconducting loop.

37. A second dielectric layer is formed by depositing a dielectric material on at least a portion of the surface of the device loop superconducting wiring layer. A shielded superconducting wiring layer is formed by depositing a layer of the relatively low inductance superconducting material on top of the second dielectric layer, The method according to claim 35, further comprising:

38. The process involves forming a motion inductance layer directly on a substrate, wherein at least a first portion of the motion inductance layer is a first device loop conductor segment of a superconducting loop of the body of a superconducting controllable device, and the process includes forming the motion inductance layer, wherein at least the first portion of the motion inductance layer is a first qubit loop conductor segment of a superconducting qubit loop of the qubit body of a superconducting qubit, and The method according to claim 35, comprising forming a device loop superconducting wiring layer on top of the first dielectric layer, wherein at least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming the device loop superconducting wiring layer is a qubit loop superconducting wiring layer, and at least a portion of the qubit loop superconducting wiring layer is a second qubit loop conductor segment of the qubit superconducting loop.

39. The manufacturing of the superconducting circuit is Forming a Josephson junction, wherein the Josephson junction is galvanically coupled to the superconducting qubit loop of the qubit body, To form one or more pairs of coupler connection interfaces, It further includes, Forming the motion inductance layer comprises depositing the high-inductance superconducting material and patterning the deposited high-inductance superconducting material to include one or more pairs of coupler connection leads for the first qubit loop conductor segment and the qubit body, wherein each pair of the one or more pairs of coupler connection leads is patterned along the length of the first qubit loop conductor segment at a distance from the Josephson junction such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction. The method according to claim 38, wherein the one or more pairs of coupler connection interfaces are for galvanically coupling a corresponding pair of coupler connection leads of the qubit body of the superconducting qubit to a corresponding pair of coupler leads of the superconducting coupler.

40. A first intermediate superconducting wiring layer is formed so as to overlap at least a portion of the first dielectric layer, A second dielectric layer is formed so as to overlap at least a portion of the first intermediate superconducting wiring layer, A third dielectric layer is formed so as to overlap at least a portion of the qubit loop conductor segment superconducting wiring layer, A second intermediate superconducting wiring layer is formed so as to overlap at least a portion of the third dielectric layer, It further includes, To form each pair of the one or more pairs of coupler connection interfaces, Forming the first intermediate superconducting wiring layer includes depositing a second layer of the relatively low inductance superconducting material and patterning the second layer of the relatively low inductance superconducting material to include a pair of first layer coupler connection portions that directly overlap a corresponding pair of coupler connection leads, The formation of the qubit loop superconducting wiring layer further includes patterning the first layer of the relatively low inductance superconducting material to include a pair of qubit loop layer coupler connection portions that directly overlap the pair of first layer coupler connection portions, and The method according to claim 39, wherein forming the second intermediate superconducting wiring layer comprises depositing a third layer of the relatively low inductance superconducting material and patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions that directly overlap the pair of qubit loop layer coupler connection portions.

41. The method according to claim 40, wherein patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions, the pair of second layer coupler connection portions being directly galvanically coupled to the pair of coupler leads.

42. A fourth dielectric layer is formed so as to overlap at least a portion of the second intermediate superconducting wiring layer, A third intermediate superconducting wiring layer is formed so as to overlap at least a portion of the fourth dielectric layer, It further includes, For each pair of the aforementioned coupler connection interfaces, Patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions, and patterning the third layer of the relatively low inductance superconducting material to include a first second layer coupler connection portion of the pair of second layer coupler connection portions that can be directly galvanically coupled to a first coupler lead of the pair of coupler leads, and The method according to claim 40, wherein forming the third intermediate superconducting wiring layer comprises depositing a fourth layer of the relatively low inductance superconducting material and patterning the fourth layer of the relatively low inductance superconducting material such that it includes a third layer coupler connection portion that directly overlaps a second second layer coupler connection portion of a pair of second layer coupler connection portions, the third layer coupler connection portion being directly galvanically coupled to a second coupler lead of a pair of coupler leads.

43. Forming a first intermediate superconducting wiring layer so as to overlap the first dielectric layer, wherein the first intermediate superconducting wiring layer includes one or more first bias loop conductor segments. A second dielectric layer is formed so as to overlap at least a portion of the first intermediate superconducting wiring layer, A third dielectric layer is formed so as to overlap at least a portion of the device loop superconducting wiring layer, Forming a second intermediate superconducting wiring layer so as to overlap the third dielectric layer, wherein the formation of the second intermediate superconducting wiring layer includes forming one or more second bias loop conductor segments, A fourth dielectric layer is formed so as to overlap at least a portion of the second intermediate superconducting wiring layer, The method according to claim 35, further comprising:

44. Forming the first intermediate superconducting wiring layer includes depositing a first layer of the relatively low inductance superconducting material, and patterning the first layer of the relatively low inductance superconducting material to form each of the one or more first bias loop conductor segments in a position that aligns with the first device loop conductor segment along the cross-section of the superconducting circuit and overlaps with the first device loop conductor segment, and The method according to claim 43, wherein forming a second intermediate superconducting wiring layer comprises depositing a second layer of the relatively low inductance superconducting material and patterning the second layer of the relatively low inductance superconducting material to form each of the one or more second bias loop conductor segments in a position that aligns with and overlaps with one of the first bias loop conductor segments along the cross-section of the superconducting circuit.

45. The method described above is Forming an external superconducting wiring layer of the body of the superconducting controllable device, which includes at least one pair of bias line interfaces, Forming one or more flux bias loops including at least a corresponding first bias loop conductor segment and a corresponding second bias loop conductor segment, wherein each flux bias loop surrounds a portion of the length of the second device loop conductor segment. It further includes, The method according to claim 44, wherein each pair of bias line interfaces is directly electrically coupled to the corresponding magnetic flux bias loop.

46. Forming each of the one or more magnetic flux bias loops is Forming multiple superconducting vias to electrically couple a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, To electrically couple the second bias loop conductor segment to the corresponding first bias loop conductor segment, a plurality of superconducting vias are formed. The method according to claim 45, including the method described in claim 45.

47. To form each of the one or more magnetic flux bias loops, Forming the first intermediate superconducting wiring layer includes depositing a first layer of the relatively low inductance superconducting material and patterning the first layer of the relatively low inductance superconducting material to include a corresponding first bias loop conductor segment and a first bias loop portion that directly overlaps the first bias loop conductor segment. Forming the device loop superconducting wiring layer further includes depositing a second layer of the relatively low inductance superconducting material, and patterning the second layer of the relatively low inductance superconducting material to include the second device loop conductor segment and the second bias loop portion that directly overlaps the first bias loop portion, and The method according to claim 45, further comprising forming a second intermediate superconducting wiring layer by depositing a third layer of the relatively low inductance superconducting material and patterning the third layer of the relatively low inductance superconducting material to include a corresponding second bias loop conductor segment and a third bias loop portion that directly overlaps the corresponding second bias loop conductor segment and is located below a corresponding pair of bias line interfaces.

48. The method according to claim 38, further comprising forming a feedback path that electrically couples the second device loop conductor segment of the superconducting loop to the motion inductance layer, wherein the feedback path has a relatively low inductance value and at least partially surrounds the first device loop conductor segment.

49. The method according to claim 48, wherein forming the return path includes forming a plurality of superconducting vias to communicately couple the second device loop conductor segment to the first device loop conductor segment.

50. Forming the motion inductance layer includes depositing the relatively high inductance superconducting material and patterning the relatively high inductance superconducting material such that it includes the first device loop conductor segment and, along the cross-section of the superconducting circuit, a first motion inductance layer feedback path termination and a second motion inductance layer feedback path termination on the first and second sides of the first device loop conductor segment, respectively. The method described above is Forming a first intermediate superconducting wiring layer, comprising: depositing a first layer of the relatively low inductance superconducting material; and patterning the first layer of the relatively low inductance superconducting material to include a first intermediate layer feedback portion and a second intermediate layer feedback portion that directly overlap the first and second motion inductance layer feedback end portions, respectively. Forming a second dielectric layer that overlaps at least a portion of the first intermediate superconducting wiring layer, wherein the device loop superconducting wiring layer overlaps the second dielectric layer. Furthermore, including, The method according to claim 48, wherein forming the device loop superconducting wiring layer comprises depositing a second layer of the relatively low inductance superconducting material and patterning the second layer of the relatively low inductance superconducting material to include the second device loop conductor segment, wherein the second device loop conductor segment directly overlaps the first intermediate feedback path portion and the second intermediate feedback path portion.

51. The further includes forming a shield structure, and forming the shield structure is Forming a shielded superconducting wiring layer on the outer surface of the main body of the superconducting controllable device in the superconducting circuit, To form a first shield arm and a second shield arm that at least partially surround the second device loop conductor segment and the return path, The method according to claim 50, including the method described in claim 50.

52. The method according to claim 51, wherein forming the first shield arm and the second shield arm includes forming superconducting vias extending from the shield superconducting wiring layer through the superconducting circuit to the first intermediate superconducting wiring layer.

53. The further includes forming a third dielectric layer that overlaps at least a portion of the device loop superconducting wiring layer, and Furthermore, in order to form the first shield arm and the second shield arm, The formation of the first intermediate superconducting wiring layer further includes patterning the first layer of the relatively low inductance superconducting material such that the first intermediate layer shielding structure portion and the second intermediate layer shielding structure portion are each located at corresponding lateral positions along the width of the cross-section of the superconducting circuit. The formation of the device loop superconducting wiring layer further includes patterning the second layer of the relatively low inductance superconducting material such that it includes a first device loop layer shielding structure and a second device loop layer shielding structure that directly overlap the first intermediate layer shielding structure and the second intermediate layer shielding structure, respectively, and The method according to claim 51, wherein forming the shield superconducting wiring layer includes depositing a shield layer of the relatively low inductance superconducting material that directly overlaps at least the first device loop layer shield structure portion and the second device loop layer shield structure portion.

54. The manufacturing of the superconducting circuit is To form a Josephson junction, wherein the Josephson junction is galvanically coupled to the superconducting loop of the body of the superconducting controllable device. To form one or more pairs of coupler connection interfaces, It further includes, Forming the kinetic inductance layer involves patterning the high-inductance superconducting material to include one or more pairs of coupler connection leads of the body of the superconducting controllable device, further including patterning each pair of the one or more pairs of coupler connection leads on the kinetic inductance layer at a distance from the Josephson junction along the length of the first device loop conductor segment, such that the majority of the total inductance of the superconducting controllable device is located between each pair and the Josephson junction. The method according to claim 52, wherein the one or more pairs of coupler connection interfaces are for galvanically coupling a corresponding pair of coupler connection leads of the body of the superconducting controllable device to a corresponding pair of coupler leads of a superconducting coupler.

55. A fourth dielectric layer is formed so as to overlap at least a portion of the device loop superconducting wiring layer, A second intermediate superconducting wiring layer is formed so as to overlap at least a portion of the fourth dielectric layer, It further includes, To form each pair of the one or more pairs of coupler connection interfaces, Forming the first intermediate superconducting wiring layer includes depositing a second layer of the relatively low inductance superconducting material and patterning the second layer of the relatively low inductance superconducting material such that it includes a pair of first layer coupler connection portions that directly overlap a corresponding pair of coupler connection leads. The formation of the device loop superconducting wiring layer further includes patterning the first layer of the relatively low inductance superconducting material such that it includes a pair of device loop layer coupler connection portions that directly overlap the pair of first layer coupler connection portions, and The method according to claim 54, wherein forming the second intermediate superconducting wiring layer includes depositing a third layer of the relatively low inductance superconducting material and patterning the third layer of the relatively low inductance superconducting material such that it includes a pair of second layer coupler connection portions that directly overlap the pair of device loop layer coupler connection portions.

56. The method according to claim 55, comprising patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions, or patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions that can be directly galvanically coupled to the pair of coupler leads.

57. A fourth dielectric layer is formed so as to overlap at least a portion of the second intermediate superconducting wiring layer, A third intermediate superconducting wiring layer is formed so as to overlap at least a portion of the fourth dielectric layer, It further includes, To form each pair of the one or more pairs of coupler connection interfaces, Patterning the third layer of the relatively low inductance superconducting material to include a pair of second layer coupler connection portions, and patterning the third layer of the relatively low inductance superconducting material to include a first second layer coupler connection portion of the pair of second layer coupler connection portions that can be directly galvanically coupled to a first coupler lead of the pair of coupler leads, and The method according to claim 55, wherein forming the third intermediate superconducting wiring layer comprises depositing a fourth layer of the relatively low inductance superconducting material and patterning the fourth layer of the relatively low inductance superconducting material such that it includes a third layer coupler connection portion that directly overlaps a second second layer coupler connection portion of a pair of second layer coupler connection portions, the third layer coupler connection portion being directly galvanically coupled to a second coupler lead of a pair of coupler leads.

58. Forming the first intermediate superconducting wiring layer involves patterning the first layer of the relatively low inductance superconducting material such that it includes one or more first bias interface loop conductor segments, and further includes patterning such that each of the one or more first bias loop conductor segments is aligned with and overlaps the first device loop conductor segment along the cross-section of the superconducting circuit, and The method described above is Forming a second intermediate superconducting wiring layer on top of the third dielectric layer, wherein forming the second intermediate superconducting wiring layer includes depositing a third layer of the relatively low inductance superconducting material and patterning the third layer of the relatively low inductance superconducting material to include one or more second bias loop conductor segments, wherein each of the one or more second bias loop conductor segments is positioned to align with and overlap one of the corresponding first bias loop conductor segments along the cross-section of the superconducting circuit. A fourth dielectric layer is formed so as to overlap at least a portion of the second intermediate superconducting wiring layer, The method according to claim 53, further comprising:

59. The method described above is Forming an external superconducting wiring layer of the body of the superconducting controllable device, which includes at least one pair of bias line interfaces, Forming one or more flux bias loops including at least a corresponding first bias loop conductor segment and a corresponding second bias loop conductor segment, wherein each flux bias loop surrounds a portion of the length of the second device loop conductor segment. It further includes, The method according to claim 58, wherein each pair of bias line interfaces is directly galvanically coupled to the corresponding magnetic flux bias loop.

60. Forming each of the one or more magnetic flux bias loops is Forming multiple superconducting vias to electrically couple a corresponding pair of bias line interfaces to a corresponding second bias loop conductor segment, To electrically couple the second bias loop conductor segment to the corresponding first bias loop conductor segment, a plurality of superconducting vias are formed. The method according to claim 59, including the method described in claim 59.

61. To form each of the one or more magnetic flux bias loops, The formation of the first intermediate superconducting wiring layer further includes patterning the first layer of the relatively low inductance superconducting material such that it includes a corresponding first bias loop conductor segment and a first bias loop portion that directly overlaps the first bias loop conductor segment. The formation of the device loop superconducting wiring layer further includes patterning the second layer of the relatively low inductance superconducting material such that it includes a second bias loop portion that directly overlaps the first bias loop portion, and The method according to claim 59, further comprising patterning the third layer of the relatively low inductance superconducting material such that the formation of the second intermediate superconducting wiring layer includes a corresponding second bias loop conductor segment and a third bias loop portion that directly overlaps the corresponding second bias loop conductor segment and is located below a corresponding pair of bias line interfaces.

62. The method according to claim 35, wherein forming the kinetic inductance layer includes forming the kinetic inductance layer from one of titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

63. The method according to claim 35, wherein forming the superconducting loop layer includes forming the superconducting wiring layer from one of aluminum, niobium, and tantalum.

64. The process involves forming a motion inductance layer directly on a substrate, wherein at least a first portion of the motion inductance layer is a first device loop conductor segment of a superconducting loop of the body of a superconducting controllable device, and the process includes forming the motion inductance layer, wherein at least the first portion of the motion inductance layer is a first coupler loop conductor segment of a superconducting coupler loop of the coupler body of a superconducting coupler, and The method according to claim 35, wherein forming a device loop superconducting wiring layer on top of the first dielectric layer, wherein at least a portion of the loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming the loop superconducting wiring layer, wherein at least a portion of the coupler loop superconducting wiring layer is a second coupler loop conductor segment of the coupler superconducting loop.

65. The formation of a kinetic inductance layer directly superimposed on a substrate, wherein at least a first portion of the kinetic inductance layer is a first device loop conductor segment of a superconducting loop of the body of a superconducting controllable device, the formation of the kinetic inductance layer, wherein the first loop conductor segment is a portion of the superconducting body loop of a quantum flux parametron (QFP), The method according to claim 35, wherein forming a device loop superconducting wiring layer on top of the first dielectric layer, wherein at least a portion of the device loop superconducting wiring layer is a second device loop conductor segment of the superconducting loop, and forming the device loop superconducting wiring layer, wherein the second device loop conductor segment is a second portion of the superconducting body loop of the QFP.

66. A qubit body comprising a superconducting qubit loop including a first qubit loop conductor segment communicatively coupled to a second qubit loop conductor segment, wherein the first qubit loop conductor segment comprises a relatively high inductance superconducting material having a relatively high inductance value and exhibiting superconducting behavior below a critical temperature, and the second qubit loop conductor segment comprises a relatively low inductance superconducting material having a relatively low inductance value compared to the relatively high inductance value of the relatively high inductance superconducting material and exhibiting superconducting behavior below a critical temperature, wherein the second qubit loop conductor segment overlaps the first qubit loop conductor segment within at least a portion of the superconducting circuit comprising the superconducting qubit, A Josephson junction electrically coupled to the superconducting qubit loop of the qubit body, A superconducting qubit equipped with this feature.

67. The superconducting qubit according to claim 66, wherein the qubit body further includes a shielding structure that at least partially surrounds the superconducting qubit loop, the shielding structure includes at least a planar shielding portion on the outer surface of the qubit body that overlaps the second qubit loop conductor segment in at least a portion of the superconducting circuit, and the planar shielding portion includes the relatively low inductance superconducting material.

68. The superconducting qubit according to claim 67, wherein the shield structure further comprises a pair of shield arms, each of which extends from the planar shield portion to at least a portion of the superconducting circuit such that it at least partially surrounds the second qubit loop conductor segment, and the shield arms include the relatively low inductance superconducting material.

69. The superconducting qubit according to claim 66, wherein the qubit body further includes a feedback path extending from the second qubit loop conductor segment to the feedback path termination, the feedback path termination comprising the relatively high inductance superconducting material, and the feedback path is located on the same layer as the first qubit loop conductor segment, at least partially surrounding the first qubit loop conductor segment, and at least a majority of the feedback path comprises the relatively low inductance superconducting material.

70. The first qubit loop conductor segment comprises one or more pairs of coupler connection leads, and The superconducting qubit according to claim 66, wherein the qubit body further comprises one or more pairs of coupler connection interfaces, and each pair of the one or more pairs of coupler connection interfaces is configured to galvanically couple one pair of the one or more pairs of coupler connection leads to a corresponding pair of coupler leads of a superconducting coupler.

71. The superconducting qubit according to claim 70, wherein each pair of the one or more pairs of coupler connection leads is positioned at a distance from the Josephson junction along the length of the qubit body such that the majority of the total qubit inductance of the superconducting qubit is located between each pair and the Josephson junction.

72. Each pair of the one or more pairs of coupler connection interfaces of the qubit body includes a first coupler connection interface and a second coupler connection interface, and each of the first coupler connection interface and the second coupler connection interface extends through at least a portion of the superconducting circuit from the first coupler connection lead and the second coupler connection lead of a corresponding pair of coupler connection leads to the first coupler connection site and the second coupler connection site of the qubit body, and the first coupler connection site and the second coupler connection site are located on the same layer of at least a portion of the superconducting circuit that overlaps the second qubit loop conductor segment, and The superconducting qubit according to claim 70, wherein the first coupler connection interface and the second coupler connection interface include the relatively low inductance superconducting material.

73. Each of the one or more pairs of coupler connection interfaces is A first coupler connection interface, wherein the first coupler connection interface extends through at least a portion of the superconducting circuit from a first coupler connection lead of a corresponding pair of coupler connection leads to a first coupler connection site of the qubit body that the first coupler connection interface can galvanically couple to the first coupler lead of the corresponding pair of coupler leads, and the first coupler connection site overlaps the second qubit loop conductor segment. A second coupler connection interface, wherein the second coupler connection interface extends through at least a portion of the superconducting circuit from the second coupler connection lead of the pair of coupler connection leads to the second coupler connection site of the qubit body, to which the second coupler connection interface can galvanically couple to the second coupler connection lead of the pair of coupler leads, and the second coupler connection site overlaps the first coupler connection site. Equipped with, The superconducting qubit according to claim 70, wherein the first coupler connection interface and the second coupler connection interface include the relatively low inductance superconducting material.

74. The qubit body further comprises one or more bias connection interfaces, each bias connection interface for electrically coupling the superconducting qubit loop to a corresponding pair of analog lines for transmitting bias signals, and each bias connection interface is A first bias loop conductor segment interposed between the first qubit loop conductor segment and the second qubit loop conductor segment, wherein the first bias loop conductor segment is aligned with the first qubit loop conductor segment along the width of at least a portion of the superconducting circuit, A second bias loop conductor segment overlapping the second qubit loop conductor segment, wherein the second bias loop conductor segment is aligned with the first bias loop conductor segment along the width of at least a portion of the superconducting circuit, A superconducting qubit according to claim 66, including the above.

75. Each of the one or more bias connection interfaces is A pair of bias line interfaces on the outer surface of the qubit body in the superconducting circuit, overlapping the second qubit loop conductor segment, wherein the pair of bias line interfaces can be directly electrically coupled to a corresponding pair of analog lines, A flux bias loop of the qubit body surrounding a portion of the length of the second qubit loop conductor segment, wherein the flux bias loop includes the first bias loop conductor segment and the second bias loop conductor segment, and the flux bias loop galvanically couples the first bias loop conductor segment, the second bias loop conductor segment, and the pair of bias line interfaces, Includes, The superconducting qubit according to claim 74, wherein the pair of bias line interfaces and the magnetic flux bias loop include the relatively low inductance superconducting material.

76. The superconducting qubit according to claim 75, wherein the pair of bias line interfaces can be directly and communicatively coupled to the corresponding pair of analog lines such that the principal axes of the first and second analog lines of the corresponding pair of analog lines are perpendicular to the principal axes of the first qubit loop conductor segment and the second qubit loop conductor segment.

77. The superconducting qubit according to claim 74, wherein the outer surface of the qubit body in at least a portion of the superconducting circuit further includes at least a portion of a shielding structure, the shielding structure includes the relatively low inductance superconducting material.

78. The superconducting qubit according to claim 66, wherein the superconducting qubit is symmetrical with respect to a vertical center line along the width of the qubit body.

79. The superconducting qubit according to claim 66, wherein the superconducting material having relatively high inductance includes one of titanium nitride, niobium nitride, titanium niobium nitride, and aluminum nitride.

80. The superconducting qubit according to claim 66, wherein the superconducting material with relatively low inductance includes one or more of aluminum, niobium, and tantalum.

81. The superconducting qubit according to claim 66, wherein the inductance per unit length of the relatively high inductance superconducting material is 50 times greater than the inductance per unit length of the relatively low inductance superconducting material.

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