Semiconductor device, method for operating a semiconductor device, and method for manufacturing a semiconductor device.

Abstract

According to one embodiment, the semiconductor device (100) comprises a semiconductor body (1) having a first type contact region (11) of a first conductivity type, a second type contact region (12) of a second conductivity type, and a drift region (14) of a first conductivity type. The semiconductor device further comprises a main electrode (2) and a gate electrode (3). A second type barrier region (42) is positioned longitudinally between the drift region and the second type contact region. The second type barrier region forms a barrier for the second type of charge carriers. The first type contact region and the second type contact region are separated laterally from each other by a portion of the drift region. The gate electrode is positioned laterally at least partially between the first type contact region and the second type contact region. The second type contact region is positioned longitudinally between the top surface (10) of the semiconductor body and the second type barrier region. The main electrode is in electrical contact with the first type contact region and the second type contact region. The area positioned vertically between the top surface of the semiconductor body and the second type of barrier region allows the current of the second type of charge carrier to flow only laterally between the contact region and the portion of the main electrode and the drift region.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices, methods for operating semiconductor devices, and methods for manufacturing semiconductor devices. [Overview of the project] [Problems that the invention aims to solve]

[0002] One objective to be achieved is to provide a semiconductor device that contributes to an improved plasma profile and / or improved injection enhancement effect, while reducing the possibility of latch-up, particularly during turn-off, and thus improving RBSOA capability. [Means for solving the problem]

[0003] First, semiconductor devices will be explained. According to one embodiment, the semiconductor device comprises a semiconductor body having a first type of contact region of a first conductivity type, a second type of contact region of a second conductivity type, and a drift region of a first conductivity type. The semiconductor device further comprises a main electrode and a gate electrode. A second type of barrier region is arranged longitudinally between the drift region and the second type of contact region. The second type of barrier region forms a barrier for the second type of charge carriers. The first type of contact region and the second type of contact region are separated laterally from each other by a portion of the drift region. The gate electrode is arranged laterally at least partially between the first type of contact region and the second type of contact region. The second type of contact region is arranged longitudinally between the top surface of the semiconductor body and the second type of barrier region. The main electrode is in electrical contact with the first type of contact region and the second type of contact region. The area vertically positioned between the top surface of the semiconductor body and the second type of barrier region allows the current of the second type of charge carrier to flow only between the main electrode and the portion of the drift region positioned laterally between the contact region.

[0004] The present invention is based, in particular, on the idea of ​​providing a further second type of charge carrier extraction unit. Since the second type of charge carrier can be holes, this unit is also called a "hole extracting accumulation-mode FET," abbreviated as HEAF, or a "hole extracting enhancement-mode FET," abbreviated as HEEF. This extraction unit provides an alternative path for the second type of charge carrier extraction, and since this alternative path is away from the first type of contact region, the entire device is less susceptible to parasitic thyristor latch-up and therefore provides improved resistance to RBSOA breakdown.

[0005] The semiconductor body may contain or be composed of Si or SiC. The semiconductor body has a top surface and a bottom surface opposite the top surface. Furthermore, the semiconductor body has a principal extension surface, and the top surface and / or bottom surface may extend at least partially parallel to the principal extension surface. In this specification, the transverse direction is defined as the direction parallel to the principal extension surface, and the longitudinal direction is defined as the direction perpendicular to the principal extension surface.

[0006] The first type of contact region is, for example, n-type, i.e., a first conductivity type that is n-doped. The second conductivity type is the opposite of the first conductivity type, i.e., it may be p-type, i.e., p-doped. The maximum or average doping concentration in the first type and / or second type of contact region is, for example, at least 10 18 cm -3 or at least 10 19 cm -3 or at least 10 20 cm -3 The contact area may also be referred to herein as the “source area.” The first and / or second type of contact area may be adjacent to, or form part of, the upper surface of the semiconductor body.

[0007] The drift region has the same conductivity type as the first type of contact region. Its maximum and / or average doping concentration is, for example, at least 10 times, at least 100 times, or at least 1000 times lower than those of the first type and / or second type of contact region.

[0008] The main electrode, also referred to herein as the "first main electrode," may be positioned on the upper surface of the semiconductor body. It contacts both the first type of contact region and the second type of contact region. In particular, the main electrode is adjacent to both the first type of contact region and the second type of contact region. The main electrode may be formed from a metal. For example, the main electrode is the emitter electrode.

[0009] A further main electrode, sometimes called a "second main electrode," may be located on the bottom surface of the semiconductor body and may be in contact with the semiconductor body at the bottom surface. This further main electrode may be a collector electrode.

[0010] The second type of barrier region forms a barrier for the second type of charge carriers. Therefore, during normal operation of the semiconductor device, the second type of charge carriers cannot pass through the second type of barrier region. The second type of barrier region may be formed from a highly doped semiconductor material of the first conductivity type or from an electrical insulating material, such as an oxide like SiO2. The second type of barrier region may be adjacent to a drift region on one side and / or a second type of contact region on another side.

[0011] The second type of barrier region can extend parallel to the top surface. For example, the length and width of the second type of barrier region measured laterally may be at least 5 times, or at least 10 times, and / or at most 50 times, the thickness of the second type of barrier region measured longitudinally.

[0012] The first type of contact region and the second type of contact region are spaced laterally, which is also referred to herein as the “first lateral direction.” A portion of the drift region is located laterally between the contact regions, i.e., in the first lateral direction. This portion of the drift region is also referred to herein as the “intermediate portion.” The intermediate portion may be adjacent to the top surface of the semiconductor body.

[0013] In the first lateral direction, at least a portion of the gate electrode is positioned between the contact regions. The gate electrode may be made of metal or highly doped polysilicon. For example, the gate electrode is electrically insulated from the semiconductor body. In this case, the semiconductor device may be a gate-insulating device. In a top view of the top surface of the semiconductor body, the gate electrode may overlap with a portion of the lateral drift region between the contact regions. Furthermore, in this top view, the gate electrode may at least partially overlap with a second type of barrier region. In this top view, the gate electrode may at least partially overlap with the first type of contact region and the second type of contact region.

[0014] Furthermore, the second type of contact area is positioned vertically, that is, vertically between the top surface and the second type of barrier area. In a top view of the top surface, the second type of contact area overlaps with the second type of barrier area.

[0015] The (entire) area vertically positioned between the top surface of the semiconductor body and the second type of barrier region is not composed of first type charge carriers, but only allows currents of second type charge carriers to flow laterally between the main electrode and the portion of the drift region in the contact region. In this specification, this area means the area that overlaps with the second type of barrier region in a top view of the top surface. In other words, the (entire) area vertically positioned between the top surface of the semiconductor body and the second type of barrier region is configured such that, during normal operation (i.e., on and off), currents of first type charge carriers do not flow through the second type of contact region between the main electrode and the intermediate portion of the drift region. For example, this area does not include contact regions of first conductivity type electrically in contact with the main electrode. For example, in this area, only semiconductor material of second conductivity type is in contact with the main electrode.

[0016] The second type of barrier and contact area may have a second transverse primary extension direction perpendicular to the first transverse direction. For example, the length of the second type of barrier and contact area measured in this second transverse direction is greater than the width and thickness of these areas measured in the first transverse and longitudinal directions, respectively, for example, at least twice, at least five times, or at least ten times greater. The second type of contact area and the second type of barrier area may be formed continuously without interruption. For example, the length of the second type of contact area is essentially the same as the length of the second type of barrier area, for example, with a deviation of at most 10%.

[0017] In a further embodiment, the semiconductor device is designed such that a current of a second type of charge carrier from the drift region to the main electrode via a second type of contact region is conductible during normal / intended operation, for example, during the turn-off state. In particular, during normal operation, a current of a second type of charge carrier from the intermediate portion of the drift region to the main electrode via the second type of contact region is conductible.

[0018] According to a further embodiment, all paths of the second type of charge carriers from the drift region to the main electrode via the second type of contact region are arranged vertically between the upper surface and the second type of barrier region and have at least one section extending in the lateral direction, particularly in the first lateral direction. In other words, the current path of the second type of charge carriers from the (middle part of the) drift region through the second type of contact region extends at least partially, preferably mainly, in the lateral direction. In particular, in the area arranged vertically between the upper surface and the second type of barrier region that overlaps the gate electrode when viewed from above the upper surface of the semiconductor body, the current path extends essentially in the (first) lateral direction.

[0019] This can be achieved, for example, by electrically contacting between the main electrode and the second type of contact region being offset in the first lateral direction from the edge of the second type of barrier region. In particular, the second type of contact region is further spaced apart from the first contact region in the first lateral direction than the edge of the second type of barrier region facing the first contact region. The offset or difference in the spacing can each be, for example, at least 1 μm or at least 2 μm. In particular, the width of the second type of barrier region may be greater than the width of the second type of contact region, and the width is measured in the first lateral direction herein.

[0020] According to a further embodiment, the semiconductor body further comprises a second type of base region that is of either the first conductivity type or the second conductivity type. The second type of base region is arranged vertically, for example, between the second type of barrier region and the upper surface. In the top view of the upper surface, the second type of base region may overlap the gate electrode and / or the second type of barrier region. For example, the second type of barrier region is adjacent to the upper surface and / or the second type of barrier region.

[0021] According to a further embodiment, the second type of contact region is separated from the drift region, particularly from an intermediate portion of the drift region, at least in a lateral direction, particularly at least in a first lateral direction, by the second type of base region. The second type of contact region may be adjacent to the second type of base region. For example, the second type of base region is arranged only laterally adjacent to the second type of contact region and is not arranged either vertically above or vertically below the second type of contact region.

[0022] According to a further embodiment, the doping concentration within the second type of base region, for example the maximum and / or average doping concentration, is lower, for example at least 10 times or at least 100 times or at least 1000 times lower, than within the second type of contact region.

[0023] According to a further embodiment, in a top view of the upper surface of the semiconductor body, the gate electrode overlaps with the second type of base region. For example, in this top view, the gate electrode completely overlaps with the second type of base region.

[0024] In a further embodiment, the semiconductor device is configured such that, in the on-state of the semiconductor device (e.g., Vge≧0), a second type of base region blocks second type of charge carriers, thereby preventing current of second type charge carriers from the drift region, particularly its intermediate portion, through the second type of contact region to the main electrode. For example, by appropriately designing the second type of base region and appropriately setting the potentials of the gate electrode, main electrode, and further main electrodes, first type charge carriers may accumulate in the second type of base region, thereby preventing the flow of current of second type charge carriers through the base region. For example, the second type of base region remains completely depleted during the on-state. This feature during the on-state prevents degradation of the on-state (Vce-sat). In particular, the second type of base region is designed to remain completely depleted during normal on-state operation. Therefore, it does not allow any second type charge carrier current to flow. This is, for example, when the thickness of the second type of base region is small (e.g., <1 μm) and / or its doping concentration is small (e.g., <10 μm). 15 cm -3 This can be achieved when, or both of the above occur.

[0025] In a further embodiment, the semiconductor device is configured such that, in the turn-off state of the semiconductor device (e.g., Vge < 0V), a second type base region is passable to the second type charge carriers, and as a result, current of the second type charge carriers is conductible from the drift region, particularly from its intermediate portion, through the second type contact region to the main electrode. For this purpose, the electrode potential must be appropriately set. For example, the aforementioned thickness and / or doping concentration of the second type base region allows current flow in the turn-off state. In particular, the semiconductor device is designed such that all current paths of the second type charge carriers from the intermediate portion of the drift region to the second type contact region must pass through the second type base region. For example, by appropriately setting the potential of the gate electrode, the second type charge carriers can accumulate in the portion of the second type base region facing the gate electrode, and as a result, this portion allows the formation of a current path.

[0026] According to a further embodiment, the semiconductor body comprises a first type base region which is a second conductivity type. This first type base region is also called a “well region”. The average and / or maximum doping concentration in the first type base region is, for example, at least 10 times, at least 100 times, or at least 1000 times lower than, for example, in the first type contact region.

[0027] In a further embodiment, the first type of contact region is separated from the drift region by the first type of base region. For example, the first type of contact region is adjacent to the first type of base region. The first type of contact region may be incorporated into the first type of base region.

[0028] In a further embodiment, in a top view of the top surface of the semiconductor body, the gate electrode overlaps with a first type of base region. In particular, in this top view, a portion of the first type of base region positioned laterally between the middle of the drift region and the first type of contact region is overlapped by the gate electrode. The first type of base region, especially the portion overlapping with the gate electrode, is depleted and subsequently inverted in the ON state of the semiconductor device. This allows for the flow of current of first type charge carriers from the main electrode to the drift region through the first type of contact region and the inverted first type of base region in the ON state of the semiconductor device. For this purpose, the potential of the electrodes must be appropriately set.

[0029] Semiconductor devices are, in particular, so-called planar devices that have a gate electrode on the upper surface of the semiconductor body.

[0030] In a further embodiment, the semiconductor device further comprises a first type barrier region longitudinally positioned between a drift region and a first type contact region. The first type barrier region forms a barrier for a second type of charge carrier. In particular, in a top view of the top surface, the first type contact region and optionally the first type base region overlap with the first type barrier region. With respect to the properties and dimensions of the first type barrier region, all features disclosed herein for the second type barrier region are also disclosed for the first type barrier region, and vice versa.

[0031] For example, the first type of contact area and / or the first type of base area are adjacent to the first type of barrier area. The first type of barrier area may also be adjacent to a drift area. The first type of contact area may be laterally offset from the edge of the first type of barrier area. In particular, the width of the first type of contact area is smaller than the width of the first type of barrier area.

[0032] According to a further embodiment, the first type of contact region is arranged vertically between the top surface and the first type of barrier region in a top view of the top surface and overlaps with the first type of barrier region.

[0033] Recently, trench devices such as trench insulated gate bipolar transistors (IGBTs) have been regarded as a more favorable design option than mainly planar devices due to their excellent on-state performance and improved characteristic curves (Eoff-Vcesat trade-off). The trench design benefits, inter alia, from its excellent plasma profile resulting from the dense vertical flow of electrons and holes near the emitter contact leading to the well-known injection enhancement effect. The plasma profile in the trench structure, and thus its on-state performance, can be further improved by reducing the length (L pcont ) of the emitter contact, or rather, by reducing the distance between trenches. In contrast, in conventional planar devices, electrons injected from the planar channel are forced to enter the emitter contact laterally near its edge with holes. As a result, simply reducing the emitter contact length as in trench devices does not improve the plasma profile, and thus Vce-sat, in the conventional planar design. However, planar devices offer other benefits such as better long-term reliability (lifetime) and rugged (SOA) performance compared to trench designs, along with a less complex (and thus less expensive) manufacturing process.

[0034] Herein, a first type of barrier region and a first type of contact region, also referred to as a trench-like planar (TLP) design, enables the creation of electron and hole flows in a planar design to achieve the same or even improved on-state performance compared to trench designs while retaining the original benefits of the planar design. In short, a design that includes the best of both worlds (trench and planar) is realized.

[0035] In further embodiments, the first type of barrier region and the second type of barrier region are spaced apart from each other laterally, particularly the first type. The first type of barrier region and the second type of barrier region may be arranged at the same height in the vertical direction.

[0036] Such a semiconductor device having a barrier region beneath a first type of contact region is also referred to herein as a “trench-like semiconductor device”. It uses the barrier region to block the vertical path of a second type of charge carrier, such as holes, and instead reroutes the holes to flow parallel to the first type of charge carrier. This feature allows L pcont By reducing the side-emitter contact dimensions, the injection enhancement effect is further improved, enabling improved on-state performance and characteristic curves, similar to those in trench-designed devices. Furthermore, unlike trench-designed devices, the design described herein has a vertical dimension L pcont By reducing the size, it becomes possible to realize true point-contact emitter devices without the limitations of lithography. In short, the introduction of the above features leads to significantly improved on-state losses and characteristic curves compared to planar designs, for example, making it a potential candidate for next-generation novel planar technology suitable for both low-voltage and high-voltage platforms.

[0037] According to further embodiments, the semiconductor device comprises a further second type of barrier region longitudinally positioned between a second type of barrier region and a second type of contact region. The further second type of barrier region may overlap with the second type of contact region and / or the second type of barrier region and / or gate electrode in a top view of the top surface of the semiconductor body. In particular, the second type of barrier region and the further second type of barrier region may have the same width and / or length within the limits of manufacturing tolerances.

[0038] According to further embodiments, a further second type of contact region of the second conductivity type is positioned longitudinally between the second type of barrier region and the further second type of barrier region. In a top view, the further second type of contact region may overlap with the second type of contact region and / or the further second type of barrier region. The main electrode may be in electrical contact with the further second type of contact region, for example, on its side. The second type of contact region may be separated and spaced apart from the drift region via a further second type of base region. The features disclosed above for the second type of contact region and the second type of base region are also disclosed for the further second type of contact region and the further second type of base region.

[0039] According to further embodiments, the main electrode is electrically in contact with a further second type of contact area, for example, on its side surface. The side surface is, as used herein, a side surface that faces laterally, i.e., a side surface that extends obliquely or perpendicularly to the main extension surface or the top surface, respectively.

[0040] A semiconductor device may have multiple, i.e., two or more, further second-type barrier regions arranged longitudinally between a second-type barrier region and a second-type contact region. Further second-type contact regions, and optionally further second-type base regions, may each be formed longitudinally between two second-type barrier regions. All features disclosed for one further second-type barrier region and one further second-type contact region are also disclosed for other further second-type barrier regions and other further second-type contact regions.

[0041] Stacking multiple (HEAF) units vertically further enhances the beneficial effects of the HEAF units.

[0042] Similarly, a semiconductor device may include one or more further first type barrier regions arranged longitudinally between a first type barrier region and a first type contact region. In this case, one or more further first type contact regions, and optionally one or more further first type base regions, may be arranged longitudinally between the first type barrier region and the further first type barrier regions, or between each of the two further first type barrier regions. Similar to the first type contact region, the further first type contact regions may be in electrical contact with the main electrode.

[0043] In a further embodiment, a portion of the main electrode extends longitudinally, thereby passing through a plurality of second-type barrier regions and making electrical contact with further second-type contact regions, particularly on the sides of further second-type contact regions.

[0044] According to further embodiments, the second type of barrier region is or comprises an electrically insulating material such as SiO2. Additionally or alternatively, the second type of barrier region is or comprises a semiconductor material of the first conductivity type. In this case, the maximum and / or average doping concentration of the semiconductor material in the second type of barrier region is at least 10 16 cm -3 or at least 10 18 cm -3 or at least 10 20 cm -3 This is possible. The same applies to the first type of barrier region.

[0045] According to a further embodiment, a further second type of barrier region comprises a conductive layer electrically insulated from the semiconductor body by a dielectric layer.

[0046] In further embodiments, the conductive layer is in electrical contact with either the gate electrode or the main electrode. The conductive layer may also be floating.

[0047] In a further embodiment, the semiconductor device comprises a plug region of a second conductivity type laterally adjacent to a first type contact region. For example, the plug region is adjacent to the first type contact region. Furthermore, the plug region may be adjacent to a first type base region. For example, the plug region is incorporated into the first type base region, like the first type contact region. The maximum and / or average doping concentrations of the plug region may be, for example, at least 10 times, at least 100 times, or at least 1000 times greater than those of the first type base region. The plug region allows for the formation of further pathways for extracting the second type charge carriers in the turn-off state.

[0048] In a further embodiment, the main electrode is in electrical contact with the plug region, for example, adjacent to the plug region.

[0049] According to further embodiments, the gate electrode comprises at least two portions, namely a first and a second portion, that are at least partially spaced laterally apart from one another. In particular, the two portions may be at least partially spaced laterally apart from the first portion. Such a gate electrode can reduce gate capacitance.

[0050] In a further embodiment, the first portion of the gate electrode is positioned to correspond to a first type of contact region, and the second portion of the gate electrode is positioned to correspond to a second type of contact region. For example, the second portion of the gate electrode overlaps with a second type of barrier region in a top view of the top surface of the semiconductor body, and the first portion of the gate electrode overlaps with a first type of barrier region in this top view. Furthermore, in this top view, the space between the two portions of the gate electrode may overlap with the middle portion of the drift region.

[0051] In a further embodiment, the main electrode electrically contacts a first type of contact region on its side and a second type of contact region on the top surface of the semiconductor body. This contact method, particularly contact on the side of the first type of contact region, makes it possible to reduce the emitter contact length in the first type of contact region. In this way, the plasma profile and Vce-sat can be improved.

[0052] According to a further embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured for a maximum voltage between the main electrodes of at least 0.2kV, at least 0.6kV, or at least 1.2kV. Alternatively or additionally, the semiconductor device is configured for a current between the main electrodes of at least 0.01kA, at least 0.1kA, at least 1kA and / or at most 100kA, or at most 10kA. That is, the flow of current through the semiconductor device can be controlled by the gate electrode and by having respective voltages between the main electrodes, and in particular, it can be switched on and off by switching the voltage at the gate electrode on and off.

[0053] Semiconductor devices can be transistors, such as gate-insulated transistors. In particular, semiconductor devices can be insulated-gate bipolar transistors, abbreviated as IGBTs, or reverse-conducting IGBTs, abbreviated as RC-IGBTs. IGBTs can be planar in design.

[0054] Next, the method for operating semiconductor devices will be explained. According to one embodiment, a method for operating a semiconductor device is for operating a semiconductor device according to any of the embodiments described herein. The method includes the step of operating the semiconductor device in an ON state in which a first type of charge carrier is injected from the main electrode into a first type of contact area. In another step, for example, after operating the semiconductor device in an ON state, the semiconductor device is turned OFF, i.e., turned OFF, and a second type of charge carrier is discharged from the semiconductor body through a second type of contact area into the first main electrode.

[0055] For example, during device operation, the first main electrode is at a negative potential relative to the second main electrode. In the ON state, the gate electrode may be at a positive potential relative to the first main electrode. In the turn-off state, the gate electrode may then be at a negative potential relative to the first main electrode.

[0056] Next, a method for manufacturing a semiconductor device is described. The method is particularly suitable for manufacturing a semiconductor device according to any of the embodiments described herein. Thus, all features disclosed in relation to a semiconductor device are also disclosed in relation to the method, and vice versa.

[0057] According to one embodiment, the method includes the steps of providing a base semiconductor body having a drift region of a first conductivity type, and forming a barrier region of a second type. The method further includes the step of manufacturing a semiconductor body from the base semiconductor body by forming a semiconductor region, i.e., a first type contact region of a first conductivity type and a second type contact region of a second conductivity type. The semiconductor region is formed such that the second type barrier region is longitudinally positioned between the drift region and the second type contact region, forming a barrier for the second type of charge carriers. The first type contact region and the second type contact region are separated laterally from each other by a portion of the drift region, and the second type contact region is longitudinally positioned between the top surface of the semiconductor body and the second type barrier region. The method further includes the steps of depositing a gate electrode such that the gate electrode is at least partially positioned laterally between the contact regions, and depositing a main electrode such that the main electrode is in electrical contact with the first type contact region and the second type contact region.

[0058] A second type of contact region may be formed on or above the upper surface of the base semiconductor body. For example, a second type of barrier region may be formed by ion implantation into the base semiconductor body or by depositing an electrically insulating material on the base semiconductor body.

[0059] According to a further embodiment, the method includes the step of growing a semiconductor material on top of a second type of barrier region. For example, by growing the semiconductor material, the second type of barrier region is fully incorporated into the semiconductor material.

[0060] In a further embodiment, a second type of contact region is formed within the grown semiconductor material. For example, the second type of contact region is formed within the grown semiconductor material by ion implantation.

[0061] According to a further embodiment, the method includes the step of depositing a sacrificial layer and a mask layer on a second type of barrier region in this order, i.e., the sacrificial layer is deposited on the second type of barrier region before the mask layer. For example, the sacrificial layer is adjacent to the second type of barrier region and / or the mask layer is adjacent to the sacrificial layer.

[0062] According to further embodiments, the sacrificial layer is then removed at least partially between the mask layer and the second type of barrier region. This may be done by etching. For example, the sacrificial layer is removed so that the (intermediate) portion of the drift region positioned laterally between the first type of contact region and the second type of contact region is exposed. As an example, the mask layer and the second type of barrier region are etched less by the corrosive solution than the sacrificial layer so that the sacrificial layer and the second type of barrier region remain intact when the etching process is applied.

[0063] According to further embodiments, the semiconductor material is then grown between the mask layer and a second type of barrier region, with the growth direction being at least partially lateral. For example, the growth process begins from the exposed (intermediate) portion of the drift region. The semiconductor material can then grow in a first lateral direction until it protrudes beyond the mask layer.

[0064] This method eliminates the need for a subsequent polishing step to provide a uniform top surface for the semiconductor body.

[0065] The following describes semiconductor devices, methods for operating semiconductor devices, and methods for manufacturing semiconductor devices in more detail with reference to drawings based on exemplary embodiments. The accompanying figures are included for further understanding. In the figures, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. The description of each of the following figures will not be repeated to the extent that elements or components correspond to each other in terms of their function in different figures. For clarity, elements may not appear with corresponding reference symbols in all figures. [Brief explanation of the drawing]

[0066] [Figure 1] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 2] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 3] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 4] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 5] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 6] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 7] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 8] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 9] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 10] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 11] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 12]This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 13] This is a flowchart illustrating an exemplary embodiment of a method for operating a semiconductor device. [Figure 14] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 15] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 16] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 17] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 18] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 19] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 20] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 21] This figure shows different locations in a first exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 22] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 23] This is a cross-sectional view showing different exemplary embodiments of a semiconductor device. [Figure 24] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 25] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 26] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 27] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 28] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 29] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 30] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 31] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 32] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 33] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 34] This figure shows different locations in a second exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 35] This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 36] This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 37] This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 38] This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 39] This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 40]This figure shows different locations in a third exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 41] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 42] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 43] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 44] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 45] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 46] This figure shows different locations in a fourth exemplary embodiment of a method for manufacturing semiconductor devices. [Modes for carrying out the invention]

[0067] Figure 1 shows a cross-sectional view of a first exemplary embodiment of semiconductor device 100. Semiconductor device 100 is a planar IGBT. The longitudinal direction V and the first transverse direction L1 are shown in Figure 1. These directions are the same in the following figures, but are not shown again in the following figures.

[0068] The semiconductor device 100 comprises a semiconductor body 1 having a top surface 10 and a bottom surface 19. The semiconductor body 1 includes, for example, a drift region 14 of a first conductivity type, which is n-type below. The bottom surface 19 of the semiconductor body 1 is accordingly formed by a contact layer 13 of a second conductivity type, which is p-type below.

[0069] On the upper surface 10, the semiconductor body 1 includes a first type of contact region 11 and a second type of contact region 12. The first type of contact region 11 is of the first conductivity type, and the second type of contact region 12 is of the second conductivity type. The contact regions 11 and 12 are spaced apart from each other in the first lateral direction L1.

[0070] The second type of barrier region 42 is positioned longitudinally, i.e., longitudinally V, between the second type of contact region 12 and the drift region 14. During normal operation of the semiconductor device 100, the second type of barrier region 42 is impermeable to the second type of charge carriers (holes). For example, the second type of barrier region 42 is a highly n-doped semiconductor material or an oxide such as SiO2.

[0071] The semiconductor device 100 further comprises a p-doped first type base region 15 and a second type base region 16. In the exemplary embodiment shown in Figure 1, the second type base region 16 is also p-doped, i.e., has the same conductivity as the second type contact region 12.

[0072] The doping concentration in the first type of base region 15, also called the "well region 15," is, for example, at least 100 times lower than in the first type of contact region 11. The first type of contact region 11 is incorporated into the first type of base region 15 and separated from the drift region 14 by the first type of base region 15.

[0073] The doping concentration in the second type base region 16 is, for example, at least 100 times lower than in the second type contact region 12. The second type base region 16 separates the second type contact region 12 from the drift region 14.

[0074] The gate electrode 3 and the first main electrode 2 are located on the top surface 10 of the semiconductor body 1. The second main electrode 4 is located on the bottom surface 19 of the semiconductor body 1. The first main electrode 2 is in electrical contact with the first type of contact region 11 and the second type of contact region 12. The second main electrode 4 is in electrical contact with the contact layer 13. The gate electrode 3 is electrically insulated from the semiconductor body 1 and the first main electrode 2 by the insulating material 23. In a top view of the top surface 10, the gate electrode 3 overlaps with the base regions 15 and 16, and as a result, the base regions 15 and 16 can be depleted / inverted by appropriately setting the potential of the gate electrode 3.

[0075] The operation of the semiconductor device 100 in Figure 1 may be as follows. In the ON state, the first main electrode 2 is at a negative potential relative to the second main electrode 4. The gate electrode 3 is at a positive potential relative to the first main electrode 2. Accordingly, the base regions 15 and 16 below the gate electrode 3 are depleted from holes, and subsequently, the n-type channel region below the gate electrode is inverted and formed. Thus, electrons can be injected from the main electrode 2 into the first type contact region 11, and can flow through the inverted portion or channel region of the first type base region 15 into the drift region 14. In the drift region 14, electrons can then recombine with holes injected from the second main electrode 4 through the p-type contact layer 13. Note that during ON-state operation (Vge > 0V), the base region 16 remains completely depleted, and therefore, the portion of the hole current does not flow out through the second contact region 12.

[0076] When the semiconductor device 100 is turned off, i.e., in the turn-off state, the potential of the gate electrode 3 can be negative relative to the potential of the first main electrode 2. Accordingly, holes accumulate in the portion of the second base region 16 facing the gate electrode 3. Holes from the drift region 14 can move through the accumulation portion of the second type base region 16 into the second type contact region 12, from where they can be injected into the main electrode 2. This is indicated by the arrow in Figure 1. The holes then move through the second type base region 16 in a direction parallel to the first lateral direction L1. Thus, the second type contact region 12, together with the second type base region 16, forms an alternative path for holes to reduce the electron-hole plasma in the drift region 14. However, some of the holes are also extracted through the first type base region 15, as indicated by the vertical arrow in Figure 1.

[0077] Figures 2 and 3 show a second exemplary embodiment of the semiconductor device 100, where again the semiconductor device 100 is a planar IGBT. In contrast to the exemplary embodiment of Figure 1, the first type of barrier region 41 is located beneath the first type of contact region 11 and the first type of base region 15. This first type of barrier region 41 is impermeable to holes during the normal operation of the semiconductor device 100. Therefore, during turn-off operation (Vge < 0V) (as shown in Figure 2), holes extracted through the first type of base region 15 must move laterally beneath the first type of contact region 11. Thus, the direction of hole flow is essentially parallel to the direction of electron flow in the on state. In other words, during turn-off (Vge < 0V), there is p-type channel formation (by accumulation or inversion) within the second base region 16, which provides an alternative path to hole extraction in addition to the path through the first base region 15, as indicated by the arrow in Figure 2. The direction of electron flow is indicated by the arrow in Figure 3, which shows the ON state of the semiconductor device 100.

[0078] Figure 4 shows an exemplary embodiment of semiconductor device 100 in which the structure shown in Figure 3 is mirror-reversed to the right. Here, there are two first-type contact regions 11 having associated first-type base regions 15 and first-type barrier regions 41. A second-type contact region 12 is positioned laterally between the two first-type contact regions 11 and sandwiched laterally between the two second-type base regions 16. As can be seen in Figure 4, the width of the second-type barrier region 42 is greater than the width of the second-type contact regions 12, i.e., the second-type barrier region 42 protrudes beyond the second-type contact regions 12 in the first lateral direction L1 and in the direction opposite to the first lateral direction L1.

[0079] In the previous exemplary embodiment, the barrier regions 41, 42 are formed from an electrical insulating material such as SiO2.

[0080] The exemplary embodiment in Figure 5 shows a case where the barrier regions 41 and 42 are formed from a highly doped n-type semiconductor material. This also forms a barrier against holes.

[0081] Figure 6 shows an exemplary embodiment of a semiconductor device 100 in which a plurality of further second type barrier regions 42' are arranged longitudinally between a second type contact region 12 and a second type barrier region 42. The second type barrier region 42 thereby protrudes in a first lateral direction L1 beyond the further second type barrier regions 42'. The further second type contact regions 12' are arranged between each pair of second type barrier regions 42'. Each of the further second type contact regions 12' is separated from the first lateral drift region 14 by a further second type base region 16'. Furthermore, the further second type contact regions 12' and the further second type base regions 16' are arranged between the second type barrier region 42' closest to the second type barrier region 42 and the second type barrier region 42. Further second type contact regions 12' and associated further second type base regions 16' may be formed in exactly the same way as the second type contact regions 12 and 16, for example, with respect to doping concentration and relative spatial arrangement. The first main electrode 2 extends longitudinally across the second type contact regions 12, 12' and contacts the second type contact regions 12, 12' on its sides. Each unit comprising the second type contact regions 12, 12' and the second type base regions 16, 16' provides an additional path for hole extraction during the turn-off state.

[0082] Similar structures are formed on the sides of the first type regions 11, 41, and 16. Here again, a plurality of further first type barrier regions 41' are arranged longitudinally between the first type barrier region 41 and the first type contact region 11. At least one corresponding first type contact region 11' and a corresponding first type base region 15' are each arranged between two further first type barrier regions 41'. The first main electrode 2 extends longitudinally V across the first type contact region 11 and further first type contact regions 11' and is in electrical contact with them on their sides. Each unit comprising further first type base regions 15' and further first type contact regions 11' provides a current path for electrons during the ON state of the semiconductor device 100.

[0083] The semiconductor device 100 in Figure 6 can be considered a multi-trench planar device having barrier regions 41, 41', 42, and 42' that form trench-like structures extending in the transverse direction instead of the longitudinal direction.

[0084] In Figure 6, the further barrier regions 41' and 42' each comprise a conductive layer 47 electrically insulated from the semiconductor body 1 by a dielectric layer 48. The conductive layer 47 may be at the same potential as the gate electrode 3 or the first main electrode 2, or it may be floating.

[0085] Figure 7 shows a further exemplary embodiment of the semiconductor device 100. Here, the plug region 17 is provided longitudinally between the first type of barrier region 41 and the upper surface 10 of the semiconductor body 1. The plug region 17 is of the second conductivity type, i.e., p-doped, and has a higher doping concentration than the first type of base region 15. The first main electrode 2 is in electrical contact with the plug region 17.

[0086] This plug region 17 enables improved coverage of the emitter metal of the first main electrode 2 above the base region 15 / plug region 17, leading to reduced contact resistance, especially compared to a side-only contact design during the turn-off transient. In the latter case, L pcont L is determined by the thickness of the base region 15, and therefore, pcont Further injection enhancement can be achieved by reducing the size. Note that, unlike in Figure 7, the plug region 17 can also extend longitudinally below the first type of contact region 11, i.e., between the first type of contact region 11 and the first type of barrier region 1.

[0087] In the previous exemplary embodiments, the gate electrode 3 is formed to extend continuously in a first lateral direction L1 from the area of ​​the first type of contact region 11 to the area of ​​the second type of contact region 12. In these exemplary embodiments, the gate electrode is formed in a bridge-like structure such that a portion of the lateral gate electrode 3 between the base regions 15 and 16 is further from the semiconductor body 1 than the portion overlapping with the base regions 15 and 16. This reduces the gate capacitance.

[0088] In the exemplary embodiment shown in Figure 8, the gate electrode 3 instead has a hole in the lateral region between the base regions 15, 16. Thus, the gate electrode 3 comprises two portions 31, 32 that are at least partially spaced apart from each other in a first lateral direction L1. Each of the portions 31, 32 is positioned corresponding to either their first type contact region 11 and first type base region 15, or a second type contact region 12 and second type base region 16. Such a so-called split gate electrode makes it possible to further reduce the gate capacitance.

[0089] Figure 9 shows an exemplary embodiment of a semiconductor device 100 in which a conductive element 33 is positioned laterally between two portions 31 and 32. The conductive element 33 is either floating or electrically connected to the first main electrode 2. Furthermore, the conductive element 33 is either larger than portions 31 and 32 of the gate electrode 3 or at a distance to the same semiconductor body 1.

[0090] In the previous exemplary embodiment, the second type base region 16 was always formed from a semiconductor material of the second conductivity type, i.e., p-type. In the exemplary embodiment of Figure 10, the second type base region 16 is formed from a semiconductor material of the first conductivity type, i.e., n-type. The doping concentration may be lower than that in the second type contact region 12. In the off state of the semiconductor device 100, the portion of the second type base region 16 facing the gate electrode 3 is depleted and subsequently inverted to form channels for the second type charge carriers. In this way, during the turn-off state, holes can be extracted from the drift region 14 through the inverted portion of the second type base region 16 and the second type contact region 12 and injected from there into the first main electrode 2.

[0091] In contrast to the previous exemplary embodiment, in which the first main electrode 2 is always formed to protrude beyond the first type of contact region 11 in the direction opposite to the longitudinal direction V and to be in electrical contact with the first type of contact region 11 on its side, Figure 12 shows an exemplary embodiment of a semiconductor device 100 in which the first main electrode 2 is in electrical contact with the first type of contact region 11 on the upper surface 10 of the semiconductor body 1. The first type of barrier region 41 is adjacent to the side of the first type of contact region 11 and covers this side. In particular, the first type of contact region 11 and the first type of barrier region 41 are at least partially located at the same height in the longitudinal direction.

[0092] Figure 12 shows an exemplary embodiment of the semiconductor device 100, in which the first main electrode 2 is guided longitudinally across the second type of contact region 12, electrically contacts the second type of contact region 12 on its side, and reaches the second type of barrier region 42.

[0093] Figure 13 shows a flowchart of an exemplary embodiment of a method for operating a semiconductor device, for example, one of the semiconductor devices described in relation to Figures 1 to 12. In step S1, the semiconductor device operates in its ON state, where a first type of charge carrier, such as electrons, is injected from the main electrode 2 into a first type of contact region 11 (see, for example, Figure 3). In step S2, the semiconductor device is then turned OFF, i.e., operates in its turn-off state, where a second type of charge carrier is discharged from the semiconductor body through a second type of contact region 12 into the first main electrode 2 (see, for example, Figures 1 and 2).

[0094] Figure 14 shows a first position in a first exemplary embodiment of a method for manufacturing a semiconductor device. A base semiconductor body 1' is provided, comprising a drift region 14 and a contact layer 13. The drift region 14 is of a first conductivity type, and the contact layer 13 is of a second conductivity type.

[0095] Figure 15 shows the position where the barrier layer 40 is deposited on the upper surface of the base semiconductor body 1'. Figure 16 shows the position where a portion of the barrier layer 40 has been removed, leaving two barrier regions spaced apart in the first lateral direction L1, namely a first type of barrier region 41 and a second type of barrier region 42.

[0096] At the location shown in Figure 17, the semiconductor material 18 is growing on the first type of barrier region 41 and the second type of barrier region 42 18, and in the lateral region between them.

[0097] At the position shown in Figure 18, a first-type contact region 11 of the first conductivity type and a first-type base region 15 of the second conductivity type are formed within the area of ​​the first-type barrier region 41. Furthermore, a second-type contact region 12 and a second-type base region 16 are formed on top of the second-type barrier region 42. Both regions 12 and 16 are of the second conductivity type. In this way, the semiconductor body 1 is formed from the base semiconductor body 1'.

[0098] Figure 19 shows the location where a layer of electrical insulating material 23, such as SiO2, is deposited on the upper surface of the semiconductor body 1.

[0099] At the location shown in Figure 20, a portion of the semiconductor body 1 is removed, for example, by etching, thereby exposing the side surface of the first type contact region 11 and the side surface of the first type base region 15, and the top surface of the first type barrier region 41.

[0100] Figure 21 shows the position of the gate electrode 3 after it has been deposited on top of the electrical insulating material 23. In a top view of the semiconductor body 1, the gate electrode 3 overlaps with a portion of the first type base region 15, which is positioned laterally between the first type contact region 11 and the second type contact region 12, and also overlaps with the second type base region 16 in the same top view.

[0101] At the position shown in Figure 22, the gate electrode 3 is covered by an additional electrical insulating material 23. In Figure 23, the first main electrode 2 is deposited on the upper surface of the semiconductor body 1 so as to be electrically in contact with the first type of contact region 11 and the first type of base region 15 on their sides, and with the second type of contact region 12 on its upper surface. The first main electrode 2 thereby extends laterally over the gate electrode 3. Furthermore, the second main electrode 4 is deposited on the bottom surface of the semiconductor body 1 so as to be in contact with the contact layer 30. Simultaneously, Figure 23 shows a completed semiconductor device 100 in the form of a planar IGBT.

[0102] Figure 24 shows the first position in a second exemplary embodiment of the method, which is the same position as shown in Figure 14.

[0103] Figure 25 shows a further location of a second exemplary embodiment of the method, which is the same location as shown in Figure 15.

[0104] At the location shown in Figure 26, a portion of the barrier layer 40 is removed, as described in relation to Figure 16. Furthermore, the sacrificial layer 5 is deposited on the exposed portions of the base semiconductor body 1' in the lateral direction between the barrier regions 41 and 42. The sacrificial layer 5 is made of, for example, carbon.

[0105] At the location shown in Figure 27, the mask layer 6 is deposited on top of the sacrificial layer 5. The mask layer 6 may be a photoresist layer or a hard mask layer such as a metal layer.

[0106] At the location shown in Figure 28, a portion of the mask layer 6 has been removed so that the top surface of the sacrificial layer 5 is exposed. This may be done using an additional mask.

[0107] In Figure 29, a portion of the sacrificial layer 5 beneath the mask layer 6 has been removed, for example, by etching, thereby exposing a portion of the drift region 14 and the first type of barrier region 41.

[0108] Figure 30 shows the position of the semiconductor material 18 after it has grown over the exposed drift region 14 and the exposed first type of barrier region 41, so that the semiconductor material 18 grows laterally between the first type of barrier region 41 and the mask layer 6.

[0109] In Figure 31, the remaining sacrificial layer 5 between the mask layer 6 and the second type of contact region 42 has been removed, for example, by etching, thereby exposing a portion of the drift region 14 and the second type of barrier region 42.

[0110] In Figure 32, a different growth process is being performed, resulting in the semiconductor material 18 growing between the mask layer 6 and the second type of barrier region 42 in a first lateral growth direction.

[0111] In Figure 33, the mask layer has been removed so that the top surface of the grown semiconductor material 18 is exposed.

[0112] In Figure 34, a first type contact region 11, a first type base region 15, a second type contact region 12, and a second type base region 16 are formed on the growing portion of the semiconductor material, for example, by ion implantation. In this way, a semiconductor body 1 is manufactured that can be used to manufacture, for example, the semiconductor device 100 shown in Figure 23.

[0113] Figure 35 shows the location in a third exemplary embodiment of the method for manufacturing a semiconductor device. It is the same location as shown in Figure 27. However, the mask layer 6 remains symmetrical here, and the sacrificial layer beneath the mask layer 6 is completely removed, for example, by etching (see location in Figure 36).

[0114] At the location shown in Figure 37, the semiconductor material 18 grows on the exposed drift region 14, and as a result, the semiconductor material grows laterally between the first type of barrier region 41 and the mask layer 6, and between the second type of barrier region 42 and the mask layer 6.

[0115] At the location shown in Figure 38, the mask layer 6 and the portion of the grown semiconductor material 18 are removed, for example, by etching. Etching of the semiconductor material 18 may be performed before or after the removal of the mask layer 6 (see location shown in Figure 39).

[0116] Figure 40 shows the positions of the first type contact region 11, the first type base region 15, the second type contact region 12, and the second type base region 16 after they have been formed on the growing portion of the semiconductor material, for example, by ion implantation. In this way, a semiconductor body 1 is manufactured that can be used to manufacture, for example, the semiconductor device 100 shown in Figure 23.

[0117] In contrast to the second exemplary embodiment, the third exemplary embodiment of the method uses only one overgrowth step to manufacture the semiconductor body 1 from the base semiconductor body 1'.

[0118] Figure 41 shows the locations in a fourth exemplary embodiment of the method for manufacturing a semiconductor device. The locations are the same as those shown in Figure 28.

[0119] At the location shown in Figure 42, a portion of the sacrificial layer 5 beneath the mask layer 6 has been removed, for example, by etching, thereby exposing a portion of the drift region 14 and the first type of barrier region 41.

[0120] At the location shown in Figure 43, the semiconductor material 18 is growing on the exposed drift region 14 and the exposed first-type barrier region 41 so that the semiconductor material 18 grows laterally between the first-type barrier region 41 and the mask layer 6. The semiconductor material is in-situ doped, i.e., doped during growth, so that a first-type base region 15 is formed.

[0121] Figure 44 shows the remaining sacrificial layer 5 between the mask layer 6 and the second type of contact region 42, which has been removed, for example, by etching, and the location where a portion of the drift region 14 and the second type of barrier region 42 are thus exposed.

[0122] At the location shown in Figure 45, a different growth process is being performed, resulting in the growth of the semiconductor material 18 between the mask layer 6 and the second type of barrier region 42 in a first lateral growth direction. Here again, in-situ doping is performed so that the second type of base region 16 and the second type of contact region 12 are formed during growth.

[0123] Figure 46 shows the position after the mask layer 6 has been removed and the first type of contact region 11 has been formed by injection. Thus, in the fourth exemplary embodiment, only one injection step is required. From the position in Figure 46, for example, the semiconductor device 100 shown in Figure 23 can be manufactured.

[0124] As stated, the embodiments shown in Figures 1 to 46 represent exemplary embodiments of semiconductor devices, methods for operating semiconductor devices, and methods for manufacturing semiconductor devices, and therefore they do not constitute a complete list of all embodiments of semiconductor devices, methods for operating semiconductor devices, and methods for manufacturing semiconductor devices. Actual semiconductor devices, methods for operating semiconductor devices, and methods for manufacturing semiconductor devices may differ from the embodiments shown, for example, with respect to arrangement, elements, and the order of method steps. [Explanation of symbols]

[0125] Reference sign 1. Semiconductor body 1' Base semiconductor body 2 (First) Main Electrode 3. Foodstuffs 4. Further / Second Main Electrode 5 layers of victims 6 Mask Layers 10 Top side 11. First type of contact area 11' Further first type contact area 12. Second type of contact area 12' Further second type of contact area 13 Contact Layer 14. Drift Region 15. Base region of the first type 15' Further first type base region 16. Base region of the second type 16' A further second type of base region 17 Plug area 18 Semiconductor Materials 19. Base 23 Electrical insulating materials 31. First part of the gate 32 The second part of the gate 33 Conductive elements 40 Barrier layer 41. First type of barrier region 41' Further first type barrier region 42. Second type of barrier region 42' A second type of barrier region 47 Conductive layer 48 Dielectric layer 100 Semiconductor Devices L1 First lateral direction V vertical direction S1 Method Step S2 Method Steps

Claims

1. A semiconductor body (1) having a first type of contact region (11) of a first conductivity type, a second type of contact region (12) of a second conductivity type, and a drift region (14) of the first conductivity type, Main electrode (2) and gate electrode (3) A semiconductor device (100) comprising, A second type of barrier region (42) is positioned longitudinally between the drift region (14) and the second type of contact region (12), and the second type of barrier region (42) forms a barrier for the second type of charge carrier. The first type of contact region (11) and the second type of contact region (12) are spaced laterally apart from each other by a portion of the drift region (14), The terminal electrode (3) is at least partially positioned laterally between the contact regions (11, 12), The second type of contact region (12) is arranged vertically between the upper surface (10) of the semiconductor body (1) and the second type of barrier region (42). The main electrode (2) is in electrical contact with the first type of contact region (11) and the second type of contact region (12), The area, which is vertically positioned between the upper surface (10) of the semiconductor body (1) and the second type of barrier region (42), allows only the current of the second type of charge carrier to flow between the main electrode (2) and the portion of the drift region (14) that is horizontally positioned between the contact regions (11, 12). Semiconductor device (100).

2. The semiconductor device (100) In normal operation, current of the second type of charge carrier can be conducted from the drift region (14) to the main electrode (2) via the second type of contact region (12). All paths of the second type of charge carriers from the drift region (14) to the first main electrode (2) via the second type of contact region (12) have a cross section that is longitudinally positioned between the upper surface (10) and the second type of barrier region (42) and extends transversely. Designed to do so, The semiconductor device (100) according to claim 1.

3. The semiconductor body (1) further comprises a second type of base region (16) which is either the first conductivity type or the second conductivity type, The second type of contact region (12) is separated from the drift region (14) by the second type of base region (16) at least in the lateral direction (L1), The doping concentration in the second type base region (16) is lower than that in the second type contact region (12), The gate electrode (3) overlaps with the second type of base region (16) in a top view of the top surface (10) of the semiconductor body (1), and as a result, In the ON state of the semiconductor device (100), the second type base region (16) blocks the second type charge carriers such that current of the second type charge carriers from the drift region (14) to the main electrode (2) via the second type contact region (12) is prevented. In the turn-off state of the semiconductor device (100), the second type base region (16) is permeable to the second type charge carriers so that current of the second type charge carriers can be conducted from the drift region (14) to the first main electrode (2) via the second type contact region (12). The semiconductor device (100) according to claim 2.

4. The semiconductor body (1) comprises a first type base region (15) which is the second conductivity type, The first type of contact region (11) is separated from the drift region (14) by the first type of base region (15), The gate electrode (3) overlaps with the first type base region (15) in a top view of the top surface (10) of the semiconductor body (1) so that the potential of the gate electrode (3) is appropriately set to allow current flow of first type charge carriers from the main electrode (2) to the drift region (14) via the first type contact region (11) and the inverted first type base region (15) in the ON state of the semiconductor device (100), thereby depleting and subsequently inverting the first type base region (15). A semiconductor device (100) according to any one of the preceding claims.

5. A first type barrier region (41) is positioned longitudinally between the drift region (14) and the first type contact region (11) to form a barrier for a second type of charge carrier. Furthermore, The first type of contact region (11) is arranged vertically between the upper surface (10) and the first type of barrier region (41), and overlaps with the first type of barrier region (41) in a top view of the upper surface (10). The first type of barrier region (41) and the second type of barrier region (42) are spaced apart from each other laterally. A semiconductor device (100) according to any one of the preceding claims.

6. A further second type barrier region (42') is positioned longitudinally between the second type barrier region (42) and the second type contact region (12). Equipped with, The at least one further second type of barrier region (42') overlaps with the second type of contact region (12) in a top view of the top surface (10), A further second type of contact region (12') of the second conductive type is arranged longitudinally between the second type of barrier region (42) and the further second type of barrier region (42'), The main electrode (2) is in electrical contact with the further second type of contact region (12'), A semiconductor device (100) according to any one of the preceding claims.

7. A portion of the main electrode (2) extends in the longitudinal direction (V), thereby passing through the plurality of second-type barrier regions (42, 42') and electrically contacting the further second-type contact region (12'). The semiconductor device (100) according to claim 6.

8. The second type of barrier region (42) is made of an electrical insulating material and / or The second type of barrier region (42) is made of the first conductive semiconductor material. A semiconductor device (100) according to any one of the preceding claims.

9. The further second type of barrier region (42') comprises a conductive layer (47) electrically insulated from the semiconductor body (1) by a dielectric layer (48), The conductive layer (47) is in electrical contact with either the gate electrode (3) or the main electrode (2). A semiconductor device (100) according to claim 6 or any one of claims 7 and 8 dependent on claim 6.

10. The second conductive plug region (17) is laterally adjacent to the first type of contact region (11). Furthermore, The main electrode (2) makes electrical contact with the plug region (17). A semiconductor device (100) according to any one of the preceding claims.

11. The gate electrode (3) comprises at least two portions (31, 32) that are at least partially spaced apart from each other in the lateral direction. The first portion (31) of the above-ground part (3) is positioned in correspondence with the first type of contact area (11), The second portion (32) of the gate electrode (3) is positioned corresponding to the second type of contact region (12), A semiconductor device (100) according to any one of the preceding claims.

12. The main electrode (2) electrically contacts the first type of contact region (11) on its side surface and contacts the second type of contact region (12) on the upper surface (10) of the semiconductor body (1). A semiconductor device (100) according to any one of the preceding claims.

13. The semiconductor device (100) is an IGBT. A semiconductor device (100) according to any one of the preceding claims.

14. A method for operating a semiconductor device (100) as described in any one of the preceding claims, The semiconductor device (100) is operated in an ON state in which a first type of charge carrier is injected from the main electrode (2) into the first type of contact region (11), The semiconductor device (100) is operated in a turn-off state in which a second type of charge carrier is released from the semiconductor body (1) into the main electrode (2) via the second type of contact region (12). Methods that include...

15. A method for manufacturing a semiconductor device (100), A base semiconductor body (1') having a first conductivity type drift region (14) is provided, To form a second type of barrier region (42), The semiconductor body (1) is manufactured from the base semiconductor body (1') by forming semiconductor regions, that is, a first type contact region (11) of the first conductivity type and a second type contact region (12) of the second conductivity type, and as a result, The second type of barrier region (42) is positioned longitudinally between the drift region (14) and the second type of contact region (12), forming a barrier for the second type of charge carriers. The first type of contact region (11) and the second type of contact region (12) are spaced laterally apart from each other by a portion of the drift region (14), The second type of contact region (12) is arranged vertically between the upper surface (10) of the semiconductor body (1) and the second type of barrier region (42) during manufacturing. The gate electrode (3) is deposited such that it is at least partially positioned laterally between the contact regions (11, 12), The main electrode (2) is deposited such that it is in electrical contact with the first type of contact area (11) and the second type of contact area (12). Methods that include...

16. Growing a semiconductor material (18) on top of the second type of barrier region (42) It further includes, The second type of contact region (12) is formed within the grown semiconductor material (18). The method according to claim 15.

17. A sacrificial layer (5) and a mask layer (6) are deposited in this order on the second type of barrier region (42). Next, the sacrificial layer (5) is at least partially removed between the mask layer (6) and the second type of barrier region (42), Next, the semiconductor material (18) grows between the mask layer (6) and the second type of barrier region (42), with the growth direction being at least partially transverse. The method according to claim 16.

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