Chip time synchronization method, apparatus, electronic device, storage medium, and computer program

Abstract

Embodiments of this disclosure disclose a chip time synchronization method, apparatus, electronic device, and storage medium. The method includes generating a pulse signal according to a predetermined period; capturing a time snapshot representing the time information of at least one timer in at least one chip at a predetermined state of the pulse signal in response to the pulse signal; and performing time synchronization for each timer in at least one chip based on the time snapshot of each timer. Embodiments of this disclosure enable time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip based on a unified time snapshot. Since the time snapshot can be captured entirely in hardware without software involvement, errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved.

Description

Technical Field

[0001] This disclosure claims the priority of a Chinese patent application filed with the State Intellectual Property Office of China on January 19, 2024, with the application number CN202410083732.5 and the invention title "Chip Time Synchronization Method, Device, Electronic Device, and Storage Medium", and incorporates all of its content into this disclosure by reference.

[0002] This disclosure relates to the technical field of computer-assisted driving, and particularly to a chip time synchronization method, device, electronic device, and storage medium.

Background Art

[0003] Time synchronization is fundamental to sensor data fusion in scenarios such as intelligent driving. Time synchronization typically involves two crucial steps: measuring time errors and adjusting time. Measuring time errors usually involves measuring the time difference between a slave clock and a master clock, while time adjustment typically involves achieving time synchronization between the slave clock and the master clock by compensating for the slave clock's time based on the time difference. A System on Chip (SOC) typically includes multiple hardware timers, such as a Real-Time Clock (RTC), hardware timers within an Ethernet card, and hardware timers in Peripheral Component Interconnect Express (PCIE) modules. These hardware timers maintain the time of their corresponding modules. For a single chip, these hardware timers are typically distributed across one or more core domains. Each core domain may include a processor core (which may also be abbreviated as a core) and at least one hardware timer corresponding to that core. The software of one processor core cannot access the hardware timers corresponding to other processor cores. When using multi-level synchronization to synchronize the hardware timers of multiple processor cores on a single chip, significant delays are likely to occur. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] According to embodiments of this disclosure, a chip time synchronization method, apparatus, electronic device, and storage medium are provided that can effectively avoid or reduce the occurrence of delays and improve the accuracy of time synchronization. [Means for solving the problem]

[0005] According to one embodiment of the present disclosure, a method for synchronizing the time of a chip is provided. The method includes generating a pulse signal according to a predetermined period; capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal, representing the time information of the timer at a predetermined state of the pulse signal; and performing time synchronization for each of the timers in at least one chip based on the time snapshot of each of the timers.

[0006] According to another embodiment of the embodiments of the present disclosure, a time synchronization device for a chip is provided. The device comprises: a pulse signal generation module used to generate pulse signals according to a predetermined period; a time snapshot capture module used to capture a time snapshot of at least one timer in at least one chip representing the time information of the timer at a predetermined state of the pulse signal; and a time synchronization module used to perform time synchronization on each of the timers in at least one chip based on the time snapshot of each of the timers. In yet another embodiment of the embodiments of the present disclosure, a computer-readable storage medium is provided. The storage medium stores a computer program used to perform the time synchronization method of the chip described in any one of the embodiments of the present disclosure.

[0007] According to yet another embodiment of the embodiments of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory used for storing instructions that can be executed by the processor, wherein the processor is used to implement a time synchronization method for a chip as described in any one of the embodiments of the present disclosure by reading the instructions from the memory and executing the instructions, or the electronic device comprises a time synchronization device for a chip provided in any one of the embodiments.

[0008] According to yet another embodiment of the embodiments of the present disclosure, a computer program product is provided, and instructions within the computer program product, when executed by a processor, perform a chip time synchronization method provided by any one of the embodiments of the present disclosure. [Effects of the Invention]

[0009] According to the methods, apparatus, electronic devices, and storage media provided in the above embodiments of this disclosure, it is possible to trigger the capture of a time snapshot of at least one hardware timer in at least one chip based on a periodic pulse signal, and furthermore, to achieve time synchronization of each timer based on the time snapshot, thereby enabling time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip based on a unified time snapshot. Since the time snapshot can be captured entirely in hardware without software involvement, the occurrence of errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows one exemplary application scenario of the time synchronization method for the chip provided in this disclosure. [Figure 2] This is a schematic flowchart of a time synchronization method for a chip provided by one exemplary embodiment of the present disclosure. [Figure 3] This is a schematic flowchart of a time synchronization method for a chip provided in another exemplary embodiment of the present disclosure. [Figure 4] This figure shows time snapshots of different timers provided by one exemplary embodiment of the present disclosure. [Figure 5] This is a schematic flowchart of a time synchronization method for a chip provided in another exemplary embodiment of the present disclosure. [Figure 6] This is a schematic flowchart of a time synchronization method for a chip provided in yet another exemplary embodiment of the present disclosure. [Figure 7] This is a schematic flowchart of a time synchronization method for a chip provided in another exemplary embodiment of the present disclosure. [Figure 8] This figure shows the principle of a time synchronization method for a chip provided by one exemplary embodiment of the present disclosure. [Figure 9] This is a schematic flowchart of a time synchronization method for a chip provided in yet another exemplary embodiment of the present disclosure. [Figure 10] This is a schematic flowchart of a time synchronization method for a chip provided in another exemplary embodiment of the present disclosure. [Figure 11] This figure shows the principle of the chip time synchronization method provided by yet another exemplary embodiment of the present disclosure. [Figure 12] This figure shows the structure of a chip time synchronization device provided by one exemplary embodiment of the present disclosure. [Figure 13] This figure shows the structure of a time-synchronizing device for a chip provided by another exemplary embodiment of the present disclosure. [Figure 14] This figure shows the structure of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure. [Figure 15] This figure shows the structure of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure. [Figure 16] This figure shows the structure of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure. [Figure 17] This figure shows the structure of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure. [Figure 18] This is a configuration diagram of an electronic device according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] To explain the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is clear that the described embodiments are only some of the embodiments of the present application, not all of them. It should be understood that the present disclosure is not limited to the exemplary embodiments.

[0012] In addition, the relative arrangements, mathematical formulas, and numerical values of the components and steps described in these embodiments do not limit the scope of the present disclosure unless otherwise specified.

[0013] <Overview of the Present Disclosure> In the process of exploring this disclosure, the inventors discovered that time synchronization is fundamental to sensor data fusion in scenarios such as intelligent driving. Time synchronization typically involves two important steps: measuring time error and adjusting time. Measuring time error typically involves measuring the time difference between a slave clock and a master clock, while adjusting time typically involves achieving time synchronization between the slave clock and the master clock by compensating for the slave clock's time based on the time difference. A System on Chip (SOC) typically includes multiple hardware timers, such as a Real Time Clock (RTC), hardware timers within an Ethernet card (which may also be referred to as a network card timer), and hardware timers in a Peripheral Component Interconnect Express (PCIE) module (which may also be referred to as a PCIe timer). These hardware timers hold the time of the corresponding module. For a single chip, these hardware timers are typically distributed across one or more core domains of the chip. Each core domain may include a processor core (which may be abbreviated as "core") and at least one hardware timer corresponding to that core. The software of one processor core cannot access the hardware timers corresponding to other processor cores. When performing time synchronization using multilevel synchronization for hardware timers corresponding to multiple processor cores on a single chip, significant delays are likely to occur.

[0014] <Example Summary> FIG. 1 is a diagram showing one exemplary application scenario of the chip time synchronization method provided by the present disclosure. As shown in FIG. 1, in a scenario where it is necessary to perform time synchronization for at least one chip (SOC), such as scenarios of autonomous driving, driving assistance, etc., in FIG. 1, three chips (including SOC1, SOC2, and SOC3) are taken as an example, and each chip may include one or more core domains. FIG. 1 includes CORE1 domain, CORE2 domain, etc., and each core domain may include a core and one or more timers corresponding to the core. For example, the core domain may include a core (such as CORE1 in the figure), a network card timer, a PCIE timer, etc. According to the chip time synchronization method of the present disclosure, any one of the at least one chip (such as SOC1) generates a pulse signal according to a predetermined period, and according to the pulse signal, a time snapshot representing the time information of the timer in the predetermined state of the pulse signal of at least one timer in the at least one chip is captured, and based on the time snapshot of each timer, time synchronization can be performed for each timer in the at least one chip. According to the present disclosure, time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip can be realized based on a unified time snapshot. Since the time snapshot can be completely captured by hardware without the involvement of software, the occurrence of errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved.

[0015] The chip time synchronization method of the present disclosure is not limited to applications in intelligent driving scenarios, but is also applicable to any other scenario that requires time synchronization of other chips, and the specific scenario is not limited.

[0016] <Exemplary method> Figure 2 is a schematic flowchart of a chip time synchronization method provided by one exemplary embodiment of the present disclosure. This embodiment is applicable to electronic devices, specifically, for example, automotive computing platforms. As shown in Figure 2, the method of the embodiment of the present disclosure may include the following steps.

[0017] In step 201, a pulse signal is generated according to a predetermined period.

[0018] Here, the predetermined period may be any period. For example, the predetermined period may be 1 second, 2 seconds, 5 seconds, etc., or it may be 1 millisecond, 2 milliseconds, 4 milliseconds, etc., or it may be 1 microsecond, 2 microseconds, 4 microseconds, etc. The specific predetermined period and the time scale of the period can be set according to the actual needs.

[0019] In some preferred embodiments, the pulse signal may include a high-level (or 1) signal and a low-level (or 0) signal.

[0020] In some preferred embodiments, the pulse signal may be generated by any implementable pulse signal generation circuit. For example, the pulse signal generation circuit may be provided in any one of the timer circuits. The pulse signal generation circuit is triggered when the timer timing reaches a predetermined period, and generates a pulse signal, for example, changing a low-level signal to a high-level signal.

[0021] In some preferred embodiments, a common timer may be provided on any one of the chips, and the pulse signal may be generated by the common timer.

[0022] In some preferred examples, step 201 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by the hardware circuitry of the pulse signal generation module.

[0023] In step 202, in response to the pulse signal, a time snapshot is captured representing the time information of at least one timer in at least one chip at a predetermined state of the pulse signal.

[0024] Of these, at least one chip is a chip waiting for time-synchronized execution. The number of chips can be configured according to the actual needs. Each chip may contain at least one timer, such as the real-time clock, network card timer, or PCIe timer mentioned above.

[0025] In some preferred embodiments, for any one of the timers, the timer hardware circuitry may capture a time snapshot of the timer in response to a pulse signal. For example, the timer hardware circuitry may take a time snapshot of the timer in response to a pulse signal of a predetermined state and write the time snapshot to a register in preparation for subsequent time synchronization. The predetermined state may be the rising edge of the pulse signal, i.e., the state at which the pulse signal changes from a low level to a high level.

[0026] In some preferred examples, step 202 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by the hardware circuitry of the time snapshot capture module.

[0027] In step 203, time synchronization is performed for each timer in at least one chip based on a time snapshot of each timer.

[0028] Here, after capturing a time snapshot of each timer, time synchronization can be performed on each timer waiting for time synchronization, according to the time synchronization needs. For example, one timer, Timer A, can be designated as the master clock (or master time), and the times of the other timers, excluding Timer A, can be synchronized with Timer A. Alternatively, multiple timers can be designated as master clocks, and the other timers can be synchronized with their respective master clocks to form multiple time domains. The specific time synchronization method can be configured according to the actual needs.

[0029] In some preferred embodiments, for the time synchronization of multiple timers within a single chip, a predetermined timer within the chip may be designated as the master clock, and other timers within the chip other than the predetermined timer may be designated as slave clocks (or slave times). The time of the other timers may then be adjusted to synchronize the time of the predetermined timer with that of the other timers.

[0030] In some preferred embodiments, for time synchronization of multiple chips, each chip may include one or more timers. A predetermined chip among the multiple chips may be designated as the master chip, a predetermined timer within the master chip as the master clock, and other timers in the master chip other than the predetermined timer, as well as timers in the other chips among the multiple chips other than the predetermined chip, as slave clocks. The slave clocks may be adjusted based on the time difference between the time snapshot of the slave clocks and the time snapshot of the master clock to achieve time synchronization between the slave clocks and the master clocks. Alternatively, multiple timers within the master chip may each be designated as master clocks, and the other timers may be synchronized with their respective master clocks to form multiple time domains. For example, by designating the network card timer and PCIe timer corresponding to a predetermined core of the master chip as master clocks, synchronizing the time between the network card timer corresponding to another core within the master chip and the network card timer of other chips with the network card timer corresponding to the predetermined core of the master chip, and synchronizing the time between the PCIe timer corresponding to another core within the master chip and the PCIe timer of other chips with the PCIe timer corresponding to the predetermined core of the master chip, two time domains, a network card time domain and a PCIe time domain, can be formed. The specific number of time domains can be set according to the actual synchronization needs.

[0031] In some preferred embodiments of this disclosure, the time synchronization of timers may be achieved by the chip processor taking time snapshots of the timer as a master clock and the timer as a slave clock, and adjusting the time of the slave clock timer based on the master clock time snapshots and the slave clock time snapshots. If the chip processor includes multiple cores, the time synchronization may be achieved by each core taking time snapshots of the timer as a master clock and the timer as a slave clock corresponding to that core, and further adjusting the time of the slave clock timer according to the master clock time snapshots and the slave clock time snapshots. Preferably, the chip processor or each core within the processor can synchronize the time of the slave clock timer with the corresponding master clock timer by executing a time synchronization software program to adjust the time of the slave clock timer based on the master clock time snapshots and the slave clock time snapshots.

[0032] In some preferred examples, step 203 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a time synchronization module.

[0033] According to the chip time synchronization method provided in this embodiment, a time snapshot capture of at least one hardware timer within at least one chip is triggered based on a periodic pulse signal, and time synchronization of each timer is achieved based on the time snapshot. Therefore, time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip can be achieved based on a unified time snapshot. Since the time snapshot can be captured entirely in hardware without software involvement, the occurrence of errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved.

[0034] Figure 3 is a schematic flowchart of a chip time synchronization method provided in another exemplary embodiment of the present disclosure.

[0035] In some preferred embodiments, as shown in Figure 3, capturing a time snapshot of at least one timer in at least one chip in response to a pulse signal in step 202 may include the following steps:

[0036] In step 2021, the pulse signal is transmitted to each timer in at least one chip so that each timer responds to the pulse signal and writes a time snapshot corresponding to each timer to the corresponding register.

[0037] Here, the generated pulse signal may be transmitted to each timer within each chip, triggering each timer to capture its own time snapshot and write the time snapshot to the corresponding register.

[0038] In some preferred embodiments, pulse signals can be transmitted to each timer within each chip in any feasible manner. For example, the pulse signal output terminal of a timer generating a pulse signal may be connected to a time snapshot capture circuit for each timer on each chip. The pulse signal output terminal may be further connected to the time snapshot capture circuit of the timer generating the pulse signal. When a predetermined state appears in the pulse signal, the time snapshot capture circuit for each timer is triggered to capture the time information of that timer at the predetermined state of the pulse signal and to create a time snapshot of that timer. Each timer may also be provided with a register used to store the time snapshot of that timer, and the captured time snapshot may be written to the register for storage.

[0039] In some preferred examples, step 2021 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by hardware circuitry such as pulse signal transmission units, capture units, and registers.

[0040] In step 2022, a time snapshot of each timer is obtained from the register corresponding to each timer.

[0041] Here, the processor of each chip (or each core within the processor) may take a time snapshot of the timer as master time and a time snapshot of the timer as slave time within the processor from the register corresponding to the timer.

[0042] In some preferred embodiments, the register may be located within or outside the timer, and the register may be connected to the timer's time snapshot capture circuit so that the time snapshot capture circuit can easily write time snapshots to the register.

[0043] In some preferred examples, step 2022 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a snapshot acquisition unit executed by the processor.

[0044] In this embodiment, a pulse signal is transmitted to each timer, triggering each timer to simultaneously capture a time snapshot. Furthermore, since the time snapshot can be written to a register, it is easier to record the time information of each timer at the same time, allowing for accurate measurement of the time difference between the master and slave time timers. Additionally, because delay compensation does not need to be considered, it contributes to improved accuracy of time synchronization.

[0045] In some preferred embodiments, Figure 4 shows time snapshots of different timers provided by one exemplary embodiment of the present disclosure. As shown in Figure 4, Timer A and Timer B are two timers, where T0 is a time snapshot captured by the hardware (capture circuit) of Timer A, and T1 is a time snapshot captured by the hardware of Timer B. At the rising edge of the pulse signal (i.e., a predetermined state), the hardware of Timer A and Timer B simultaneously capture time snapshots, and the obtained T0 and T1 represent the time information of Timer A and Timer B at the same time (i.e., the rising edge of the pulse signal). The time difference can be calculated by subtracting T0 from T1 and can be used for time synchronization between Timer B and Timer A. Based on this, after capturing time snapshots of each timer, time compensation can be performed on the slave time timer by calculating the time difference between the timer as master time and the timer as slave time, according to the actual synchronization needs, thereby achieving time synchronization between the slave time timer and the master time timer.

[0046] In some preferred embodiments, taking a time snapshot of each timer from the register corresponding to each of the timers in step 2022 is: This may include detecting interrupt requests triggered based on pulse signals or registers corresponding to each timer, and, in response to detecting an interrupt request, taking a time snapshot of each timer from the registers corresponding to each timer.

[0047] Here, the processor (or each core within the processor) of each chip can detect interrupt requests. Interrupt requests may be triggered based on pulse signals, or based on registers corresponding to each of the timers. For example, a pulse signal may be transmitted to a logic device that generates an interrupt signal, which is connected to the processor (or core) and sends the interrupt signal to the processor (or core), which detects the interrupt signal and confirms the detection of the interrupt request. Alternatively, for example, an interrupt signal may be triggered when a new time snapshot is written to a register, and the processor (or core) detects the interrupt signal and confirms the detection of the interrupt request. After detecting an interrupt request, the processor may take a time snapshot of the master time timer and a time snapshot of the slave time timers within the processor. Or, each core takes a time snapshot of the master time timer and a time snapshot of the slave time timer corresponding to that core. This provides time compensation to the slave time timers within the processor and synchronizes the time between the slave time timers and the master time timers. In other words, each processor is responsible for synchronizing its own internal slave time timer with the master time timer, or each core is responsible for synchronizing its own corresponding slave time timer with the master time timer.

[0048] In some preferred embodiments, when a master time timer is located within a predetermined chip in a time synchronization situation of multiple chips, a non-predetermined chip among the multiple chips can obtain a time snapshot of the master time timer from the predetermined chip via a communication interface with the predetermined chip.

[0049] This embodiment triggers an interrupt request using a pulse signal or a register corresponding to each timer, and, upon detection of the interrupt request, acquires a timer time snapshot from the timer-corresponding register. This enables real-time and effective triggering of time synchronization, ensures that accurate and valid time snapshots can be acquired, and improves the reliability of time synchronization by avoiding the acquisition of incorrect time snapshots due to the failure to capture new time snapshots.

[0050] Figure 5 is a schematic flowchart of a chip time synchronization method provided in another exemplary embodiment of the present disclosure.

[0051] In some preferred embodiments, as shown in Figure 5, performing time synchronization for each timer in at least one chip based on a time snapshot of each timer in step 203 may include the following steps.

[0052] In step 2031, a first time difference between the other timers and the first predetermined timer is determined based on a time snapshot of the first predetermined timer among the timers and time snapshots of the other timers among the timers other than the first predetermined timer.

[0053] Here, the first predetermined timer may be a predetermined timer set in advance as a master timer. The other timers are timers as slave timers. The number of other timers may be one or more.

[0054] In some preferred embodiments, in the case of time synchronization of a single chip, if the processor of the chip is a single-core processor, the processor of the chip takes time snapshots of a first predetermined timer and time snapshots of other timers, calculates the time difference between the time snapshots of the other timers and the time snapshots of the first predetermined timer, and sets this as the first time difference between the other timers and the first predetermined timer. If the chip processor includes multiple cores, each core takes a time snapshot of the first predetermined timer and a time snapshot of other timers corresponding to that core, and determines the first time difference between the other timers corresponding to that core and the first predetermined timer.

[0055] In some preferred embodiments, in the case of time synchronization of multiple chips, each chip determines a first time difference between other timers within the chip and the first predetermined timer, according to the method of the embodiments (including the single-core and multi-core cases as described above). Of course, for a predetermined chip where the first predetermined timer is located, the predetermined chip can directly take a time snapshot of the first predetermined timer. For chips that do not contain the first predetermined timer, the chip may take a time snapshot of the first predetermined timer from the predetermined chip via a communication interface with the predetermined chip containing the first predetermined timer. For example, after capturing a time snapshot, the predetermined chip may transmit the time snapshot of the first predetermined timer to other chips via the communication interface.

[0056] In some preferred examples, step 2031 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a time-delay decision unit.

[0057] In step 2032, the time of the other timers is synchronized with the first predetermined timer by performing time compensation on the other timers based on the first time difference.

[0058] Each of these other timers may have a corresponding first time difference. Time compensation may be performed on any one of the other timers based on the first time difference corresponding to that other timer. Since the first time difference represents the time difference between the other timer and the first predetermined timer, by performing time compensation on the other timer based on the first time difference, the difference between the other timer and the first predetermined timer can be eliminated or reduced, thereby achieving the purpose of time synchronization.

[0059] In some preferred examples, step 2032 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a time compensation unit.

[0060] This embodiment calculates a first time difference between a time snapshot of another timer and a time snapshot of a first predetermined timer, and performs time compensation on the other timer based on this first time difference, thereby synchronizing the time between the other timer and the first predetermined timer. Since the first time difference is calculated based on time snapshots of the two timers at the same time, the accuracy of the first time difference is high, and the accuracy of time synchronization between the other timer and the first predetermined timer can be improved.

[0061] In some preferred embodiments, in step 2031, determining the first time difference between the other timers and the first predetermined timer based on a time snapshot of the first predetermined timer among the timers and time snapshots of the other timers other than the first predetermined timer is: The method may include: designating each of the at least one chips as a target chip, determining a first time difference between the other timers and the first predetermined timer based on time snapshots of other timers in the target chip other than the first predetermined timer, depending on whether the target chip includes the first predetermined timer; transmitting the time snapshot of the first predetermined timer to the other chips other than the target chip among the at least one chips; and receiving a time snapshot of the first predetermined timer from a chip including the first predetermined timer, depending on whether the target chip does not include the first predetermined timer, and determining a first time difference between each timer and the first predetermined timer based on the time snapshot of the first predetermined timer and the time snapshots of each timer in the target chip.

[0062] Here, for each of the at least one chips, if the chip is designated as the target chip and the target chip includes a first predetermined timer, the first time difference between the other timers and the first predetermined timer may be calculated based on the time snapshots of the other timers in the target chip and the time snapshot of the first predetermined timer. Specifically, for any one of the other timers, the first time difference may be the difference between the time snapshot of the first predetermined timer and the time snapshot of that other timer, or the difference between the time snapshot of that other timer and the time snapshot of the first predetermined timer; the method is not specifically limited. Furthermore, after capturing a time snapshot, the target chip may transmit the time snapshot of the first predetermined timer to the other chips other than the target chip, thereby causing the other chips to synchronize the time of the first predetermined timer with the timers in those chips, using the first predetermined timer as the master time timer. Specifically, the target chip may transmit the time snapshot of the first predetermined timer to the other chips via a communication interface with the other chips. The communication interface may be any available interface, such as a synchronous serial bus interface (Serial Peripheral Interface: SPI), a bidirectional bus interface (Inter IC: I2C), a CAN interface, a universal asynchronous receiver-transmitter (UART), or Ethernet. Specifically, it can be flexibly configured according to the actual needs.If the target chip includes multiple cores and the first predetermined timer is one timer corresponding to a predetermined core among the multiple cores, each core may be designated as a target core. If the timers corresponding to the target cores include the first predetermined timer, the first time difference between the other timers and the first predetermined timer may be determined based on time snapshots of the other timers corresponding to the target cores and the time snapshot of the first predetermined timer. If the timers corresponding to the target cores do not include the first predetermined timer, the time snapshot of the first predetermined timer may be received from the predetermined core, and the first time difference between each timer corresponding to the target core and the first predetermined timer may be calculated based on the time snapshots of each timer corresponding to the target core and the time snapshot of the first predetermined timer. The target core may obtain the first time difference of the first predetermined timer from the predetermined core via inter-core communication. If the first predetermined timer is a common timer other than that of multiple cores in the target chip, each core in the target chip may access the common timer and take a time snapshot of the first predetermined timer, and each core may calculate a first time difference between each timer corresponding to that core and the first predetermined timer based on the time snapshots of the timers corresponding to that core and the time snapshot of the first predetermined timer.

[0063] If the target chip does not include the first predetermined timer, the target chip may receive a time snapshot of the first predetermined timer from a chip that includes the first predetermined timer. The target chip may determine a first time difference between each timer in the target chip and the first predetermined timer based on the time snapshot of the first predetermined timer and the time snapshots of each timer in the target chip. Similarly, if the target chip includes multiple cores, each core may determine a first time difference between each timer corresponding to that core and the first predetermined timer based on the time snapshot of the first predetermined timer and the time snapshot of each timer corresponding to that core.

[0064] According to this embodiment, time synchronization between multiple chips can be achieved. Furthermore, since the time synchronization of each timer on multiple chips is achieved based on time snapshots of each timer at the same time, and the accuracy of the first time difference calculated is high, it contributes to improving the accuracy of multi-chip time synchronization.

[0065] Figure 6 is a schematic flowchart of a chip time synchronization method provided in yet another exemplary embodiment of the present disclosure.

[0066] In some preferred embodiments, each of the at least one chip may include at least one processor core, and each of the processor cores may correspond to at least one timer.

[0067] In some preferred embodiments, as shown in Figure 6, in step 201, generating a pulse signal according to a predetermined period is performed as follows: The step 2011 may include a common timer within a predetermined chip, at least one of the chips, which generates a pulse signal according to a predetermined period.

[0068] Of these, the predetermined chip can be configured according to actual needs. The predetermined chip may be provided with a common timer, and the common timer may include a pulse signal generation circuit, which is responsible for generating pulse signals according to a predetermined period.

[0069] In some preferred embodiments, a common timer may be connected to each timer in a given chip and each timer in another chip, and may transmit pulse signals to each timer so that each timer is triggered to capture a time snapshot of the timer at a predetermined state of the pulse signal.

[0070] In some preferred embodiments, a common timer may be connected to each timer via a transmission line. Specifically, the pulse signal output terminal of the common timer may be connected to a time snapshot capture circuit for each timer, thereby triggering the time snapshot capture circuit for the timer. The common timer may further trigger the capture of a time snapshot of the common timer by transmitting a pulse signal to the time snapshot capture circuit for the common timer.

[0071] In some preferred embodiments, the pulse signal of the common timer may be transmitted to other chips via a connection between a pin on one chip and a pin on another chip.

[0072] In some preferred examples, step 2011 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a common timer in a given chip of at least one chip.

[0073] In step 202, capturing a time snapshot of at least one timer in at least one chip in response to a pulse signal may include the following steps:

[0074] In step 202a, each of the at least one chips is designated as a target chip, and depending on whether the target chip is a predetermined chip, the target chip captures a time snapshot of at least one timer corresponding to at least one processor core within the target chip and a time snapshot of a common timer in response to a pulse signal.

[0075] Of these, the predetermined chip is a chip that includes a common timer. When the target chip is the predetermined chip, the target chip can capture time snapshots of each timer corresponding to each core within the target chip, and a time snapshot of the common timer, in response to pulse signals. Specifically, a time snapshot capture circuit for each timer corresponding to each core within the target chip may capture a time snapshot of that timer in response to pulse signals. A time snapshot capture circuit for the common timer captures a time snapshot of the common timer in response to pulse signals.

[0076] In some preferred embodiments, the common timer may be located outside the core within a given chip, or within a given core (i.e., a given processor core) within the given chip. When the common timer is located outside the core, any of the cores within the given chip can access the common timer and take a time snapshot of the common timer. In this case, access rights for each core to the common timer can be set. For example, only write and read access to the common timer may be permitted for a given core, while only read access to the common timer may be permitted for other cores. That is, a given core can read a time snapshot of the common timer and perform time compensation on the common timer to synchronize the common timer with any timer corresponding to that given core. By setting access rights for each core to the common timer, the time reliability of the common timer can be guaranteed, and time instability of the common timer due to write access to the common timer by different cores can be avoided. When the common timer is located within a given core, a given core can perform read / write access to the common timer, while other cores can only perform read access to the common timer, for example, by reading a time snapshot of the common timer via inter-core communication, or by other means. Alternatively, the common timer may be located outside each core domain within the predetermined chip, for example, outside each domain of SOC1 in Figure 1, and access rights for each core of SOC1 to the common timer may be set. Alternatively, the common timer may be located within a predetermined core domain of the predetermined chip, for example, within the CORE1 domain of SOC1 in Figure 1, so that a predetermined core within the predetermined core domain can perform write and read access to the common timer, while other cores can only perform read access to the common timer.

[0077] In some preferred examples, step 202a may be performed by the processor calling a corresponding instruction stored in memory, and may be implemented by a first capture unit corresponding to each timer in a given chip and a second capture unit corresponding to a common timer.

[0078] The time synchronization for each timer in at least one chip based on a time snapshot of each timer in step 203 may include the following steps:

[0079] In step 2031a, a second time difference between the common timer and the second predetermined timer is determined based on a time snapshot of a second predetermined timer corresponding to a predetermined processor core in the target chip and a time snapshot of the common timer.

[0080] Of these, the predetermined processor core and the second predetermined timer can be set to any core and any corresponding timer according to the actual chip time synchronization needs. For example, the predetermined processor core may be CORE1 in Figure 1, and the second predetermined timer may be the network card timer corresponding to CORE1 in the CORE1 domain in Figure 1. Based on the time snapshot of the second predetermined timer and the time snapshot of the common timer, the time difference between the common timer and the second predetermined timer can be calculated and used as the second time difference between the common timer and the second predetermined timer. For example, the difference between the time snapshot of the common timer and the time snapshot of the second predetermined timer may be used as the second time difference.

[0081] In some preferred examples, step 2031a may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a first time difference determination unit in a given chip.

[0082] In step 2032a, the common timer and the second predetermined timer are synchronized by performing time compensation on the common timer based on the second time difference.

[0083] Here, after obtaining a second time difference between the common timer and the second predetermined timer, time compensation is performed on the common timer based on the second time difference. This eliminates or reduces the time difference between the common timer and the second predetermined timer, thereby synchronizing the times of the common timer and the second predetermined timer.

[0084] In some preferred embodiments, if the second time difference is the difference between the time snapshot of the common timer and the time snapshot of the second predetermined timer, the difference may be a positive or negative value, and the time obtained by subtracting the second time difference from the time of the common timer may be the compensated time of the common timer. If the second time difference is the difference between the time snapshot of the second predetermined timer and the time snapshot of the common timer, the time obtained by adding the second time difference to the time of the common timer may be the compensated time of the common timer. For example, if the time snapshot of the common timer is 500 microseconds, the time snapshot of the second predetermined timer is 800 microseconds, and the second time difference is 300 microseconds, the time of the common timer and the second predetermined timer are synchronized by compensating the real time of the common timer by 300 microseconds. For example, when performing time compensation, if the real time of the second predetermined timer is 1000 microseconds and the real time of the common timer is 700 microseconds, the time of the common timer and the second predetermined timer are synchronized by compensating the real time of the common timer by 300 microseconds, making the real time of the common timer 1000 microseconds. In actual applications, differences in the timer hardware circuitry can cause changes in the difference between the real-time time of the common timer and the real-time time of the second predetermined timer, as well as the difference between time snapshots, between the capture of a time snapshot and the time compensation for the common timer. For example, when performing time compensation, the real-time time of the second predetermined timer may be 1000 microseconds, while the real-time time of the common timer may be 650 microseconds. Therefore, in this time compensation, the difference between the common timer and the second predetermined timer can be reduced by compensating the common timer by 300 microseconds so that the real-time time of the common timer becomes 950 microseconds. The remaining 50 microsecond difference can be continuously reduced by the next time synchronization and subsequent time synchronizations. In this way, time synchronization between the common timer and the second predetermined timer is achieved through multiple time synchronizations.In practical applications, the time snapshot is not limited to the microsecond order as described above, but may also be on other time orders such as nanoseconds.

[0085] In some preferred examples, step 2032a may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a first time compensation unit in a given chip.

[0086] In step 2033a, time compensation is performed on the time snapshot of the common timer based on the second time difference to obtain the compensated time snapshot of the common timer.

[0087] Here, the principle of time compensation for the time snapshot of the common timer is similar to the real-time compensation principle described above, and therefore will not be explained here. For example, the sum of the time snapshot of the common timer and the second time difference may be taken as the compensated time snapshot of the common timer. Alternatively, the time snapshot of the second predetermined timer may be taken as the compensated time snapshot of the common timer.

[0088] In some preferred examples, step 2033a may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a second time difference determination unit in a given chip.

[0089] In step 2034a, a third time difference is determined between each of the other timers and the common timer, based on time snapshots of the other timers in the target chip other than the second predetermined timer and the compensated time snapshot of the common timer.

[0090] Here, for any one of the other timers, the third time difference between that other timer and the compensated common timer (which may be called the third compensated time difference) may be determined directly based on the time snapshot of that other timer and the compensated time snapshot of the common timer. Each of the other timers may correspond to one third time difference.

[0091] In some preferred examples, step 2034a may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a second time difference determination unit in a given chip.

[0092] In step 2035a, time compensation is performed on each of the other timers based on the third time difference corresponding to each of the other timers, thereby synchronizing the time of each other timer with the time-compensated common timer.

[0093] Here, the specific operation of performing time compensation on any one other timer based on a third time difference corresponding to that other timer is similar to the specific operation of performing time compensation on the common timer as described above, so it will not be explained here. For example, if the time snapshot of the common timer is 500 microseconds, the time snapshot of the second predetermined timer is 800 microseconds, and the second time difference is 300 microseconds, then 300 microseconds are compensated for the time snapshot of the common timer to obtain a compensated time snapshot of 800 microseconds. If the time snapshot of other timer B is 600 microseconds, and the third time difference between the time snapshot of other timer B and the compensated time snapshot of the common timer is 200 microseconds, then 200 microseconds are compensated for the real time of the other timer to eliminate or reduce the time difference between the other timer and the compensated common timer, and furthermore, the time difference between the other timer and the second predetermined timer is eliminated or reduced.

[0094] In some preferred examples, step 2035a may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a second time compensation unit in a given chip.

[0095] Note that steps 2033a through 2035a and step 2032a can be executed in any order.

[0096] In this embodiment, time compensation is performed on the common timer by a second time difference between the common timer and a second predetermined timer, thereby achieving time synchronization between the common timer and the second predetermined timer. Furthermore, by determining a third time difference between other timers and the common timer based on time snapshots of other timers and the compensated time snapshot of the common timer, and using this for time compensation to the other timers, the difference between the real time of the other timers and the real time of the compensated common timer can be eliminated or reduced, thereby reducing the difference between the real time of the other timers and the real time of the second predetermined timer. Time synchronization between other timers and the second predetermined timer is achieved by the common timer, and since the time synchronization is achieved based on time snapshots of the same time captured by hardware, it is less affected by software delays and the synchronization accuracy is high. In addition, this embodiment can achieve accurate and effective time synchronization between timers corresponding to multiple cores of multiple chips using the common timer, and compared to conventional multi-stage synchronization which tends to generate large delays, this embodiment can significantly reduce the delays and measurement errors that occur.

[0097] Figure 7 is a schematic flowchart of a chip time synchronization method provided in another exemplary embodiment of the present disclosure.

[0098] In some preferred embodiments, as shown in Figure 7, performing time synchronization for each timer in at least one chip based on a time snapshot of each timer in step 203 may include the following steps.

[0099] In step 2031a, a second time difference between the common timer and the second predetermined timer is determined based on a time snapshot of a second predetermined timer corresponding to a predetermined processor core in the target chip and a time snapshot of the common timer.

[0100] In step 2032a, the common timer and the second predetermined timer are synchronized by performing time compensation on the common timer based on the second time difference.

[0101] For specific details of the operations in steps 2031a and 2032a in this embodiment, refer to the embodiment described above.

[0102] In step 2033b, a third time difference is determined between each of the other timers and the common timer, based on the time snapshots of each other timer and the common timer.

[0103] Here, for any one other timer, the difference between the time snapshot of that other timer and the time snapshot of the common timer can be defined as the third time difference between that other timer and the common timer (which may also be called the third snapshot time difference).

[0104] In some preferred examples, step 2033b may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a second time difference determination unit in a given chip.

[0105] In step 2034b, time compensation is performed on each of the other timers based on the second and third time differences, thereby synchronizing the time of each other timer with the time-compensated common timer.

[0106] Here, the second time difference represents the difference between the time snapshot of the common timer and the time snapshot of the second predetermined timer, and for any one other timer, the third time difference represents the difference between the time snapshot of the other timer and the time snapshot of the common timer. By performing time compensation on the other timer based on the second and third time differences, the time difference between the other timer and the second predetermined timer can be compensated, and the times of the other timer and the second predetermined timer can be synchronized. For example, if the time snapshot of the common timer is 500 microseconds, the time snapshot of the second predetermined timer is 800 microseconds, the second time difference is 300 microseconds, the time snapshot of other timer B is 600 microseconds, and the third time difference between the time snapshot of other timer B and the time snapshot of the common timer is -100 microseconds, then by compensating the real time of the other timer by 200 (=300-100) microseconds, the difference between the compensated real time of the other timer and the real time of the second predetermined timer can be significantly reduced.

[0107] In some preferred examples, step 2034b may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a second time compensation unit in a given chip.

[0108] According to this embodiment, a third time difference between the other timer and the common timer is calculated based on the time snapshots of the other timer and the common timer. This third difference is then combined with the second time difference between the common timer and the second predetermined timer to perform time compensation on the other timer. This effectively eliminates or reduces the time difference between the other timer and the second predetermined timer, thereby achieving time synchronization between the other timer and the second predetermined timer and improving the accuracy of time synchronization.

[0109] In some preferred embodiments, after determining a third time difference between each of the other timers and the common timer based on the time snapshots of each other timer and the common timer, time compensation may be further performed on the other timers based on the third time difference. Thus, in this time synchronization, only the difference in time snapshots between the other timers and the common timer is compensated, and the second time difference between the common timer and the second predetermined timer is not compensated in this instance, but may be compensated in the next time synchronization. In this way, the difference between the other timers and the second predetermined timer can also be continuously reduced by periodic time synchronization. For example, if the time snapshot of the common timer is 600 microseconds, the time snapshot of the second predetermined timer is 800 microseconds, and the second time difference is 200 microseconds, then 200 microseconds of compensation is applied to the real time of the common timer. The time snapshot of other timer B is 500 microseconds, the third time difference between the time snapshot of other timer B and the time snapshot of the common timer is 100 microseconds, and the time difference in time snapshots between other timer B and the second predetermined timer is 300 microseconds. By compensating the real-time time of the other timer by 100 microseconds, the difference in real-time between the other timer and the second predetermined timer can be reduced by 100 microseconds. At the next time synchronization, the time snapshot of the second predetermined timer captured will be, for example, 1800 microseconds. Since time compensation was performed on the common timer during the previous time synchronization, the difference between the time snapshot of the common timer captured this time and the time snapshot of the second predetermined timer will be significantly reduced compared to the previous time. For example, the time snapshot of the common timer may be 1750 microseconds, and the difference between the time snapshot of the other timer B and the time snapshot of the common timer will include the compensated second time difference of the common timer from the previous time.Therefore, the difference in time snapshots between the other timer B and the common timer in this case may be larger than in the previous case. For example, if the time snapshot of the other timer B is 1580, then in this time synchronization, the second time difference between the common timer and the second predetermined timer is 50 microseconds, the third time difference between the time snapshot of the other timer B and the time snapshot of the common timer is 170 microseconds, and the time snapshot difference between the other timer B and the second predetermined timer is 220 microseconds, compensating the common timer by 50 microseconds and the other timer B by 170 microseconds. As can be seen from this, the real-time difference between the other timer B and the second predetermined timer is gradually decreasing, and time synchronization between the other timer B and the second predetermined timer can be gradually achieved through periodic and multiple time synchronizations.

[0110] In some preferred embodiments, Figure 8 shows the principle of a time synchronization method for a chip provided by one exemplary embodiment of the present disclosure. As shown in Figure 8, an example is shown in which at least one chip comprises two chips, SOC1 and SOC2, and each chip comprises two core domains, the CORE1 domain and the CORE2 domain. Each core domain comprises a core (not shown, see Figure 1) and a plurality of timers corresponding to that core. SOC1 is a predetermined chip, and a second predetermined timer is a network card timer (i.e., a network card timer in the CORE1 domain) corresponding to CORE1 (which is a predetermined core) of SOC1, and SOC1 includes a common timer, which generates a pulse signal at a predetermined period and transmits it via a transmission channel to each timer corresponding to each core of SOC1 and each timer corresponding to each core of SOC2, and the pulse signal may be transmitted to the common timer itself, specifically to a time snapshot capture circuit of the common timer. When the pulse signal is in a predetermined state, each timer on each chip (including the common timer and the timers corresponding to each core) is triggered to capture a time snapshot of the timer. Each core of SOC1 may access the common timer and capture a time snapshot of the common timer. Here, CORE1 of SOC1 may determine a second time difference between the common timer and the second predetermined timer based on the time snapshot of the common timer and the time snapshot of a second predetermined timer (network card timer), and synchronize the times of the common timer and the second predetermined timer by performing time compensation on the common timer according to the second time difference. CORE1 of SOC1 may synchronize the time of other timers other than the second predetermined timer with the common timer, or it may directly synchronize the time of other timers with the second predetermined timer. Each core of SOC1's CORE2 may determine a third time difference between each other timer and the common timer based on the time snapshot of each timer corresponding to the core (also referred to as other timers) and the time snapshot of the common timer, and synchronize the times of other timers and the common timer by performing time compensation on the other timers according to the third time difference.Alternatively, CORE1 may transmit a second time difference to CORE2, and CORE2 may synchronize the time between the other timers corresponding to CORE2 and the second predetermined timer by performing time compensation on the other timers corresponding to CORE2 based on the second and third time differences. Alternatively, CORE1 may transmit a time snapshot of the common timer after compensation to CORE2, and CORE2 may determine a third time difference based on the time snapshot of the common timer after compensation and the time snapshot of the other timers corresponding to CORE2, and perform time compensation on the other timers. After capturing a time snapshot, SOC1 may further transmit a time snapshot of the common timer or a time snapshot of the common timer after compensation to SOC2 via a communication interface with SOC2, and each core of SOC2 may acquire a time snapshot of the common timer or a time snapshot of the common timer after compensation via the communication interface and perform time compensation on the timer corresponding to the core, thereby achieving time synchronization between the timer corresponding to the core and the common timer or the compensated common timer, and achieving the objective of time synchronization with the second predetermined timer.

[0111] Figure 9 is a schematic flowchart of a chip time synchronization method provided in yet another exemplary embodiment of the present disclosure.

[0112] In some preferred embodiments, as shown in Figure 9, after capturing a time snapshot of at least one timer corresponding to at least one processor core in the target chip and a time snapshot of a common timer in step 202a, The step 301 may further include transmitting a compensated time snapshot of the common timer to at least one chip other than the designated chip.

[0113] Here, if the target chip is a predetermined chip, the target chip may transmit a time snapshot after compensation of the common timer to another chip. The other chip is, for example, SOC2 in Figure 8 above. The target chip may transmit a time snapshot after compensation of the common timer to the other chip via a communication interface with the other chip.

[0114] In some preferred examples, step 301 may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a first transmission unit.

[0115] In step 202, capturing a time snapshot of at least one timer in at least one chip in response to a pulse signal is: Depending on whether the target chip is a predetermined chip, the target chip may further include step 202b, which captures a time snapshot of at least one timer corresponding to at least one processor core within the target chip in response to a pulse signal, and also obtains a compensated time snapshot of a common timer from the predetermined chip.

[0116] If the target chip is not the predetermined chip, the pulse signal generated by the common timer in the predetermined chip is transmitted to each timer on the target chip. Each timer on the target chip captures a time snapshot of its timer in response to the pulse signal. The target chip may also obtain a compensated time snapshot of the common timer from the predetermined chip via a communication interface.

[0117] In some preferred examples, step 202b may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a third capture unit and a first acquisition unit corresponding to each timer in the other chip.

[0118] In step 203, time synchronization is performed for each timer in at least one chip based on the time snapshot of each timer. The process may further include step 2031c, which determines a fourth time difference between each timer and the common timer based on time snapshots of each timer in the target chip and a compensated time snapshot of the common timer.

[0119] Here, for any one timer in the target chip, the specific operation for determining the fourth time difference between that timer and the common timer based on the time snapshot of that timer and the compensated time snapshot of the common timer can refer to the third time difference (third compensated time difference) in the embodiment described above.

[0120] In some preferred examples, step 2031c may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a third time-determination unit in another chip.

[0121] In step 2032c, time compensation is performed on each timer based on the fourth time difference corresponding to each timer, thereby synchronizing the time of each timer with the time-compensated common timer.

[0122] The specific operation of time compensation can be found in the examples described above, so we will omit the explanation here.

[0123] In some preferred examples, step 2032c may be performed by the processor calling a corresponding instruction stored in memory, or it may be implemented by a third time compensation unit in another chip.

[0124] This embodiment achieves the objective of time synchronization between the timer on the target chip and a second predetermined timer on the predetermined chip by acquiring a time snapshot of the common timer after compensation from the predetermined chip for a target chip that is not one of the predetermined chips, and further performing time synchronization between the timer in the target chip and the time after compensation from the common timer. This enables time synchronization of timers corresponding to multi-chip multi-core systems and improves the accuracy of time synchronization.

[0125] Figure 10 is a schematic flowchart of a chip time synchronization method provided in another exemplary embodiment of the present disclosure.

[0126] In some preferred embodiments, as shown in Figure 10, performing time synchronization for each timer in at least one chip based on a time snapshot of each timer in step 203 may include the following steps.

[0127] In step 2031d, each of the chips among at least one chip is designated as a target chip.

[0128] In step 2032d, depending on whether the target chip is a predetermined chip, a time snapshot of the target chip's third predetermined timer is transmitted to a first other chip other than the predetermined chip among at least one chip, and a time snapshot of the target chip's common timer is transmitted to a second other chip other than the predetermined chip among at least one chip, wherein the third predetermined timer is a timer as a reference time, and the predetermined chip is a chip that includes the third predetermined timer.

[0129] Here, the predetermined chip and the third predetermined timer may be set as any timer within any chip among at least one of the chips. For example, in Figure 8 above, the predetermined chip may be SOC1, and the third predetermined timer may be a network card timer. The first other chip may include one or more other chips other than the predetermined chip. The first other chip may be a chip waiting for time synchronization execution with the third predetermined timer. The second other chip may be a chip waiting for time synchronization execution with a common timer. The second other chip may include one or more chips. The second other chip may or may not be the same chip as the first other chip. Specifically, it can be set according to the needs of the time domain. For example, the third predetermined timer may be a network card timer in the CORE1 domain of SOC1, and the network card timer of each chip may be formed as one time domain, and the other timers and the common timer may be formed as separate time domains. In this case, the first other chip is another chip containing a network card timer, and the second other chip is another chip containing another timer. If each chip contains a network card timer and other timers, then the first other chip and the second other chip are the same chip.

[0130] In some preferred embodiments, when the target chip is a predetermined chip, the target chip can synchronize the time between the fourth predetermined timer and the third predetermined timer by transmitting a time snapshot of the target chip's third predetermined timer to a first other chip, thereby allowing the first other chip to perform time compensation on an internal timer (fourth predetermined timer) waiting to perform time synchronization with the third predetermined timer. The target chip can also synchronize the time between the fifth predetermined timer and the common timer by transmitting a time snapshot of a common timer to a second other chip, thereby allowing the second other chip to perform time compensation on an internal timer (fifth predetermined timer) waiting to perform time synchronization with the common timer. Thus, two time domains can be formed across multiple chips.

[0131] In some preferred embodiments, the third predetermined timer and the common timer may be provided on different chips.

[0132] In some preferred embodiments, more time domains may be provided depending on the actual needs.

[0133] In some preferred embodiments, the target chip can further perform time compensation to other timers waiting to perform time synchronization with a third predetermined timer within the target chip, thereby achieving time synchronization between these other timers and the third predetermined timer. The target chip can further perform time compensation to other timers waiting to perform time synchronization with a common timer within the target chip, thereby achieving time synchronization between these other timers and the common timer. For example, the third predetermined timer is a network card timer in the CORE1 domain of SOC1 in Figure 8, and SOC1 may perform time synchronization between the network card timer in the CORE2 domain of SOC1 and the third predetermined timer, and also perform time synchronization between timers other than the network card timer and the common timer in the CORE1 and CORE2 domains.

[0134] In step 2033d, depending on whether the target chip is a first other chip, a fifth time difference between the fourth predetermined timer and the third predetermined timer is determined based on a time snapshot of the third predetermined timer and a time snapshot of the fourth predetermined timer in the target chip, and the times of the fourth predetermined timer and the third predetermined timer are synchronized by performing time compensation on the fourth predetermined timer based on the fifth time difference.

[0135] Of these, the fourth predetermined timer may include one or more timers. For example, the fourth predetermined timer is the network card timer in each core domain of the SOC2 in Figure 8. The specific operation of determining the fifth time difference and time compensation for the fourth predetermined timer can be found in the embodiments described above, so it will not be explained here.

[0136] In step 2034d, depending on whether the target chip is a second other chip, a sixth time difference between the fifth predetermined timer and the common timer is determined based on a time snapshot of the common timer and a time snapshot of the fifth predetermined timer in the target chip, and the times of the fifth predetermined timer and the common timer are synchronized by performing time compensation on the fifth predetermined timer based on the sixth time difference.

[0137] Of these, the fifth predetermined timer may include one or more timers. For example, the fifth predetermined timer may include other timers other than the network card timer in each core domain of SOC2 in Figure 8. The specific operation of determining the sixth time difference and time compensation for the fifth predetermined timer can be found in the embodiments described above, so it will not be explained here.

[0138] In some preferred embodiments, one or more timers included in each core domain may be located within the core included in that core domain. That is, each core domain includes a core, and each core includes one or more timers corresponding to that core. For example, in Figure 8, the network card timer, PCIe timer, etc., in each domain may be timers located within a core. The specific relationship between the core and the timers is not limited.

[0139] In some preferred examples, steps 2031d to 2034d described above may be performed by the processor calling corresponding instructions stored in memory, or they may be implemented by corresponding units included in the time synchronization module 53.

[0140] This embodiment can achieve time synchronization of multiple time domains on at least one chip, and is useful in meeting different time synchronization needs.

[0141] In some preferred embodiments, Figure 11 shows the principle of a time synchronization method for a chip provided by yet another exemplary embodiment of the present disclosure. As shown in Figure 11, at least one chip comprises three chips, SOC1, SOC2, and SOC3, where SOC1 is a predetermined chip, and SOC2 and SOC3 are a first other chip and a second other chip. To enable the transmission of time snapshots, SOC1, SOC2, and SOC3 are connected via a communication interface. SOC1 includes a common timer, which may transmit pulse signals it generates to each timer corresponding to each core (not shown) in each core domain of each chip (e.g., CORE1 domain, CORE2 domain, CORE3 domain), where each timer may be triggered to capture a time snapshot of that timer under predetermined conditions of the pulse signal. After capturing a time snapshot, SOC1 may transmit a time snapshot of the network card timer corresponding to CORE1 to SOC2 and SOC3. SOC2 and SOC3 then perform time compensation on their network card timers based on the time snapshot transmitted by SOC1, synchronizing all network card timers with the network card timer of CORE1 in SOC1, thereby forming a network card time domain. SOC1 may also transmit a time snapshot of a common timer to SOC2 and SOC3. SOC2 and SOC3 then perform time compensation on other timers in SOC2 and SOC3, other than the network card timers, based on the time snapshot transmitted by SOC1, thereby synchronizing each other timer with the common timer and forming a common time domain. As a result, two time domains are formed on the three chips.

[0142] In some preferred embodiments, other chips besides the predetermined chip may include common timers (which may also be referred to as other common timers), and pulse signals generated by the predetermined chip's common timers may be transmitted to the other common timers on the other chips to cause the other common timers on the other chips to capture time snapshots, thereby facilitating time synchronization between the other common timers on the other chips and the predetermined chip's common timers. For example, in Figure 11, both SOC2 and SOC3 may include other common timers (see the configuration of the common timer of SOC1), and the pulse signal output terminal of the common timer of SOC1 is connected to the other common timers of SOC2 and SOC3.

[0143] In some preferred embodiments, if any other chip besides the predetermined chip includes other common timers, the other chip may further synchronize each of its internal timers with other common timers within that chip, thereby achieving the objective of time synchronization between each timer within the other chip and the common timer of the predetermined chip, and further achieving the objective of time synchronization with the predetermined timer within the predetermined chip. Alternatively, the other common timers of the other chip are used for time synchronization of the timers within that other chip. The specific synchronization principle can be found in the embodiments described above, so it will not be explained here.

[0144] According to the chip time synchronization method provided in the embodiments of this disclosure, a common timer is provided within the chip to support the generation of pulse signals, and each hardware timer within the chip (including the common timer and other timers) can receive these pulse signals. The pulse signals allow the timer hardware to automatically record time snapshots of the timers, and, according to the time snapshot, synchronize the common timer with any one time within the chip, and then other timers within the chip can synchronize with the common timer. Since this process does not require inter-core communication, communication time can be reduced. Next, the pulse signal of the common timer may be transmitted to other chips via a pin on the chip, triggering the other chips to capture time snapshots of their timers. Furthermore, the time snapshot of the common timer may be transmitted to other chips via an inter-chip communication interface, facilitating time synchronization between the timers of other chips and the common timer. This enables time synchronization within a chip and between different chips. Additionally, the consistent time difference measurement method for time synchronization within a chip and between different chips contributes to simplifying the software architecture of time synchronization. Furthermore, since there is no need to trigger the capture of time snapshots at the same time using pulse signals, calculate the time difference from the time snapshots, and perform delay compensation, the accuracy of the time difference can be significantly improved as it is not affected by delays caused by software processing. In addition, according to the method of the embodiment of this disclosure, the inter-chip communication interface can support the transmission of time snapshots via any communication interface, which contributes to improving the suitability of the method according to the embodiment of this disclosure.

[0145] Each of the embodiments described herein may be implemented individually or in any combination that is not inconsistent, and may be specifically configured according to the actual needs, and the embodiments described herein are not limited thereto.

[0146] Any chip time synchronization method provided by the embodiments of this disclosure may be performed by any suitable device having data processing capabilities, including but not limited to terminal devices and servers. Alternatively, any chip time synchronization method provided by the embodiments of this disclosure may be performed by a processor. For example, a processor may perform any chip time synchronization method referred to in the embodiments of this disclosure by calling a corresponding instruction stored in memory. Further explanation is omitted below.

[0147] It will be understood by those skilled in the art that all or part of the steps of the above-described method embodiment can be achieved by instructing the relevant hardware through a program, and that the above-described program may be stored in a computer-readable storage medium, and that when this program is executed, the steps of the above-described method embodiment will be performed. On the other hand, the above-described storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0148] <Example device> Figure 12 shows the structure of a chip time synchronization device provided by one exemplary embodiment of the present disclosure. The chip time synchronization device of this embodiment may be used to implement an embodiment of a corresponding chip time synchronization method of the present disclosure. The device shown in Figure 12 may include a pulse signal generation module 51, a time snapshot capture module 52, and a time synchronization module 53.

[0149] The pulse signal generation module 51 is used to generate pulse signals according to a predetermined period.

[0150] Here, the pulse signal generation module 51 may be a pulse signal generation circuit, such as a pulse signal generation circuit provided in a timer (e.g., a common timer), or a pulse signal generation circuit connected to a timer.

[0151] The time snapshot capture module 52 is used to capture a time snapshot representing the time information of at least one timer in at least one chip at a predetermined state of the pulse signal, in response to the pulse signal.

[0152] Here, the time snapshot capture module 52 may include time snapshot capture circuits (which may be referred to as time snapshot capture units or capture units) distributed across each timer in at least one chip. Preferably, the time snapshot capture module is a hardware module that can ensure consistency of the capture times of time snapshots for each timer.

[0153] The time synchronization module 53 is used to perform time synchronization for each timer in at least one chip based on a time snapshot of each timer.

[0154] Here, the time synchronization module 53 may include a synchronization processing unit for each core of each chip, and the synchronization processing unit may be a part used to execute synchronization processing software within the processor or core, or it may be a software program module.

[0155] Figure 13 shows the structure of a chip time synchronization device provided by another exemplary embodiment of the present disclosure.

[0156] In some preferred embodiments, as shown in Figure 13, the time snapshot capture module 52 may include a pulse signal transmission unit 521, a capture unit 522, a register 523, and a snapshot acquisition unit 524.

[0157] The pulse signal transmission unit 521 is used to transmit pulse signals to each timer in at least one chip.

[0158] Here, the pulse signal transmission unit 521 may be any transmission line used to transmit pulse signals.

[0159] A capture unit 522 corresponding to each timer within at least one chip is used to write a time snapshot of the timer corresponding to the capture unit to the corresponding register in response to a pulse signal.

[0160] Here, each timer may have a corresponding capture unit 522 used to capture a time snapshot of that timer.

[0161] Register 523 is used to store a time snapshot.

[0162] Here, each timer may have a corresponding register 523 used to store a time snapshot of that timer.

[0163] In some preferred embodiments, for any one timer, the register corresponding to the timer may be located within the timer's hardware circuitry, outside the timer, or outside the core in which the timer is located, and is not specifically limited.

[0164] The snapshot acquisition unit 524 is used to acquire a time snapshot of each timer from the register corresponding to each timer.

[0165] Here, the snapshot acquisition unit 524 may be part of the synchronization processing unit of the chip's processor or core.

[0166] In some preferred embodiments, the snapshot acquisition unit 524 may be a unit within the time synchronization module 53.

[0167] In some preferred embodiments, the snapshot unit 524 is specifically used to detect interrupt requests triggered based on pulse signals or registers corresponding to each of the timers, and, in response to detecting an interrupt request, to take a time snapshot of each timer from the registers corresponding to each of the timers.

[0168] In some preferred embodiments, the time synchronization module 53 may include a time difference determination unit 531 and a time compensation unit 532.

[0169] The time difference determination unit 531 is used to determine a first time difference between the other timers and the first predetermined timer, based on a time snapshot of the first predetermined timer among the timers and time snapshots of the other timers among the timers other than the first predetermined timer.

[0170] The time compensation unit 532 is used to synchronize the time between other timers and the first predetermined timer by performing time compensation on the other timers based on the first time difference.

[0171] In some preferred embodiments, the time difference determination unit 531 is specifically: The system is used to determine a first time difference between the first predetermined timer and other timers based on time snapshots of other timers in the target chip, depending on whether the target chip includes the first predetermined timer, transmit the time snapshot of the first predetermined timer to other chips in the target chip, depending on whether the target chip does not include the first predetermined timer, receive a time snapshot of the first predetermined timer from a chip that includes the first predetermined timer, and determine a first time difference between each timer and the first predetermined timer based on the time snapshot of the first predetermined timer and the time snapshots of each timer in the target chip.

[0172] Figure 14 shows the structure of a chip time synchronization device provided in yet another exemplary embodiment of the present disclosure.

[0173] In some preferred embodiments, each of the at least one chip may include at least one processor core, and each of the processor cores may correspond to at least one timer.

[0174] As shown in Figure 14, the pulse signal generation module 51 may include a common timer 511 within one of the chips, which is used to generate pulse signals according to a predetermined period.

[0175] The time snapshot capture module 52 may include a first capture unit 521a corresponding to each timer in a predetermined chip, and a second capture unit 522a corresponding to a common timer in a predetermined chip.

[0176] A first capture unit 521a, corresponding to each timer in a predetermined chip, is used to capture a time snapshot of the timer in response to a pulse signal.

[0177] A second capture unit 522a, corresponding to a common timer within a predetermined chip, is used to capture a time snapshot of the common timer in response to a pulse signal.

[0178] The time synchronization module 53 is A first time difference determination unit 531a within a predetermined chip is used to determine a second time difference between a common timer and a second predetermined timer based on a time snapshot of a second predetermined timer corresponding to a predetermined processor core within the predetermined chip and a time snapshot of a common timer, A first time compensation unit 532a within a predetermined chip is used to synchronize the time between a common timer and a second predetermined timer by performing time compensation on the common timer based on a second time difference, A second time difference determination unit 533a within a predetermined chip is used to determine a third time difference between each of the other timers and the common timer, based on the second time difference, by performing time compensation on the time snapshot of the common timer to obtain a compensated time snapshot of the common timer, and based on the time snapshots of the other timers other than the second predetermined timer and the compensated time snapshot of the common timer. The system may also include a second time compensation unit 534a within a predetermined chip, which synchronizes the time of each other timer with the time-compensated common timer by performing time compensation on each of the other timers based on a third time difference corresponding to each of the other timers.

[0179] In some preferred embodiments, a second time difference determination unit 533a within a given chip is used to determine a third time difference between each of the other timers and the common timer, based on time snapshots of each of the other timers and the common timer.

[0180] The second time compensation unit 534a within the predetermined chip is used to synchronize the time of each other timer with the time-compensated common timer by performing time compensation on each other timer based on the second time difference and the third time difference.

[0181] In some preferred embodiments, the time snapshot capture module 52 is A first transmission unit 521b used to transmit a time snapshot after compensation of a common timer to at least one chip other than a predetermined chip, A third capture unit 522b, corresponding to each timer in another chip, is used to capture a time snapshot of the timer in response to a pulse signal, The system may also include a first acquisition unit 523b used to acquire a compensated time snapshot of a common timer from a predetermined chip.

[0182] The time synchronization module 53 is A third time difference determination unit 531b in another chip is used to determine a fourth time difference between each timer and the common timer, based on time snapshots of each timer in the other chip and a compensated time snapshot of the common timer. The system may further include a third time compensation unit 532b in another chip, which is used to synchronize the time of each timer with a time-compensated common timer by performing time compensation on each timer based on a fourth time difference corresponding to each of the timers.

[0183] Figure 15 shows the structure of a chip time synchronization device provided in yet another exemplary embodiment of the present disclosure.

[0184] In some preferred embodiments, as shown in Figure 15, the time synchronization module 53 is: A snapshot transmission unit 531c of a predetermined chip is used to transmit a time snapshot of a third predetermined timer of a predetermined chip to a first other chip other than the predetermined chip among at least one chip, and to transmit a time snapshot of a common timer of a predetermined chip to a second other chip other than the predetermined chip among at least one chip, wherein the third predetermined timer is a timer as a reference time, and the predetermined chip is a chip containing the third predetermined timer, A fourth time difference determination unit 532c in the first other chip is used to determine a fifth time difference between the fourth predetermined timer and the third predetermined timer based on a time snapshot of the third predetermined timer and a time snapshot of the fourth predetermined timer in the first other chip, A fourth time compensation unit 533c in the first other chip is used to synchronize the time between the fourth predetermined timer and the third predetermined timer by performing time compensation on the fourth predetermined timer based on the fifth time difference, A fifth time difference determination unit 534c in the second chip is used to determine a sixth time difference between the fifth predetermined timer and the common timer based on a time snapshot of the common timer and a time snapshot of a fifth predetermined timer in the second chip, The system may also include a fifth time compensation unit 535c in a second chip, which is used to synchronize the time between the fifth predetermined timer and a common timer by performing time compensation on the fifth predetermined timer based on the sixth time difference.

[0185] Furthermore, each unit of each module in the embodiments of this disclosure may be distributed within the same or different chips, or within the same or different cores within the same or different chips.

[0186] In some preferred embodiments, Figure 16 shows the structure of a time synchronization device for a chip provided in yet another exemplary embodiment of the present disclosure. As shown in Figure 16, for a predetermined chip, SOC1, the chip may include a common timer 511 and at least one core domain. The drawing illustrates a case in which there are two core domains, CORE1 domain and CORE2 domain. Each core domain may include one core and several timers (e.g., a network card timer and a PCIe timer), each timer may include a first capture unit 521a and a register 523. The common timer 511 may include a second capture unit 522a and a register 523. Each core may include a snapshot acquisition unit 524 used to acquire a time snapshot from the register 523. The predetermined core CORE1 in SOC1 comprises a first time difference determination unit 531a and a first time compensation unit 532a. The non-predetermined core CORE2 in SOC1 comprises a second time difference determination unit 533a and a second time compensation unit 534a. For specific functions of each unit, please refer to the examples described above.

[0187] In some preferred embodiments, Figure 17 shows the structure of a time synchronization device for a chip provided in yet another exemplary embodiment of the present disclosure. As shown in Figure 17, for a non-specified chip SOC2, each timer in the SOC2 may comprise a first capture unit 521a and a register 523. Each core in the SOC2 may include a snapshot acquisition unit 524, a second time difference determination unit 533a, and a second time compensation unit 534a. For specific functions of each unit, refer to the embodiments described above.

[0188] The beneficial technical effects corresponding to the exemplary embodiment of this device can be found by referring to the corresponding beneficial technical effects in the section on the example method described above, so a detailed explanation is omitted here.

[0189] <Example electronic device> Figure 18 is a diagram illustrating the configuration of an electronic device including at least one processor 11 and memory 12 according to an embodiment of the present disclosure.

[0190] The processor 11 may be a central processing unit (CPU) or another form of processing unit having data processing capability and / or instruction execution capability, and can control other components in the electronic device 10 to perform a desired function.

[0191] The memory 12 may include one or more computer program products, the computer program products may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage media, and the processor 11 can implement the methods of each embodiment of the present disclosure described above and / or other desired functions by executing one or more computer program instructions.

[0192] In one example, the electronic device 10 may further include an input device 13 and an output device 14, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0193] The input device 13 may include, for example, a keyboard, mouse, touchscreen, microphone, and various sensors. Sensors include, for example, image sensors (e.g., cameras, webcams), laser radar, millimeter-wave radar, ultrasonic radar, positioning sensors, pressure sensors, air quality sensors, and temperature sensors. Image sensors, laser radar, millimeter-wave radar, and ultrasonic radar may be used to sense the surrounding environment, that is, to detect dynamic and static objects in the surrounding environment. Dynamic and static objects may include, for example, static objects such as lane boundaries, road shoulders, arrows, signs, trees, and buildings, and dynamic objects such as surrounding vehicles, pedestrians, and motorcyclists. Positioning sensors are used to position the moving device (e.g., the vehicle itself, a robot, etc.) on which the electronic device is located. Positioning sensors may include, for example, an Inertial Measurement Unit (IMU) and a Global Positioning System (GPS). Pressure sensors may be used to detect seat pressure. A temperature sensor may be used to detect the temperature inside the vehicle's cabin. An air quality sensor may be used to detect the air quality inside the vehicle's cabin.

[0194] This output device 14 may output various types of information to the outside, and may include, for example, a display, speaker, printer, communication network and remote output device connected thereto.

[0195] Of course, for the sake of simplification, Figure 18 shows only some of the components of the electronic device 10 relevant to this disclosure, and components such as buses and input / output interfaces are omitted. In addition, the electronic device 10 may include any other suitable components depending on the specific application needs.

[0196] Furthermore, according to embodiments of the present application, an electronic device is further provided. This electronic device comprises a time synchronization device for a chip provided in any one of the above embodiments.

[0197] <Examples of computer program products and computer-readable storage media> In addition to the methods and apparatus described above, embodiments of the present disclosure can further provide computer program products including computer program instructions. When executed by a processor, the computer program instructions cause the processor to perform the steps in the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0198] Computer program products can be created using one or any combination of programming languages ​​to produce program code for performing the actions of the embodiments of this disclosure, the programming languages ​​include object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as the C language or similar programming languages. The program code may run entirely on the user's computing device, partially on the user's computing device, run as a single standalone software package, run partially on the user's computing device and partially on a remote computing device, or run entirely on a remote computing device or server.

[0199] Furthermore, embodiments of the present disclosure may be computer-readable storage media storing computer program instructions. When executed by a processor, the computer program instructions cause the processor to perform the steps in the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0200] A computer-readable storage medium may be any combination of one or more readable media. A readable media may be a readable signal medium or a readable storage medium. A readable storage medium may be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exclusive list) include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical memory devices, magnetic memory devices, or any suitable combination of the above.

[0201] While the basic principles of this disclosure have been explained above in relation to specific embodiments, the advantages, benefits, and effects mentioned herein are illustrative, not limiting, and should not be considered essential to each embodiment of this disclosure. Furthermore, the specific details of the above disclosure are illustrative and for ease of understanding, not limiting. The above details do not limit the implementation of this disclosure to using the above specific details.

[0202] Those skilled in the art can make various modifications and alterations to the present application without departing from the spirit and scope of the present disclosure. Thus, if these modifications and alterations fall within the scope of the claims of the present disclosure and the equivalent art, the present disclosure is intended to include these modifications and alterations.

Claims

1. A method for synchronizing the time of a chip, To generate a pulse signal according to a predetermined period, In response to the pulse signal, capture a time snapshot of at least one timer in at least one chip, representing the time information of the timer at a predetermined state of the pulse signal; Time synchronization is performed on each of the timers in at least one chip based on the time snapshot of each of the timers, A method that includes this.

2. Performing time synchronization for each of the timers in at least one chip based on the time snapshot of each of the timers is: Based on the time snapshot of the first predetermined timer among the timers and the time snapshots of the other timers among the timers other than the first predetermined timer, a first time difference between the other timers and the first predetermined timer is determined. By performing time compensation on the other timer based on the first time difference, the time of the other timer and the first predetermined timer are synchronized. The method according to claim 1, including the method described in claim 1.

3. Determining the first time difference between the other timers and the first predetermined timer based on the time snapshot of the first predetermined timer among the timers and the time snapshots of the other timers among the timers other than the first predetermined timer is: Each of the at least one chips is designated as a target chip, and depending on whether the target chip includes the first predetermined timer, a first time difference between the other timers and the first predetermined timer is determined based on the time snapshot of the other timers in the target chip other than the first predetermined timer, and the time snapshot of the first predetermined timer is transmitted to the other chips among the at least one chip other than the target chip. Depending on whether the target chip does not include the first predetermined timer, the time snapshot of the first predetermined timer is received from a chip that includes the first predetermined timer, and the first time difference between each timer and the first predetermined timer is determined based on the time snapshot of the first predetermined timer and the time snapshots of each timer in the target chip. The method according to claim 2, including the method described in claim 2.

4. Capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal is: The pulse signal is transmitted to each of the timers in at least one chip such that each of the timers responds to the pulse signal and writes a time snapshot corresponding to each of the timers to the corresponding register, To obtain a time snapshot of each timer from the register corresponding to each of the timers, The method according to claim 1, including the method described in claim 1.

5. Taking a time snapshot of each timer from the register corresponding to each of the timers is: Detecting an interrupt request triggered based on the pulse signal or the register corresponding to each of the timers, Upon detecting an interrupt request, the time snapshot of each timer is obtained from the register corresponding to each of the timers, The method according to claim 4, including the method described in claim 4.

6. Each of the aforementioned at least one chip includes at least one processor core, Each of the processor cores corresponds to at least one of the timers, Generating a pulse signal according to a predetermined period is The common timer in a predetermined chip among the at least one of the aforementioned chips generates the pulse signal according to the predetermined period, Capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal is: Each of the at least one chips is designated as a target chip, and depending on whether the target chip is the predetermined chip, the target chip includes capturing a time snapshot of at least one timer corresponding to at least one processor core within the target chip and a time snapshot of the common timer in response to the pulse signal. Performing time synchronization for each of the timers in at least one chip based on the time snapshot of each of the timers is: Based on the time snapshot of the second predetermined timer corresponding to a predetermined processor core in the target chip and the time snapshot of the common timer, a second time difference between the common timer and the second predetermined timer is determined. By performing time compensation on the common timer based on the second time difference, the times of the common timer and the second predetermined timer are synchronized. Based on the second time difference, time compensation is performed on the time snapshot of the common timer to obtain a compensated time snapshot of the common timer, and a third time difference is determined between each of the other timers and the common timer based on the time snapshots of the other timers in the target chip other than the second predetermined timer and the compensated time snapshot of the common timer. By performing time compensation on each of the other timers based on the third time difference corresponding to each of the other timers, the time of each of the other timers and the time-compensated common timer are synchronized, or Based on the time snapshots of each of the other timers and the time snapshot of the common timer, a third time difference is determined between each of the other timers and the common timer. By performing time compensation on each of the other timers based on the second time difference and the third time difference, the time of each of the other timers and the time-compensated common timer are synchronized. The method according to claim 1, including the method described in claim 1.

7. After capturing the time snapshot of at least one timer corresponding to at least one processor core in the target chip and the time snapshot of the common timer, The method further includes transmitting the compensated time snapshot of the common timer to another chip among the at least one chip other than the predetermined chip, Capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal is: Depending on whether the target chip is the predetermined chip, the target chip further includes capturing the time snapshot of at least one timer corresponding to at least one processor core within the target chip in response to the pulse signal, and obtaining the compensated time snapshot of the common timer from the predetermined chip, Performing time synchronization for each of the timers in at least one chip based on the time snapshot of each of the timers is: Based on the time snapshot of each of the timers in the target chip and the compensated time snapshot of the common timer, a fourth time difference is determined between each of the timers and the common timer. The further includes synchronizing the time of each timer with the time-compensated common timer by performing time compensation on each timer based on the fourth time difference corresponding to each of the timers, The method according to claim 6.

8. Performing time synchronization for each of the timers in at least one chip based on the time snapshot of each of the timers is: Each of the at least one chips is designated as a target chip, and depending on whether the target chip is a predetermined chip, the time snapshot of the third predetermined timer of the target chip is transmitted to a first other chip other than the predetermined chip among the at least one chip, and the time snapshot of the common timer of the target chip is transmitted to a second other chip other than the predetermined chip among the at least one chip, and the third predetermined timer is a timer as a reference time, and the predetermined chip is a chip that includes the third predetermined timer, Depending on whether the target chip is the other chip mentioned above, a fifth time difference between the fourth predetermined timer and the third predetermined timer is determined based on the time snapshot of the third predetermined timer and the time snapshot of the fourth predetermined timer within the target chip, and time compensation is performed on the fourth predetermined timer based on the fifth time difference, thereby synchronizing the times of the fourth predetermined timer and the third predetermined timer. The process includes determining a sixth time difference between the fifth predetermined timer and the common timer based on the time snapshot of the common timer and the time snapshot of the fifth predetermined timer in the target chip, depending on whether the target chip is the second other chip, and synchronizing the time between the fifth predetermined timer and the common timer by performing time compensation on the fifth predetermined timer based on the sixth time difference. The method according to claim 1.

9. A time synchronization device for chips, A pulse signal generation module used to generate pulse signals according to a predetermined period, A time snapshot capture module used to capture a time snapshot representing the time information of at least one timer in at least one chip at a predetermined state of the pulse signal, in response to the pulse signal, A time synchronization module used to perform time synchronization on each of the timers in at least one chip based on the time snapshot of each of the timers, A time synchronization device for chips equipped with the following features.

10. The aforementioned time snapshot capture module is A pulse signal transmission unit used to transmit the pulse signal to each of the timers in at least one chip, A capture unit corresponding to each of the timers in at least one chip, used to write a time snapshot of the timer corresponding to the capture unit to the corresponding register in response to the pulse signal, The register used to store the aforementioned time snapshot, The system includes a snapshot acquisition unit used to acquire a time snapshot of each timer from the register corresponding to each of the timers, The apparatus according to claim 9.

11. Each of the aforementioned at least one chip includes at least one processor core, Each of the processor cores corresponds to at least one of the timers, The pulse signal generation module is A common timer is provided within one of the at least one chips, which is used to generate the pulse signal according to the predetermined period, The aforementioned time snapshot capture module is A first capture unit corresponding to each of the timers in the predetermined chip is used to capture the time snapshot of the timer in response to the pulse signal, The system comprises a second capture unit corresponding to the common timer in a predetermined chip, which is used to capture a time snapshot of the common timer in response to the pulse signal, The aforementioned time synchronization module is A first time difference determination unit within the predetermined chip is used to determine a second time difference between the common timer and the second predetermined timer based on the time snapshot of the second predetermined timer corresponding to a predetermined processor core within the predetermined chip and the time snapshot of the common timer, A first time compensation unit within the predetermined chip is used to synchronize the time between the common timer and the second predetermined timer by performing time compensation on the common timer based on the second time difference, A second time difference determination unit within the predetermined chip is used to determine a third time difference between each of the other timers and the common timer, based on the second time difference, by performing time compensation on the time snapshot of the common timer based on the second time difference, obtaining a compensated time snapshot of the common timer, and based on the time snapshots of the other timers other than the second predetermined timer and the compensated time snapshot of the common timer. The chip comprises a second time compensation unit that synchronizes the time of each of the other timers with the time-compensated common timer by performing time compensation on each of the other timers based on the third time difference corresponding to each of the other timers, Alternatively, the second time difference determination unit is used to determine a third time difference between each of the other timers and the common timer based on the time snapshots of each of the other timers and the time snapshot of the common timer. The second time compensation unit is used to synchronize the time of each of the other timers with the time-compensated common timer by performing time compensation on each of the other timers based on the second time difference and the third time difference. The apparatus according to claim 9.

12. A computer-readable storage medium that stores computer programs, The computer program is used to perform the time synchronization method for the chip described in any one of claims 1 to 8. Computer-readable storage medium.

13. Processor and Includes a memory used to store instructions that can be executed by the aforementioned processor, The processor is used to realize the time synchronization method for the chip described in any one of claims 1 to 8 by reading the executable instructions from the memory and executing the instructions, or A time synchronization device for a chip according to any one of claims 9 to 11, electronic equipment.

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