Solid cooling device with grid point contacts

Abstract

A solid cooling device is disclosed. The solid cooling device includes a first part having a normal-conducting metal heat sink layer and a plurality of first parallel ridges disposed on the normal-conducting metal heat sink layer, and a second part having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction and a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction. A plurality of lattice point contacts are provided by the plurality of first parallel ridges contacting and orthogonal to the plurality of second parallel ridges.

Description

Technical Field

[0001] The present invention generally relates to refrigeration, and more specifically, to a solid cooling device with lattice point contacts. This application claims the priority of US Patent Application No. 18 / 363450 filed on August 1, 2023, the entire content of which is incorporated herein by reference.

Background Art

[0002] Solid-state electronic cooling by tunneling of "hot" electrons through a normal metal-insulator-superconductor (NIS) junction using a bias voltage has been demonstrated to operate below 1 K and behaves substantially like more common and expensive Peltier thermoelectric coolers near room temperature. These NIS cryocoolers are composed of the same materials and fabricated using the same lithography process as the Josephson junctions used in superconducting circuits and are essentially fully compatible with the components of Josephson junctions. They can be integrated and manufactured simultaneously with the Josephson junction itself. However, currently, the temperature range of NIS coolers is very limited, and the maximum temperature difference between the high-temperature side and the low-temperature side is about 150 mK.

[0003] One of the main limitations to the maximum performance of NIS coolers is the presence of non-equilibrium quasiparticles in the superconducting leads resulting from large currents flowing through the device. The low quasiparticle relaxation rate and thermal conductivity in superconductors couple these hot particles near the junction, leading to significant overheating of the superconducting electrodes. There are several ways to reduce the accumulation of quasiparticles in superconductors. The most common method is to use a normal metal coupled to the superconductor called a quasiparticle trap to move the quasiparticles to the normal metal and relax the energy through electron-electron and electron-phonon interactions. This device is called a normal metal-insulator-superconductor-normal metal (NISN) junction. However, the phonon heat generated within the quasiparticle trap can return to the superconducting electrodes, which is a factor limiting the temperature difference between the high-temperature side and the low-temperature side of NISN junction solid coolers.

Summary of the Invention

[0004] In one embodiment, a solid cooling device is disclosed. The solid cooling device comprises a first portion having a normal-conducting metal heat sink layer and a plurality of first parallel ridges disposed on the normal-conducting metal heat sink layer, and a second portion having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction and a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction. A plurality of lattice point contacts are provided by the plurality of first parallel ridges contacting and being orthogonal to the plurality of second parallel ridges.

[0005] In another embodiment, a refrigeration system is disclosed. The refrigeration system comprises a refrigeration container formed from one or more plates and a plurality of solid cooling devices surrounding the outside of the refrigeration container. Each of the plurality of solid cooling devices comprises a first portion having a normal-conducting metal heat sink layer, a superconductor interface layer disposed on the normal-conducting metal heat sink layer, and a plurality of first parallel superconductor ridges disposed on the superconductor interface layer. Each of the plurality of solid cooling devices further comprises a second portion having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction and a plurality of second parallel superconductor ridges disposed on the superconductor layer of the NIS junction. The plurality of first parallel superconductor ridges contact and are orthogonal to the plurality of second parallel superconductor ridges, providing a plurality of lattice point contacts that provide a path for moving quasiparticles from the normal-conducting metal layer to the normal-conducting metal heat sink layer of the NIS junction in response to a critical current flowing through the NIS junction.

[0006] In yet another embodiment, a method for forming a solid cooling device is disclosed. The method comprises manufacturing a first chip, which includes forming an interface layer on a normal-conducting metal heat sink layer and forming a plurality of first parallel ridges disposed on the interface layer. The method further comprises manufacturing a second chip, which includes forming a normal-conducting metal-insulator-superconductor (NIS) junction and forming a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction. The second chip is flip-chip bonded onto the first chip such that the plurality of first parallel ridges are in contact with and orthogonal to the plurality of second parallel ridges in order to provide a plurality of lattice point contacts that provide a path for moving quasiparticles from the normal-conducting metal layer of the NIS junction to the normal-conducting metal heat sink layer in response to a critical current flowing through the NIS junction. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a cross-sectional view showing an example of a solid point cooling device. [Figure 2] Figure 2 is a cross-sectional view showing an example of the high-temperature side or tip of a solid point cooler. [Figure 3] Figure 3 is a plan view of the high-temperature side portion or chip shown in Figure 2. [Figure 4] Figure 4 is a cross-sectional view showing an example of the low-temperature side or tip of a solid point cooler. [Figure 5] Figure 5 is a plan view of the low-temperature side portion or chip of Figure 4. [Figure 6] Figure 6 shows a diagram for forming a solid point cooler by joining using a flip-chip vacuum bonding process, and shows the high-temperature side portion or the low-temperature side portion or the chip that covers the chip. [Figure 7] Figure 7 is a cross-sectional view of the solid cooler after bonding along line CC in Figure 6. [Figure 8] Figure 8 is a block diagram showing a refrigeration system that uses solid-state devices, such as the solid-state device shown in Figure 1. [Modes for carrying out the invention]

[0008] This disclosure relates to a refrigeration system comprising a solid-state point cooler and a refrigeration container defined by refrigeration plates, and a plurality of solid-state coolers arranged around one or more refrigeration plates. The solid-state cooler may form the final refrigeration stage in a plurality of refrigeration stages to provide cooling down to a millikelvin temperature. The solid-state cooler is formed from a low-temperature portion (or low-temperature chip) having a normal-conducting metal-insulator-superconductor (NIS) junction with a plurality of first parallel ridges, and a high-temperature portion (or high-temperature chip) having a normal-conducting metal heat sink and a plurality of second parallel ridges. The plurality of first parallel ridges contact and are perpendicular to the plurality of second parallel ridges, thereby forming a plurality of grid point contacts between the NIS junction and the normal-conducting metal heat sink. The normal-conducting metal is a metal that does not superconduct at a given cryogenic operating temperature.

[0009] A point cooler is a novel type of solid cooler based on a normal-conducting / insulating / superconductor (NIS) tunnel junction. An example of a point cooler can be found in U.S. Patent No. 11,333,413 by the same applicant, titled "Solid-state Cooler Device," the entirety of which is incorporated herein by reference. A point cooler uses two chips (or parts) connected by a number of small contacts. The low-temperature chip includes an NIS cooler junction and is in contact with a cooled payload. The high-temperature chip includes a heat sink (or quasi-particle trap) which dissipates waste heat to another refrigerator providing a subsequent cooling stage.

[0010] The large-area geometric contact between the NIS junction superconductor and the coupled normal-conducting metal heatsink can lead to leakage of hot phonons backflowing into the NIS junction superconductor and normal-conducting metal layer, which is expected to significantly limit the performance of the solid-state cooler. By modifying the geometric shape and reducing the contact area using lattice point contacts, the thermal boundary resistance (TBR) present between the superconductor layer and the normal-conducting metal heatsink is utilized, thereby reducing backflow of heat from the normal-conducting metal heatsink to the NIS junction superconductor layer. This makes it possible to raise the exhaust temperature compared to conventional NIS or NISN coolers by reducing backflow of heat from the high-temperature exhaust side without hindering the thermal rise of quasiparticles when the normal-conducting metal heatsink functions as a quasiparticle trap.

[0011] This disclosure provides a structure and method for manufacturing a point cooler that uses a plurality of narrow parallel ridges arranged as orthogonal lines in an intersecting pattern on both a high-temperature side chip and a low-temperature side chip that are joined together. When pressed together, a grid of small-area grid point contacts arranged at narrow intervals is formed by the cross-shaped ridges. The grid point contacts provide short paths for the diffusion of high-temperature quasiparticles from the low-temperature side chip to the high-temperature side chip. The dense pattern of grid point contacts provides short diffusion path lengths for the high-temperature quasiparticles to efficiently conduct waste heat from the low-temperature side to the high-temperature side heat sink.

[0012] Multiple parallel ridges offer an improvement over bump junctions by allowing for the patterning of smaller ridge structures at smaller pitches than standard lift-off processes, which are generally considered optimal for large metal structures. Point coolers utilize the different properties and functions of point cooler grid point junctions compared to integrated circuit flip-chip junctions. All point cooler grid point junctions function in parallel to transport quasiparticles from the cold side chip to the hot side chip. Since any junction forms a grid point junction, it is not necessary to connect a specific point on the cold side to a precise location on the hot side.

[0013] This disclosure enables the formation of finer contact grids using the same manufacturing tools used to form bump junctions. In certain manufacturing processes, when using a metal lift-off deposition process, bump junctions may be limited to 1 μm bumps on a 10 μm grid. In one example, a cross-shaped intersecting ridge can be etched as a 0.25 μm contact on a 2.5 μm grid. For example, a 0.25 μm aluminum (Al) ridge can be dry-etched at any pitch greater than 0.5 μm. The dense pitch of these dry-etched ridges allows for more efficient utilization of the junction area, thereby increasing the overall chip junction contact area and, consequently, the junction shear strength.

[0014] Solid point coolers can be configured to raise waste heat to higher exhaust temperatures than when using bump bonding. At higher exhaust temperatures, the density of thermally activated quasiparticles (QPs) increases, which shortens the quasiparticle diffusion decay length. As QP decays, waste heat accumulates on the cooler side, degrading the cooler's performance. A shorter diffusion path reduces QP decay on the cooler side, thereby allowing the cooler to operate efficiently at higher heatsink temperatures.

[0015] Point coolers with grid point junctions are intended to cool solids to operating temperatures below 2 Kelvin (K). Point coolers with grid point junctions utilize established materials and processes suitable for silicon CMOS equipment using materials such as tungsten (W), titanium tungsten (TiW), aluminum (Al), niobium (Nb), and Nb / aluminum oxide (AlOx) / Al tunnel junctions. Point coolers with grid point junctions can provide continuous cooling when a DC bias current of several amperes is applied across a single large tunnel junction, resulting in a thermal rise of tens of microwatts in a small 1 square centimeter assembly. Ten thousand of these point coolers with grid point junctions can cover an area of ​​approximately 1 square meter by placing them on or between one or more of the two copper sheets in the final stage of a refrigeration system, providing a large thermal rise at 50 mK.

[0016] Point coolers can be formed from various normal-conducting metallic and superconducting materials. Normal-conducting metals can be selected from materials such as gold (Au), platinum (Pt), tungsten (W), titanium-tungsten (TiW), copper (Cu), doped superconducting materials, metals exceeding their superconducting transition temperature such as titanium or chromium, or combinations thereof. Superconducting materials can be selected from materials such as indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), or other doped or undoped superconducting materials.

[0017] Point coolers with grid point contacts provide a solid-state alternative to conventional, expensive helium-3 based dilution refrigerators. This point cooler also offers an alternative to adiabatic demagnetizing refrigerators (ADRs). Point coolers with grid point contacts can provide continuous cooling as long as a DC current is applied to the NIS tunnel junction. ADRs have single-shot operation. ADRs require a separate heating and cooling cycle after cooling until the fixed capacity of the cooling salt is exhausted.

[0018] Figure 1 shows a cross-sectional view of an example of a solid point cooler 10. The solid point cooler 10 can be configured as a refrigeration stage used for cryogenic cooling applications. In cryogenic cooling applications, the solid structure is one of several solid coolers arranged around a refrigeration container that is located in a vacuum and holds a superconducting circuit. The multiple solid structures provide the final stage of the cryogenic refrigeration system, preventing heat from returning from the high-temperature refrigeration stage to the final stage within the multiple refrigeration stages by removing heat from the low-temperature refrigeration stage to enable efficient cooling.

[0019] The solid-state point cooling device includes a low-temperature side portion 14 and a high-temperature side portion 12. The high-temperature side portion 12 includes a normal-conducting metal heat sink layer 18 located on a silicon layer or substrate 16, an interface layer 20 located on the normal-conducting metal heat sink layer 18, and a plurality of first parallel superconductor ridges 22 that are spaced apart from each other and located on the interface layer 20. The plurality of first parallel ridges 22 are disposed on the interface layer 20 and are spaced apart from each other at substantially equal distances. The plurality of first parallel superconductor ridges 22 can have a width of about 50 nm to about 500 nm (e.g., a width of about 250 nm) and can be spaced apart from each other at an interval of about 1 μm to about 5 μm (e.g., an interval of about 2.5 μm). The interface layer 20 can be formed of a superconductor material or a normal-conducting metal material. The interface layer 20 increases the contact area for quasiparticles to spread and enter the normal-conducting metal heat sink layer 18.

[0020] The low-temperature side portion 14 includes a NIS junction 15 disposed on a silicon layer or silicon substrate 32. The NIS junction 15 includes a normal-conducting metal layer 30, an insulator layer 28 disposed on the normal-conducting metal layer 30, and a superconductor layer 26 disposed on the insulator layer 28. A plurality of second parallel superconductor ridges 24 are disposed on the superconductor layer 26 and are spaced apart from each other at substantially equal distances. The plurality of second parallel superconductor ridges 26 can have a width of about 50 nm to about 500 nm (e.g., a width of about 250 nm) and can be spaced apart from each other at an interval of about 1 μm to about 5 μm (e.g., an interval of about 2.5 μm). The plurality of second parallel superconductor ridges 24 are coupled to the plurality of first superconductor ridges, for example, within a vacuum bond. The plurality of second parallel superconductor ridges 24 and the plurality of first parallel superconductor ridges 22 extend orthogonally to each other to form a plurality of lattice point contacts (see 80 in FIG. 7).

[0021] In one example, the cooling current (I COOLER) is injected so as to flow through the NIS junction, and when hot electrons tunnel into the superconductor, the normal conductor can be cooled to 100 mK. The injected quasiparticles diffuse through the contact points between the ridges. In one example, the total contact area between the high-temperature side portion and the low-temperature side portion can be less than 1% of the chip areas of both the high-temperature side portion and the low-temperature side portion. By making the contacts smaller, it becomes possible to bring the contacts closer to each other, and the path from the quasiparticle injection point on the low-temperature side to the heat sink on the high-temperature side is shortened. The return of the heat extracted from the low-temperature side of the solid-state point cooling device is reduced by the reduction of the contact areas on the high-temperature side and the low-temperature side through a plurality of lattice point contacts.

[0022] In one example, a plurality of different superconductor materials can be used to form two or more of the superconductor layer 26, the plurality of second parallel ridges 24, the plurality of first parallel superconductor ridges 22, and the interface layer 20. The plurality of different superconductor materials can be selected to have an energy band gap such that when quasiparticles move through the NIS junction to the normal-conducting metal heat sink layer, they progress from a high-energy band gap to a low-energy band gap via the quasiparticle path. For example, the superconductor layer 26 and the plurality of second parallel ridges 24 are formed of a first superconductor material having a first energy band gap, the plurality of first parallel ridges 22 are formed of a second superconductor material having a second energy band gap, and the interface layer 20 can be formed of a third superconductor material having a third energy band gap. The first energy band gap is higher than the second energy band gap, and the second energy band gap is higher than the third energy band gap.

[0023] In another example, the superconducting layer 26 may be formed of a first superconducting material, the plurality of second parallel ridges 24 may be formed of a second superconducting material, and the plurality of first parallel ridges 22 and interface layer 20 may be formed of a third superconducting material. In yet another example, the superconducting layer 26 and the plurality of second parallel ridges 24 may be formed of a first superconducting material, and the plurality of first parallel ridges 22 and interface layer 20 may be formed of a second superconducting material. In this case, the energy band gap of the first superconducting material is higher than the energy band gap of the second superconducting material. The type of superconducting material selected may be modified on the basis of achieving a desired multi-stage energy band gap. Some of these materials for variable multi-stage band gaps can be found in U.S. Patent No. 11,189,773 by the same applicant, titled “Superconductor Thermal Filter,” the entire contents of which are incorporated herein by reference.

[0024] For example, the first superconducting material has a coefficient of 2Δ = 30.5 × 10 -4 The second superconducting material is formed from niobium (Nb) with a superconducting energy band gap of 10^2, and the second superconducting material has a band gap of 2Δ = 11.5 × 10^2. -4 Formed from tin (Sn) with a superconducting energy band gap of ev, the third superconducting material has a band gap of 2Δ = 3.4 × 10⁻¹⁰. -4 It is formed from aluminum (Al) having a superconducting energy band gap of eV. In yet another example, the first superconducting material is 2Δ = 3.4 × 10⁻¹⁰. -4 The second superconducting material is made of aluminum (Al) with a superconducting energy band gap of 10^2, and has a band gap of 2Δ = 2.7 × 10^2. -4 Formed from molybdenum (Mo) with a superconducting energy band gap of ev, the third superconducting material has a band gap of 2Δ = 1.2 × 10⁻¹⁰. -4 It is formed of titanium (Ti) having a superconducting energy band gap of eV. Note that various different superconducting materials can be used, as long as they are selected to gradually decrease the superconducting energy band gap from the normal-conducting metal layer 30 to the normal-conducting metal heat sink layer 18.

[0025] Figure 2 shows a cross-sectional view of an example of the high-temperature side portion or chip 40 of a solid point cooler. Figure 3 shows a plan view of the high-temperature side portion or chip 40 of Figure 2. The high-temperature side portion 40 includes a normal-conducting metal heat sink layer 44 disposed on a silicon layer or substrate 42, an interface layer 46 disposed on the normal-conducting metal heat sink layer 44, and a plurality of first parallel ridges 48 disposed on the interface layer 46 at intervals from each other. The plurality of first parallel ridges 48 are disposed on the interface layer 46 and spaced approximately equidistant from each other, as described in Figure 1. The plurality of first parallel ridges 48 may be formed of a superconducting material or a normal-conducting metal. The interface layer 46 may be formed of a superconducting material or a normal-conducting metal material. The interface layer 46 increases the contact area for quasiparticles to spread and enter the plurality of first parallel ridges 48.

[0026] In one example, the multiple first parallel ridges 48 and the interface layer 46 are formed from the same superconducting material. In another example, the multiple first parallel ridges 48 and the interface layer 46 are formed from different superconducting materials, and the interface layer 46 is formed from a superconducting material having a lower band gap than the multiple first parallel ridges 48. In yet another example, the multiple first parallel ridges 48 are formed from a superconducting material layer, and the interface layer 46 is formed from a normal-conducting metal layer different from the normal-conducting metal forming the normal-conducting metal heat sink layer 44. In yet another example, the multiple first parallel ridges 48 are placed directly on the normal-conducting metal heat sink layer 44, and the interface layer 46 is removed.

[0027] Multiple first parallel ridges 48 can be formed by depositing a superconducting material or a normal-conducting metal layer on a normal-conducting metal heat sink layer 44, forming a photoresist pattern on the superconducting material or normal-conducting metal layer having a pattern to protect the ridge pattern, partially etching the layer of superconducting material to leave multiple first parallel ridges 48, and then removing the photoresist layer to provide multiple first ridges 48 and an interface layer 46 beneath the multiple first parallel ridges 48. In another example, multiple first parallel ridges 48 and the interface layer 46 are formed from different materials. In this alternative example, multiple first parallel ridges 48 can be formed by depositing a superconducting material or a normal-conducting metal layer on a normal-conducting metal heat sink layer 44 to form an interface layer 46, forming a photoresist pattern having ridge pattern openings on the superconducting material or normal-conducting metal layer, depositing a second material different from the material forming the interface layer 46 on the photoresist material, and then performing a lift-off process to remove the photoresist material and excess second material to leave multiple first parallel ridges 48 on the interface layer 46.

[0028] Figure 4 shows a cross-sectional view of an example of the low-temperature portion or chip 60 of a solid point cooler. Figure 5 shows a plan view of the low-temperature portion or chip 60 of Figure 4. The low-temperature portion 60 includes an NIS junction 72 disposed on a silicon layer or silicon substrate 70. The NIS junction 72 includes a normal-conducting metal layer 68, an insulating layer 66 disposed on the normal-conducting metal layer 68, and a superconducting layer 64 disposed on the insulating layer 66. Multiple second parallel ridges 62 are disposed on the superconducting layer 64 and are spaced approximately equidistant from each other. The multiple second parallel ridges 62 may be formed of a superconducting material or a normal-conducting metal material.

[0029] In one example, the multiple second parallel ridges 62 and the superconducting layer 64 are formed from the same material. In this example, the multiple second parallel ridges 62 can be formed by partially etching the superconducting material layer placed on the insulating layer 66. For example, by depositing a superconducting layer, forming a photoresist pattern having a pattern to protect the ridge pattern on the superconducting material, partially etching the superconducting material layer to leave the multiple second parallel ridges 62, and then removing the photoresist layer, the multiple second parallel ridges 62 placed on the superconducting layer 62 can be provided.

[0030] In another example, the multiple second parallel ridges 62 are formed from a different material than the superconducting layer 64. In this alternative example, the multiple second parallel ridges 62 may be formed by depositing a superconducting material or a normal-conducting metal layer on the superconducting layer 64, forming a photoresist pattern with ridge pattern openings on the superconducting material or normal-conducting metal layer, depositing a second material different from the superconducting material that forms the multiple second parallel ridges 62 on the photoresist material, and then performing a lift-off process to remove the photoresist material and excess second material, leaving the multiple second parallel ridges 62 on the superconducting layer 64.

[0031] Figure 6 shows a low-temperature portion or tip 60 covering a high-temperature portion or tip 40 for forming a solid point cooler by a flip-chip vacuum coupling process. Multiple second parallel ridges 62 are aligned and oriented orthogonally with respect to multiple first parallel ridges 48. By moving the low-temperature portion 60 along arrow A and / or the high-temperature portion 40 along arrow B, the multiple first parallel ridges 48 engage with the multiple second parallel ridges 62, and the low-temperature portion 60 is joined to the high-temperature portion 40 at multiple grid point contacts 80, shown in Figure 7 as a cross-sectional view along line CC in Figure 6. Despite the small size and narrow spacing of the grid point contacts 80, there is a large tolerance for misalignment during joining. All grid point contacts perform the same function regardless of their specific position between the tips. It is important to shorten the diffusion path to minimize the attenuation of quasiparticles during diffusion. The quasiparticles transport the waste heat from the cooler to the normal-conducting metal heat sink layer 44. As the quasiparticles decay, waste heat may leak into the lower temperature portion 60. The solid point cooling system utilizes the translational invariance of this function to construct a fine, high-density point-contact grid using an existing toolset.

[0032] Figure 8 shows a block diagram of a refrigeration system 110 using solid-state devices such as the solid-state device 10 in Figure 1. The refrigeration system 110 includes a number of stages, indicated as stages #1 to #N, where N is an integer greater than or equal to 2. Each refrigeration stage provides an additional temperature drop from the preceding stage, with the Nth stage being the final stage, resulting in the final temperature drop and lowest temperature of the refrigeration system 110. In other examples, the Nth stage is not the final stage, but rather the first or intermediate stage. Stage #N in the refrigeration system 110 includes a refrigeration container 120 formed of one or more refrigeration plates with a number of solid-state devices 122 similar to those shown in Figure 1. These multiple solid-state devices 122 surround the refrigeration container 120 and cooperate to bring about the final lowest temperature of the refrigeration system 110 within the refrigeration container 120. The container 120 may be located in a vacuum environment and may be configured to house superconducting circuits. In another example, one or more of the other stages result in a gradual temperature reduction throughout the refrigeration system 110 by using multiple solid devices similar to those in stage #N. In yet another example, the refrigeration container 120 and / or refrigeration plate may be formed of a normal-conducting metal that provides the final normal-conducting metal layer for each solid device 122.

[0033] The above description is illustrative of the disclosure of the subject matter. It is, of course, impossible to describe every conceivable combination of components or methods for the purpose of illustrating the disclosure, and those skilled in the art will recognize that many more combinations and substitutions of the disclosure are possible. Accordingly, the disclosure is intended to encompass all such substitutions, variations, and modifications that fall within the scope of the application, including the appended claims. Where the disclosure or claims list elements such as “one,” “first,” or “another,” or their equivalents, it should be construed as including one or more such elements, and not as requiring or excluding two or more such elements. Where the term “includes” is used in either this specification or the claims, it is intended to be as comprehensive as the interpretation of the term “composes.” Finally, the term “based on” means based at least in part.

Claims

1. A solid cooling device, A first portion having a normal-conducting metal heat sink layer and a plurality of first parallel ridges disposed on the normal-conducting metal heat sink layer, A second portion having a normal-conducting metal layer-insulating layer-superconductor layer (NIS) junction and a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction, wherein the plurality of first parallel ridges contact and are perpendicular to the plurality of second parallel ridges, thereby providing a plurality of lattice point contacts in the second portion, A solid cooling device equipped with the following features.

2. The solid cooling device according to claim 1, wherein the solid cooling device is configured to move quasiparticles from the normal-conducting metal layer of the NIS junction to the normal-conducting metal heat sink layer in response to an electric current flowing through the NIS junction.

3. The solid cooling device according to claim 2, further comprising an interface layer disposed between the plurality of first parallel ridges and the normal-conducting metal heat sink layer, which increases the contact area for the quasiparticles to spread and enter the normal-conducting metal heat sink layer.

4. The solid cooling device according to claim 3, wherein the interface layer is formed of the same material as the plurality of first parallel ridges.

5. The solid cooling device according to claim 3, wherein two or more of the materials forming the superconducting layer of the NIS junction, the plurality of second parallel ridges, the plurality of first parallel ridges, and the interface layer are formed of different superconducting materials that gradually reduce the superconducting energy band gap from the superconducting layer of the NIS junction to the interface layer.

6. The solid cooling device according to claim 1, wherein the plurality of first parallel ridges are formed of one of a superconducting material and a metal that contacts the trap, and the plurality of second parallel ridges are formed of a superconducting material.

7. The solid cooling device according to claim 1, wherein the plurality of first parallel ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm, and the plurality of second parallel ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm.

8. The solid cooling device according to claim 1, wherein the total contact area of ​​the plurality of lattice point junctions is less than 1% of the area of ​​the superconductor layer of the NIS junction and the area of ​​the normal-conducting metal heat sink layer.

9. The solid cooler according to claim 1, wherein the material of the normal conducting metal of the solid cooler is selected from the group including gold (Au), platinum (Pt), tungsten (W), titanium tungsten (TiW), copper (Cu), titanium (Ti), and chromium (Cr), and the material of the superconductor of the solid cooler is selected from the group including indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), tantalum (Ta), and vanadium (V).

10. A refrigeration system comprising a plurality of refrigeration stages, wherein the final stage comprises a refrigeration container formed from one or more plates, and a plurality of solid cooling devices disposed outside the refrigeration container, wherein the solid cooling devices are the solid cooling devices described in claim 1.

11. It is a freezing system, A freezer container formed from one or more plates, A plurality of solid cooling devices surrounding the outside of the aforementioned freezer container, wherein each of the plurality of solid cooling devices is A first portion having a normal-conducting metal heat sink layer, a superconductor interface layer disposed on the normal-conducting metal heat sink layer, and a plurality of first parallel superconductor ridges disposed on the superconductor interface layer, A second portion having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction and a plurality of second parallel superconductor ridges disposed on the superconductor layer of the NIS junction, wherein the plurality of first parallel superconductor ridges are in contact with and orthogonal to the plurality of second parallel superconductor ridges, thereby providing a plurality of lattice point contacts that provide a path for moving quasiparticles from the normal-conducting metal layer to the normal-conducting metal heat sink layer of the NIS junction in response to a critical current flowing through the NIS junction, A refrigeration system equipped with the following features.

12. The refrigeration system according to claim 11, wherein two or more of the materials forming the superconducting layer of the NIS junction, the plurality of second parallel superconducting ridges, the plurality of first parallel superconducting ridges, and the superconducting interface layer are formed of different superconducting materials that progressively reduce the superconducting energy band gap from the superconducting layer of the NIS junction to the superconducting interface layer.

13. The refrigeration system according to claim 11, wherein two or more of the materials forming the superconductor layer of the NIS junction, the plurality of second parallel superconductor ridges, the plurality of first parallel superconductor ridges, and the superconductor interface layer are formed of a normal conducting metal in contact with the trap.

14. The refrigeration system according to claim 11, wherein the plurality of first parallel superconducting ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm, and the plurality of second parallel superconducting ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm.

15. A method for forming a solid cooling device, The first chip is manufactured, Forming an interface layer on a normal-conducting metal heat sink layer, To form a plurality of first parallel ridges arranged on the interface layer, To manufacture the first chip including, The process involves creating a second chip, Forming a normal-conducting metal-insulator-superconductor (NIS) junction, To form a plurality of second parallel ridges arranged on the superconductor layer of the NIS junction, To manufacture the second chip including, In order to provide a plurality of lattice point contacts that provide a path for moving quasiparticles from the normal-conducting metal layer of the NIS junction to the normal-conducting metal heat sink layer in response to the critical current flowing through the NIS junction, the plurality of first parallel ridges contact and perpendicular to the plurality of second parallel ridges, the second chip or wafer is flip-chip or wafer-bonded onto the first chip, A method for providing this.

16. The method according to claim 15, wherein two or more of the materials forming the superconductor layer of the NIS junction, the plurality of second parallel ridges, the plurality of first parallel ridges, and the interface layer are formed of different superconducting materials that progressively reduce the superconducting energy band gap from the superconductor layer of the NIS junction to the interface layer.

17. The method according to claim 15, wherein forming a plurality of first parallel ridges disposed on the interface layer includes forming a pattern of photoresist having a pattern protecting the ridge pattern on the interface layer, partially etching the interface layer so as to leave the plurality of first parallel ridges, and removing the photoresist layer to provide the plurality of first parallel ridges and the interface layer remaining below the plurality of first parallel ridges.

18. The method according to claim 15, wherein forming a plurality of first parallel ridges disposed on the interface layer includes forming a pattern of photoresist having ridge pattern openings on the interface layer, depositing ridge material on the photoresist material, and leaving the plurality of first parallel ridges on the interface layer by performing a lift-off process to remove the photoresist material and excess ridge material.

19. The method according to claim 15, wherein forming a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction includes forming a pattern of photoresist having a pattern protecting the ridge pattern on the superconductor layer of the NIS junction, leaving the plurality of second parallel ridges by partially etching the superconductor layer of the NIS junction, and removing the photoresist layer to provide the plurality of second parallel ridges and the superconductor layer of the NIS junction remaining below the plurality of second parallel ridges.

20. The method according to claim 15, wherein forming a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction includes forming a pattern of photoresist having ridge pattern openings on the interface layer, depositing ridge material on the photoresist material, and leaving the plurality of first parallel ridges on the interface layer by performing a lift-off process to remove the photoresist material and excess ridge material.

Images