Solid cooling device with normal-conducting metal substrate

Abstract

A solid cooling device is provided. The solid cooling device comprises a first part having a normal-conducting metal heat sink layer and a second part having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction. The second part is coupled to the first part by a plurality of point contacts. The normal-conducting metal heat sink layer and / or the normal-conducting metal layer of the NIS junction is a normal-conducting metal substrate layer.

Description

Technical Field

[0001] The present invention generally relates to refrigeration, and more specifically to a solid cooling device with a superconducting metal substrate. This application claims the priority of U.S. Patent Application No. 18 / 363472, filed on August 1, 2023, the entire content of which is incorporated herein by reference.

Background Art

[0002] Solid-state electronic cooling by tunneling of "hot" electrons through a superconducting metal (normal metal)-insulator-superconductor (NIS) junction using a bias voltage has been demonstrated to operate below 1 K and behaves substantially like more common and expensive Peltier thermoelectric refrigerators near room temperature. These NIS cryocoolers are composed of the same materials and fabricated using the same lithography process as the Josephson junctions used in superconducting circuits and are essentially fully compatible with the components of Josephson junctions. They can be integrated and manufactured simultaneously with the Josephson junctions themselves. However, currently, the temperature range of NIS coolers is very limited, and the maximum temperature difference between the high-temperature side and the low-temperature side is about 150 mK.

[0003] One of the main limitations to the maximum performance of NIS coolers is the presence of non-equilibrium quasiparticles in the superconducting leads resulting from large currents flowing through the device. The low quasiparticle relaxation rate and thermal conductivity in superconductors couple these hot particles near the junction, leading to significant overheating of the superconducting electrodes. There are several ways to reduce the accumulation of quasiparticles in superconductors. The most common method is to use a normal metal coupled to the superconductor called a quasiparticle trap to move the quasiparticles to the normal metal and relax the energy through electron-electron and electron-phonon interactions. This device is called a normal metal-insulator-superconductor-normal metal (NISN) junction. However, the phonon heat generated within the quasiparticle trap can potentially return to the superconducting electrodes, which is a factor limiting the temperature difference between the high-temperature side and the low-temperature side of NISN junction solid coolers.

Summary of the Invention

[0004] In one embodiment, a solid cooling device is provided. The solid cooling device comprises a first part having a normal-conducting metal heat sink layer, and a second part having a normal-conducting metal layer-insulator layer-superconductor layer (NIS) junction and coupled to the first part by a plurality of point contacts. The normal-conducting metal heat sink layer and / or the normal-conducting metal layer of the NIS junction is a normal-conducting metal substrate layer.

[0005] In another embodiment, a refrigeration system is provided. The refrigeration system comprises a refrigeration container formed from one or more plates and a plurality of solid cooling devices surrounding the outside of the refrigeration container. Each of the plurality of solid cooling devices comprises a first portion having a normal-conducting metal heat sink substrate layer and a second portion having a normal-conducting metal substrate layer-insulator layer-superconductor layer (NIS) junction and coupled to the first portion by a plurality of point contacts. Both the normal-conducting metal heat sink substrate layer and the normal-conducting metal substrate layer of the NIS junction each have a thickness of about 100 μm to about 1500 μm. The plurality of point contacts provide a path for moving quasiparticles from the normal-conducting metal substrate layer of the NIS junction to the normal-conducting metal heat sink substrate layer in response to a critical current flowing through the NIS junction.

[0006] In yet another embodiment, a method for forming a solid cooling device is provided. The method comprises: fabricating a first chip, which includes forming an interface layer on a normal-conducting metal heat sink substrate layer; forming a second chip, which includes forming a normal-conducting metal substrate layer-insulator-superconductor (NIS) junction; and flip-chip bonding the second chip onto the first chip by a plurality of point contacts bonding the first chip to the second chip. The plurality of point contacts provide a path for moving quasiparticles from the normal-conducting metal substrate layer of the NIS junction to the normal-conducting metal heat sink substrate layer in response to a critical current flowing through the NIS junction. Both the normal-conducting metal heat sink substrate layer and the normal-conducting metal substrate layer of the NIS junction each have a thickness of about 100 μm to about 1500 μm. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a cross-sectional view showing an example of a solid point cooling device. [Figure 2] Figure 2 is a cross-sectional view showing an example of the high-temperature side or tip of a solid point cooler. [Figure 3] Figure 3 is a plan view of the high-temperature side portion or chip shown in Figure 2. [Figure 4] Figure 4 is a cross-sectional view showing an example of the low-temperature side or tip of a solid point cooler. [Figure 5] Figure 5 is a plan view of the low-temperature side portion or chip of Figure 4. [Figure 6] Figure 6 shows a diagram for forming a solid point cooler by joining using a flip-chip vacuum bonding process, and shows the high-temperature side portion or the low-temperature side portion or the chip that covers the chip. [Figure 7] Figure 7 is a cross-sectional view of the solid cooler after bonding along line CC in Figure 6. [Figure 8] Figure 8 is a block diagram showing a refrigeration system that uses solid-state devices, such as the solid-state device shown in Figure 1. [Modes for carrying out the invention]

[0008] This disclosure relates to a refrigeration system comprising a solid-state point cooler and a refrigeration container defined by refrigeration plates, and a plurality of solid-state coolers arranged around one or more refrigeration plates. The solid-state cooler may form the final refrigeration stage in a plurality of refrigeration stages to provide cooling down to a millikelvin temperature. The solid-state cooler is formed by coupling a low-temperature portion (or low-temperature chip) having a normal-conducting metal-insulator-superconductor (NIS) junction to a high-temperature portion (or high-temperature chip) having a normal-conducting metal heatsink portion through a plurality of contacts such as grid point contacts, bump junctions, or other types of point contacts. The normal-conducting metal layer of the NIS junction is formed from a thick normal-conducting metal substrate, and / or the normal-conducting metal heatsink portion is formed from a thick normal-conducting metal substrate. The normal-conducting metal is a metal that does not superconduct at a given cryogenic operating temperature.

[0009] A point cooler is a novel type of solid cooler based on a normal-conducting / insulating / superconductor (NIS) tunnel junction. An example of a point cooler can be found in U.S. Patent No. 11,333,413 by the same applicant, titled "Solid-state Cooler Device," the entirety of which is incorporated herein by reference. A point cooler uses two chips (or parts) connected by a number of small contacts. The low-temperature chip includes an NIS cooler junction and is in contact with a cooled payload. The high-temperature chip includes a heat sink (or quasi-particle trap) which dissipates waste heat to another refrigerator providing a subsequent cooling stage.

[0010] Solid coolers with a normal-conducting metal substrate are constructed on a normal-conducting metal substrate rather than on a silicon wafer. Typically, point coolers are constructed on a silicon substrate using standard silicon integrated circuit tools and processes. Solid coolers with a normal-conducting metal substrate offer cost advantages due to the use of less expensive materials. A thick normal-conducting metal substrate allows for efficient heat transfer between phonons and electrons. The temperature of the cooler body approaches the electron temperature on both the low-temperature body (payload) side and the high-temperature heatsink side. The strong coupling between the end plates of the cooler and the internal electron temperature allows multiple coolers to operate in parallel, enabling them to extract a large amount of heat from a 50mK body (payload) while sharing a single bias current as coolers in a series circuit. The thickness of each normal-conducting metal substrate can range from approximately 100μm to 1500μm. Normal-conducting metal substrates are used in power silicon devices and can be formed from normal-conducting metals such as gold (Au), platinum (Pt), tungsten (W), titanium-tungsten (TiW), copper (Cu), doped superconducting materials, or metals above their superconducting transition temperature, such as titanium or chromium, or combinations thereof.

[0011] The large-area geometric contact between the NIS junction superconductor and the coupled normal-conducting metal heatsink can lead to leakage of hot phonons back into the NIS junction superconductor and normal-conducting metal layer, which is expected to significantly limit the performance of the solid-state cooler. By modifying the geometric shape and reducing the contact area by using point contacts, the thermal boundary resistance (TBR) present between the superconductor layer and the normal-conducting metal heatsink is utilized, thereby reducing back-leaking heat from the normal-conducting metal heatsink to the NIS junction superconductor layer. This makes it possible to raise the exhaust temperature compared to conventional NIS or NISN coolers by reducing back-leaking heat from the high-temperature exhaust side without hindering the thermal rise of quasiparticles when the normal-conducting metal heatsink functions as a quasiparticle trap.

[0012] Examples in Figures 1 to 7 provide a structure and method for manufacturing a point cooler that uses multiple narrow parallel ridges arranged as orthogonal lines in an intersecting pattern on both the high-temperature and low-temperature chips that are joined together. When pressed together, a grid of small-area grid point contacts arranged at narrow intervals is formed by the cross-shaped ridges. The grid point contacts provide a short path for the diffusion of high-temperature quasiparticles from the low-temperature chip to the high-temperature chip. The dense pattern of grid point contacts provides a short diffusion path length for the high-temperature quasiparticles to efficiently conduct waste heat from the low-temperature body side to the high-temperature heat sink. However, as mentioned above, other point contact structures, such as those shown in U.S. Patent No. 11,333,413, or simple bump joints, can also be used to join the low-temperature portion to the high-temperature portion, each with its own advantages.

[0013] Multiple parallel ridges offer an improvement over bump junctions by allowing for the patterning of smaller ridge structures at smaller pitches than standard lift-off processes, which are generally considered optimal for large metal structures. Point coolers utilize the different properties and functions of point cooler grid point junctions compared to integrated circuit flip-chip junctions. All point cooler grid point junctions function in parallel to transport quasiparticles from the cold side chip to the hot side chip. Since any junction forms a grid point junction, it is not necessary to connect a specific point on the cold side to a precise location on the hot side.

[0014] In certain manufacturing processes, when using a metal lift-off deposition process, bump bonding may be limited to 1 μm bumps on a 10 μm grid. For example, a cross-shaped intersecting ridge can be etched as a 0.25 μm contact on a 2.5 μm grid. For instance, a 0.25 μm aluminum (Al) ridge can be dry-etched at any pitch larger than 0.5 μm. The dense pitch of these dry-etched ridges allows for more efficient utilization of the bonding area, thereby increasing the overall chip bonding contact area and, consequently, the bonding shear strength.

[0015] Solid point coolers can be configured to raise waste heat to higher exhaust temperatures than when using bump bonding. At higher exhaust temperatures, the density of thermally activated quasiparticles (QPs) increases, which shortens the quasiparticle diffusion decay length. As QP decays, waste heat accumulates on the cooler side, degrading the cooler's performance. A shorter diffusion path reduces QP decay on the cooler side, thereby allowing the cooler to operate efficiently at higher heatsink temperatures.

[0016] Point coolers with point contacts are intended to cool solids to operating temperatures below 2 Kelvin (K). Point coolers with point contacts utilize established materials and processes suitable for silicon CMOS equipment using materials such as tungsten (W), titanium tungsten (TiW), aluminum (Al), niobium (Nb), and Nb / aluminum oxide (AlOx) / Al tunnel junctions. Point coolers with point contacts can provide continuous cooling when a DC bias current of several amperes is applied across a single large tunnel junction, resulting in a thermal rise of tens of microwatts in a small 1 square centimeter assembly. Ten thousand of these point coolers with grid point contacts can cover an area of ​​approximately 1 square meter by placing them on or between one or more of the two copper sheets in the final stage of a refrigeration system, providing a significant thermal rise at 50 mK.

[0017] Point coolers can be formed from various normal-conducting metallic and superconducting materials. Normal-conducting metals can be selected from materials such as gold (Au), platinum (Pt), tungsten (W), titanium-tungsten (TiW), copper (Cu), doped superconducting materials, metals exceeding their superconducting transition temperature such as titanium or chromium, or combinations thereof. Superconducting materials can be selected from materials such as indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), tantalum (Ta), vanadium (V), or other doped or undoped superconducting materials.

[0018] A point cooler with a point contact provides a solid-state device that replaces conventional dilution refrigerators based on expensive helium-3. Also, this point cooler provides an alternative to adiabatic demagnetization refrigerators (ADRs). A point cooler with a lattice point contact can provide continuous cooling power as long as a DC current is applied to the NIS tunnel junction. An ADR has a single-shot operation. After cooling until the fixed capacity of the cooling salt is exhausted, an ADR requires another heating and cooling cycle.

[0019] FIG. 1 shows a cross-sectional view of an example of a solid-state point cooling device 10. The solid-state point cooling device 10 can be configured as a refrigeration stage used for cryogenic cooling applications. In cryogenic cooling applications, the solid structure is one of a plurality of solid cooling devices arranged around a refrigeration container that is located in a vacuum and holds a superconducting circuit. The plurality of solid structures provide the final stage of a cryogenic refrigeration system, removing heat from the low-temperature side refrigeration stage to enable efficient cooling, and preventing the return of heat from the high-temperature side refrigeration stage of the final stage within the plurality of refrigeration stages.

[0020] The solid-state point cooling device includes a low-temperature side portion 14 and a high-temperature side portion 12. The high-temperature side portion 12 includes a normal-conducting metal heat sink substrate layer 18, an interface layer 20 located on the normal-conducting metal heat sink substrate layer 18, and a plurality of first parallel superconductors or normal-conducting metal ridges 22 that are spaced apart from each other and located on the interface layer 20. The plurality of first parallel ridges 22 are arranged on the interface layer 20 and are spaced apart from each other at substantially equal distances. The plurality of first parallel superconducting ridges 22 can have a width of about 50 nm to about 500 nm (e.g., a width of about 250 nm) and can be spaced apart from each other at an interval of about 1 μm to about 5 μm (e.g., an interval of about 2.5 μm). The interface layer 20 can be formed of a superconducting material or a normal-conducting metal material. The interface layer 20 increases the contact area for quasiparticles to spread and enter the normal-conducting metal heat sink layer 18. The normal-conducting metal heat sink substrate layer 18 has a thickness of about 100 μm to about 1500 μm compared to a thickness of about 0.1 μm to about 1.5 μm in a typical normal-conducting metal heat sink layer.

[0021] The low-temperature side portion 14 includes the NIS junction 16. The NIS junction 16 includes a normal-conducting metal substrate layer 30, an insulator layer 28 disposed on the normal-conducting metal substrate layer 30, and a superconductor layer 26 disposed on the insulator layer 28. Compared with the thickness of about 0.1 μm to about 1.5 μm in the normal-conducting metal layer of a typical NIS junction, the normal-conducting metal substrate layer 30 has a thickness of about 100 μm to about 1500 μm. A plurality of second parallel superconductor ridges 24 are disposed on the superconductor layer 26 and are spaced apart from each other at substantially equal distances.

[0022] In one example, the plurality of first parallel superconductor ridges 22 and / or the plurality of second parallel superconductor ridges 24 may not exhibit superconductivity and may be formed of a normal-conducting metal material. The plurality of second parallel superconductor ridges 26 may have a width of about 50 nm to about 500 nm (e.g., a width of about 250 nm) and may be spaced apart from each other at an interval of about 1 μm to about 5 μm (e.g., an interval of about 2.5 μm). The plurality of second parallel superconductor ridges 24 are coupled to the plurality of first superconductor ridges, for example, in a vacuum bond. The plurality of second parallel superconductor ridges 24 and the plurality of first parallel superconductor or normal-conducting metal ridges 22 extend perpendicular to each other to form a plurality of lattice point contacts (see 80 in FIG. 7).

[0023] In one example, by injecting a cooling current (I COOLER )(e.g., a critical current) to flow through the NIS junction 16, the normal conductor can be cooled to 100 mK when hot electrons tunnel into the superconductor. The injected quasiparticles diffuse through the contact points between the ridges. In one example, the total contact area between the high-temperature side portion and the low-temperature side portion may be less than 1% of the chip areas of both the high-temperature side portion and the low-temperature side portion. By making the contacts smaller, it becomes possible to bring the contacts closer to each other, and the path from the quasiparticle injection point on the low-temperature side to the heat sink on the high-temperature side is shortened. The return of heat extracted from the low-temperature side of the solid-state point cooling device is reduced by the decrease in the contact areas on the high-temperature side and the low-temperature side passing through the plurality of lattice point contacts.

[0024] In one example, multiple different superconducting materials may be used to form two or more of the superconducting layer 26, multiple second parallel ridges 24, multiple first parallel superconducting ridges 22, and interface layer 20. The multiple different superconducting materials may be selected to have energy band gaps that advance from a high-energy band gap to a low-energy band gap via a quasiparticle path as quasiparticles migrate through the NIS junction to the normal-conducting metal heat sink layer. For example, the superconducting layer 26 and the multiple second parallel ridges 24 may be formed from a first superconducting material having a first energy band gap, the multiple first parallel ridges 22 may be formed from a second superconducting material having a second energy band gap, and the interface layer 20 may be formed from a third superconducting material having a third energy band gap. The first energy band gap is higher than the second energy band gap, and the second energy band gap is higher than the third energy band gap.

[0025] In another example, the superconducting layer 26 may be formed of a first superconducting material, the plurality of second parallel ridges 24 may be formed of a second superconducting material, and the plurality of first parallel ridges 22 and interface layer 20 may be formed of a third superconducting material. In yet another example, the superconducting layer 26 and the plurality of second parallel ridges 24 may be formed of a first superconducting material, and the plurality of first parallel ridges 22 and interface layer 20 may be formed of a second superconducting material. In this case, the energy band gap of the first superconducting material is higher than the energy band gap of the second superconducting material. The type of superconducting material selected may be modified on the basis of achieving a desired multi-stage energy band gap. Some of these materials for variable multi-stage band gaps can be found in U.S. Patent No. 11,189,773 by the same applicant, titled “Superconductor Thermal Filter,” the entire contents of which are incorporated herein by reference.

[0026] For example, the first superconducting material has a coefficient of 2Δ = 30.5 × 10 -4The second superconducting material is formed from niobium (Nb) with a superconducting energy band gap of 10^2, and the second superconducting material has a band gap of 2Δ = 11.5 × 10^2. -4 Formed from tin (Sn) with a superconducting energy band gap of ev, the third superconducting material has a band gap of 2Δ = 3.4 × 10⁻¹⁰. -4 It is formed from aluminum (Al) having a superconducting energy band gap of eV. In yet another example, the first superconducting material is 2Δ = 3.4 × 10⁻¹⁰ -4 The second superconducting material is made of aluminum (Al) with a superconducting energy band gap of 10^2, and has a band gap of 2Δ = 2.7 × 10^2. -4 Formed from molybdenum (Mo) with a superconducting energy band gap of ev, the third superconducting material has a band gap of 2Δ = 1.2 × 10⁻¹⁰. -4 It is formed of titanium (Ti) having a superconducting energy band gap of eV. Note that various different superconducting materials can be used, as long as they are selected to gradually decrease the superconducting energy band gap from the normal-conducting metal layer 30 to the normal-conducting metal heat sink layer 18.

[0027] Figure 2 shows a cross-sectional view of an example of the high-temperature side portion or tip 40 of a solid point cooler. Figure 3 shows a plan view of the high-temperature side portion or tip 40 of Figure 2. The high-temperature side portion 40 includes a normal-conducting metal heat sink substrate layer 42, an interface layer 44 disposed thereon, and a plurality of first parallel ridges 46 disposed on the interface layer 44 at intervals from each other. The plurality of first parallel ridges 46 are disposed on the interface layer 44 and spaced approximately equidistant from each other, as described in Figure 1. The plurality of first parallel ridges 46 may be formed of a superconducting material or a normal-conducting metal. The interface layer 44 may be formed of a superconducting material or a normal-conducting metal material. The interface layer 44 increases the contact area for quasiparticles to spread and enter the plurality of first parallel ridges 46.

[0028] In one example, the multiple first parallel ridges 46 and the interface layer 44 are formed from the same superconducting material. In another example, the multiple first parallel ridges 46 and the interface layer 44 are formed from different superconducting materials, and the interface layer 44 is formed from a superconducting material having a lower band gap than the multiple first parallel ridges 46. In yet another example, the multiple first parallel ridges 46 are formed from a superconducting material layer, and the interface layer 44 is formed from a normal-conducting metal layer different from the normal-conducting metal forming the normal-conducting metal heat sink substrate layer 42. In yet another example, the multiple first parallel ridges 46 are formed from a normal-conducting metal material layer, and the interface layer 44 is formed from a normal-conducting metal layer different from the normal-conducting metal forming the normal-conducting metal heat sink substrate layer 42. In yet another example, the multiple first parallel ridges 46 are placed directly on the normal-conducting metal heat sink substrate layer 42, and the interface layer 44 is removed.

[0029] Multiple first parallel ridges 46 can be formed by depositing a superconducting material or a normal-conducting metal layer on a normal-conducting metal heat sink substrate layer 42, forming a photoresist pattern having a pattern to protect the ridge pattern on the superconducting material or normal-conducting metal layer, partially etching the superconducting material layer to leave the multiple first parallel ridges 46, and then removing the photoresist layer to provide the multiple first ridges 46 and the interface layer 44 beneath the multiple first parallel ridges 46. In another example, the multiple first parallel ridges 46 and the interface layer 44 are formed from different materials. In this alternative example, multiple first parallel ridges 46 may be formed by depositing a superconducting material or a normal-conducting metal layer on a normal-conducting metal heat sink substrate layer 42 to form an interface layer 44, forming a photoresist pattern having ridge pattern openings on the superconducting material or normal-conducting metal layer, depositing a second material different from the material forming the interface layer 44 on the photoresist material, and then performing a lift-off process to remove the photoresist material and excess second material, leaving multiple first parallel ridges 46 on the interface layer 44.

[0030] Figure 4 shows a cross-sectional view of an example of the low-temperature portion or tip 60 of a solid point cooler. Figure 5 shows a plan view of the low-temperature portion or tip 60 of Figure 4. The low-temperature portion 60 includes a NIS junction 72. The NIS junction 72 includes a normal-conducting metal substrate layer 68, an insulating layer 66 disposed on the normal-conducting metal substrate layer 68, and a superconducting layer 64 disposed on the insulating layer 66. A plurality of second parallel ridges 62 are arranged on the superconducting layer 64 and are spaced approximately equidistant from one another. The plurality of second parallel ridges 62 may be formed of a superconducting material or a normal-conducting metal material.

[0031] In one example, the multiple second parallel ridges 62 and the superconducting layer 64 are formed from the same material. In this example, the multiple second parallel ridges 62 can be formed by partially etching a superconducting material layer placed on an insulating layer 66. For example, a superconducting layer can be deposited, a photoresist pattern having a pattern to protect the ridge pattern can be formed on the superconducting material, the superconducting material layer can be partially etched to leave the multiple second parallel ridges 62, and then the photoresist layer can be removed to provide the multiple second parallel ridges 62 to be placed on the superconducting layer 64.

[0032] In another example, the multiple second parallel ridges 62 are formed from a different material than the superconducting layer 64. In this alternative example, the multiple second parallel ridges 62 may be formed by depositing a superconducting material or a normal-conducting metal layer on the superconducting layer 64, forming a photoresist pattern with ridge pattern openings on the superconducting material or normal-conducting metal layer, depositing a second material different from the superconducting material that forms the multiple second parallel ridges 62 on the photoresist material, and then performing a lift-off process to remove the photoresist material and excess second material, leaving the multiple second parallel ridges 62 on the superconducting layer 64.

[0033] Figure 6 shows a low-temperature portion or chip 60 covering a high-temperature portion or chip 40 for forming a solid point cooler by a flip-chip vacuum coupling process. Multiple second parallel ridges 62 are aligned and oriented orthogonally with respect to multiple first parallel ridges 46. By moving the low-temperature portion 60 along arrow A and / or the high-temperature portion 40 along arrow B, the multiple first parallel ridges 46 engage with the multiple second parallel ridges 62, and the low-temperature portion 60 is joined to the high-temperature portion 40 at multiple grid point contacts 80, shown in Figure 7 as a cross-sectional view along line CC in Figure 6. Despite the small size and narrow spacing of the grid point contacts 80, there is a large tolerance for misalignment during joining. All grid point contacts perform the same function regardless of their specific position between the chips. It is important to shorten the diffusion path to minimize the attenuation of quasiparticles during diffusion. The quasiparticles transport the waste heat from the cooler to the normal-conducting metal heat sink substrate layer 42. As the quasiparticles decay, waste heat may leak into the lower temperature portion 60. The solid point cooling system utilizes the translational invariance of this function to construct a fine, high-density point-contact grid using an existing toolset.

[0034] Figure 8 shows a block diagram of a refrigeration system 110 using solid-state devices such as the solid-state device 10 in Figure 1. The refrigeration system 110 includes a number of stages, indicated as stages #1 to #N, where N is an integer greater than or equal to 2. Each refrigeration stage provides an additional temperature drop from the preceding stage, with the Nth stage being the final stage, resulting in the final temperature drop and lowest temperature of the refrigeration system 110. In other examples, the Nth stage is not the final stage, but rather the first or intermediate stage. Stage #N in the refrigeration system 110 includes a refrigeration container 120 formed of one or more refrigeration plates with a number of solid-state devices 122 similar to those shown in Figure 1. These multiple solid-state devices 122 surround the refrigeration container 120 and cooperate to bring about the final lowest temperature of the refrigeration system 110 within the refrigeration container 120. The container 120 may be located in a vacuum environment and may be configured to house superconducting circuits. In another example, one or more of the other stages result in a gradual temperature reduction throughout the refrigeration system 110 by using multiple solid devices similar to those in stage #N. In yet another example, the refrigeration container 120 and / or refrigeration plate may be formed of a normal-conducting metal that provides the final normal-conducting metal layer for each solid device 122.

[0035] The above description is illustrative of the disclosure of the subject matter. It is, of course, impossible to describe every conceivable combination of components or methods for the purpose of illustrating the disclosure, and those skilled in the art will recognize that many more combinations and substitutions of the disclosure are possible. Accordingly, the disclosure is intended to encompass all such substitutions, variations, and modifications that fall within the scope of the application, including the appended claims. Where the disclosure or claims list elements such as “one,” “first,” or “another,” or their equivalents, it should be construed as including one or more such elements, and not as requiring or excluding two or more such elements. Where the term “includes” is used in either this specification or the claims, it is intended to be as comprehensive as the interpretation of the term “composes.” Finally, the term “based on” means based at least in part.

Claims

1. A solid cooling device, A first portion having a normal-conducting metal heat sink layer, A second portion having a normal-conducting metal layer-insulating layer-superconductor layer (NIS) junction and coupled to the first portion by a plurality of point contacts, A solid cooling device wherein the normal-conducting metal heat sink layer and / or the normal-conducting metal layer of the NIS junction is a normal-conducting metal substrate layer.

2. The solid cooling apparatus according to claim 1, wherein the normal-conducting metal substrate layer has a thickness of about 100 μm to about 1500 μm.

3. The solid cooling device according to claim 1, wherein the normal-conducting metal material of the solid cooling device is selected from the group including gold (Au), platinum (Pt), tungsten (W), titanium tungsten (TiW), copper (Cu), titanium (Ti), silver (Ag), and chromium (Cr).

4. The solid cooler according to claim 1, wherein the superconducting material of the solid cooler is selected from the group comprising indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), tantalum (Ta), and vanadium (V).

5. The solid cooling device according to claim 1, further comprising an interface layer disposed between the plurality of point contacts and the normal-conducting metal heat sink layer, which increases the contact area for quasiparticles to spread and enter the normal-conducting metal heat sink layer.

6. The NIS junction further comprises a plurality of first parallel ridges located above the normal-conducting metal heat sink layer and a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction. The solid cooling device according to claim 5, wherein the plurality of first parallel ridges contact and orthogonally intersect with the plurality of second parallel ridges, thereby providing a plurality of grid point contacts corresponding to the plurality of point contacts.

7. The solid cooling device according to claim 6, wherein two or more of the materials forming the superconducting layer of the NIS junction, the plurality of second parallel ridges, the plurality of first parallel ridges, and the interface layer are formed of normal-conducting metals, or are formed of different superconducting materials that stepwise reduce the superconducting energy band gap from the superconducting layer of the NIS junction to the interface layer.

8. The solid cooling device according to claim 7, wherein the plurality of first parallel ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm, and the plurality of second parallel ridges have a width of about 50 nm to about 500 nm and are spaced apart from each other at intervals of about 1 μm to about 5 μm.

9. The solid cooling device according to claim 1, wherein the solid cooling device is configured to move quasiparticles from the normal-conducting metal layer of the NIS junction to the normal-conducting metal heat sink layer in response to an electric current flowing through the NIS junction.

10. A refrigeration system comprising a plurality of refrigeration stages, wherein the final stage comprises a refrigeration container formed from one or more plates, and a plurality of solid cooling devices disposed outside the refrigeration container, wherein the solid cooling devices are the solid cooling devices described in claim 1.

11. It is a freezing system, A freezer container formed from one or more plates, A plurality of solid cooling devices surrounding the outside of the aforementioned freezer container, wherein each of the plurality of solid cooling devices is A first portion having a normal-conducting metal heat sink substrate layer, A second portion having a normal-conducting metal substrate layer-insulating layer-superconductor layer (NIS) junction and coupled to the first portion by a plurality of point contacts, A refrigeration system in which both the normal-conducting metal heat sink substrate layer and the normal-conducting metal substrate layer of the NIS junction each have a thickness of about 100 μm to about 1500 μm, and the plurality of point contacts provide a path for moving quasiparticles from the normal-conducting metal substrate layer of the NIS junction to the normal-conducting metal heat sink substrate layer in response to a critical current flowing through the NIS junction.

12. The refrigeration system according to claim 10, wherein the normal conducting metal material of each of the plurality of solid cooling devices is selected from the group including gold (Au), platinum (Pt), tungsten (W), titanium tungsten (TiW), copper (Cu), titanium (Ti), silver (Ag), and chromium (Cr), and the superconducting material of the solid cooling device is selected from the group including indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), tantalum (Ta), and vanadium (V).

13. The refrigeration system according to claim 10, further comprising, for each of the plurality of solid cooling devices, an interface layer disposed between the plurality of point contacts and the normal-conducting metal heat sink layer, which increases the contact area for quasiparticles to spread and enter the normal-conducting metal heat sink layer.

14. The refrigeration system according to claim 12, wherein each of the plurality of solid cooling devices further comprises a plurality of first parallel ridges located above the normal-conducting metal heat sink layer and a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction, and the plurality of first parallel ridges contact and orthogonal to the plurality of second parallel ridges, thereby providing a plurality of grid point contacts corresponding to the plurality of point contacts.

15. The refrigeration system according to claim 13, wherein, for each of the plurality of solid cooling devices, two or more of the materials forming the superconducting layer of the NIS junction, the plurality of second parallel ridges, the plurality of first parallel ridges, and the interface layer are formed of a normal conducting metal, or are formed of different superconducting materials that gradually reduce the superconducting energy band gap from the superconducting layer of the NIS junction to the interface layer.

16. A method for forming a solid cooling device, Manufacturing a first chip or wafer, which includes forming an interface layer on a normal-conducting metal heat sink substrate layer, Forming a second chip or wafer, which includes forming a normal-conducting metal substrate layer-insulator-superconductor (NIS) junction, The flip-chip / wafer bonding of the first chip or wafer to the second chip or wafer by a plurality of point contacts connecting the first chip or wafer to the second chip or wafer, wherein the plurality of point contacts provide a path for moving quasiparticles from the normal-conducting metal substrate layer of the NIS bonding to the normal-conducting metal heat sink substrate layer in response to a critical current flowing through the NIS bonding, and both the normal-conducting metal heat sink substrate layer and the normal-conducting metal substrate layer of the NIS bonding each have a thickness of approximately 100 μm to approximately 1500 μm. A method for providing this.

17. The method according to claim 16, wherein the normal conducting metal material of each of the plurality of solid coolers is selected from the group including gold (Au), platinum (Pt), tungsten (W), titanium tungsten (TiW), copper (Cu), titanium (Ti), silver (Ag), and chromium (Cr), and the superconducting material of the solid cooler is selected from the group including indium (In), niobium (Nb), aluminum (Al), titanium (Ti), tin (Sn), molybdenum (Mo), tantalum (Ta), and vanadium (V).

18. The method according to claim 16, further comprising forming a plurality of first parallel ridges above the normal-conducting metal heat sink substrate layer and forming a plurality of second parallel ridges on the superconductor layer of the NIS junction, wherein the plurality of first parallel ridges contact and orthogonal to the plurality of second parallel ridges, thereby providing a plurality of lattice point contacts corresponding to the plurality of point contacts.

19. The method according to claim 18, wherein two or more of the materials forming the superconductor layer of the NIS junction, the plurality of second parallel ridges, the plurality of first parallel ridges, and the interface layer are formed of a normal conducting metal, or are formed of different superconducting materials that stepwise reduce the superconducting energy band gap from the superconductor layer of the NIS junction to the interface layer.

20. The method according to claim 18, wherein forming a plurality of first parallel ridges disposed on the interface layer includes forming a pattern of photoresist having a pattern protecting the ridge pattern on the interface layer, partially etching the interface layer so as to leave the plurality of first parallel ridges, and removing the photoresist layer to provide the plurality of first parallel ridges and the interface layer remaining below the plurality of first parallel ridges, or forming a pattern of photoresist having ridge pattern openings on the interface layer, depositing ridge material on the photoresist material, and leaving the plurality of first parallel ridges on the interface layer by performing a lift-off process to remove the photoresist material and excess ridge material.

21. The method according to claim 18, wherein forming a plurality of second parallel ridges disposed on the superconductor layer of the NIS junction includes forming a pattern of photoresist having a pattern protecting the ridge pattern on the superconductor layer of the NIS junction, leaving the plurality of second parallel ridges by partially etching the superconductor layer of the NIS junction, and removing the photoresist layer to provide the plurality of second parallel ridges and the superconductor layer of the NIS junction remaining below the plurality of second parallel ridges, or forming a pattern of photoresist having ridge pattern openings on the interface layer, depositing ridge material on the photoresist material, and leaving the plurality of first parallel ridges on the interface layer by performing a lift-off process to remove the photoresist material and excess ridge material.

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