Display board and method for manufacturing the same, display device

Abstract

The present invention relates to a display board, a method for manufacturing the same, and a display device. The display board includes a plurality of subpixels, each subpixel includes a pixel driving circuit, each pixel driving circuit is connected to a data signal line and a compensation signal line, each pixel driving circuit includes at least a memory capacitor, each memory capacitor includes at least two stacked capacitor plates, the two capacitor plates are installed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, with the first distance being smaller than the second distance. According to the present invention, the influence of data voltage jumps on the data signal line on the memory capacitor can be reduced, and the influence of data voltage jumps on the normal operation of the pixel driving circuit can be avoided.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on August 10, 2023, with an application number of 202311018194.3 and an invention title of "Display Substrate, Its Manufacturing Method, and Display Device", and its content should be understood to be incorporated into this application by reference.

[0002] This disclosure relates to the field of display technology, but is not limited thereto, and particularly relates to a display substrate, its manufacturing method, and a display device.

Background Art

[0003] Organic Light Emitting Diode (abbreviated as OLED) and Quantum-dot Light Emitting Diodes (abbreviated as QLED) are active light-emitting display devices, and have advantages such as self-luminous, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightweight and thin, bendable, and low cost. With the continuous development of display technology, display devices that use OLED or QLED as light-emitting devices and perform signal control by Thin Film Transistor (abbreviated as TFT) have become the main products in the current display field.

Summary of the Invention

[0004] The following is an overview of the subject matter that will be described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a display board comprising a plurality of repeating units, at least one repeating unit comprising a plurality of subpixels forming at least two pixel rows and at least two pixel columns, at least one subpixel comprising a pixel driving circuit, the pixel driving circuit being connected to a data signal line and a compensation signal line, respectively, extending along the pixel column direction, the data signal line being configured to supply a data signal to the pixel driving circuit, the compensation signal line being configured to supply a compensation signal to the pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least two stacked capacitor plates, the two capacitor plates being installed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, the first distance being smaller than the second distance, and the first and second distances being sizes in the pixel row direction.

[0006] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.35 to 0.75.

[0007] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.6 to 0.7.

[0008] In an exemplary embodiment, the first distance is 5.5 μm to 6.5 μm, and the second distance is 8.5 μm to 9.5 μm.

[0009] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.4 to 0.5.

[0010] In an exemplary embodiment, the first distance is 5.5 μm to 6.5 μm, and the second distance is 12.5 μm to 13.5 μm.

[0011] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.65 to 0.75.

[0012] In an exemplary embodiment, the first distance is 8.5 μm to 9.5 μm, and the second distance is 12.5 μm to 13.5 μm.

[0013] In an exemplary embodiment, the two capacitor plates include a first plate and a second plate, the pixel driving circuit further includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor being connected to the data signal line, the second electrode of the first transistor being connected to the first plate and the gate electrode of the second transistor, respectively, the first electrode of the third transistor being connected to the compensation signal line, the second electrode of the third transistor being connected to the second plate and the second electrode of the second transistor, the second electrode of the third transistor having a first distance between the edge of the second plate closest to the compensation signal line and the edge of the compensation signal line closest to the second plate, and the second distance between the edge of the second plate closest to the data signal line and the edge of the data signal line closest to the second plate.

[0014] In an exemplary embodiment, the first transistor includes at least a first active layer, and the first active layer and the second electrode plate are connected to each other in an integrated structure.

[0015] In exemplary embodiments, the pixel driving circuit is further connected to a first power line extending along the pixel row direction, and at least one repeating unit includes one compensation signal line, two first power lines, and four data signal lines, wherein the one compensation signal line is located in the middle of the repeating unit in the pixel row direction, the two first power lines are located on either side of the repeating unit in the pixel row direction, two of the four data signal lines are located on the side of one first power line closer to the compensation signal line, and the other two of the four data signal lines are located on the side of the other first power line closer to the compensation signal line.

[0016] In an exemplary embodiment, the two first power lines include a first power line and a second power line installed sequentially along the pixel row direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line installed sequentially along the pixel row direction, the first data signal line is located on the side of the first power line closer to the compensation signal line, the second data signal line is located on the side of the first data signal line closer to the compensation signal line, the two capacitor plates are installed between the second data signal line and the compensation signal line, and there is a first distance between the edge of the capacitor plate closer to the compensation signal line and the edge of the compensation signal line closer to the capacitor plate. There is a second distance between the edge of the capacitor plate closest to the second data signal line and the edge of the second data signal line closest to the capacitor plate, the fourth data signal line is located on the side of the second first power line closest to the compensation signal line, the third data signal line is located on the side of the fourth data signal line closest to the compensation signal line, the two capacitor plates are installed between the third data signal line and the compensation signal line, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and there is a second distance between the edge of the capacitor plate closest to the third data signal line and the edge of the third data signal line closest to the capacitor plate.

[0017] In exemplary embodiments, the pixel driving circuit is further connected to a first power line extending along the pixel row direction, and at least one repeating unit includes two compensation signal lines, two first power lines, and four data signal lines, the four data signal lines located in the middle of the repeating unit in the pixel row direction, the two compensation signal lines located on either side of the repeating unit in the pixel row direction, and the two first power lines each located on the side of the four data signal lines closer to the compensation signal lines.

[0018] In an exemplary embodiment, the two compensation signal lines include a first compensation signal line and a second compensation signal line installed sequentially along the pixel row direction, the two first power lines include a first power line and a second power line installed sequentially along the pixel row direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line installed sequentially along the pixel row direction, the first power line is located on the side of the first data signal line closer to the first compensation signal line, the two capacitor plates are installed between the first compensation signal line and the first power line, the second power line is located on the side of the fourth data signal line closer to the second compensation signal line, and the two capacitor plates are installed between the second compensation signal line and the second power line.

[0019] In other embodiments, the disclosure further provides a display device comprising the display board described above.

[0020] In yet another aspect, the Disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of subpixels forming at least two pixel rows and at least two pixel columns, and the manufacturing method is A pixel driving circuit is formed in at least one subpixel, the pixel driving circuit is connected to a data signal line and a compensation signal line extending along the pixel row direction, the data signal line is configured to supply a data signal to the pixel driving circuit, and the compensation signal line is configured to supply a compensation signal to the pixel driving circuit, the pixel driving circuit includes at least a memory capacitor, the memory capacitor includes at least two stacked capacitor plates, the two capacitor plates are placed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, the first distance being smaller than the second distance, and the first and second distances being the size in the pixel row direction.

[0021] After reading and understanding the drawings and detailed explanations, one can then understand other aspects. [Brief explanation of the drawing]

[0022] The drawings are provided to provide a further understanding of the technical proposal of this disclosure, and are part of the specification, and together with the embodiments of this disclosure, they are intended to interpret the technical proposal of this disclosure and not to limit the technical proposal of this disclosure. The shapes and sizes of the parts in the drawings do not reflect actual proportions and are for schematic illustration of the contents of this disclosure. [Figure 1] This is a schematic diagram of the structure of a display device. [Figure 2] This is a schematic diagram of the planar structure of a display substrate in an exemplary embodiment of the present disclosure. [Figure 3] This is an equivalent circuit diagram of a pixel driving circuit in one repeating unit of an exemplary embodiment of the present disclosure. [Figure 4] This is a schematic diagram of the structure of the drive circuit layer in the display substrate of an embodiment of the present disclosure. [Figure 5]This is a schematic diagram after forming a first conductive layer pattern on the display substrate of the present disclosure. [Figure 6A] This is a schematic diagram after forming a second conductive layer pattern on the display substrate of the present disclosure. [Figure 6B] This is a schematic diagram after forming a second conductive layer pattern on the display substrate of the present disclosure. [Figure 7A] This is a schematic diagram after forming a semiconductor layer pattern on the display substrate of the present disclosure. [Figure 7B] This is a schematic diagram after forming a semiconductor layer pattern on the display substrate of the present disclosure. [[ID=cribed layer pattern on the display substrate of the present disclosure. [Figure 7C] This is a schematic diagram after forming a semiconductor layer pattern on the display substrate of the present disclosure. [Figure 8] This is a schematic diagram after forming a second insulating layer pattern on the display substrate of the present disclosure. <l substrate of the present disclosure. [Figure 9A] This is a schematic diagram after forming a third conductive layer pattern on the display substrate of the present disclosure. [Figure 9B] This is a schematic diagram after forming a third conductive layer pattern on the display substrate of the present disclosure. [Figure 10] This is a schematic diagram after forming a third insulating layer and a planar layer pattern on the display substrate of the present disclosure. [Figure 11A] This is a schematic diagram after forming a fourth conductive layer pattern on the display substrate of the present disclosure. [Figure 11B] . This is a schematic diagram after forming a fourth conductive layer pattern on the display substrate of the present disclosure. [Figure 12] This is a schematic diagram after forming a pixel definition layer pattern on the display substrate of the present disclosure. <l substrate of the present disclosure. [Figure 13] This is a schematic diagram of the structure of a driving circuit layer in another display substrate of an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0023] To further clarify the purpose, technical proposals, and advantages of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments can be carried out in many different forms. The methods and content can be transformed into various forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, embodiments and features of embodiments of this disclosure can be combined with each other.

[0024] The proportions in the drawings in this disclosure may, but are not limited to, those shown in the drawings for reference in actual processes. For example, the ratio of channel width to length, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels on the display substrate and the number of subpixels in each pixel are not limited to those shown in the drawings, and the drawings described in this disclosure are merely schematic diagrams of the structure. One aspect of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0025] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion regarding the constituent elements and do not limit them in terms of quantity.

[0026] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0027] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or an electrical connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the specific meaning of these terms in this disclosure depending on the specific context.

[0028] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0029] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be converted to each other, and the "source terminal" and the "drain terminal" can be converted to each other.

[0030] In this specification, "electrically connected" includes cases where components are connected via an element having an electrical function. The "element having an electrical function" is not particularly limited and only needs to be capable of transmitting and receiving electrical signals between the connected components. Examples of "elements having an electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements with different functions.

[0031] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0032] In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0033] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0034] In this disclosure, "approximately" means that the boundary is not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0035] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scanning driver, and a pixel array. The timing controller is connected to the data driver and the scanning driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), respectively. The scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), respectively. The pixel array may include a plurality of sub-pixels Pxij, each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scanning signal line, where i and j are natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The light-emitting unit may include at least a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scanning signal line and the j-th data signal line. In exemplary embodiments, the timing controller may provide the data driver with gray values ​​and control signals conforming to the data driver's specifications, and may also provide the scan driver with clock signals, scan start signals, etc., conforming to the scan driver's specifications. The data driver can use the gray values ​​and control signals received from the timing controller to generate data voltages supplied to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can use the clock signal to sample gray values ​​and apply data voltages corresponding to the gray values ​​to data signal lines D1 to Dn on a pixel row basis, where n is a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially supply scan signals having turn-on level pulses to scan signal lines S1 to Sm.For example, the scan driver may be configured in the form of a shift register and generate scan signals by sequentially transporting scan start signals, provided in the form of turn-on level pulses under the control of a clock signal, to the next level of circuitry, where m may be a natural number. In an exemplary embodiment, the pixel array may be mounted on a display board.

[0036] An exemplary embodiment of the present disclosure provides a display board comprising a plurality of repeating units, at least one repeating unit comprising a plurality of subpixels forming at least two pixel rows and at least two pixel columns, at least one subpixel comprising a pixel drive circuit, the pixel drive circuit being connected to data signal lines and compensation signal lines extending along the pixel column direction, the data signal lines being configured to supply data signals to the pixel drive circuit, the compensation signal lines being configured to supply compensation signals to the pixel drive circuit, the pixel drive circuit comprising at least a storage capacitor, the storage capacitor being at least The device includes two stacked capacitor plates, the two capacitor plates being positioned between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, wherein the first distance is smaller than the second distance, and the first and second distances are sizes in the pixel row direction.

[0037] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.35 to 0.75.

[0038] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.6 to 0.7.

[0039] In another exemplary embodiment, the ratio of the first distance to the second distance is 0.4 to 0.5.

[0040] In yet another exemplary embodiment, the ratio of the first distance to the second distance is 0.65 to 0.75.

[0041] In an exemplary embodiment, the pixel driving circuit is further connected to a first power line extending along the second direction, and at least one repeating unit includes one compensation signal line, two first power lines, and four data signal lines, wherein the one compensation signal line is located in the middle of the repeating unit in the first direction, the two first power lines are located on either side of the repeating unit in the first direction, two of the four data signal lines are located on the side of one first power line closer to the compensation signal line, and the other two of the four data signal lines are located on the side of the other first power line closer to the compensation signal line.

[0042] In an exemplary embodiment, the two first power lines include a first power line and a second power line installed sequentially along the first direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line installed sequentially along the first direction, the first data signal line is located on the side of the first power line closer to the compensation signal line, the second data signal line is located on the side of the first data signal line closer to the compensation signal line, the two capacitor plates are installed between the second data signal line and the compensation signal line, and there is a first distance between the edge of the capacitor plate closer to the compensation signal line and the edge of the compensation signal line closer to the capacitor plate. There is a second distance between the edge of the capacitor plate closest to the second data signal line and the edge of the second data signal line closest to the capacitor plate, the fourth data signal line is located on the side of the second first power line closest to the compensation signal line, the third data signal line is located on the side of the fourth data signal line closest to the compensation signal line, the two capacitor plates are installed between the third data signal line and the compensation signal line, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and there is a second distance between the edge of the capacitor plate closest to the third data signal line and the edge of the third data signal line closest to the capacitor plate.

[0043] In an exemplary embodiment, the pixel driving circuit is further connected to a first power line extending along the second direction, and at least one repeating unit includes two compensation signal lines, two first power lines, and four data signal lines, the four data signal lines located in the middle of the repeating unit in the first direction, the two compensation signal lines located on either side of the repeating unit in the first direction, and the two first power lines each located on the side of the four data signal lines closer to the compensation signal lines.

[0044] In an exemplary embodiment, the two compensation signal lines include a first compensation signal line and a second compensation signal line installed sequentially along the first direction, the two first power lines include a first power line and a second power line installed sequentially along the first direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line installed sequentially along the first direction, the first power line is located on the side of the first data signal line closer to the first compensation signal line, the two capacitor plates are installed between the first compensation signal line and the first power line, the second power line is located on the side of the fourth data signal line closer to the second compensation signal line, and the two capacitor plates are installed between the second compensation signal line and the second power line.

[0045] The display substrate of this disclosure will be described below by several exemplary embodiments.

[0046] Figure 2 is a schematic diagram of the planar structure of a display substrate in an exemplary embodiment of the present disclosure. As shown in Figure 2, in the exemplary embodiment, the display substrate may include a plurality of repeating units 100 in a direction parallel to the display substrate, and at least one repeating unit 100 may include a plurality of subpixels forming at least two pixel rows and at least two pixel columns. In the exemplary embodiment, the repeating units are basic units constituting the display substrate and constitute the display substrate by being repeatedly and continuously installed along at least one direction, that is, the display substrate is formed by joining a plurality of repeating units.

[0047] In an exemplary embodiment, one repeating unit 100 may include four subpixels, the four subpixels may include a first subpixel P1 that emits a first color ray, a second subpixel P2 that emits a second color ray, a third subpixel P3 that emits a third color ray, and a fourth subpixel P4 that emits a fourth color ray, and the four subpixels may be arranged in a square pattern, which can effectively increase the aperture ratio and the light transmission area.

[0048] In an exemplary embodiment, in at least one repeating unit 100, a second subpixel P2 may be located on the first direction X side of the first subpixel P1, a third subpixel P3 may be located on the second direction Y side of the first subpixel P1, and a fourth subpixel P4 may be located on the first direction X side of the third subpixel P3. Multiple subpixels sequentially located along the first direction X may be called pixel rows, and multiple subpixels sequentially located along the second direction Y may be called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array, and the first direction X and the second direction Y intersect.

[0049] In exemplary embodiments, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, the third subpixel P3 may be a white subpixel (W) emitting white light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light. In some possible embodiments, the arrangement of the RBWG can be adjusted according to the actual needs, and this disclosure is not specifically limited herein.

[0050] In exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate may include at least a drive circuit layer mounted on the base and a light-emitting structure layer mounted on the side of the drive circuit layer away from the base. In at least one repeating unit, the drive circuit layer may include a plurality of circuit units, each circuit unit may include at least a pixel drive circuit, each pixel drive circuit being connected to a scan signal line and a data signal line, respectively, and the pixel drive circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and to output a current corresponding to a light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, each light-emitting unit may include at least a light-emitting device, each light-emitting device being connected to a pixel drive circuit of the circuit unit of the sub-pixel where it is located, and the light-emitting device being configured to emit light of a corresponding brightness in response to the current output by the pixel drive circuit of the sub-pixel where it is located.

[0051] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a drive circuit layer mounted on the base, a color film structure layer mounted on the side of the drive circuit layer away from the base, and a light-emitting structure layer mounted on the side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer may include a plurality of color film units, each color film unit may include at least a color filter layer, the color filter layer configured to emit light rays of a desired color from the corresponding subpixels.

[0052] In exemplary embodiments, the circuit unit referred to in this disclosure means a region divided according to a pixel driving circuit. The color film unit referred to in this disclosure means a region divided according to a color filter layer. The light-emitting unit referred to in this disclosure means a region divided according to a light-emitting device. The positions of the orthographic projections at the base of the circuit unit, the orthographic projections at the base of the color filter layer, and the orthographic projections at the base of the light-emitting unit may or may not correspond.

[0053] In exemplary embodiments of this disclosure, the positions of the orthographic projections on the base of the circuit unit, the color filter layer, and the light-emitting unit correspond one-to-one, and the circuit unit, color film unit, and light-emitting unit constitute subpixels. Therefore, hereafter, the circuit unit, color film unit, and light-emitting unit will be consistently referred to as subpixels.

[0054] Figure 3 is an equivalent circuit diagram of a pixel driver circuit in one repeating unit of an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driver circuits, the four pixel driver circuits may be arranged in a square configuration, and the pixel driver circuits may have a 3T1C structure.

[0055] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (first transistor T1, second transistor T2, and third transistor T3) and one memory capacitor C, and the pixel driving circuit is connected to the scan signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53, respectively.

[0056] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the memory capacitor C, respectively, while the second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the memory capacitor C, respectively.

[0057] In an exemplary embodiment, the first end of the memory capacitor C is connected to the first node N1, the second end of the memory capacitor C is connected to the second node N2, and the memory capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0058] In the exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor.

[0059] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 30, the first electrode of the first transistor T1 is connected to the data signal line 52, and the second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs the data signal from the data signal line 52 to the gate electrode of the second transistor T2.

[0060] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power line 51, and the second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received by its gate electrode.

[0061] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the scan signal line 30, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, thereby compensating for the threshold voltage Vth.

[0062] In the exemplary embodiment, in the pixel driving circuit for at least one subpixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0063] In an exemplary embodiment, in a plurality of pixel driving circuits for at least one pixel row, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0064] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0065] In exemplary embodiments, the light-emitting device EL may be an OLED including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to a second node N2, and the second electrode of the light-emitting device EL is connected to a second power line VSS, and the light-emitting device EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2. In exemplary embodiments, the first electrode may be an anode and the second electrode may be a cathode. Alternatively, the first electrode may be a cathode and the second electrode may be an anode.

[0066] In an exemplary embodiment, the signal on the first power line 51 is a continuously supplied high-level signal, and the signal on the second power line VSS is a continuously supplied low-level signal.

[0067] In exemplary embodiments, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In some possible implementations, the first to third transistors T1 to T3 may include both P-type and N-type transistors.

[0068] In exemplary embodiments, the first to third transistors T1 to T3 may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display properties.

[0069] Figure 4 is a schematic diagram of the structure of a drive circuit layer in a display substrate of an exemplary embodiment of the present disclosure, showing the structure of a pixel drive circuit in one repeating unit (four subpixels) of a bottom emission display substrate. In the exemplary embodiment, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square manner, each subpixel including a pixel drive circuit.

[0070] In exemplary embodiments, at least one repeating unit may include one scan signal line 30, two first power lines 51, four data signal lines 52, and one compensation signal line 53, the signal lines being connected to pixel drive circuits in the corresponding subpixels, respectively. The scan signal line 30 is configured to supply scan signals to the pixel drive circuits, the first power lines 51 are configured to supply power signals to the pixel drive circuits, the data signal lines 52 are configured to supply data signals to the pixel drive circuits, and the compensation signal line 53 is configured to supply compensation signals to the pixel drive circuits.

[0071] In an exemplary embodiment, the shape of the scanning signal line 30 may be linear, with the main body extending along the first direction X (pixel row direction), and the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be linear, with the main body extending along the second direction Y (pixel column direction), and the first direction X and the second direction Y intersect. In exemplary embodiments, the scan signal line 30 may be located in the middle of the second direction Y of the repeating unit, one compensation signal line 53 may be located in the middle of the first direction X of the repeating unit, two first power lines 51 may be located on both sides of the first direction X of the repeating unit, four data signal lines 52 and the compensation signal line 53 may be located between the two first power lines 51, two of the four data signal lines 52 may be located on the side of one first power line 51 closer to the compensation signal line 53, and the other two of the four data signal lines 52 may be located on the side of the other first power line 51 closer to the compensation signal line 53. Thus, a single scan signal line 30 extending along the first direction X can form two pixel rows, and a single compensation signal line 53 extending along the second direction Y can form two pixel columns, thereby forming the first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4 of a repeating unit.

[0072] In an exemplary embodiment, in at least one repeating unit, the first subpixel P1 and the third subpixel P3 may be mirror-symmetric with respect to the scan signal line 30, the second subpixel P2 and the fourth subpixel P4 may be mirror-symmetric with respect to the scan signal line 30, the first subpixel P1 and the second subpixel P2 may be mirror-symmetric with respect to the compensation signal line 53, and the third subpixel P3 and the fourth subpixel P4 may be mirror-symmetric with respect to the compensation signal line 53.

[0073] In an exemplary embodiment, the pixel driving circuit for at least one subpixel may include a first transistor, a second transistor, a third transistor, and a capacitor plate, each transistor may include an active layer, a gate electrode, a first electrode, and a second electrode, and the memory capacitor may include a first electrode 61 and a second electrode 62. In an exemplary embodiment, the first electrode of the first transistor is connected to a data signal line 52, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the second electrode 62 of the memory capacitor, respectively, the first electrode of the second transistor is connected to a first power line, the first electrode of the third transistor is connected to a compensation signal line 53, and the second electrode of the third transistor is connected to the second electrode of the second transistor and the first electrode 61 of the memory capacitor, respectively.

[0074] In an exemplary embodiment, in at least one subpixel, the first electrode plate 61 and the second electrode plate 62 may be placed between the data signal line 52 and the compensation signal line 53.

[0075] In exemplary embodiments, the two first power lines 51 in at least one repeating unit may include a first power line 51-1 and a second power line 51-2 that are installed sequentially along a first direction X, the first power line 51-1 may be installed on the opposite side of the repeating unit from the first direction X, and the second power line 51-2 may be installed on the side of the repeating unit from the first direction X. The four data signal lines 52 in at least one repeating unit may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3, and a fourth data signal line 52-4, which are sequentially installed along a first direction X, the first data signal line 52-1 and the second data signal line 52-2 may be installed between a first power line 51-1 and a compensation signal line 53, and the third data signal line 52-3 and the fourth data signal line 52-4 may be installed between a second power line 51-2 and a compensation signal line 53.

[0076] In an exemplary embodiment, the first data signal line 52-1 may be located on the side of the first power line 51-1 closer to the compensation signal line 53, the second data signal line 52-2 may be located on the side of the first data signal line 52-1 closer to the compensation signal line 53, and the first plate 61 and the second plate 62 may be installed between the second data signal line 52-2 and the compensation signal line 53. The fourth data signal line 52-4 may be located on the side of the second power line 51-2 closer to the compensation signal line 53, the third data signal line 52-3 may be located on the side of the fourth data signal line 52-4 closer to the compensation signal line 53, and the first plate 61 and the second plate 62 may be installed between the third data signal line 52-3 and the compensation signal line 53.

[0077] In an exemplary embodiment, in at least one subpixel, for at least one capacitor plate among the first plate 61 and the second plate 62, there is a first distance L1 between the edge of the capacitor plate closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the capacitor plate, and a second distance L2 between the edge of the capacitor plate closest to the data signal line 52 and the edge of the data signal line 52 closest to the capacitor plate, wherein the first distance L1 may be smaller than the second distance L2, and the first distance L1 and the second distance L2 may be the size of the first direction X.

[0078] In an exemplary embodiment, the ratio of the first distance L1 to the second distance L2 in at least one subpixel may be 0.35 to 0.75.

[0079] As shown in Figure 4, for the second electrode plate 62 in the first subpixel P1, there is a first distance L1 between the edge of the second electrode plate 62 closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the second electrode plate 62, and there is a second distance L2 between the edge of the second electrode plate 62 closest to the second data signal line 52-2 and the edge of the second data signal line 52-2 closest to the second electrode plate 62, and the ratio of the first distance L1 to the second distance L2 may be 0.6 to 0.7.

[0080] In an exemplary embodiment, the first distance L1 in the first subpixel P1 may be approximately 5.5 μm to 6.5 μm, and the second distance L2 may be approximately 8.5 μm to 9.5 μm. For example, the first distance L1 may be approximately 6 μm, and the second distance L2 may be approximately 9 μm.

[0081] As shown in Figure 4, for the second electrode plate 62 in the second subpixel P2, there is a first distance L1 between the edge of the second electrode plate 62 closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the second electrode plate 62, and there is a second distance L2 between the edge of the second electrode plate 62 closest to the third data signal line 52-3 and the edge of the third data signal line 52-3 closest to the second electrode plate 62, and the ratio of the first distance L1 to the second distance L2 may be 0.4 to 0.5.

[0082] In an exemplary embodiment, the first distance L1 in the second subpixel P2 may be approximately 5.5 μm to 6.5 μm, and the second distance L2 may be approximately 12.5 μm to 13.5 μm. For example, the first distance L1 may be approximately 6 μm, and the second distance L2 may be approximately 13 μm.

[0083] As shown in Figure 4, for the second electrode plate 62 in the third subpixel P3, there is a first distance L1 between the edge of the second electrode plate 62 closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the second electrode plate 62, and there is a second distance L2 between the edge of the second electrode plate 62 closest to the second data signal line 52-2 and the edge of the second data signal line 52-2 closest to the second electrode plate 62, and the ratio of the first distance L1 to the second distance L2 may be 0.65 to 0.75.

[0084] In an exemplary embodiment, the first distance L1 in the third subpixel P3 may be approximately 8.5 μm to 9.5 μm, and the second distance L2 may be approximately 12.5 μm to 13.5 μm. For example, the first distance L1 may be approximately 9 μm, and the second distance L2 may be approximately 13 μm.

[0085] In exemplary embodiments, the first transistor of each subpixel may include at least a first active layer 21, and the first active layer 21 and the second electrode plate 62 may be connected in an integrated structure.

[0086] The manufacturing process of a display substrate will be described below with illustrative examples. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, but is not limited to these. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the manufacturing process, the “thin film” may also be referred to as a “layer.” If the “thin film” requires a patterning process throughout the manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process includes at least one “pattern.” As described in this disclosure, “A and B are placed on the same layer” means that A and B are formed simultaneously by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0087] In an exemplary embodiment, taking four subpixels (first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4) of one repeating unit as an example, the manufacturing process of the display substrate according to this embodiment may include the following operations.

[0088] (1) Form a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 5, forming a first conductive layer pattern includes depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern on the base.

[0089] In exemplary embodiments, the first conductive layer of each subpixel on the display substrate may include at least a first connecting electrode 11, a second connecting electrode 12, and a first electrode plate 61 of a memory capacitor.

[0090] In exemplary embodiments, the shape of the first electrode plate 61 may be rectangular, chamfers may be provided on the corners of the rectangle, the first electrode plate 61 may be one of the transparent electrodes of a transparent memory capacitor, and the first electrode plate 61 is configured to form a transparent memory capacitor with a second electrode plate formed subsequently.

[0091] In exemplary embodiments, the first connecting electrode 11 and the second connecting electrode 12 may be located on either side of the first electrode plate 61 in the second direction Y, respectively.

[0092] In exemplary embodiments, in the first subpixel P1 and the second subpixel P2, the first connecting electrode 11 may be installed on the opposite side of the first electrode plate 61 in the second direction Y, and the second connecting electrode 12 may be installed on the side of the first electrode plate 61 in the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connecting electrode 11 may be installed on the side of the first electrode plate 61 in the second direction Y, and the second connecting electrode 12 may be installed on the opposite side of the first electrode plate 61 in the second direction Y.

[0093] In an exemplary embodiment, the shape of the first connecting electrode 11 may be a strip with a main body extending along a second direction Y, the first end of the first connecting electrode 11 is connected to the first electrode plate 61, the second end of the first connecting electrode 11 extends away from the second connecting electrode 12, and the first connecting electrode 11 is configured to be connected to a subsequently formed third connecting electrode.

[0094] In an exemplary embodiment, the shape of the second connecting electrode 12 may be a strip with a main body extending along the second direction Y, the first end of the second connecting electrode 12 is connected to the first electrode plate 61, the second end of the second connecting electrode 12 extends away from the first connecting electrode 11, and the second connecting electrode 12 is configured to be connected to a subsequently formed fourth connecting electrode.

[0095] In exemplary embodiments, in the first pixel row, the edge of the first connecting electrode 11 closest to the second pixel row may be essentially flush with the edge of the first electrode plate 61 closest to the second pixel row. In the second pixel row, the edge of the first connecting electrode 11 closest to the first pixel row may be essentially flush with the edge of the first electrode plate 61 closest to the first pixel row.

[0096] In exemplary embodiments, the first connecting electrode 11, the second connecting electrode 12, and the first electrode plate 61 of each subpixel may be an integrated structure connected to one another.

[0097] In exemplary embodiments, the positions of each pattern of the first conductive layer in the first subpixel P1 and the positions of each pattern of the first conductive layer in the third subpixel P3 may be basically mirror-symmetric with respect to a horizontal reference line, and the positions of each pattern of the first conductive layer in the second subpixel P2 and the positions of each pattern of the first conductive layer in the fourth subpixel P4 may be basically mirror-symmetric with respect to a horizontal reference line. The positions of each pattern of the first conductive layer in the first subpixel P1 and the positions of each pattern of the first conductive layer in the second subpixel P2 may be basically mirror-symmetric with respect to a vertical reference line, and the positions of each pattern of the first conductive layer in the third subpixel P3 and the positions of each pattern of the first conductive layer in the fourth subpixel P4 may be basically mirror-symmetric with respect to a vertical reference line. The horizontal reference line may be a straight line extending along a first direction X and bisecting the repeating unit in a second direction Y, and the vertical reference line may be a straight line extending along a second direction Y and bisecting the repeating unit in a first direction X.

[0098] In exemplary embodiments, the material of the first conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0099] (2) Forming a second conductive layer pattern. In exemplary embodiments, as shown in Figures 6A and 6B, forming a second conductive layer pattern may include depositing a second conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the second conductive thin film by a patterning process to form a second conductive layer. Figure 6B is a schematic diagram of the second conductive layer in Figure 6A. In exemplary embodiments, the second conductive layer may be referred to as a shielding layer.

[0100] In exemplary embodiments, the second conductive layer of each subpixel on the display substrate may include at least a third connecting electrode 13 and a fourth connecting electrode 14.

[0101] In exemplary embodiments, the shape of the third connecting electrode 13 may be block-shaped (e.g., rectangular), and the third connecting electrode 13 may be located on the side of the first electrode plate 61 away from the second connecting electrode 12, and the orthographic projection of the third connecting electrode 13 at the base at least partially overlaps with the orthographic projection of the first connecting electrode 11 at the base, and the third connecting electrode 13 directly overlaps with the first connecting electrode 11. In exemplary embodiments, the third connecting electrode 13 is configured, on the one hand, to connect to a subsequently formed fifth connecting electrode, and on the other hand, to reduce the effect of light irradiation on the characteristics of the second transistor by shielding the second transistor from light, reducing the intensity of light irradiated onto the second transistor, and reducing the leakage current of the second transistor.

[0102] In exemplary embodiments, the shape of the fourth connecting electrode 14 may be block-shaped (e.g., rectangular), the fourth connecting electrode 14 may be located on the side of the first electrode plate 61 away from the first connecting electrode 11, the orthographic projection of the base of the fourth connecting electrode 14 at least partially overlaps with the orthographic projection of the base of the second connecting electrode 12, the fourth connecting electrode 14 directly overlaps with the second connecting electrode 12, and the fourth connecting electrode 14 is configured to connect to a subsequently formed sixth connecting electrode.

[0103] In an exemplary embodiment, the second conductive layer of each repeating unit on the display board may include at least two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0104] In exemplary embodiments, the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be straight or bent with the main body extending along the second direction Y, the compensation signal line 53 may be located in the middle of the first direction X of the repeating unit, the first first power line 51 may be located on the opposite side of the first direction X of the repeating unit, the second first power line 51 may be located on the first direction X side of the repeating unit, two of the four data signal lines 52 may be located between the first first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 may be located between the second first power line 51 and the compensation signal line 53.

[0105] In an exemplary embodiment, a first power line 51 and a compensation signal line 53 can be formed to limit a first pixel row, and two data signal lines 52 are installed in the first pixel row. A second first power line 51 and a compensation signal line 53 can be formed to limit a second pixel row, and two data signal lines 52 are installed in the second pixel row.

[0106] In exemplary embodiments, the positions of the two first power lines 51 may be basically mirror-symmetric with respect to a vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the compensation signal line 53 may be basically mirror-symmetric with respect to a vertical reference line. The positions of the third and fourth connection electrodes 13 and 14 in the first subpixel P1 may be basically mirror-symmetric with respect to a horizontal reference line, and the positions of the third and fourth connection electrodes 13 and 14 in the second subpixel P2 may be basically mirror-symmetric with respect to a horizontal reference line.

[0107] In the exemplary embodiment, the first power line 51, data signal line 52, and compensation signal line 53 may be polylines of non-equal width. By employing polylines of variable width, not only is the layout of the pixel structure made easier, but parasitic capacitance can also be reduced.

[0108] (3) Forming a semiconductor layer pattern. In exemplary embodiments, as shown in Figures 7A and 7B, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base on which the aforementioned pattern has been formed, and then patterning the semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer placed on the first insulating layer. Figure 7B is a schematic diagram of the semiconductor layer in Figure 7A.

[0109] In an exemplary embodiment, the semiconductor layer of each subpixel on the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second plate 62 of a memory capacitor, the first active layer 21 may be the active layer of the first transistor T1, the second active layer 22 may be the active layer of the second transistor T2, the third active layer 23 may be the active layer of the third transistor T3, the second plate 62 may be the other transparent plate of a transparent memory capacitor, and the second plate 62 is configured to form a transparent memory capacitor with the first plate 61.

[0110] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 may be installed on the second direction Y side of the first electrode plate 61 of the subpixel, and the second active layer 22 may be installed on the opposite side of the second direction Y of the first electrode plate 61 of the subpixel.

[0111] In exemplary embodiments, for the first subpixel P1, the first active layer 21 may be installed on the side of the subpixel away from the second subpixel P2, and the third active layer 23 may be installed on the side of the subpixel closer to the second subpixel P2. For the second subpixel P2, the first active layer 21 may be installed on the side of the subpixel away from the first subpixel P1, and the third active layer 23 may be installed on the side of the subpixel closer to the first subpixel P1.

[0112] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 may be installed on opposite sides of the first electrode plate 61 of the subpixel in the second direction Y, and the second active layer 22 may be installed on the side of the first electrode plate 61 of the subpixel in the second direction Y.

[0113] In exemplary embodiments, for the third subpixel P3, the first active layer 21 may be installed on the side away from the fourth subpixel P4, and the third active layer 23 may be installed on the side closer to the fourth subpixel P4. For the fourth subpixel P4, the first active layer 21 may be installed on the side away from the third subpixel P3, and the third active layer 23 may be installed on the side closer to the third subpixel P3.

[0114] In exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions.

[0115] In an exemplary embodiment, the orthographic projection at the base of a first region of the first active layer 21 of each subpixel at least partially overlaps with the orthographic projection at the base of the corresponding data signal line 52, and the second region of the first active layer 21 is connected to the second electrode plate 62.

[0116] In an exemplary embodiment, the orthographic projection of the first region of the second active layer 22 of each subpixel does not overlap with the orthographic projection of the third connecting electrode 13 of the subpixel at the base, and the orthographic projections of the second region and channel region of the second active layer 22 at the base at least partially overlap with the orthographic projection of the third connecting electrode 13 at the base. As a result, the shielding layer, the third connecting electrode 13, shields the channel region of the second transistor T2, avoids the influence of light rays on the channel, and ensures the electrical characteristics of the second transistor T2.

[0117] In an exemplary embodiment, the orthogonal projection of the base of the first region of the third active layer 23 of each subpixel at least partially overlaps with the orthogonal projection of the base of the compensation signal line 53, and the orthogonal projection of the base of the second region of the third active layer 23 at least partially overlaps with the orthogonal projection of the base of the fourth connecting electrode 14 of the subpixel.

[0118] In the exemplary embodiment, the first region of the third active layer 23 in the first subpixel P1 and the first region of the third active layer 23 in the second subpixel P2 may be connected to each other, and the first region of the third active layer 23 in the third subpixel P3 and the first region of the third active layer 23 in the fourth subpixel P4 may be connected to each other.

[0119] In exemplary embodiments, the third active layer 23 in the first subpixel P1 and the third active layer 23 in the second subpixel P2 may be an integrated structure connected to each other, and the third active layer 23 in the third subpixel P3 and the third active layer 23 in the fourth subpixel P4 may also be an integrated structure connected to each other. In this disclosure, by arranging the third transistors of two adjacent subpixels in one pixel row to share the first region of the third active layer, the number of vias can be effectively reduced, the occupied area of ​​the pixel driving circuit can be reduced, which is advantageous for improving resolution, and the via connection structure can be reduced, simplifying the manufacturing process.

[0120] In exemplary embodiments, the shape of the second electrode plate 62 may be rectangular, chamfers may be provided on the corners of the rectangle, and it may be placed between the second active layer 22 and the third active layer 23 of the subpixel, the orthographic projection of the base of the second electrode plate 62 at least partially overlaps with the orthographic projection of the base of the first electrode plate 61, the second electrode plate 62 may also be a transparent intermediate electrode plate of a transparent memory capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent memory capacitor.

[0121] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each subpixel may be an integrated structure connected to one another.

[0122] In an exemplary embodiment, the area of ​​the overlapping region between the orthographic projection at the base of the first electrode plate 61 and the orthographic projection at the base of the second electrode plate 62 may be essentially the same for each subpixel, thereby the capacitance of the memory capacitor in each subpixel is essentially the same.

[0123] In exemplary embodiments, the semiconductor layer can be made of metal oxides, such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multi-layer layer.

[0124] In exemplary embodiments, the positions of each pattern in the semiconductor layer in the first subpixel P1 may be basically mirror-symmetric with respect to a horizontal reference line with respect to the positions of each pattern in the semiconductor layer in the third subpixel P3, the positions of each pattern in the semiconductor layer in the second subpixel P2 may be basically mirror-symmetric with respect to a horizontal reference line with respect to the positions of each pattern in the semiconductor layer in the fourth subpixel P4, the positions of each pattern in the semiconductor layer in the first subpixel P1 may be basically mirror-symmetric with respect to a vertical reference line with respect to the positions of each pattern in the semiconductor layer in the second subpixel P2, and the positions of each pattern in the semiconductor layer in the third subpixel P3 may be basically mirror-symmetric with respect to a vertical reference line with respect to the positions of each pattern in the semiconductor layer in the fourth subpixel P4.

[0125] Figure 7C is a schematic diagram of the location of a memory capacitor according to an exemplary embodiment of the present disclosure. As shown in Figure 7C, for at least one of the first plate 61 and second plate 62 of each subpixel, there is a first distance L1 between the edge of the capacitor plate closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the capacitor plate, and a second distance L2 between the edge of the capacitor plate closest to the data signal line 52 and the edge of the data signal line 52 closest to the capacitor plate, where the first distance L1 and the second distance L2 are the size of the first direction X. In at least one subpixel, the first distance L1 may be smaller than the second distance L2.

[0126] In an exemplary embodiment, the second electrode plate 62 is taken as an example. There is a first distance L1 between the edge of the second electrode plate 62 closest to the compensation signal line 53 and the edge of the compensation signal line 53 closest to the second electrode plate 62, and there is a second distance L2 between the edge of the second electrode plate 62 closest to the data signal line 52 and the edge of the data signal line 52 closest to the second electrode plate 62.

[0127] In an exemplary embodiment, L1 / L2 = 0.35 to 0.75 in at least one subpixel.

[0128] In an exemplary embodiment, the L1 / L2 ratio in the first subpixel P1 is 0.6 to 0.7. For example, L1 / L2 = 0.67.

[0129] In an exemplary embodiment, in the first subpixel P1, L1 is 5.5 μm to 6.5 μm and L2 is 8.5 μm to 9.5 μm. For example, L1 is 6 μm and L2 is 9 μm.

[0130] In an exemplary embodiment, the L1 / L2 ratio in the second subpixel P2 is 0.4 to 0.5. For example, L1 / L2 = 0.46.

[0131] In an exemplary embodiment, in the second subpixel P2, L1 is 5.5 μm to 6.5 μm and L2 is 12.5 to 13.5 μm. For example, L1 is 6 μm and L2 is 13 μm.

[0132] In an exemplary embodiment, the L1 / L2 ratio in the third subpixel P3 is between 0.65 and 0.75. For example, L1 / L2 = 0.7.

[0133] In an exemplary embodiment, the third subpixel P3 has L1 = 8.5 μm to 9.5 μm and L2 = 12.5 to 13.5 μm. For example, L1 = 9 μm and L2 = 13 μm.

[0134] In exemplary embodiments, the first distance L1 and the second distance L2 may be minimum distances or average distances, and this disclosure is not limited thereto.

[0135] In an exemplary embodiment, the first distance L1 may be the distance between the first plate 61 and the compensation signal line 53, and the second distance L2 may be the distance between the first plate 61 and the data signal line 52.

[0136] (4) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in Figure 8, forming a second insulating layer pattern may include depositing a second insulating thin film on the base on which the aforementioned pattern is formed, patterning the second insulating thin film by a patterning process to form a second insulating layer pattern covering the semiconductor layer, and providing a plurality of vias in the second insulating layer.

[0137] In an exemplary embodiment, the multiple vias of each subpixel on the display substrate may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0138] In an exemplary embodiment, the orthographic projection of the first via V1 at its base lies within the range of the orthographic projection of the first region of the first active layer 21 and the data signal line 52 at its base. The first via V1 is a via in a relay structure and includes a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched and removed to expose the surface of the first region of the first active layer 21, and the first and second insulating layers in the deep half-hole are etched and removed to expose the surface of the data signal line 52, thereby the via in the relay structure consisting of two half-holes simultaneously exposes the first region of the first active layer 21 and the data signal line 52, and the first via V1 is configured to simultaneously connect a subsequently formed seventh connecting electrode to the first region of the first active layer 21 and the data signal line 52 via the via.

[0139] In an exemplary embodiment, the orthographic projection of the second via V2 on the base lies within the range of the orthographic projection of the first region of the second active layer on the base, the second insulating layer within the second via V2 is etched and removed to expose the surface of the first region of the second active layer, and the second via V2 is configured to connect a subsequently formed eighth connecting electrode to the first region of the second active layer via the via.

[0140] In an exemplary embodiment, the orthographic projection of the third via V3 at its base lies within the range of the orthographic projection of the second region of the second active layer 22 and the third connecting electrode 13 at its base. The third via V3 is a via in a relay structure and includes a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched and removed to expose the surface of the second region of the second active layer 22, and the first and second insulating layers in the deep half-hole are etched and removed to expose the surface of the third connecting electrode 13, thereby allowing the via in the relay structure, consisting of two half-holes, to simultaneously expose the second region of the second active layer 22 and the third connecting electrode 13, and the third via V3 is configured to simultaneously connect a subsequently formed fifth connecting electrode to the second region of the second active layer 22 and the third connecting electrode 13 via the via.

[0141] In an exemplary embodiment, the orthographic projection of the base of the fourth via V4 lies within the range of the orthographic projection of the base of the first region of the third active layer 23 and the compensation signal line 53. The fourth via V4 is a via in a relay structure and includes a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the third active layer 23, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the compensation signal line 53, thereby allowing the via in the relay structure consisting of the two half-holes to simultaneously expose the first region of the third active layer 23 and the compensation signal line 53, and the fourth via V4 is configured to connect a subsequently formed ninth connecting electrode to the first region of the third active layer 23 and the compensation signal line 53 simultaneously via the via.

[0142] In an exemplary embodiment, the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 are connected to each other, and the first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are connected to each other, so that the first subpixel P1 and the second subpixel P2 share one fourth via V4, and the third subpixel P3 and the fourth subpixel P4 share one fourth via V4. In this disclosure, by arranging adjacent subpixels to share one fourth via V4, the number of vias can be effectively reduced, the occupied area of ​​the pixel driving circuit can be reduced, which is advantageous for improving resolution, and the via connection structure can be reduced, simplifying the manufacturing process.

[0143] In an exemplary embodiment, the orthographic projection of the fifth via V5 at its base lies within the orthographic projection of the second region of the third active layer 23 and the fourth connecting electrode 14 at its base. The fifth via V5 is a via in a relay structure, comprising a shallow half-hole and a deep half-hole, wherein the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the third active layer 23, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the fourth connecting electrode 14, thereby allowing the via in the relay structure, consisting of two half-holes, to simultaneously expose the second region of the third active layer 23 and the fourth connecting electrode 14, and the fifth via V5 is configured to simultaneously connect a subsequently formed fifth connecting electrode to the second region of the third active layer 23 and the fourth connecting electrode 14 via the via.

[0144] In an exemplary embodiment, the orthographic projection of the sixth via V6 on its base lies within the orthographic projection of the second electrode plate 62 on its base, the second insulating layer within the sixth via V6 is etched and removed to expose the surface of the second electrode plate 62, and the sixth via V6 is configured to connect a subsequently formed second gate electrode to the second electrode plate 62 via the via.

[0145] In an exemplary embodiment, the orthographic projection of the seventh via V7 at its base lies within the range of the orthographic projection of the first power line 51 at its base, the first and second insulating layers within the seventh via V7 are etched and removed to expose the surface of the first power line 51, and the seventh via V7 is configured to connect a subsequently formed eighth connecting electrode to the first power line 51 via the via.

[0146] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a plurality of vias are formed using a dry etching process, and the semiconductor layer exposed within the vias is subjected to a first conductive treatment to form a first conductive region in the semiconductor layer exposed within the vias. In the first conductive treatment, the edge portion of the semiconductor layer covered by the second insulating layer, which is close to the vias, is also made conductive; that is, the first conductive semiconductor layer extends in a direction away from the vias.

[0147] (5) Forming a third conductive layer pattern. In exemplary embodiments, as shown in Figures 9A and 9B, forming a third conductive layer pattern may include depositing a third conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the second insulating layer. Figure 9B is a schematic diagram of the third conductive layer in Figure 9A. In exemplary embodiments, the third conductive layer may be referred to as a gate metal (GT) layer.

[0148] In exemplary embodiments, the third conductive layer of each subpixel on the display substrate may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a ninth connecting electrode 19, a scanning signal line 30, a first gate electrode 31, a second gate electrode 32, and a third gate electrode 33.

[0149] In an exemplary embodiment, the shape of the scanning signal line 30 may be linear with the main body extending along a first direction X, and the scanning signal line 30 may be located in the middle of the repeating unit in a second direction Y, i.e., between the first subpixels P1 and the second subpixels P2 and the third subpixels P3 and the fourth subpixels P4, and the scanning signal line 30 is configured to simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the four subpixels of the repeating unit.

[0150] In an exemplary embodiment, the orthographic projection of the scanning signal line 30 at the base does not overlap with the orthographic projection of the first active layer 21 and the third active layer 23 at the base.

[0151] In exemplary embodiments, the shape of the first gate electrode 31 may be a strip extending along a second direction Y, and the first gate electrode 31 may be located on the side of the scan signal line 30 closer to the first active layer 21, with the first end of the first gate electrode 31 connected to the scan signal line 30, the second end of the first gate electrode 31 extending toward the first active layer 21, and the orthographic projection of the first gate electrode 31 at the base at least partially overlapping with the orthographic projection of the base of the first active layer 21. In exemplary embodiments, the first gate electrode 31 may also be the gate electrode of the first transistor T1, so that the scan signal line 30 can control the on or off of the first transistor T1.

[0152] In an exemplary embodiment, the shape of the second gate electrode 32 may be a strip extending along the second direction Y, the first end of the second gate electrode 32 is connected to the second electrode plate 62 via the sixth via V6, the second end of the second gate electrode 32 extends along the direction of the second active layer 22, and the orthographic projection of the second gate electrode 32 at the base at least partially overlaps with the orthographic projection of the second active layer 22 at the base. In an exemplary embodiment, the second gate electrode 32 may also be the gate electrode of the second transistor T2, thereby allowing control of the on or off state of the second transistor T2.

[0153] In an exemplary embodiment, the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the second region of the first active layer 21. As a result, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the memory capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0154] In exemplary embodiments, the shape of the third gate electrode 33 may be a strip extending along the second direction Y, and the third gate electrode 33 may be located on the side of the scan signal line 30 closer to the third active layer 23, with the first end of the third gate electrode 33 connected to the scan signal line 30, the second end of the third gate electrode 33 extending toward the third active layer 23, and the orthographic projection of the base of the third gate electrode 33 at least partially overlapping the orthographic projection of the base of the third active layer 23. In exemplary embodiments, the third gate electrode 33 may also be the gate electrode of the third transistor T3, so that the scan signal line 30 can control the on or off of the third transistor T3.

[0155] In an exemplary embodiment, in one subpixel, one scan signal line 30 is simultaneously connected to a first gate electrode 31 and a third gate electrode 33, thereby allowing the scan signal line 30 to control the on or off state of a first transistor T1 and a third transistor T3 in one subpixel.

[0156] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors T3 in multiple subpixels, thereby allowing the scan signal line 30 to control the on or off state of the first transistor T1 and third transistor T3 in one pixel row.

[0157] In an exemplary embodiment, in one repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors T3 in multiple subpixels, thereby allowing the scan signal line 30 to simultaneously control the on or off states of the first transistor T1 and the third transistor T3 in one repeating unit.

[0158] In exemplary embodiments, the shape of the fifth connecting electrode 15 may be block-shaped (e.g., rectangular), and the fifth connecting electrode 15 may be installed on the side of the second electrode plate 62 away from the scanning signal line 30, and the fifth connecting electrode 15 is simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 via the third via V3.

[0159] In an exemplary embodiment, the fifth connecting electrode 15 is simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13, the third connecting electrode 13 is connected to the first connecting electrode 11, and the first connecting electrode 11 is connected to the first plate 61. Thus, the fifth connecting electrode 15 brings the second electrode of the second transistor and the first plate 61 to the same potential. In an exemplary embodiment, the fifth connecting electrode 15 is configured to be connected to a subsequently formed tenth connecting electrode.

[0160] In exemplary embodiments, the shape of the sixth connecting electrode 16 may be block-shaped (e.g., rectangular), and the sixth connecting electrode 16 may be installed on the side of the second electrode plate 62 closer to the scanning signal line 30, and the sixth connecting electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14 via the fifth via V5.

[0161] In an exemplary embodiment, the sixth connecting electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14, the fourth connecting electrode 14 is connected to the second connecting electrode 12, and the second connecting electrode 12 is connected to the first electrode plate 61. Thus, the sixth connecting electrode 16 brings the second electrode of the third transistor and the first electrode plate 61 to the same potential.

[0162] In an exemplary embodiment, the fifth connecting electrode 15 and the sixth connecting electrode 16 realize a connection between the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode plate 61 (the second terminal of the memory capacitor), forming a second node in the pixel driving circuit. Therefore, the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0163] In an exemplary embodiment, the first plate 61 has the potential of the second node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit. Therefore, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form a memory capacitor.

[0164] In this exemplary embodiment, a transparent conductive material is used for the first electrode plate 61 and a transparent metal oxide is used for the second electrode plate 62, so the memory capacitor is a transparent capacitor.

[0165] In an exemplary embodiment, the shape of the seventh connecting electrode 17 may be block-shaped (e.g., rectangular), and the seventh connecting electrode 17 may be installed between the first gate electrode 31 and the first power line 51, and the seventh connecting electrode 17 is simultaneously connected to the first region of the first active layer 21 and the data signal line 52 via the first via V1, thereby enabling the data signal line 52 to write data signals to the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 may be connected to the first region of the first active layer in one subpixel via the first via V1, thereby enabling the four data signal lines 52 to write data signals to the first electrodes of four first transistors T1 in one repeating unit.

[0166] In exemplary embodiments, the four data signal lines 52 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on the first direction X side of the first power line 51 in the first pixel row and may be connected to a first region of the first active layer in the first subpixel P1 via a seventh connecting electrode 17. The second data signal line may be located on the first direction X side of the first data signal line and may be connected to a first region of the first active layer in the third subpixel P3 via a seventh connecting electrode 17. The third data signal line may be located on the first direction X side of the compensation signal line 53 and may be connected to a first region of the first active layer in the second subpixel P2 via a seventh connecting electrode 17. The fourth data signal line may be located on the first direction X side of the third data signal line and may be connected to a first region of the first active layer in the fourth subpixel P4 via a seventh connecting electrode 17.

[0167] In an exemplary embodiment, the eighth connecting electrode 18 may be a strip extending along the first direction X, and may be located on the side of the second electrode plate 62 away from the scan signal line 30. The first end of the eighth connecting electrode 18 is connected to the first power line 51 via the seventh via V7, and the second end of the eighth connecting electrode 18 is connected to the first region of the second active layer 22 via the second via V2. This enables the first power line 51 to write the first power signal to the first electrode of the second transistor T2.

[0168] In an exemplary embodiment, the first power line 51 of the first pixel row can simultaneously supply a first power signal to the pixel drive circuits of the first sub-pixel P1 and the third sub-pixel P3, and the first power line 51 of the second pixel row can simultaneously supply a first power signal to the pixel drive circuits of the second sub-pixel P2 and the fourth sub-pixel P4, so that the first power line 51 in one repeating unit has a 1:2 structure. By designing the compensation signal lines in a 1:2 structure, the display board of this disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution.

[0169] In an exemplary embodiment, two first power lines 51 in one repeating unit are arranged symmetrically with respect to the compensation signal line 53, and the second transistor T2 of the first pixel row and the second transistor T2 of the second pixel row are arranged symmetrically with respect to the compensation signal line 53. Such a symmetrical structure of the present disclosure ensures that the voltage drop written to the second transistor T2 by the first power lines is essentially the same, thereby ensuring display uniformity.

[0170] In exemplary embodiments, the shape of the ninth connecting electrode 19 may be block-shaped (e.g., rectangular), and the ninth connecting electrode 19 may be placed between the third gate electrodes 33 of two adjacent subpixels in a first direction X, and the ninth connecting electrode 19 is simultaneously connected to a first region of the third active layer 23 and a compensation signal line 53 via a fourth via V4, thereby enabling the compensation signal line 53 to write a compensation signal to the first electrode of the third transistor T3.

[0171] In an exemplary embodiment, the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 are connected to each other, and the first subpixel P1 and the second subpixel P2 share one fourth via V4, so the first subpixel P1 and the second subpixel P2 share one ninth connecting electrode 19. The first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are connected to each other, and the third subpixel P3 and the fourth subpixel P4 share one fourth via V4, so the third subpixel P3 and the fourth subpixel P4 share one ninth connecting electrode 19.

[0172] In an exemplary embodiment, the compensation signal line 53 can simultaneously supply compensation signals to the pixel drive circuits in four subpixels, so that the four pixel drive circuits in one repeating unit can share one compensation signal line 53, i.e., the compensation signal line 53 in one repeating unit has a 1:4 structure. By designing the compensation signal line in a 1:4 structure, the display substrate of this disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution.

[0173] In an exemplary embodiment, the compensation signal line 53 is positioned between the first and second pixel rows, and the third transistor T3 of the first pixel row and the third transistor T3 of the second pixel row are positioned symmetrically with respect to the compensation signal line 53. Such a symmetrical structure as described herein ensures that the RC delay of the compensation signal written to the third transistor T3 is essentially the same, thereby ensuring display uniformity.

[0174] In exemplary embodiments, the positions of each pattern of the third conductive layer in the first subpixel P1 and the positions of each pattern of the third conductive layer in the third subpixel P3 may be basically mirror-symmetric with respect to a horizontal reference line, the positions of each pattern of the third conductive layer in the second subpixel P2 and the positions of each pattern of the third conductive layer in the fourth subpixel P4 may be basically mirror-symmetric with respect to a horizontal reference line, the positions of each pattern of the third conductive layer in the first subpixel P1 and the positions of each pattern of the third conductive layer in the second subpixel P2 may be basically mirror-symmetric with respect to a vertical reference line, and the positions of each pattern of the third conductive layer in the third subpixel P3 and the positions of each pattern of the third conductive layer in the fourth subpixel P4 may be basically mirror-symmetric with respect to a vertical reference line.

[0175] In an exemplary embodiment, the process for forming the third conductive layer pattern involves first forming the third conductive layer pattern using a wet etching process, thereby enabling at least one connecting electrode to be simultaneously connected to the second conductive layer and the semiconductor layer via vias of a relay structure. The vias of the relay structure may include at least two half-holes, one shallow and one deep. The second insulating layer in the shallow half-hole is etched and removed to expose the surface of the semiconductor layer, and the second insulating layer and the first insulating layer in the deep half-hole are etched and removed to expose the surface of the second conductive layer, thereby enabling the connecting electrode to be simultaneously connected to the semiconductor layer and the second conductive layer via the shallow and deep half-holes. In the exemplary embodiment, a certain distance is provided between the end of the connecting electrode located in the shallow half-hole region and the edge of the shallow half-hole, i.e., the connecting electrode does not completely cover the shallow half-hole.

[0176] In an exemplary embodiment, after forming a third conductive layer pattern using a wet etching process, the second insulating layer in areas other than the third conductive layer is etched using a dry etching process with the third conductive layer as a mask. As the second insulating layer is etched and removed, the exposed semiconductor layer is made a second conductor, forming a second conductive region.

[0177] In an exemplary embodiment, during the second conduction process, the edge portion of the semiconductor layer covered by the third conductive layer is also made conductive. That is, the second conductive semiconductor layer extends toward the first conductive region, forming two conductive regions in the overlapping region of the first and second conductive regions, thereby ensuring a reliable connection between the third conductive layer and the semiconductor layer.

[0178] (6) Forming a third insulating layer and a flat layer pattern. In an exemplary embodiment, as shown in Figure 10, forming a third insulating layer and a flat layer pattern may include depositing a third insulating thin film on a base on which the aforementioned pattern has been formed, then applying a flat thin film, patterning the flat thin film and the third insulating thin film by a patterning process to form a third insulating layer covering the third conductive layer and a flat layer pattern placed on the third insulating layer, and placing a plurality of vias in the flat layer.

[0179] In an exemplary embodiment, each subpixel via on the display board includes at least an 11th via V11.

[0180] In an exemplary embodiment, the orthographic projection of the 11th via V11 on its base lies within the range of the orthographic projection of the 5th connecting electrode 15 on its base, the 3rd insulating layer and the planar layer within the 11th via V11 are etched and removed to expose the surface of the 5th connecting electrode 15, and the 11th via V11 is configured to connect a subsequently formed 10th connecting electrode to the 5th connecting electrode 15 via the via.

[0181] In an exemplary embodiment, the present process employs a single patterning process, i.e., a masking process in which the third insulating layer and the planar layer share a single halftone or gray tone, thereby simultaneously forming vias in the third insulating layer and the planar layer, effectively reducing the number of patterning processes.

[0182] (7) Forming a fourth conductive layer pattern. In exemplary embodiments, as shown in Figures 11A and 11B, forming a fourth conductive layer pattern may include depositing a fourth conductive thin film on a base on which the aforementioned pattern has been formed, and then patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern on the color film layer. Figure 11B is a schematic diagram of the fourth conductive layer in Figure 11A.

[0183] In exemplary embodiments, the fourth conductive layer of each subpixel on the display substrate may include at least a tenth connecting electrode 20 and a first electrode 63.

[0184] In exemplary embodiments, the shape of the first electrode 63 may be rectangular, and the corners of the rectangle may be chamfered, recessed, or convex, and the orthogonal projection of the first electrode 63 on the base at least partially overlaps with the orthogonal projection of the second electrode plate 62 on the base.

[0185] In an exemplary embodiment, the shape of the tenth connecting electrode 20 may be block-shaped (e.g., rectangular), and the tenth connecting electrode 20 may be located on the side of the first electrode 63 away from the scan signal line 30, with the first end of the tenth connecting electrode 20 connected to the first electrode 63, and the second end of the tenth connecting electrode 20 extending away from the scan signal line 30 and then connected to the fifth connecting electrode 15 via the eleventh via V11.

[0186] In an exemplary embodiment, the tenth connecting electrode 20 and the first electrode 63 may be an integrated structure connected to each other in at least one subpixel.

[0187] In an exemplary embodiment, four first electrodes 63 in one repeating unit are arranged in a square, with the upper left first electrode connected to the pixel driving circuit in the first subpixel P1, the upper right first electrode connected to the pixel driving circuit in the second subpixel P2, the lower left first electrode connected to the pixel driving circuit in the third subpixel P3, and the lower right first electrode connected to the pixel driving circuit in the fourth subpixel P4. In several possible implementations, the first electrodes may also be anodes of the light-emitting device, and the arrangement of the first electrodes may be adjusted according to actual needs, and is not specifically limited herein.

[0188] In exemplary embodiments, the material of the first conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0189] In an exemplary embodiment, the first electrode 63 may serve as an auxiliary capacitor for the memory capacitor. The first electrode 63 is connected to the tenth connecting electrode 20, which is connected to the first plate 61 via the fifth connecting electrode 15, the third connecting electrode 13, and the first connecting electrode 11. As a result, the first electrode 63 has the potential of the second node in the pixel driving circuit. Thus, the first electrode 63 having the potential of the second node and the second plate 62 having the potential of the first node form an auxiliary capacitor, and the auxiliary capacitor and the memory capacitor are connected in parallel. In this disclosure, an auxiliary capacitor is formed using the first electrode, and the auxiliary capacitor and the memory capacitor are connected in parallel. On the one hand, the capacitance value of the memory capacitor can be effectively increased, and on the other hand, the plate area can be reduced while maintaining the capacitance value of the memory capacitor, effectively reducing the occupied area.

[0190] (8) Form a pixel definition layer. In an exemplary embodiment, as shown in Figure 12, forming a pixel definition layer pattern may include applying a pixel definition thin film to a base on which the aforementioned pattern has been formed, and then patterning the pixel definition thin film by a patterning process to form a pixel definition layer that covers the fourth conductive layer.

[0191] In an exemplary embodiment, a pixel aperture K is opened in the pixel definition layer of each subpixel on the display substrate, the pixel definition thin film within the pixel aperture K is removed to expose a portion of the surface of the first electrode 63, and the orthogonal projection of the pixel aperture K at the base is located within the range of the orthogonal projection of the first electrode 63 at the base.

[0192] In exemplary embodiments, the shape of the pixel aperture K may be similar to the shape of the first electrode 63 in a plane parallel to the base, and the cross-sectional shape of the pixel aperture K may be rectangular, trapezoidal, or the like in a plane perpendicular to the base.

[0193] In exemplary embodiments, the shape of the pixel aperture may include one or more of the following: triangle, rectangle, trapezoid, parallelogram, quinogram, hexogram, circle, and ellipse.

[0194] In the exemplary embodiment, the shapes of the pixel apertures of the four subpixels may be the same or different. The areas of the pixel apertures of the four subpixels may be the same or different.

[0195] In exemplary embodiments, the shapes and areas of the pixel apertures of the four subpixels may differ to accommodate the transmittance of different subpixel filters, thereby allowing the four subpixel light-emitting devices to emit the same brightness at different currents, maximizing the lifespan of the four subpixel light-emitting devices and ensuring product life.

[0196] In exemplary embodiments, at least one blocking groove M may be further provided in the pixel definition layer of each repeating unit on the display substrate, the shape of which the blocking groove M may be a strip with its main body extending along a second direction Y, and the blocking groove M may be provided between adjacent pixel apertures K in a first direction X. For example, the blocking groove M may be provided between the pixel aperture K of a first subpixel P1 and the pixel aperture K of a second subpixel P2. Alternatively, for example, the blocking groove M may be provided between the pixel aperture K of a third subpixel P3 and the pixel aperture K of a fourth subpixel P4. In exemplary embodiments, the blocking groove M is configured to block the subsequently formed organic light-emitting layer, block the lateral propagation path of hole carriers, eliminate lateral leakage current, and eliminate lateral crosstalk of subpixels.

[0197] In exemplary embodiments, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0198] (9) Form the organic light-emitting layer and cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern may include first forming the organic light-emitting layer pattern, the organic light-emitting layer being connected to the first electrode 63 via the pixel aperture K, and then forming a second electrode connected to the organic light-emitting layer. In an exemplary embodiment, the second electrode may be the cathode of the light-emitting device.

[0199] In exemplary embodiments, the organic light-emitting layer may include an emissive layer (EML) and one or more layers selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In exemplary embodiments, the organic light-emitting layer may be formed by deposition using a fine metal mask (FMM) or an open mask, or by employing an inkjet process.

[0200] (10) Forming a package structure layer pattern. In exemplary embodiments, forming a package structure layer pattern may include depositing a first inorganic thin film using an open mask to form a first package layer, then inkjet printing an organic material onto the first package layer using an inkjet printing process, curing to form a film, and then forming a second package layer, and subsequently depositing a second inorganic thin film using an open mask to form a third package layer, wherein the first, second, and third package layers constitute a package structure layer. The first and third package layers may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), carbon silicon nitride (SiCN), and silicon nitride (SiON), and may be single layers, multilayers, or composite layers. The second package layer may employ a resin material to form an inorganic / organic / inorganic laminated structure, and the organic material layer may be placed between two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0201] Up to this point, the manufacturing of a display substrate according to an exemplary embodiment of the present disclosure is complete. The display substrate may include a drive circuit layer installed on a base, a light-emitting structure layer installed on the side of the drive circuit layer away from the base, and a package structure layer installed on the side of the light-emitting structure layer away from the base. In a plane perpendicular to the display substrate, the drive circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a flat layer installed sequentially on the base; the light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode; and the package structure layer may include a first package layer, a second package layer, and a third package layer that are stacked.

[0202] In exemplary embodiments, a display substrate including a color film structure layer may first form a third conductive layer, then a third insulating layer, followed by the sequential formation of a red color film layer, a green color film layer, and a blue color film layer, and finally a flat layer; however, this will not be described again here.

[0203] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may be one or more types of glass and quartz, but is not limited thereto, and the flexible base may be one or more types of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited thereto. In exemplary embodiments, the flexible base may include a laminated first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials for the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials for the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the hydroxyl resistance of the base. The semiconductor layer can be amorphous silicon (a-si).

[0204] In exemplary embodiments, the first and third conductive layers may be made of metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be single-layer or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, and third insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The flat layer may be made of an organic material, such as a resin.

[0205] Currently, existing display boards have problems such as signal interference. As a result of their research, the inventors of this invention have found that when four data signal lines in a single repeating unit are installed on both sides of the first direction X of the repeating unit and are connected across wires, the data signal lines cause signal interference between the second electrode of the first transistor and the memory capacitor. Taking the first and second data signal lines as an example, the first data signal line is connected to the first electrode of the first transistor T1 in the first sub-pixel P1, and the second data signal line is connected to the first electrode of the first transistor T1 in the third sub-pixel P3. Since the second data signal line is located on the first direction X side of the first data signal line, and the first transistor T1 is located on the first direction X side of the second data signal line, the first electrode of the first transistor T1 in the first sub-pixel P1 needs to be connected to the first data signal line across the second data signal line. In this disclosure, by positioning the memory capacitor closer to the compensation signal line and further away from the data signal line, the second plate of the memory capacitor and the second electrode of the first transistor T1 are connected to each other in an integrated structure. As a result, the first transistor T1 is separated from the data signal line, and therefore the influence of data voltage jumps on the data signal line on the second electrode of the first transistor T1 and the memory capacitor is reduced, preventing the normal operation of the pixel driving circuit from being affected by data voltage jumps, and improving the display effect and display quality.

[0206] Currently, existing display substrates suffer from the problems of complex manufacturing processes and high manufacturing costs. For example, the manufacturing process for the drive structure layer in a display substrate requires nine patterning (MASK) processes, resulting in low production efficiency, high production costs, and an impact on the product yield rate. The embodiment of this disclosure provides a display substrate with a bottom emission structure, in which structures such as the first power line, data signal line, and compensation signal line are placed on the SHIELD layer, located closer to the base of the semiconductor layer, and structures such as the scanning signal line and gate electrodes of multiple transistors are placed on the GT layer, located further away from the base of the semiconductor layer. This not only reduces the number of conductive layers by one, but also reduces the patterning process for transfer vias and transfer conductive layers. As a result, the manufacturing process for the drive structure layer requires only six patterning processes, reducing the number of patterning processes, efficiently improving production costs, and maximizing the product yield rate.

[0207] The display board of the embodiment of this disclosure employs a 3T1C pixel drive circuit with one scan signal line. This single scan signal line is connected to the first and third transistors in the pixel drive circuit. By reducing the number of scan signal lines, the structure of the pixel drive circuit is simplified, the area occupied by the pixel drive circuit can be reduced, and this is advantageous for achieving high-resolution display. Furthermore, since one repeating unit is driven by only one scan signal line, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be doubled. This effectively reduces the area occupied by the gate drive circuits and clock signal lines, enabling a narrow bezel and enhancing the product's competitive advantage.

[0208] In the exemplary embodiment of the present disclosure, the display substrate is made of a transparent memory capacitor consisting of a transparent conductive layer and a transparent semiconductor layer. Since light rays can be emitted through the transparent memory capacitor, the memory capacitor can be placed within the pixel aperture, and not only the capacitance of the memory capacitor but also the pixel aperture ratio can be effectively increased.

[0209] The pixels in the embodiments of this disclosure are arranged in a square pattern, and by employing a non-mesh first power line structure, the pixel aperture ratio can be effectively increased, improving the display effect and making it more suitable for display-type displays.

[0210] The manufacturing process disclosed herein is highly compatible with existing manufacturing processes, is easy to implement and realize, boasts high production efficiency, low manufacturing costs, and a high yield rate.

[0211] The structures and manufacturing processes described herein are illustrative only, and in exemplary embodiments, corresponding structures can be modified or patterning processes can be added or removed depending on actual needs, and this disclosure is not limited thereto.

[0212] Figure 13 is a schematic diagram of the structure of the drive circuit layer in another display substrate of an exemplary embodiment of the present disclosure, showing the arrangement of signal lines in one repeating unit (four subpixels) of a bottom emission display substrate. In the exemplary embodiment, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square manner, each subpixel including a pixel drive circuit 54.

[0213] In an exemplary embodiment, at least one repeating unit may include one scan signal line 30, two first power lines 51, two compensation signal lines 53, and four data signal lines 52, each of which is connected to a pixel drive circuit 54 in the corresponding subpixel.

[0214] In exemplary embodiments, the shape of the scan signal line 30 may be linear with the main body extending along a first direction X, and the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be linear with the main body extending along a second direction Y. In exemplary embodiments, the scan signal line 30 may be located in the middle region of the repeating unit in the second direction Y, the two first power lines 51 and four data signal lines 52 may be located in the middle region of the repeating unit in the first direction X, and the two compensation signal lines 53 may be located on both sides of the repeating unit in the first direction X. One of the two first power lines 51 may be located between one compensation signal line 53 and a data signal line 52, and the other of the two first power lines 51 may be located between the other compensation signal line 53 and a data signal line 52.

[0215] In exemplary embodiments, the pixel driving circuit for at least one subpixel may include a first transistor, a second transistor, a third transistor, and a memory capacitor, and the associated connection structure is essentially the same as in the embodiments described above and will not be repeated here.

[0216] In exemplary embodiments, the memory capacitor may include at least a first plate and a second plate as capacitor plates. In at least one subpixel, the first plate and the second plate may be placed between the first power line 51 and the compensation signal line 53.

[0217] In exemplary embodiments, in at least one repeating unit, two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2 installed sequentially along a first direction X, the first compensation signal line 53-1 may be installed on the opposite side of the repeating unit in the first direction X, and the second compensation signal line 53-2 may be installed on the side of the repeating unit in the first direction X. Two first power lines 51 may include a first first power line 51-1 and a second first power line 51-2 installed sequentially along the first direction X, and four data signal lines 52 may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3 and a fourth data signal line 52-4 installed sequentially along the first direction X, the four data signal lines 52 may be installed between the first first power line 51-1 and the second first power line 51-2.

[0218] In this disclosure, by placing a memory capacitor between the first power line and the compensation signal line, and placing four data signal lines between two first power lines, the constant voltage first power line can effectively shield the second electrode of the first transistor T1 and the memory capacitor from the effect of data voltage jumps on the data signal lines, thereby avoiding the effect of data voltage jumps on the normal operation of the pixel driving circuit and improving the display effect.

[0219] In exemplary embodiments, the display substrate of the present disclosure may be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), and the present disclosure is not limited thereto.

[0220] Exemplary embodiments of the present disclosure further provide a method for manufacturing a display substrate for manufacturing the aforementioned display substrate. In the exemplary embodiment, the display substrate comprises a plurality of repeating units, at least one repeating unit comprising a plurality of subpixels forming at least two pixel rows and at least two pixel columns, and the manufacturing method is: A pixel driving circuit is formed in at least one subpixel, the pixel driving circuit is connected to a data signal line and a compensation signal line extending along the pixel row direction, the data signal line is configured to supply a data signal to the pixel driving circuit, and the compensation signal line is configured to supply a compensation signal to the pixel driving circuit, the pixel driving circuit includes at least a memory capacitor, the memory capacitor includes at least two stacked capacitor plates, the two capacitor plates are placed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and there is a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, the first distance is smaller than the second distance, and the first and second distances are sizes in the pixel row direction.

[0221] This disclosure further provides a display device, including a display substrate of the embodiments described above. The display device may be a product or component that includes a display function, such as a mobile phone, tablet, television, monitor, laptop, digital frame, or navigator.

[0222] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are illustrative and not restrictive. Therefore, this disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the embodiments and details without departing from the scope of this disclosure. [Explanation of Symbols]

[0223] 11. First connecting electrode 12. Second connecting electrode 13. Third connecting electrode 14. Fourth connecting electrode 15. Fifth connecting electrode 16. Sixth connecting electrode 17. Seventh connecting electrode 18. Eighth connecting electrode 19. Ninth connecting electrode 20. 10th connecting electrode 21 1st active layer 22 2nd active layer 23 3rd active layer 30 Scanning signal lines 31 First Gate 32 Second Tetrapod 33 Third Gate 51 1st power line 52 Data signal lines 53 Compensation signal line 54 Pixel Driving Circuit 61 1st plate 62 2nd plate 63 1st electrode 100 repeating units

Claims

1. A display board comprising a plurality of repeating units, at least one repeating unit comprising a plurality of subpixels forming at least two pixel rows and at least two pixel columns, at least one subpixel comprising a pixel driving circuit, the pixel driving circuit being connected to a data signal line and a compensation signal line extending along the pixel column direction, the data signal line being configured to supply a data signal to the pixel driving circuit, the compensation signal line being configured to supply a compensation signal to the pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least two stacked capacitor plates, the two capacitor plates being placed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and there is a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, the first distance being smaller than the second distance, and the first distance and the second distance being the size in the pixel row direction.

2. The display board according to claim 1, wherein the ratio of the first distance to the second distance is 0.35 to 0.

75.

3. The display board according to claim 1, wherein the ratio of the first distance to the second distance is 0.6 to 0.

7.

4. The display substrate according to claim 3, wherein the first distance is 5.5 μm to 6.5 μm, and the second distance is 8.5 μm to 9.5 μm.

5. The display substrate according to claim 1, wherein the ratio of the first distance to the second distance is 0.4 to 0.

5.

6. The display substrate according to claim 5, wherein the first distance is 5.5 μm to 6.5 μm, and the second distance is 12.5 μm to 13.5 μm.

7. The display board according to claim 1, wherein the ratio of the first distance to the second distance is 0.65 to 0.

75.

8. The display substrate according to claim 7, wherein the first distance is 8.5 μm to 9.5 μm, and the second distance is 12.5 μm to 13.5 μm.

9. The display board according to any one of claims 1 to 8, wherein the two capacitor plates include a first plate and a second plate, the pixel driving circuit further includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the first plate and the gate electrode of the second transistor, respectively, the first electrode of the third transistor is connected to the compensation signal line, the second electrode of the third transistor is connected to the second plate and the second electrode of the second transistor, the first distance is between the edge of the second plate closest to the compensation signal line and the edge of the compensation signal line closest to the second plate, and the second distance is between the edge of the second plate closest to the data signal line and the edge of the data signal line closest to the second plate.

10. The display substrate according to claim 9, wherein the first transistor includes at least a first active layer, and the first active layer and the second electrode plate are connected to each other in an integrated structure.

11. The display board according to any one of claims 1 to 8, wherein the pixel driving circuit is further connected to a first power line extending along the pixel row direction, and at least one repeating unit includes one compensation signal line, two first power lines, and four data signal lines, the one compensation signal line located in the middle of the repeating unit in the pixel row direction, the two first power lines located on both sides of the repeating unit in the pixel row direction, two of the four data signal lines located on the side of one of the first power lines closer to the compensation signal line, and the other two of the four data signal lines located on the side of the other one of the first power lines closer to the compensation signal line.

12. The two first power lines include a first power line and a second power line that are sequentially installed along the pixel row direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line that are sequentially installed along the pixel row direction, the first data signal line is located on the side of the first power line closest to the compensation signal line, the second data signal line is located on the side of the first data signal line closest to the compensation signal line, the two capacitor plates are installed between the second data signal line and the compensation signal line, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and the second The display board according to claim 11, wherein there is a second distance between the edge of the first data signal line closest to the edge of the second data signal line closest to the capacitor plate, the fourth data signal line is located on the side of the second first power line closest to the compensation signal line, the third data signal line is located on the side of the fourth data signal line closest to the compensation signal line, the two capacitor plates are installed between the third data signal line and the compensation signal line, there is a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and there is a second distance between the edge of the capacitor plate closest to the third data signal line and the edge of the third data signal line closest to the capacitor plate.

13. The display board according to any one of claims 1 to 8, wherein the pixel driving circuit is further connected to a first power line extending along the pixel row direction, and at least one repeating unit includes two compensation signal lines, two first power lines, and four data signal lines, the four data signal lines located in the middle of the repeating unit in the pixel row direction, the two compensation signal lines located on both sides of the repeating unit in the pixel row direction, and the two first power lines each located on the side of the four data signal lines closer to the compensation signal lines.

14. The display board according to claim 13, wherein the two compensation signal lines include a first compensation signal line and a second compensation signal line installed sequentially along the pixel row direction, the two first power lines include a first power line and a second power line installed sequentially along the pixel row direction, the four data signal lines include a first data signal line, a second data signal line, a third data signal line and a fourth data signal line installed sequentially along the pixel row direction, the first power line is located on the side of the first data signal line closer to the first compensation signal line, the two capacitor plates are installed between the first compensation signal line and the first power line, the second power line is located on the side of the fourth data signal line closer to the second compensation signal line, and the two capacitor plates are installed between the second compensation signal line and the second power line.

15. A display device comprising a display board according to any one of claims 1 to 14.

16. A method for manufacturing a display board, wherein the display board includes a plurality of repeating units, at least one repeating unit includes a plurality of subpixels that form at least two pixel rows and at least two pixel columns, and the manufacturing method is A method for manufacturing a display substrate, comprising: forming a pixel driving circuit in at least one subpixel, the pixel driving circuit being connected to a data signal line and a compensation signal line extending along the pixel row direction, the data signal line being configured to supply a data signal to the pixel driving circuit, the compensation signal line being configured to supply a compensation signal to the pixel driving circuit, the pixel driving circuit including at least a memory capacitor, the memory capacitor including at least two stacked capacitor plates, the two capacitor plates being placed between the data signal line and the compensation signal line, and for at least one capacitor plate in at least one subpixel, having a first distance between the edge of the capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate, and having a second distance between the edge of the capacitor plate closest to the data signal line and the edge of the data signal line closest to the capacitor plate, the first distance being smaller than the second distance, and the first and second distances being the size in the pixel row direction.

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