System and method for generating inference information in a revisable model on a storage device

Abstract

A system and associated method comprising memory and processing circuitry for receiving multiple weights from a host device and implementing an instantiation of a model on a storage device. The instantiation of the model includes multiple weights, each weight determined using another instantiation of the model trained on the host device. The processing circuitry then generates inference information using the instantiation of the model implemented on the storage device. The processing circuitry further receives multiple updated weights from the host device and updates the instantiation of the model based on the multiple updated weights to implement the updated instantiation of the model on the storage device. The processing circuitry then generates updated inference information on the storage device using the updated instantiation of the model based on at least one signal to be processed by the processing circuitry.

Description

Technical Field

[0001] The present disclosure is directed to a system and method for generating inference information using a model on a storage device based on at least one signal received by a host system.

Summary of the Invention

[0002] This disclosure provides a system and method for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) using a revisable instantiation of a model based on at least one signal to be processed. The system and method disclosed herein allows a host to train an instantiation of a model on the host (e.g., a first instantiation of the model) without communicating with a storage device, and then update an instantiation of the model implemented on a storage device (e.g., a second instantiation of the model). This allows the first instantiation of the model to be trained by a centralized host while at least one storage device is using the implemented instantiation of the model (e.g., a second instantiation of the model), and the implemented instantiation of the model can be updated at any time by receiving updated data. When a storage device receives a signal to be processed, the storage device is to generate inference information using an instantiation of the model on the storage device based on the received at least one signal. The systems and methods disclosed herein use revisable instantiations of a model on storage devices to enable a centralized host to maintain instantiations of a trained model and then distribute updated weights to at least one storage device to implement the updated instantiations on the storage device. The systems and methods disclosed herein offload the task of training the model instantiations from each storage device, thereby enabling each storage device to focus on performing operations rather than training firmware or systems that would require the least amount of bandwidth and power from each storage device. This improves the overall access efficiency and power consumption of the processing circuits of the storage devices (e.g., solid-state drive devices).

[0003] In some embodiments, the system (e.g., a storage device) includes memory and processing circuits that are coupled to each other in a communicative manner. In some embodiments, the system may be distributed between the storage device and another separate device (e.g., a host such as a storage controller device), such as when the host provides a control circuit for implementing at least some of the functions described herein. In some embodiments, the processing circuit receives updated weights from the host device. In some embodiments, the processing circuit implements the updated instantiation of the model on the storage device by updating the instantiation of the model on the storage device based on the updated weights. The processing circuit then generates inference information on the storage device using the updated instantiation of the model, based on at least one signal to be processed. [Brief explanation of the drawing]

[0004] The following description includes a discussion of the drawings, which have examples given as implementations of embodiments of the embodiments of this disclosure. The drawings should be understood as examples, not limitations. Where used herein, references to one or more “embodiments” should be understood as describing specific features, structures, and / or characteristics contained in at least one implementation. Thus, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations, and not all necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0005] [Figure 1] The diagrams below illustrate some embodiments of the present disclosure of a system comprising a host device and a storage device having processing circuits and memory.

[0006] [Figure 2]The diagrams illustrate exemplary systems, including a host device communicating with multiple storage devices, according to some embodiments of the present disclosure.

[0007] [Figure 3] The following are illustrative diagrams of a host device for training instantiations of a model according to some embodiments of this disclosure.

[0008] [Figure 4] The flowcharts of exemplary steps for generating inference information on a storage device using a model instantiation based on at least one signal, and updating the model instantiation on the storage device, according to some embodiments of the present disclosure, are provided.

[0009] [Figure 5] The flowchart shows exemplary steps of a subprocess for generating inference information on a storage device using the instantiation of a model implemented on the storage device, as shown in Figure 4, according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0010] This disclosure provides a system and method for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) using a revisable instantiation of a model (e.g., a neural network, a machine learning neural network, or any other suitable neural network having a training / learning framework) based on at least one signal to be processed. The SSD device may implement the model to assist in instruction execution, where the model is trained on the SSD device and operations processed by the SSD are used as training data. However, if the SSD's processing circuitry is tasked with training the model, the processing circuitry has less bandwidth available to process instructions and perform operations (e.g., read and write). In addition, in a system with more than one storage device, each storage device trains its own instantiation of the model. In such a system, each SSD training its own instantiation of the model compoundes the system's limited bandwidth. This results in inefficiencies in the processing circuitry for each storage device.

[0011] If the processing circuitry of an SSD device can offload the training of model instantiations to another device (e.g., a host), the available bandwidth for each storage device improves. To improve the efficiency of the SSD device, the processing circuitry may implement model instantiation based on the trained model instantiations on the host device to process the received signals. Thus, the host is tasked with training the model instantiations and then sending the updated data (e.g., updated weights for the model) to update the model instantiations on the storage device.

[0012] The processing circuit generates inference information on the storage device by using an instantiation of the model implemented on the storage device. Each instantiation of the model includes multiple weights, each of which is determined using another instantiation of the model trained on a host coupled to the storage device. At some point after the instantiation of the model has been implemented on the storage device, the processing circuit may receive multiple updated weights from the host. Upon receiving the multiple updated weights, the processing circuit implements an updated instantiation of the model on the storage device based on these updated weights. When the processing circuit receives a signal to be processed, it generates updated inference information on the storage device using the updated instantiation of the model, based at least on the received signal to be processed. In some embodiments, the processing circuit may continuously update the instantiation of the model on the storage device by receiving further updated weights from the host.

[0013] In some embodiments, the memory of the systems disclosed herein may include any one of the following memory densities: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC), and any preferred memory density greater than 5 bits per memory cell.

[0014] For the purpose of brevity and clarity, the features of the disclosure described herein are in the context of a storage device having processing circuits and memory. However, the principles of the disclosure may be applied to any other suitable context in which it is used to generate inference information on a storage device using revisable instantiation of a model based on at least one signal to be processed. The storage device may include processing circuits and memory, which are communicatively coupled by a network bus or interface. In some embodiments, the processing circuits receive signals, updated data (e.g., updated weights), which may be driven on the network bus or interface from an external source (e.g., a host) of the storage device, or transmitted from within the storage device (e.g., from memory).

[0015] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly handling high bandwidth incoming data. For example, the processing circuit may begin generating inference information about the signal to be processed before it has finished generating inference information about previously received signals to be processed.

[0016] In some embodiments, the systems and methods of the present disclosure may refer to storage device systems (e.g., SSD storage systems) that include storage devices such as solid-state drive devices that are communicably coupled to processing circuits by a network bus or interface.

[0017] An SSD is a data storage device that uses an integrated circuit assembly as memory for permanently storing data. SSDs have no moving mechanical components, and this characteristic distinguishes them from conventional electromechanical magnetic disks such as hard disk drives (HDDs) or floppy disks, which include rotating disks and moving read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shock, operate quietly, have shorter access times, and have lower latency.

[0018] Many types of SSDs use NAND-based flash memory, including types of non-volatile storage technologies, to retain data without power. The Quality of Service (QoS) of an SSD can relate to predictable low latency and consistent high input / output operations per second (IOPS) while handling read / write input / output (I / O) workloads. This means that latency or the completion time of I / O commands must fall within a specified range without unexpected outliers. It may also be necessary to precisely adjust throughput or I / O rates without causing a sharp drop in performance levels.

[0019] The subject matter of this disclosure can be better understood by referring to Figures 1 to 5.

[0020] Figure 1 shows an exemplary diagram of a system 100 according to some embodiments of the present disclosure, comprising a host device (e.g., host 108) and a storage device 102 having processing circuitry 104 and memory 106. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive (SSD) device). In some embodiments, the processing circuitry 104 may include a processor or any preferred processing unit. In some embodiments, the memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device 102 may include a hard disk drive (HDD) device in addition to or instead of an SSD. In some embodiments, the system 100 comprises a host 108 that communicates with the storage device 102.

[0021] The host 108 includes a first instantiation 112 of the model, which may be implemented on the control circuit of the host 108. In some embodiments, the control circuit trains the first instantiation 112 of the model using simulated signals. Using the first instantiation 112 of the model, weights (e.g., updated weights 110) are determined based on the training by the host 108. Each weight of the model contributes to the decision-making of a determined outcome or result based on an input (e.g., a received signal to be processed). When the processing circuit 104 receives weights from the host 108, the processing circuit 104 implements a second instantiation 114 of the model on the storage device 102. The processing circuit 104 then generates inference information on the storage device using the second instantiation 114 of the model, based on at least one signal to be processed. The second instantiation 114 of the model may be updated when the processing circuit 104 receives updated weights 110 from the host 108. In some embodiments, the second instance 114 of the model is updatable at any time by receiving updated data (e.g., updated weights 110) via any preferred firmware update request.

[0022] In some embodiments, the processing circuit 104 is configured to generate inference information on the storage device 102 using a second instantiation 114 of the model implemented on the storage device 102. In some embodiments, the second instantiation 114 of the model is implemented based on weights received from the host 108, which determines the weights by training the first instantiation 112 of the model. The processing circuit further receives a plurality of updated weights from the host 108 and then updates the second instantiation 114 of the model based on the plurality of updated weights to implement the updated instantiation on the storage device 102. Once the second instantiation 114 of the model is updated to the updated instantiation of the model, the processing circuit 104 then determines the updated inference information on the storage device 102 using the updated instantiation of the model, based on at least one signal to be processed. In some embodiments, the garbage collection request includes a destination memory address corresponding to destination data that may be old or invalid. In some embodiments, the garbage collection request and weights (e.g., updated weights 110) are transmitted to the processing circuit 104 over a network bus or interface. In some embodiments, garbage collection requests and weights (e.g., updated weights 110) are transmitted from an external source (e.g., host 108). In some embodiments, the processing circuit 104 receives signals (e.g., garbage collection requests and updated weights 110) from both internal and external sources of the storage device 102. There may also be temporary memory (e.g., a cache or queue) located within the processing circuit 104, which is configured to store any pending requests to be processed by the processing circuit 104.

[0023] In addition, the storage device 102 includes a memory 106. In some embodiments, the memory 106 includes one or more non-volatile memories, such as Phase Change Memory (PCM), PCM and switch (PCMS), Ferroelectric Random Access Memory (FeRAM), or Ferroelectric Transistor Random Access Memory (FeTRAM), memristors, Spin-Transfer Torque Random Access Memory (STT-RAM), and Magnetoresistive Random Access Memory (MRAM), or any other suitable memory, or any combination thereof. In some embodiments, the memory 106 may also include volatile memory in the form of a cache. In some embodiments, memory 106 may include any one of single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any other suitable memory having a memory density greater than 5 bits per memory cell. In some embodiments, processing circuit 104 is communicatively coupled to memory 106 to store and access data used to execute signals / requests. In some embodiments, a data bus between memory 106 and processing circuit 104 provides a network bus for accessing or writing data to memory 106. In some embodiments, the processor or processing unit of processing circuit 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof.The processor, also referred to herein as processing circuit 104, may include any suitable software, hardware, or both for controlling the memory 106 and the processing circuit 104. In some embodiments, the storage device 102 may further include a multicore processor. The memory 106 may also include hardware elements for non-temporary storage of instructions, commands, or requests.

[0024] The processing circuit 104 is configured to generate inference information on the storage device using a revisable instantiation of the model based on at least one signal to be processed, where the instantiation of the model is implemented on the storage device using weights received from a host device having another instantiation of the trained model on the host device. Additionally, the processing circuit 104 may receive updated weights 110 from the host 108. The updated weights 110 are determined by using a first instantiation 112 of the model being trained on the host 108. The updated weights 110 are used to implement a second instantiation 114 of the model on the storage device 102. Each weight of the model contributes to a decision of a determined outcome or result based on an input (e.g., a received signal to be processed). When the processing circuit 104 receives the updated weights 110 from the host 108, the processing circuit 104 updates the second instantiation 114 of the model on the storage device 102. The processing circuit 104 then generates updated inference information on the storage device using the updated second instantiation of the model based on at least one signal to be processed. These processes enable the host 108 to train an instantiation of the model on the host 108 (e.g., the first instantiation 112 of the model) without communicating with the storage device 102 and then update the instantiation of the model implemented on the storage device 102 (e.g., the second instantiation 114 of the model). This allows at least one storage device (e.g., the storage device 102) to have the instantiation of the model being trained by the centralized host 108 while the implemented instantiation of the model is in use, and the implemented instantiation of the model can be updated at any time by receiving updated data (e.g., the updated weights 110) via any suitable firmware update request.

[0025] A storage device (e.g., an SSD device) may include one or more packages of memory dies (e.g., including memory 106), where each die includes storage cells. In some embodiments, the storage cells are organized into pages, and the pages are organized into blocks. Each storage cell may store one or more bits of information.

[0026] While system 100 shows one embodiment in which storage device 102 is configured to have the ability to generate inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed in accordance with the present disclosure, it will be understood that any other suitable device may be implemented in a similar manner.

[0027] For purposes of clarity and conciseness and not by way of limitation, the present disclosure is provided in the context of generating inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed that provides the features and functions disclosed herein. The process of generating inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed may be configured by any suitable software, hardware, or both for implementing such features and functions. Generating inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed may be implemented at least in part, for example, in storage device 102 (e.g., as part of processing circuitry 104 or as any other suitable device). For example, in the case of a solid state storage device (e.g., storage device 102), generating inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed may be implemented in processing circuitry 104.

[0028] Figure 2 shows an exemplary diagram of a system 200 including a host device 108 communicating with a plurality of storage devices (e.g., storage device_1 202, storage device_2 204, storage device_3 206, and storage device_N 208) according to some embodiments of the present disclosure.

[0029] Host 108 includes a first instantiation 112 of the model, which may be implemented on the control circuit of Host 108 and trained thereon. Host 108 is communicably coupled to each of the storage devices (e.g., 202, 204, 206, and 208) by a network interface or data bus. Each of the storage devices (e.g., 202, 204, 206, and 208) has its respective instantiations of the model implemented on the respective storage device (e.g., a second instantiation 203 of the model, a third instantiation 205 of the model, a fourth instantiation 207 of the model, and the nth instantiation 209 of the model). Host 108 is configured to train the first instantiation 112 of the model to determine the updated weights 110, and the updated weights 110 are sent via the network interface or data bus to each of the storage devices (e.g., storage device_1 202, storage device_2 204, storage device_3 206, and storage device_N 208). When each storage device receives the updated weights 110 from Host 108, each storage device 102 updates its respective instantiation of the model with the updated weights 110. This system 200 enables a distributed system with multiple storage devices having instantiations of the model, where the instantiations of the model can be updated simultaneously.

[0030] Figure 3 shows an exemplary diagram of how a host 108 trains an instantiation of a model (e.g., a first instantiation of the model 112) according to some embodiments of the present disclosure. The host 108 includes a control circuit 302, a first instantiation of the model 112 implemented on the control circuit 302, and a training module 304. The training module 304 is configured to send a simulated signal 306 to the first instantiation of the model 112 in order to train it. The first instantiation of the model 112 generates a training result 308 based on the simulated signal 306 and sends the training result 308 to the training module 304. In some embodiments, the training module 304 further compares the training result 308 generated by the first instantiation of the model 112 with the expected training result corresponding to the simulated signal 306. The weights of the first instantiation of the model 112 may be adjusted based on the comparison of the training result 308 with the expected training result corresponding to the simulated signal 306. In some embodiments, a comparison of the training result 308 with the expected training result may also be used to determine the effectiveness of the first instantiation 112 of the model and whether the first instantiation of the model needs to be further trained.

[0031] At any point in time, the control circuit 302 of the host 108 may send the updated weights 310 to the storage device 102. In some embodiments, the updated weights 310 are received by the processing circuit 104 and used to implement a second instantiation 114 of the model. In some embodiments, the updated weights 310 are sent to the storage device 102 via a data bus or network interface that connects the host 108 to the storage device 102 in a communicative manner. In some embodiments, the first instantiation 112 of the model is trained by the control circuit 302 without communicating with the storage device 102, and then the instantiation of the model implemented on the storage device 102 (e.g., a second instantiation 114 of the model) is updated.

[0032] Figure 4 shows a flowchart 400 of exemplary steps for generating inference information on a storage device using a model instantiation based on at least one signal and updating the model instantiation on the storage device, according to some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuit, memory, host, updated weights, first instantiation of the model, second instantiation of the model, control circuit, training module, and simulated signal may be implemented as storage device 102, processing circuit 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, second instantiation of the model 114, control circuit 302, training module 304, and simulated signal 306, respectively. In some embodiments, the process 400 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0033] In step 402, the processing circuit generates inference information on the storage device using an instantiation of the model implemented on the storage device, where the instantiation of the model includes multiple weights, each of which is determined using another instantiation of the model trained on a host device coupled to the storage device. In some embodiments, the processing circuit implements an instantiation of the model (e.g., a second instantiation of the model) on the storage device using the multiple weights received from the host. In some embodiments, the host includes a control circuit for training another instantiation of the model (e.g., a first instantiation of the model) using a simulated signal similar to the expected signal that the processing circuit will receive and process. In addition, the host's control circuit may include a training module for creating a simulated signal and sending it to the other instantiation of the model (e.g., the first instantiation of the model), and then comparing the expected result of the simulated signal with the test result received from the other instantiation of the model (e.g., the first instantiation of the model). In some embodiments, the host trains the other instantiation of the model based on the simulated signal while the host is not communicably coupled to the storage device. The weights are determined by the host and sent to the processing circuit of the storage device to implement the instantiation of the model (e.g., a second instantiation of the model). In some embodiments, the processing circuit generates inference information using the implemented instantiation of the model based on at least one signal received by the processing circuit. In some embodiments, the generated inference information includes a predicted action to be performed by the processing circuit based on at least one received signal. In some embodiments, the predicted action may be one of the following: a workload detection action, a thermal action, a storage device optimization action, or a storage device arbitration action. Once the inference information is generated on the storage device, the processing circuit may receive a plurality of updated weights from the host device in step 404.

[0034] In step 404, the processing circuit receives a plurality of updated weights from the host device in the storage device. In some embodiments, the processing circuit receives a plurality of updated weights from a firmware update request sent from the host. In some embodiments, the processing circuit receives updated weights from a network interface or data bus that connects the storage device to the host in a communicative manner. If the processing circuit of the storage device has received a plurality of updated weights from the host device, the processing circuit then, in step 406, updates the instantiation of the model based on the plurality of updated weights to implement the updated instantiation of the model on the storage device.

[0035] In step 406, the processing circuit updates the model instantiation based on a plurality of updated weights to implement the updated model instantiation on the storage device. In some embodiments, the number of updated weights may be the same as the number of weights that implemented the original model instantiation on the storage device. Once the updated model instantiation is implemented on the storage device, in step 408, the processing circuit generates updated inference information on the storage device using the updated model instantiation based on at least one signal to be processed.

[0036] In step 408, the processing circuit generates updated inference information on the storage device using an updated instantiation of the model, based on at least one signal to be processed. In some embodiments, the generated updated inference information is the expected behavior that the processing circuit will perform based on at least one signal. In some embodiments, even given the same signal received by the processing circuit, the updated inference information generated using the updated instantiation of the model may differ from the inference information generated using a previous version of the instantiation of the model. In some embodiments, the updated instantiation of the model may be updated when the processing circuit receives any other updated weights from the host.

[0037] Figure 5 shows a flowchart of exemplary steps of a subprocess for generating inference information on a storage device using instantiation of a model implemented on the storage device (for example, in 402 as shown in Figure 4), according to some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuit, memory, host, updated weights, first instantiation of the model, and second instantiation of the model may be implemented as storage device 102, processing circuit 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, and second instantiation of the model 114, respectively. In some embodiments, the subprocess 500 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0038] In step 502, the processing circuit determines a moving average from at least one signal to be processed and generates inference information based on the determined moving average. In some embodiments, the moving average may be determined based on a predetermined number of signals received by the processing circuit. For example, the instantiation of a model implemented on a storage device may be used to generate inference information for workload discovery. In such an example, the processing circuit of the storage device may receive signals such as instructions or operations to be processed by the processing circuit, and then predict expected instructions or operations based on a moving average of previously received signals. In some embodiments, the moving average is continuously adjusted based on the most recently received signals in the storage device.

[0039] Unless otherwise explicitly specified, the terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments.”

[0040] Unless otherwise explicitly specified, the terms “including,” “comprising,” and “having,” and their variations, mean “including, but not limited to.”

[0041] Unless otherwise explicitly stated, the list of enumerated items does not imply that any or all of the items are mutually exclusive.

[0042] Unless otherwise explicitly specified, the terms “a,” “an,” and “the” mean “one or more.”

[0043] Unless otherwise explicitly specified, multiple devices communicating with each other do not need to communicate with each other continuously. In addition, multiple devices communicating with each other may communicate directly or indirectly through one or more intermediate media.

[0044] A description of an embodiment having multiple components communicating with one another does not imply that all such components are required. On the contrary, various optional components are described to illustrate a wide variety of conceivable embodiments. Furthermore, while processing steps, method steps, algorithms, or the like may be described in a sequential order, such processing, methods, and algorithms may be configured to function in alternative orders. In other words, any order or sequence of steps that may be described does not necessarily imply that these steps must be performed in that order. The processing steps described herein may be performed in any practical order. Furthermore, several steps may be performed simultaneously.

[0045] Where a single device or article is described herein, it will be readily apparent that more than one device / article (whether they work together or not) may be used instead of a single device / article. Similarly, where more than one device or article (whether they work together or not) is described herein, it will be readily apparent that a single device / article may be used instead of more than one device or article, or that a different number of devices / articles may be used instead of the number of devices or programs shown. The functions and / or features of a device may be embodied by one or more other devices not expressly described as having such functions / features. Therefore, other embodiments do not necessarily have to include the device itself.

[0046] At least certain operations, which may be shown in the figures, represent specific events occurring in a specific order. In alternative embodiments, specific operations may be performed, modified, or omitted in a different order. Furthermore, steps may be added to the logic described above, and it may still conform to the embodiments described. Moreover, the operations described herein may be performed sequentially, or certain operations may be processed in parallel. Furthermore, operations may be performed by a single processing unit or by distributed processing units.

[0047] The above description of various embodiments is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact forms disclosed. In light of the above teachings, many modifications and variations are possible.

Claims

1. A method for processing at least one signal on a storage device: The step of generating inference information on the storage device using an instantiation of a model implemented on the storage device, wherein the instantiation of the model includes a plurality of weights, and the plurality of weights are determined using another instantiation of the model that has been trained on a host device coupled to the storage device; The storage device receives a plurality of updated weights from the host device; A step of updating the instantiation of the model based on the plurality of updated weights to implement the updated instantiation of the model; and A step of generating updated inference information on the storage device using the updated instantiation of the model based on the at least one signal. A method for providing this.

2. The method according to claim 1, wherein while the host device is not communicably coupled to the storage device, other instances of the model are trained on the host device based on simulated data.

3. The method of claim 2, wherein the simulated data used to train the other instantiations of the model is determined by the host device based on a subset of signals that are expected to be processed by the instantiations of the model on the storage device.

4. The method according to claim 1, wherein the inference information includes predicted actions from a plurality of actions.

5. The method according to claim 4, wherein the plurality of operations include one or more of the following: (a) workload detection operations, (b) thermal arbitration operations, (c) device power optimization operations, or (d) device bandwidth arbitration operations.

6. The step of generating inference information on the storage device using the instantiation of the aforementioned model is: The step of determining a moving average from at least one of the aforementioned signals, wherein the step of generating inference information includes the step of generating inference information based on the moving average. The method according to claim 1, comprising:

7. memory; and Processing circuit A storage device comprising: To implement the instantiation of the model on the storage device, a plurality of weights are received from the host device, where the instantiation of the model includes a plurality of weights, and each of the plurality of weights is determined using another instantiation of the model that has been trained on the host device. Inference information is generated using the instantiation of the model implemented on the storage device. The host device receives multiple updated weights. Based on the aforementioned multiple updated weights, update the instantiation of the model to implement the updated instantiation of the model, and Based on at least one signal to be processed, updated inference information is generated on the storage device using the updated instantiation of the model. A storage device, intended for that purpose.

8. The storage device according to claim 7, wherein while the host device is not communicably coupled to the storage device, other instances of the model are trained on the host device based on simulated data.

9. The storage device according to claim 8, wherein the simulated data used to train the other instantiations of the model is determined by the host device based on a subset of signals that are expected to be processed by the instantiations of the model on the storage device.

10. The storage device according to claim 7, wherein the inference information includes predicted actions from a plurality of actions.

11. The storage device according to claim 10, wherein the plurality of operations include one or more of the following: (a) workload detection operations, (b) thermal arbitration operations, (c) device power optimization operations, or (d) device bandwidth arbitration operations.

12. To generate inference information on the storage device using the instantiation of the aforementioned model, the processing circuit: A moving average is determined from the at least one of the aforementioned signals, wherein generating inference information includes generating inference information based on the moving average. The storage device according to claim 7, which is for the purpose of...

13. It is a system: The host, the aforementioned host is: It has a control circuit coupled to a communication bus, and the control circuit is: To provide an inference output, a first instantiation of the model is trained, where the first instantiation of the trained model includes a plurality of weights. The communication bus is used to communicate the plurality of weights to the storage device, and Multiple updated weights are communicated to the storage device using the aforementioned communication bus. It is for the purpose of, The storage device coupled to the communication bus, the storage device is: memory; and Processing circuit The processing circuit has: The receiving of the aforementioned multiple weights, Based on the aforementioned multiple weights, a second instance of the model is implemented on the storage device. Based on at least one signal to be processed, inference information is generated using a second instantiation of the model. The host receives multiple updated weights. Based on the aforementioned multiple updated weights, update the second instantiation of the model to implement the updated second instantiation of the model, and The updated inference information is generated using the updated second instance of the aforementioned model. It is for that purpose. A system equipped with these features.

14. The system according to claim 13, wherein the first instance of the trained model is trained on the host based on simulated data while the host is not communicably coupled to the storage device.

15. The system according to claim 14, wherein the simulated data used to train the first instantiation of the trained model is determined by the control circuit based on a subset of signals that are expected to be processed by the second instantiation of the model.

16. The aforementioned control circuit features: The simulated data is communicated to the first instance of the model. The training results are received from the first instantiation of the aforementioned model. In response to a comparison between the training results and the expected training results corresponding to the simulated data, corrected simulated data is determined, and The modified simulated data is communicated. The system according to claim 14, which is for the purpose of

17. The system according to claim 13, wherein the inference information includes predicted actions from a plurality of actions.

18. The system according to claim 17, wherein the plurality of operations include one or more of the following: (a) workload detection operations, (b) thermal arbitration operations, (c) power optimization operations, or (d) bandwidth arbitration operations.

19. To generate inference information using the instantiation of the aforementioned trained model, the processing circuit: A moving average is determined from the at least one of the aforementioned signals, wherein generating inference information includes generating inference information based on the moving average. The system according to claim 13, which is for the purpose of

20. The system according to claim 13, further comprising a plurality of storage devices, wherein the storage device is one of the plurality of storage devices, and each storage device is coupled to the host via the communication bus.

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