Integrated circuits with microvolt memory

Abstract

An integrated circuit is disclosed herein comprising a plurality of microvolts, each spaced apart from one another and adjacent to a first surface. The plurality of microvolts include a first microvolt. Furthermore, the integrated circuit comprises a plurality of junction areas, each located adjacent to one of the plurality of microvolts on the first surface. The plurality of junction areas include a first junction area that operably communicates with the first microvolt.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed on August 11, 2023, titled "INTEGRATED CIRCUIT HAVING MEMORIES AND A SHARED WRITE PORT", identified by filing number P23 - 133 - US - PSP, the entire content of which is incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed on November 27, 2023, titled "METHOD AND SYSTEM FOR KNOWN - GOOD - DIE TESTABILITY OF FACE - TO - FACE BONDED CHIPLETS", the entire content of which is incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed on November 27, 2023, titled "SYSTEM AND METHOD FOR HAVING CORRECT - BY - CONSTRUCTION TIMING CLOSURE", the entire content of which is incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed on March 20, 2024, titled "ASSEMBLY HAVING A FACE - TO - FACE BONDED CHIPLET", identified by filing number P24 - 052 - US - PSP, the entire content of which is incorporated herein by reference.

[0005] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed on 23 April 2024, identified by reference number P24-081-US-PSP, entitled “INTEGRATED CIRCUIT HAVING MICROVAULT MEMORIES,” the entire contents of which are incorporated herein by reference.

[0006] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed on 23 April 2024, identified by reference number P24-082-US-PSP, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS,” the entire contents of which are incorporated herein by reference.

[0007] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed on 23 July 2024, identified by reference number P24-135-US-PSP, entitled “SYSTEM, METHOD, AND APPARATUS FOR WAFER-SCALE MEMORY,” the entire contents of which are incorporated herein by reference. [Background technology]

[0008] Technical field This disclosure relates to an integrated circuit. More specifically, this disclosure relates to an integrated circuit having multiple modules, including microvolt memory.

[0009] Description of related technologies A chiplet refers to a small chip designed to function as a single entity while utilizing advanced packaging technology. This miniaturized chip is created by dividing a larger chip into several smaller chips, each possessing a unique function or capability. The concept, stemming from the semiconductor industry, requires overcoming the physical limitations of traditional monolithic chip designs and achieving higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality. [Overview of the project] [Problems that the invention aims to solve]

[0010] Chiplets are derived from different architectures such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways according to the requirements of a specific application. One of the advantages of the chiplet approach is that different chiplets from different manufacturers can be mixed and matched to create custom solutions that meet specific computing requirements. Because chiplets can be upgraded or replaced without requiring a complete system redesign, this approach also enables shorter time to market, reduced development costs, and increased flexibility.

[0011] Chiplets can be used in a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chiplets are expected to play a crucial role in future computing and are thought to unlock new possibilities for creating more powerful and / or advanced electronic devices. [Means for solving the problem]

[0012] Summary of the Invention

[0013] Integrated circuits, which may be part of semiconductor devices, are disclosed herein. Methods for manufacturing or writing and reading data to and from the modules are disclosed herein and may be used in conjunction with all examples, embodiments, and aspects described herein.

[0014] The integrated circuit may comprise a plurality of microvolts, each of which is spaced apart from the others and adjacent to a first surface. The plurality of microvolts includes a first microvolt. Furthermore, the integrated circuit may comprise a plurality of junction areas, each of which is adjacent to each of the plurality of microvolts on the first surface. The plurality of junction areas includes a first junction area that operably communicates with the first microvolt.

[0015] In some embodiments, the integrated circuit may include a first junction area located adjacent to a first microvolt on a first surface. This first junction area may optionally include a plurality of junctions, each junction operably communicating with the first microvolt.

[0016] In some embodiments, the first joint area may include a plurality of joints, each operably communicating with the first microvolt. Optionally, these plurality of joints may be bumpless joints.

[0017] In some embodiments, the integrated circuit may have a first microvolt having a capacity between 4 kilobytes and 1 megabyte.

[0018] In some embodiments, the first microvolt has a capacity between 4 kilobytes and 128 kilobytes.

[0019] In some embodiments, the microvolt may have a storage capacity ranging from 4 kilobytes to 16 kilobytes.

[0020] In some embodiments, the first microvolt has dimensions of less than 256 micrometers by less than 256 micrometers and may extend a predetermined distance in the vertical dimension.

[0021] In some embodiments, the first microvolt has dimensions of 32 micrometers by 32 micrometers and extends a predetermined distance in the vertical direction.

[0022] In some embodiments, the integrated circuit may include a first microvolt having a vertical dimension corresponding to at least eight memory layers. Specifically, in one embodiment, the first microvolt has dimensions of 32 micrometers by 32 micrometers and extends a predetermined distance in the vertical dimension. This vertical dimension corresponds to at least eight memory layers in some embodiments.

[0023] In some embodiments, the bit density of the first microvolt may be greater than 0.2 gigabits per square millimeter for each layer of the microvolt.

[0024] In some embodiments, a plurality of microvolts including the first microvolt may be disposed in the backend of the lines of the die.

[0025] Optionally, an embodiment of the integrated circuit may include a SRAM volt disposed adjacent to the first microvolt.

[0026] The integrated circuit may include a SRAM volt disposed adjacent to the first microvolt, and the first bonding area communicates operably with the SRAM volt. In some embodiments, the integrated circuit may include a second bonding area disposed on a first surface that communicates operably with the SRAM volt.

[0027] In some embodiments, the integrated circuit may further include a second bonding area disposed on the first surface and operatively communicating with the SRAM voltage. The second bonding area enables connection and data transfer between the SRAM voltage components and other components within the system.

[0028] In some embodiments, the integrated circuit may include a plurality of microvolts formed on a first die and an SRAM voltage formed on a second die, and the first and second dies are bonded together.

[0029] In some embodiments, the integrated circuit may further include a DRAM (Dynamic Random Access Memory) voltage disposed adjacent to the microvolt. The DRAM voltage provides an additional memory storage area that can be utilized with the microvolt memory.

[0030] In some embodiments, the integrated circuit may include a DRAM voltage disposed adjacent to a plurality of microvolts. The first bonding area may operatively communicate with this DRAM voltage to facilitate data transfer between the first microvolt and the DRAM voltage.

[0031] In some embodiments, the integrated circuit further includes a second bonding area disposed on the first surface mentioned above. This second bonding area operatively communicates with the DRAM voltage also mentioned above. By operatively communicating, data and signals can be exchanged between the second bonding area and the DRAM voltage.

[0032] In some embodiments, the integrated circuit may include a plurality of microvolts formed on a first die and a DRAM voltage formed on a third die. The first and third dies may be rigidly fixed together.

[0033] In some embodiments, the integrated circuit further comprises a read address register operably connected to the first junction area. The read address register may be configured to hold a read address and transmit it to the first microvolt.

[0034] In some embodiments, the integrated circuit further comprises a read data register. The read data register may be operably connected to the first microvolt to receive and hold read data from the first microvolt.

[0035] In some embodiments, the integrated circuit further comprises a read data register operably connected to the first microvolt to receive and hold read data from the first microvolt. The read data register may be operably connected to the first junction area to transmit the held read data to the first junction area.

[0036] The integrated circuit may include a read data register operably connected to a second junction area to transmit read data to a second junction area of ​​a plurality of junction areas. In some embodiments, the read data register receives and holds read data from a first microvolt and then transmits this read data to a second junction area.

[0037] In some embodiments, the integrated circuit may further include a second read data register that operably communicates with the first read data register. The second read data register may be configured to receive and hold read data from the first read data register.

[0038] The integrated circuit may include a second read data register located on a die having a second face, the second face including a read data junction area operably connected to a first junction area of ​​the first face.

[0039] In some embodiments, the integrated circuit may further include a second read data register located on a die having a second face. This second read data register is configured to receive and hold read data from the first read data register. Optionally, this second face of the die includes a read data junction area operably connected to a second junction area of ​​the first face to facilitate data communication between dies. Through this junction, data can be transferred from the first read data register on the first die to the second read data register on the second die.

[0040] In some embodiments, the integrated circuit may further include a second read data register located on a die different from the die having the plurality of microvolts.

[0041] In some embodiments, the integrated circuit further includes a second read address register located on a die different from the die containing the multiple microvolts. This additional read address register, located on a separate die, may be used for various purposes, such as increasing storage capacity or bandwidth for reading data from the microvolts. By distributing multiple read address registers across separate dies, the flexible architecture may be able to meet performance requirements while minimizing device footprint and power consumption.

[0042] In some embodiments, the integrated circuit further comprises a second read address register. The second read address register is configured to receive and hold read addresses. Optionally, the second read address register transmits read addresses to the first microvolt.

[0043] The integrated circuit may further include, in addition to the read address register and the second read address register, a second junction surface located on the second face. The second junction area provides an interface to the second face to facilitate communication and data transfer related to the read addressing function. Having this second junction area allows the integrated circuit to interface the read addressing architecture across multiple faces and dies.

[0044] In some embodiments, the integrated circuit may further include a second read address register. The second read address register may be located on a second die having a second face. The second read address register may be configured to receive and hold read addresses. Furthermore, the second read address register may transmit read addresses to a read address register on the first die via the second face, and the second face of the second die and the first face of the first die may be joined together.

[0045] In some embodiments, the integrated circuit further comprises a second face, and a second read address register is located on the second face. The second read address register is configured to receive and hold read addresses and to transmit read addresses to the read address register on the first face. Optionally, the second face and the first face may be joined together to facilitate communication of read addresses between the two faces.

[0046] In some embodiments, the integrated circuit further comprises a through-silicon electrode, the through-silicon electrode being operably connected at a first end to a third surface, the third surface being on the opposite side of the first surface.

[0047] In some embodiments, the integrated circuit further comprises an interconnect connected to a first surface on which a plurality of microvolts are arranged. This interconnect is also connected to a second end of a through-silicon electrode that facilitates communication between dies. The through-silicon electrode has a first end connected to a third surface on the opposite side of the first surface.

[0048] In some embodiments, the integrated circuit further comprises a second microvolt that operably communicates with the first junction area.

[0049] In some embodiments, the integrated circuit may further include a multiplexer operably connected to the first microvolt to receive first read data from the first microvolt. The multiplexer may also be operably connected to the second microvolt to receive second read data from the second microvolt. The multiplexer may be configured to select for output between the first read data from the first microvolt and the second read data from the second microvolt.

[0050] In some embodiments, the integrated circuit further comprises a counter operably connected to a multiplexer. The counter is configured to control the multiplexer to sequentially read first read data from a first microvolt and second read data from a second microvolt.

[0051] In some embodiments, the integrated circuit further includes a read data register configured to receive first read data from a first microvolt selected by a multiplexer or second read data from a second microvolt. The read data register internally holds the received first or second read data.

[0052] In some embodiments, the integrated circuit further comprises a second junction area on the first face. A read data register is connected to this second junction area to transmit held first or second read data from the multiplexer to the second junction area.

[0053] In some embodiments, the integrated circuit further comprises an assembly including a first die having a plurality of microvolts.

[0054] In some embodiments, the integrated circuit further comprises an assembly including a first die having a plurality of microvolts. This plurality of microvolts in the first die includes a first microvolt and a second microvolt.

[0055] In some embodiments, the integrated circuit further comprises an assembly including a first die having a plurality of microvolts, including a first microvolt and a second microvolt, and a second die having a read address register and a read data register. The first die may be bonded to the second die in this assembly.

[0056] In some embodiments, the integrated circuit may include an assembly in which a first die and a second die are joined together. The first die may have a plurality of microvolts, including a first microvolt and a second microvolt, while the second die may have a read address register and a read data register. In addition to the first joining area described above, the first die may include a second joining area on the first face. Furthermore, the second die may include a third joining area and a fourth joining area. The various joining areas may be connected such that the first joining area of ​​the first die is connected to the third joining area of ​​the second die, while the second joining area of ​​the first die is connected to the fourth joining area of ​​the second die.

[0057] In some embodiments, the integrated circuit further includes a read address register operably connected to a third junction area of ​​a second die to transmit a read address to a third junction area of ​​the second die. The read address register is configured to hold a read address and communicate the read address to a first microvolt on the first die via a third junction area connected to a first junction area of ​​the first die.

[0058] In some embodiments, the integrated circuit further comprises a read data register operably connected to a fourth junction area of ​​a second die to receive read data from the fourth junction area of ​​the second die. The read data register is configured to receive and hold read data communicated from the fourth junction area of ​​the second die, which is junctioned to a first die having a plurality of microvolts.

[0059] In some embodiments, the integrated circuit may include an assembly comprising a first die having a plurality of microvolts, such as a first microvolt and a second microvolt. The first die may also include a second read address register configured to receive and hold read addresses. This second read address register may be configured to transmit read addresses to the first and second microvolts.

[0060] In some embodiments, the assembly may include a first die having a plurality of microvolts, including a first microvolt and a second microvolt. The first die may further include a multiplexer configured to select between the output of the first microvolt and the output of the second microvolt.

[0061] In some embodiments, the integrated circuit may further include a second junction area on a second face of a first die having a plurality of microvolts. The interconnect may connect this second junction area to the input of a multiplexer configured to select between the output of the first microvolt, the output of the second microvolt, and communications received from the second junction area.

[0062] In some embodiments, the integrated circuit may further include a phase counter configured to control a multiplexer to select between outputs from a first microvolt and a second microvolt. The phase counter facilitates sequential reading of data from multiple microvolts through the use of a multiplexer.

[0063] In some embodiments, the integrated circuit may further include a third address register configured to receive and hold the output of a multiplexer. The multiplexer may be configured to select one of a plurality of microvolts, and a phase counter may be configured to control the selection of the multiplexer. The third address register may receive and hold the output selected by the multiplexer.

[0064] The integrated circuit may include an assembly comprising a first die having a plurality of microvolts, including a first microvolt and a second microvolt, and a second die having a read address register and a read data register, wherein the first die is bonded to the second die. In some embodiments, the first die may further include a multiplexer configured to select between the outputs of the first microvolt and the outputs of the second microvolt, and a third address register configured to receive and hold the output of the multiplexer. Optionally, the third address register may be operably connected to a second bonded area of ​​the first die.

[0065] The integrated circuit may further include a read address register and a through-silicon swivel (TSV) connected to a second face of the die where the read address register is located. In some embodiments, the TSV facilitates the communication of data, such as read addresses, between the read address register and components located on the opposite side of the die.

[0066] In some embodiments, the integrated circuit further comprises a second through-silicon electrode (TSV) connected to a second bonding area and a second read data register on a second face of the first die. The second TSV facilitates data communication between the second bonding area on the second face of the first die and a second read data register on another die. This configuration enables efficient transfer of read data between multiple dies that are stacked and bonded together.

[0067] In some embodiments, the integrated circuit may include a multiplexer configured to select one of several microvolts. The multiplexer enables selective access to data from different microvolts.

[0068] In some embodiments, the integrated circuit may further include a phase counter configured to control the selection operation of a multiplexer that selects one of a plurality of microvolts. The phase counter provides a control signal to the multiplexer to facilitate continuous access to data from the plurality of microvolts.

[0069] In some embodiments, the integrated circuit further comprises through-silicon electrodes (TSVs) operably connected to a first and second surface of a die having a plurality of microvolts. The TSVs facilitate communication between the first surface having the plurality of microvolts and junction areas, and the opposite second surface of the die.

[0070] In some embodiments, the integrated circuit further includes a through-silicon electrode configured to facilitate communication between a second die connected to a first die having a plurality of microvolts. The through-silicon electrode enables die-to-die communication and integration between the microvolt dies and additional dies in a multi-die assembly.

[0071] In some embodiments, the integrated circuit may include a first microvolt comprising at least one column of 3D-NOR formed from a plurality of transistors. Each transistor in the 3D-NOR column may include a gate connected to a read-write enable line, a source connected to a bit line, and a drain connected to a select line.

[0072] In some embodiments, the integrated circuit may include a first microvolt comprising a column of 3D-NAND formed from multiple transistors. Each transistor in the column may have a gate terminal connected to a read / write enable line, a source terminal connected to a bit line, and a drain terminal connected to the source terminal of an adjacent second transistor in the column. The 3D-NAND column configuration in the first microvolt can facilitate a dense vertical stacking of transistors while allowing separate control of read and write operations through independent enable lines.

[0073] In some embodiments, the integrated circuit may comprise a first microvolt containing a column of 3D-NAND having a pass gate formed from multiple transistors. Each transistor in the 3D-NAND column may have a gate connected to a read / write enable line, a source connected to a bit line, and a drain connected to the source of a second transistor. Furthermore, the pass gate may be connected to all of the multiple transistors in the 3D-NAND column.

[0074] In some embodiments, the integrated circuit may include a first microvolt comprising a column of 3D-NOR (three-dimensional Nor gate) gates formed from multiple transistors, each having independent read and write enable lines. Each transistor in the 3D-NOR gate may have a source terminal connected to a bit line, a drain terminal connected to a read enable line, and a gate terminal connected to a write enable line. The independent read and write enable lines allow for separate control of reading from and writing to the microvolt.

[0075] In some embodiments, the microvolts may include a thermal management layer configured to dissipate the heat generated by the microvolts during operation. This thermal management layer may optionally include a material having high thermal conductivity, selected from the group consisting of copper, aluminum, diamond, and graphene, to facilitate heat dissipation.

[0076] In some embodiments, the integrated circuit further comprises a thermal management layer configured to dissipate heat generated by microvolts during operation. This thermal management layer may optionally include a material having high thermal conductivity, selected from the group consisting of copper, aluminum, diamond, and graphene.

[0077] In some embodiments, the integrated circuit further comprises a hardware-based encryption module operably connected to at least one microvolt. The encryption module functions to secure data written to or read from the microvolt. By incorporating hardware-based encryption into the integrated circuit, data stored in the microvolt can be protected.

[0078] In some embodiments, the integrated circuit further includes a power management circuit configured to regulate the voltage and current supplied to a plurality of microvolts. The regulation of voltage and current by the power management circuit may be based on the operating status of the microvolts. For example, the power management circuit may include a low-power mode that reduces the power supply to the microvolts during periods of inactivity.

[0079] The integrated circuit may include a power management circuit configured to adjust the voltage and current supplied to a plurality of microvolts based on the operating status of the plurality of microvolts. In some embodiments, the power management circuit includes a low-power mode that reduces the power supply to the microvolts during periods of inactivity.

[0080] In some embodiments, the integrated circuit may further include signal conditioning circuits operably connected to a plurality of microvolts. The signal conditioning circuits may be configured to improve the signal integrity of data transfers to and from the microvolts. Optional components of the signal conditioning circuits may include filters, amplifiers, or error correction encoders.

[0081] In some embodiments, the integrated circuit further comprises signal conditioning circuits operably connected to a plurality of microvolts to improve the integrity of the data transfer signals. The signal conditioning circuits may include filters, amplifiers, or error correction encoders to improve the integrity of the signals.

[0082] In some embodiments, the integrated circuit further includes a diagnostic module configured to monitor the health and performance of the microvolt and report indicators to an external controller. The diagnostic module may also be capable of performing self-tests on the microvolt and generating alerts if a malfunction is detected.

[0083] In some embodiments, the integrated circuit further includes a diagnostic module configured to monitor the health and performance of the microvolt and report indicators to an external controller. Optionally, this diagnostic module can perform a self-test on the microvolt and generate an alert if a malfunction is detected.

[0084] In some embodiments, each microvolt may include a built-in self-healing mechanism capable of isolating and bypassing faulty memory cells. The self-healing mechanism may optionally utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace faulty cells.

[0085] In some embodiments, each microvolt may include a built-in self-healing mechanism capable of isolating and bypassing faulty memory cells. This self-healing mechanism may utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace any faulty cells detected.

[0086] In some embodiments, the microvolts may be arranged in a matrix configuration to enable parallel processing and data acquisition.

[0087] In some embodiments, the microvolts may be arranged in a matrix configuration to enable parallel processing and data acquisition. The matrix configuration may optionally include row and column decoders to facilitate access to individual microvolts.

[0088] In some embodiments, the integrated circuit further comprises a flexible substrate. The flexible substrate allows the integrated circuit to be adapted to a non-planar surface.

[0089] In some embodiments, the integrated circuit further comprises a flexible substrate that allows the circuit to conform to non-planar surfaces. The flexible substrate may be made of materials such as polyimide, PEEK (polyetheretherketone), liquid crystal polymer, flexible glass, or a combination thereof. By using a flexible substrate, embodiments can be applied to curved or irregular surfaces and function appropriately on those surfaces.

[0090] In some embodiments, the integrated circuit may include a first microvolt configured to operate as a cache memory for the processor. The cache memory may operate in one or more modes, such as write-through, write-back, write-around, or a combination thereof.

[0091] In some embodiments, the first microvolt may be configured to operate as cache memory for the processor. The cache memory may operate in one or more cache modes, such as write-through, write-back, write-around, or a combination thereof.

[0092] In some embodiments, multiple microvolts may form a redundant array of independent memory elements. This redundant array of independent memory elements enables error correction and facilitates data recovery in the event of a memory failure. Specifically, a first microvolt may be configured as one element in an array of redundant independent memory blocks, allowing data errors or defects in one block to be reconstructed from other independent blocks. The redundant array architecture provides fault tolerance and reliability to help ensure continued operation.

[0093] In some embodiments, the first microvolt may include a crossbar switch architecture to facilitate data routing between memory cells. This crossbar switch architecture can enable non-blocking data transfer within the integrated circuit.

[0094] The integrated circuit may include a crossbar switch architecture associated with a first microvolt to facilitate data routing between memory cells. In some embodiments, this crossbar switch architecture is configured to enable non-blocking data transfer within the integrated circuit.

[0095] In some embodiments, the integrated circuit may include a first microvolt that includes a dedicated read peripheral. Specifically, the first microvolt may optionally have its own read peripheral, separate from other components, to facilitate data readout. This dedicated read peripheral for the first microvolt enables optimization of readout performance.

[0096] In some embodiments, the integrated circuit may include a dedicated read port operably connected to the first microvolt. This allows read operations to be performed on the first microvolt independently of write operations, enabling simultaneous read and write access. The dedicated read port improves overall data throughput by eliminating contention between data reads and writes.

[0097] In some embodiments, the integrated circuit may include a dedicated writing peripheral associated with the first microvolt. This allows writing operations to the first microvolt to be handled by a dedicated writing circuit tuned for efficient writing. The dedicated writing peripheral facilitates rapid and reliable data storage within the microvolt by optimizing the writing path.

[0098] In some embodiments, the integrated circuit may include a dedicated write port operably connected to the first microvolt. This dedicated write port facilitates writing data to the first microvolt independently of read operations, enabling simultaneous read and write access. The dedicated write port can improve overall data throughput to and from the microvolt.

[0099] The integrated circuit may include a first transistor having a channel layer formed using a semiconductor material and a ferroelectric layer rigidly connected to the channel layer. The first transistor may further include a source terminal fixed to the channel layer, a drain terminal fixed to the channel layer, and a gate terminal fixed to the ferroelectric layer.

[0100] In some embodiments, the channel layer of the first transistor may be formed from polycrystalline silicon. Using polycrystalline silicon for the channel layer provides known electrical properties that enable the transistor to function properly.

[0101] In some embodiments, the channel layer of the transistor may be formed from an amorphous oxide semiconductor. This amorphous oxide semiconductor material can provide desirable properties such as high carrier mobility and low off-state current when used as a channel layer, while also being suitable for deposition on standard CMOS materials during back-end processing of the line. Examples of amorphous oxide semiconductors that can be used include, in particular, indium oxide, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), cadmium oxide, hafnium indium zinc oxide (HIZO), tin oxide, and indium tin zinc oxide (ITZO). The amorphous oxide semiconductor channel layer may also be doped with elements such as gallium, indium, zinc, tin, hafnium, silicon, aluminum, and others to optimize carrier concentration and mobility.

[0102] In some embodiments, the amorphous oxide semiconductor forming the channel layer of the first transistor may include at least one of the following: indium oxide, indium gallium zinc oxide, zinc tin oxide, indium zinc oxide, zinc gallium oxide, aluminum zinc oxide, cadmium oxide, hafnium indium zinc oxide, tin oxide, tin(II) oxide, tin(IV) oxide, indium tin zinc oxide, indium tungsten oxide, indium gallium zinc tin oxide, indium gallium zinc oxynitride, aluminum indium gallium zinc oxide, and zinc indium oxide.

[0103] In some embodiments, the amorphous oxide semiconductor channel layer is made of gallium (Ga), indium (In), zinc (Zn), tin (Sn), hafnium (Hf), silicon (Si), aluminum (Al), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), zirconium (Zr), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), cerium (Ce), lanthanum (La), neodymium (Nd) The transistor may be doped with at least one dopant selected from the group consisting of samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y), scandium (Sc), bismuth (Bi), lead (Pb), thallium (Tl), antimony (Sb), arsenic (As), phosphorus (P), boron (B), nitrogen (N), fluorine (F), chlorine (Cl), bromine (Br), and iodine (I). Channel layer doping may improve certain characteristics of the transistor, such as carrier mobility, threshold voltage, subthreshold swing, on-state current, and off-state current.

[0104] In some embodiments, the channel layer of the first transistor is formed from a two-dimensional material containing a transition metal dichalcogenide. The transition metal dichalcogenide may be in monovalent or divalent form. In certain embodiments, the chalcogenide element in the transition metal dichalcogenide is sulfur, selenium, or tellurium.

[0105] Transition metal dichalcogenides (TMDs) may also be written as MX2, where M refers to a transition metal atom such as molybdenum (Mo), tungsten (W), platinum (Pt), and palladium (Pd), while X refers to a chalcogen atom such as sulfur (S), selenium (Se), and tellurium (Te). TMDs exhibit a wide range of electrical properties, from semiconductors [molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), and tungsten diselenide (WSe2)] to semimetals [molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), and titanium diselenide (TiSe2)], metals [niobium disulfide (NbS2), titanium disulfide (TiS2), nickel disulfide (NiS2), and vanadium diselenide (VSe2)], and superconductors [niobium diselenide (NbSe2) and tantalum sulfide (TaS2)].

[0106] In some embodiments, the channel layer of the integrated circuit is formed from a two-dimensional material containing a transition metal dichalcogenide. In these embodiments, the transition metal dichalcogenide may be monovalent.

[0107] In some embodiments, the channel layer of the integrated circuit embodiment may be formed from a two-dimensional transition metal dichalcogenide material. Specifically, the transition metal dichalcogenide may have a divalent transition metal composition. Using a divalent transition metal dichalcogenide for the channel layer enables electrical characteristics suitable for the operation of transistors formed from the components of the integrated circuit.

[0108] In some embodiments, the transition metal dichalcogenide in which the channel layer is formed may have a chalcogenide element that is sulfur.

[0109] In some embodiments, the integrated circuit may comprise a transition metal dichalcogenide on which a channel layer is formed. The transition metal dichalcogenide may be monovalent or divalent. Optionally, the chalcogenide element in the transition metal dichalcogenide may be selenium.

[0110] In some embodiments, the integrated circuit may include a channel layer formed from a two-dimensional material containing a transition metal dichalcogenide. The transition metal dichalcogenide may have a chalcogenide element such as tellurium.

[0111] In some embodiments, the channel layer of the transistor may be formed from indium tungsten oxide (IWO). This material can provide desirable properties for the channel layer, such as high mobility with respect to charge carriers. The use of IWO enables the manufacture of high-performance transistors suitable for a variety of integrated circuit applications.

[0112] In some embodiments, the channel layer of the transistor may be formed from indium gallium zinc oxide (IGZO). When deposited as a thin film, IGZO material provides desirable properties for the channel layer, such as high electron mobility and stability, enabling the effective operation of the transistor in the integrated circuit.

[0113] In some embodiments, the channel layer may be a thin film.

[0114] The embodiment may include a ferroelectric layer composed of hafnium-zirconium oxide (Hf0.5Zr0.5O2) having an equal molar ratio of hafnium to zirconium.

[0115] In some embodiments, the integrated circuit comprising a ferroelectric FET may be located in the back-end (BEOL) portion of the semiconductor device manufacturing flow line. More specifically, this involves manufacturing the integrated circuit, which includes the ferroelectric layer and channel layer of the FET, in higher layers above the transistor level after the front-end processing of the line is complete. Depositing the integrated circuit in the BEOL portion enables integration with the underlying transistor structure and metal interconnect layer already manufactured on the chip.

[0116] In some embodiments, the ferroelectric layer in the integrated circuit is made of a transition metal oxide, perovskite, or two-dimensional material.

[0117] In some embodiments, the integrated circuit further comprises a metal layer disposed between the channel layer and the ferroelectric layer.

[0118] In some embodiments, the integrated circuit further comprises an insulating layer disposed between the metal layer and the channel layer. Specifically, the metal layer may be disposed between the channel layer and the ferroelectric layer. Furthermore, the insulating layer is disposed between this metal layer and the underlying channel layer.

[0119] In some embodiments, the integrated circuit further comprises a metal layer disposed on a ferroelectric layer, the ferroelectric layer being disposed on a channel layer.

[0120] In some embodiments, the integrated circuit further comprises a metal layer disposed on a ferroelectric layer, the ferroelectric layer being disposed on a channel layer. Furthermore, in some embodiments, an insulating layer is disposed on the channel layer, and the ferroelectric layer is also disposed on the insulating layer.

[0121] The embodiment may further include a metal layer disposed on the ferroelectric layer, where the ferroelectric layer is located on the channel layer. This additional metal layer on the ferroelectric material can serve various purposes, such as providing improved electrical contacts or functioning as a barrier layer. The integration of the ferroelectric layer and the metal layer on the channel layer enables optimization of the electrical performance and reliability of the ferroelectric field-effect transistor.

[0122] In some embodiments, the channel layer of the integrated circuit may have a thickness of less than 30 nm. Configuring the channel layer to this thinness allows for a reduction in the dimensions of the transistor formed using the channel layer, and potentially an improvement in performance.

[0123] In some embodiments, the channel layer may have a thickness of 1 nm to 30 nm. Configuring the channel layer to be less than 30 nm thick allows for effective charge modulation by adjacent ferroelectric layers within this extreme dimensional scale. Maintaining dimensions at the lower end of this range, for example, 1 nm to 10 nm, enables the integrated circuit to leverage improved channel controllability and reduced short-channel effects. Therefore, relatively thin channel layer dimensions facilitate low-voltage operation and efficient switching.

[0124] In some embodiments, the channel layer of the transistor may be formed using physical vapor deposition or chemical vapor deposition. These deposition techniques can be used to deposit the very thin film required for the channel layer. The channel layer formed by this method may have a thickness of less than 30 nm or between 1 nm and 30 nm.

[0125] In some embodiments, the channel layer of an integrated circuit is formed using atomic layer deposition. This manufacturing process allows for precise thickness control and uniform coverage during the deposition of thin channel layers. By constructing the channel layer with one atomic layer at a time through a series of self-limiting surface reactions, atomic layer deposition enables sub-nanometer thickness control.

[0126] Embodiments may include a channel layer formed by adding a dopant comprising at least one of tungsten, gallium (Ga), and zinc (Zn). In some embodiments, the channel layer is formed using physical vapor deposition or chemical vapor deposition, and the dopant helps to enable the deposition of a thin channel layer.

[0127] The embodiment may include a ferroelectric layer formed using atomic layer deposition.

[0128] In some embodiments, the ferroelectric layer of the integrated circuit may be formed using vapor deposition.

[0129] In some embodiments, a ferroelectric layer in an integrated circuit is formed by adding a dopant containing at least one of lanthanum, niobium, manganese, zirconium, tin, strontium, calcium, yttrium, or magnesium. The doped ferroelectric layer may be formed using atomic layer deposition or vapor deposition. Doping of the ferroelectric material may optionally improve properties such as crystallization temperature, remanent polarization, and leakage current.

[0130] In some embodiments, the channel layer may be configured to have a carrier concentration ranging from 10^17 / cubic centimeter to 10^20 / cubic centimeter.

[0131] In some embodiments, the channel layer comprises a two-dimensional material. The two-dimensional material may maintain an electron mobility of at least 0.1 square cm / volt-s when the thickness of the channel layer is less than 30 nm. In certain embodiments, the channel layer comprises fewer than five monolayers of the two-dimensional material.

[0132] In some embodiments, the channel layer comprises a two-dimensional material. The two-dimensional material may be configured to maintain an electron mobility of at least 0.1 square cm / volt-s when the thickness of the channel layer is less than 30 nm.

[0133] In some embodiments, the channel layer may include a two-dimensional material that maintains high electron mobility even when the channel layer thickness is less than 30 nm. Optionally, the channel layer may comprise fewer than five monolayers of this two-dimensional material. Using only a few monolayers can help minimize thickness while retaining the beneficial properties of the two-dimensional material.

[0134] In some embodiments, the ferroelectric layer used in the integrated circuit is hafnium zirconium oxide.

[0135] In some embodiments, the integrated circuit has a ferroelectric layer having a coercivity voltage of -3 volts to 3 volts. This specifies a voltage range in which the electric polarization of the ferroelectric material within the layer can be switched. By adjusting the composition and thickness of the ferroelectric layer, the ferroelectric layer may exhibit a coercivity voltage within this range, enabling switching at low voltages suitable for transistor operation. Maintaining a relatively low coercivity voltage can help reduce the operating voltage and power consumption of the device incorporating the ferroelectric layer.

[0136] In some embodiments, the integrated circuit may have a ferroelectric layer having an off-state current of less than 10^-7 amperes / cubic centimeter.

[0137] In some embodiments, the integrated circuit may include a ferroelectric layer having an on-state current greater than 10^-7 amperes / cubic centimeter.

[0138] In some embodiments, the integrated circuit has a ferroelectric layer having a crystallization annealing temperature of 500°C or less.

[0139] In some embodiments, the integrated circuit may include a ferroelectric layer having a residual polarization greater than 10 microcoulombs / square centimeter.

[0140] In some embodiments, the integrated circuit may include a channel layer that is annealed at a temperature below 450°C. Specifically, a channel layer that forms part of the transistor structure in the integrated circuit may undergo an annealing process below 450°C. Maintaining a sufficiently low annealing temperature for the channel layer facilitates the integration of ferroelectric materials while maintaining the integrity of the channel layer itself during device manufacturing.

[0141] In some embodiments, the embodiment includes a channel layer having a channel mobility of less than 100 square cm / volt-s. Specifically, the channel layer, which is part of an integrated circuit having a transistor including a channel layer, a ferroelectric layer, a source terminal, a drain terminal, and a gate terminal, has a channel mobility configured to be less than 100 cm^2 / Vs.

[0142] In some embodiments, the integrated circuit includes a channel layer having a subthreshold swing of less than 0.3 volts / decade. Subthreshold swing refers to the change in gate voltage required to reduce the current in the transistor by one decade, and a lower subthreshold swing enables faster switching speeds and lower power consumption. By using new materials and optimized interfaces between layers, the channel layer can achieve this ultra-low subthreshold swing.

[0143] In some embodiments, the channel layer in the integrated circuit may be configured to have an off-state current of less than 10^-7 amperes / micrometer.

[0144] In some embodiments, the embodiment includes a channel layer configured to have a channel bandgap greater than 2.5 electron volts.

[0145] In some embodiments, the channel layer may be configured to have an annealed threshold voltage of -1.5 volts to 1.5 volts.

[0146] In some embodiments, the integrated circuit may include a first transistor having a width of less than 200 nm and a length of 50 nm.

[0147] The first transistor may have a device area less than 30 times the square of the feature size.

[0148] In some embodiments, the integrated circuit may have a first transistor having a low-voltage threshold (LVT) level greater than -2.5V.

[0149] In some embodiments, the integrated circuit may have a first transistor having a high-voltage threshold (HVT) level greater than -2V.

[0150] In some embodiments, a memory cell incorporating a first transistor has a read voltage of 0V to 1V. Operating the memory cell with the first transistor at this read voltage range may facilitate low power consumption during read operations. Configuring the transistor characteristics to enable a low read voltage may also contribute to minimizing the overall power requirements of the integrated circuit.

[0151] In some embodiments, memory cells incorporating the first transistor may have low read energy consumption of less than 10 picojoules. Specifically, memory cells including the ferroelectric field-effect transistors detailed above may optionally be designed and configured to enable read operations that dissipate less than 10 picojoules of energy. Extremely low read energy enables the manufacture of low-power non-volatile memories that are well-suited for battery-powered and energy-constrained applications.

[0152] In some embodiments, the memory cell incorporating the first transistor may have a readout pulse width of less than 20 nanoseconds.

[0153] In some embodiments, the memory cell having the first transistor may have a read endurance of 10^9 cycles or more. This indicates that the memory cell can reliably withstand at least 1 billion read operations without failure, contributing to high reliability and a long operating life.

[0154] In some embodiments, the memory cell incorporating the first transistor may have read disturb resistance for more than 10^9 cycles. This indicates that the memory cell can withstand at least 10^9 read cycles without disturbing or corrupting the stored data, enabling reliable long-term data storage. High read disturb resistance is achieved in part by the properties and configuration of the ferroelectric layer, channel layer, and other components in the first transistor.

[0155] In some embodiments, the memory cell incorporating the first transistor may have a read-after-write latency of 10 microseconds or less. This indicates a very short time delay between the completion of a write operation to the memory cell and the reliable retrieval of stored data. This high-speed read access time enables the construction of high-performance memory systems.

[0156] In some embodiments, the memory cell incorporating the first transistor described herein has a write voltage of 3.0 volts (V) or less.

[0157] In some embodiments, the memory cell incorporating the first transistor may have a write speed of 10 microseconds or less.

[0158] In some embodiments, the memory cell having the first transistor described herein has a write energy of less than 10 picojoules.

[0159] In some embodiments, memory cells incorporating the first transistor may have write endurance of more than 10^8 cycles. This indicates that the memory cell can withstand at least 100 million write cycles without failure, enabling reliable data storage and retrieval over an extended lifespan. By leveraging the performance characteristics of the underlying ferroelectric field-effect transistor, each memory cell can offer improved endurance and lifespan compared to conventional options. Higher write endurance further leads to improved data integrity and a reduced need for error correction or redundancy.

[0160] In some embodiments, the memory cell having the first transistor described herein has an off-state resistance to on-state resistance ratio (Roff / Ron) greater than about 10^3 or 10^2.

[0161] In some embodiments, a memory cell incorporating a first transistor may have an on-state current-to-off-state current ratio (Ion / Off) greater than 100 at Vread from a DC measurement. Specifically, a memory cell having a ferroelectric field-effect transistor may achieve a high on-state-to-off-state current ratio during read operation, demonstrating excellent discrimination between logic 0 and logic 1 states stored in the cell. A high Ion / Ioff ratio contributes to reliable read operation at low voltages.

[0162] In some embodiments, the memory cell may include a first transistor as described herein and a second transistor having the same configuration as the first transistor. The first and second transistors can form bit states to store binary values ​​in the memory cell.

[0163] In some embodiments, the integrated circuit may include a memory cell having a first transistor, the first transistor configured to have three or more states, each of which corresponds to a stored value in the memory cell. This enables multi-level data storage within a single memory cell.

[0164] In some embodiments, the integrated circuit may include a first transistor having an on-state current to off-state current ratio (Ion / Ioff) at Vread from a pulse measurement that is greater than 10^2.

[0165] In some embodiments, the integrated circuit comprises a first transistor as described herein. Optionally, the first transistor is 10 -14 The transistor may include an off-state leakage current (Ioff) of less than amperes / micrometer, providing very low leakage when the transistor is not conducting in the off state. By having an off-state leakage current below this threshold, the transistor exhibits very little leakage through the channel, effectively maintaining the off state and enabling low static power consumption.

[0166] In some embodiments, the memory cell having the first transistor may have a reliability endurance of 10^11 cycles or more. This high reliability endurance allows the memory cell to withstand a very large number of read / write cycles without failing over its lifetime. Robust endurance enables applications requiring frequent data access with minimal downtime for repair or replacement.

[0167] In some embodiments, the memory cell having the first transistor described herein has a retention time of at least 1 minute when measured at room temperature of 25°C.

[0168] In some embodiments, the channel layer of the first transistor may include the incorporation of another two-dimensional material configured to improve the on-state current (ION) through the transistor. The additional two-dimensional material provides increased conductivity to enable higher ION when the transistor is switched on.

[0169] In some embodiments, the channel layer in an integrated circuit is configured to maintain high mobility despite the presence of a ferroelectric layer. Specifically, the channel layer and the ferroelectric layer are designed such that the ferroelectric layer does not significantly hinder electron mobility within the channel layer. This allows the integrated circuit transistor to operate at high channel mobility for improved performance while still utilizing the advantages of the ferroelectric layer.

[0170] In some embodiments, the integrated circuit may be configured such that the ferroelectric layer does not significantly impede electron mobility in the channel layer. The ferroelectric layer and the channel layer may be designed to maintain high mobility despite the presence of the ferroelectric layer above the channel layer. For example, the interface between the ferroelectric layer and the channel layer may be optimized to minimize scattering of electrons flowing through the channel.

[0171] In some embodiments, the channel layer is configured to be in direct contact with the ferroelectric layer without an intervening interface layer. Direct contact between the channel layer and the ferroelectric layer facilitates minimizing the voltage drop across the interface, thereby enabling low-voltage operation of the transistor. Furthermore, the absence of an interface layer between the channel layer and the ferroelectric layer may enable low-voltage operation and reduced power consumption.

[0172] In some embodiments, the integrated circuit may include a first transistor having a channel layer that directly contacts a ferroelectric layer without an intervening interface layer. This direct contact configuration may help minimize the voltage drop across the interface between the channel layer and the ferroelectric layer. By reducing this parasitic voltage drop, the first transistor may operate at a lower voltage, thereby enabling lower voltage operation and reduced power consumption. The absence of an interface layer may also contribute to faster switching times and improved transient characteristics.

[0173] The integrated circuit may include a first transistor characterized by low-voltage operation and low power consumption. This is due, in some embodiments, to the absence of an interface layer between the channel layer and the ferroelectric layer.

[0174] In some embodiments, the integrated circuit may include a first transistor characterized by low-voltage operation and low power consumption. This may be due to the absence of an interface layer between the ferroelectric layer and the gate layer of the first transistor. Reduced-voltage operation can contribute to a reduction in the overall power consumption of the integrated circuit.

[0175] In some embodiments, the integrated circuit is characterized by low-voltage operation and low power consumption due to the absence of an interface layer between the channel layer and the ferroelectric layer, or between the ferroelectric layer and the gate layer. This reduced voltage operation may contribute to a reduction in the overall power consumption of the integrated circuit.

[0176] In some embodiments, the integrated circuit may include a first transistor characterized by improved switching characteristics, such as faster on and off times. This may be due to the absence of an interface layer between the ferroelectric layer and the channel layer, or between the ferroelectric layer and the gate layer. The absence of an interface layer contributes to reduced parasitic capacitance at these interfaces, which may allow for faster charging and discharging of the ferroelectric layer during the transistor's write and erase operations.

[0177] In some embodiments, the integrated circuit may feature reduced parasitic capacitance at the interface between the channel layer and the ferroelectric layer due to the absence of an interface layer between the channel layer and the ferroelectric layer. Direct contact between the channel layer and the ferroelectric layer can minimize the voltage drop across the interface, enabling low-voltage operation of the transistor. Furthermore, the reduced parasitic capacitance may contribute to improved switching characteristics of the transistor, including faster on and off times.

[0178] In some embodiments, the ferroelectric layer may be configured to have a substantially uniform electric field distribution across the ferroelectric layer.

[0179] In some embodiments, the integrated circuit may include a ferroelectric layer configured such that there is a gradient in the electric field distribution across the ferroelectric layer.

[0180] In some embodiments, the integrated circuit further comprises a microvolt formed from a plurality of transistors, including a first transistor as described herein. The microvolt may be organized into a column comprising a 3-terminal bit cell. Optionally, the microvolt is formed via the column in one of the following configurations: 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND-PG.

[0181] In some embodiments, the microvolt comprises a column of three-terminal bit cells. Specifically, the multiple transistors constituting each microvolt may be arranged in a vertical column, with each column functioning as a bit cell having three terminals: source, drain, and gate terminals corresponding to the transistors in that column. This three-terminal bit cell configuration in column form facilitates the compact integration and wiring of the microvolt memory structure.

[0182] In some embodiments, the integrated circuit may comprise microvolts formed from multiple transistors. The microvolts may be organized into columns comprising three-terminal bit cells in one of several configurations, including 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND with additional pass gates (3D-NAND-PG).

[0183] In some embodiments, the integrated circuit may include a channel material comprising indium gallium zinc oxide (IGZO). A channel material formed from IGZO may be incorporated into the transistors described herein.

[0184] The embodiment may include a source terminal fixed to the channel layer. In some embodiments, the source terminal is formed from at least one of tungsten, titanium nitride, nickel, and molybdenum.

[0185] In some embodiments, the drain terminal of the first transistor comprises at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials may be used to form the drain contact to enable effective carrier transport and accumulation within the manufacturing process flow.

[0186] In some embodiments, the gate terminal of the first transistor includes at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials are used in semiconductor manufacturing processes due to their conductivity and integration compatibility. The selection of an appropriate gate terminal material can affect the performance and reliability of the transistor.

[0187] In some embodiments, the integrated circuit further comprises a memory formed from a plurality of first transistors. The memory may be formed as a 3D vertical device architecture selected from NAND and NOR configurations.

[0188] In some embodiments, the integrated circuit comprises a microvolt column having multiple transistors. Each of the multiple transistors in the microvolt column may be configured in the same way as the first transistor described above. Microvolt columns having multiple identical transistors may be organized into a 3D vertical architecture such as 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND with a pass gate.

[0189] In some embodiments, the integrated circuit may include a microvolt column comprising multiple transistors, each of which is identical to the first transistor. The microvolt column may be organized in a 3D-NOR configuration.

[0190] In some embodiments, the integrated circuit comprises a microvolt column having multiple transistors, each transistor configured according to a first transistor. The microvolt column may be configured as a 3D-AND structure.

[0191] In some embodiments, the integrated circuit may include a microvolt column comprising multiple transistors, each configured similarly to the first transistor. The microvolt column may be arranged in a 3D-NAND configuration.

[0192] In some embodiments, the integrated circuit may comprise a microvolt column comprising multiple transistors, each of which is configured according to the first transistor design as described above. The microvolt column may be organized in a 3D-NAND architecture having pass gates connected to all of the multiple transistors.

[0193] In some embodiments, the integrated circuit may include a microvolt column comprising multiple transistors, each transistor including a source connected to a bit line, a drain connected to a read enable line, and a gate connected to a write enable line. This microvolt column configuration allows for independent control of read and write operations through separate read enable and write enable lines.

[0194] In some embodiments, the integrated circuit may comprise a microvolt column comprising multiple transistors, each formed similarly to the first transistor. The microvolt column may be configured as a 3D-AND architecture with independent read / write enable lines connected to each transistor. Specifically, each transistor in the 3D-AND microvolt column may have a source terminal connected to a bit line, a drain terminal connected to a select line, and a gate terminal connected to a read / write enable line independent of the other transistors.

[0195] In some embodiments, the ferroelectric layer used in the integrated circuit is perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), and zinc bismuth niobate (Bi(Zn1 / 2Ti1 / 2)O3). This includes bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), lead magnesium niobate-lead titanate (PMN-PT), lead zirconate titanate lanthanum (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium oxides such as hafnium oxide (HfO2) and zirconium-doped hafnium oxide (HfZrO2), barium strontium niobate (BSN), lead barium niobate (PBN), and potassium nitalate niobate. Tungsten bronze structural materials containing (KTN), bismuth layered ferroelectric materials such as bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), and calcium bismuth niobate (CBN), organic ferroelectric materials such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), and P(VDF-TrFE) copolymer, Auribilius oxide phase, rare earth manganese such as YMnO3 and lanthanum-modified lead zirconate titanate (PLZT), nickel manganese oxide (NiMnO3), and lead niobate It is formed from a variety of ferroelectric materials, including, but not limited to, relaxa ferroelectrics containing nesium (PMN), lead scandium tantalate (PST), and lead indium niobate (PIN); multiferroic materials such as terbium manganite (TbMnO3) and europium titanium oxide (EuTiO3); SbSI (antimony iodide sulfide); GeTe (germanium telluride); SnTe (tin telluride); thin-film ferroelectrics such as PZT thin films, SBT thin films, and HfO2-based thin films; layered superlattices; and PbTiO3 / SrTiO3.A wide range of ferroelectric materials provides flexibility when designing integrated circuits, depending on the intended application and desired device characteristics.

[0196] In some embodiments, the integrated circuit comprises a first vertical structure having a dielectric column, a channel column arranged around the dielectric column, and a ferroelectric column arranged around the channel column along the length of the channel column. The integrated circuit further comprises a plurality of horizontal gate electrode layers, each arranged at a predetermined distance from one another. Each of the horizontal gate electrode layers is arranged adjacent to the ferroelectric column along the length of the ferroelectric column.

[0197] Embodiments of the integrated circuit may have a dielectric column that is substantially cylindrical in shape. Specifically, the dielectric column, around which channel columns are arranged, may be formed to have a circular or elliptical cross-section along its vertical length. Making the dielectric column cylindrical may facilitate conformal deposition of the surrounding channel layer.

[0198] In some embodiments, the dielectric column in the first vertical structure is substantially cylindrical. The dielectric column may have a first diameter at the first end and a second diameter at the second end. Optionally, the first and second diameters may be the same, or the first diameter may be larger than the second diameter.

[0199] In some embodiments, the dielectric column of the first vertical structure is substantially cylindrical, having a first diameter at the first end and a second diameter at the opposite second end. Optionally, the first and second diameters of the dielectric column may be configured to be the same.

[0200] In some embodiments, the dielectric column in the first vertical structure has a first diameter at the first end and a second diameter at the second end, where the first diameter is larger than the second diameter.

[0201] In some embodiments, the integrated circuit comprises a first vertical structure having dielectric columns. The dielectric columns may be configured as solid columns rather than hollow columns. Forming the dielectric columns as solid structures can provide mechanical stability and robustness to the entire vertical stack.

[0202] In some embodiments, the integrated circuit may include a hollow dielectric column. Specifically, the dielectric column positioned around the channel column in the first vertical structure may optionally be configured as a hollow column rather than a solid column. This hollow configuration of the dielectric column may facilitate certain manufacturing processes or allow additional components to be integrated within the column. However, in other embodiments, the dielectric column may instead be implemented as a solid column.

[0203] In some embodiments, the shape of the channel column formed around the dielectric column in the first vertical structure may be substantially cylindrical. For example, the channel column may have a circular or oval cross-section along its vertical length. A cylindrical channel column configuration may offer certain advantages related to current, capacitance, or ease of manufacture.

[0204] In some embodiments, the channel column formed around the dielectric column is substantially cylindrical, as described in the overview section. Optionally, the channel column has a first diameter at the first end and a second diameter at the second end. In certain embodiments, the first and second diameters may be the same. In other embodiments, the first diameter may be larger than the second diameter.

[0205] In some embodiments, the channel column of the first vertical structure has a substantially cylindrical shape with a uniform diameter from the first end to the second end.

[0206] In some embodiments, the integrated circuit comprises a first vertical structure having a dielectric column having a first diameter at a first end and a second diameter at a second end, wherein the first diameter is greater than the second diameter.

[0207] The ferroelectric column may be substantially cylindrical. In some embodiments, the integrated circuit further comprises a first vertical structure having a ferroelectric column arranged around a channel column. Optionally, this ferroelectric column may be formed in a substantially cylindrical shape.

[0208] In some embodiments, the integrated circuit may have a ferroelectric column that is substantially cylindrical, as described for the first vertical structure. This ferroelectric column may have a first diameter at a first end and a second diameter at the opposite second end. The first and second diameters may be the same, or in some cases, the first diameter may be larger than the second diameter.

[0209] In some embodiments, the integrated circuit has a ferroelectric column that is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end, where the first and second diameters may be configured to be the same.

[0210] In some embodiments, the integrated circuit may include a ferroelectric column that is substantially cylindrical. The ferroelectric column may have a first diameter at a first end and a second diameter at a second end, the first diameter being larger than the second diameter.

[0211] In some embodiments, the integrated circuit further comprises dielectric end columns positioned around the ends of the channel columns. These dielectric end columns are adjacent to the ends of the channel columns along their length and also adjacent to the ferroelectric columns.

[0212] In some embodiments, the integrated circuit further comprises a drain-selection layer positioned parallel to a plurality of horizontal gate electrode layers and adjacent to a dielectric edge column. This drain-selection layer is positioned adjacent to a dielectric edge column surrounding one end of a channel column. Positioning the drain-selection layer parallel to the horizontal gate electrode layers and adjacent to the dielectric edge column may allow access to the drain side of a vertical structure.

[0213] In some embodiments, the integrated circuit further comprises a second dielectric end column positioned around another end of the channel column. This second dielectric end column is adjacent to another end of the channel column's length and is also adjacent to the ferroelectric column.

[0214] The integrated circuit may further comprise a source selection layer arranged parallel to a plurality of horizontal gate electrode layers. This source selection layer is adjacent to a second dielectric end column, which is positioned around another end of the channel column. The second dielectric end column is adjacent to another end of the channel column's length and, in some embodiments, is adjacent to a ferroelectric column.

[0215] In some embodiments, the integrated circuit further comprises a second vertical structure. The second vertical structure may be formed to be substantially identical to the first vertical structure, or it may be positioned adjacent to the first vertical column at a predetermined horizontal distance.

[0216] In some embodiments, the integrated circuit may include a second vertical structure. The second vertical structure may be formed to be substantially identical to the first vertical structure, or it may be positioned adjacent to the first vertical column at a predetermined horizontal distance.

[0217] In some embodiments, the integrated circuit may comprise a first vertical structure and a second vertical structure, the second vertical structure being formed to be substantially identical to the first vertical structure but positioned adjacent to the first vertical column at a predetermined horizontal distance. The first and second vertical structures may be configured to form a single-port 3D NAND structure.

[0218] Optionally, in some embodiments, the multiple horizontal gate electrode layers of the first vertical structure are formed from at least one of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys, AlCu, TiW, and conductive polymers.

[0219] In some embodiments, the first vertical ferroelectric column is made of the following materials: perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), and bismuth titanate (Bi4Ti3O3). 12) Hafnium oxides such as bismuth zinc niobate (Bi(Zn1 / 2Ti1 / 2)O3), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), and hafnium oxide (HfO2) and zirconium-doped hafnium oxide (HfZrO2). This includes um oxides, tungsten bronze structural materials such as barium strontium niobate (BSN), lead barium niobate (PBN), and potassium niobate tantalate (KTN), bismuth layered ferroelectric materials including bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), and calcium bismuth niobate (CBN), and organic ferroelectric materials such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), and P(VDF-TrFE) copolymers. The material is formed from a body, an Aurivilius oxide phase, rare earth manganese such as YMnO3 and lanthanum-modified lead zirconate titanate (PLZT), relaxa ferroelectrics such as magnesium lead niobate (PMN), scandium lead tantalate (PST), and indium lead niobate (PIN), multiferroic materials such as terbium manganite (TbMnO3) and europium titanium oxide (EuTiO3), and in addition, thin-film ferroelectrics, layered superlattices, and others. The extensive list provides flexibility in selecting a ferroelectric material suitable for vertical structures in various embodiments.

[0220] In some embodiments, the first vertical channel column is composed of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), zinc gallium oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polysilicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-silicon), crystalline germanium (c-germanium), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and silicon. It is formed from at least one of the following: carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNT), methylammonium lead halide (CH3NH3PbX3, X=Cl, Br, I), cesium lead halide (CsPbX3, X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), skutterudite, rudolsden-popper phase, clathrate, perovskite oxide, or magnetic semiconductor.

[0221] In some embodiments, the first vertical dielectric column is made of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO3), or barium titanate. Strontium (BST), lead zirconate titanate (PZT), bismuth ferrite (BiFeO3), magnesium oxide (MgO), cerium oxide (CeO2), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd2O3), dysprosium oxide (Dy2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), terbium oxide (Tb4O7), ba Nadium (V2O5), niobium oxide (Nb2O5), chromium oxide (Cr2O3), iron oxide (Fe2O3), molybdenum oxide (MoO3), tungsten oxide (WO3), ruthenium oxide (RuO2), rhodium oxide (Rh2O3), palladium oxide (PdO), silver oxide (Ag2O), cadmium oxide (CdO), tin oxide (SnO2), antimony oxide (Sb2O3), tellurium oxide (TeO2), iridium oxide (IrO2), platinum oxide (PtO2), gold oxide (Au) It is formed from at least one of the following: 2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth oxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxide, layered oxide, or composite transition metal oxide.

[0222] In some embodiments, one of a plurality of horizontal gate electrode layers and the first vertical structure may be configured to form a plurality of transistors. These transistors may include a first transistor as described herein. The first vertical structure comprises a dielectric column, a channel column arranged around the dielectric column, a ferroelectric column arranged around the channel column, and a plurality of horizontal gate electrode layers arranged adjacent to the ferroelectric column.

[0223] In some embodiments, the integrated circuit may comprise a first vertical structure. The first vertical structure may comprise a pass gate electrode column. Dielectric columns may be arranged around the pass gate electrode column. Optionally, channel columns may be arranged around the dielectric columns. Furthermore, ferroelectric columns may be arranged around the channels along the length of the channel columns. The integrated circuit may further comprise a plurality of horizontal gate electrode layers, each layer arranged at a predetermined distance from one another. Each of the plurality of horizontal gate electrode layers may be arranged adjacent to the ferroelectric column along its length.

[0224] In some embodiments, the integrated circuit may include a pass gate electrode column that is substantially cylindrical in shape. This cylindrical pass gate electrode column may optionally have a first diameter at one end and a second diameter at the other end, with both diameters being the same, or the first diameter being larger than the second diameter. The pass gate electrode column may also be configured as a solid column or a hollow column in different variants.

[0225] The integrated circuit may have a substantially cylindrical pass gate electrode column according to one embodiment. In some embodiments, this pass gate electrode column has a first diameter at a first end and a second diameter at a second end. These first and second diameters may be the same or different in various embodiments, and the first diameter is optionally larger in some cases than the second diameter.

[0226] In some embodiments, the first vertical structure's pass gate electrode column is substantially cylindrical, having a first diameter at the first end and a second diameter at the opposite second end. Optionally, the integrated circuit may be configured such that the first and second diameters of the pass gate electrode column are the same.

[0227] In some embodiments, the pass gate electrode column of the first vertical structure is substantially cylindrical, having a first diameter at the first end and a second diameter at the second end. Optionally, the first diameter of the pass gate electrode column may be greater than the second diameter.

[0228] In some embodiments, the integrated circuit may include a pass gate electrode column that is part of a first vertical structure. This pass gate electrode column may be substantially cylindrical in shape. Optionally, the pass gate electrode column is solid rather than hollow.

[0229] In some embodiments, the integrated circuit may have a hollow pass gate electrode column. Specifically, the pass gate electrode column, which is part of the first vertical structure and is located within the channel column around the dielectric column, may be hollow rather than solid. Forming the pass gate electrode column in a hollow configuration may provide certain advantages related to material cost or simplification of processing.

[0230] In some embodiments, the integrated circuit may include a dielectric column that is substantially cylindrical in shape. This cylindrical dielectric column is positioned around the pass gate electrode column as part of a first vertical structure. The diameter of the dielectric column may be uniform along its length or may vary from one end to the other.

[0231] In some embodiments, the dielectric column of the first vertical structure is substantially cylindrical. Optionally, the dielectric column may have a first diameter at the first end and a second diameter at the second end. The first and second diameters of the dielectric column may be the same or different in various embodiments.

[0232] In some embodiments, the dielectric column in the first vertical structure is substantially cylindrical, having a first diameter at the first end and a second diameter at the second end. The first and second diameters of the dielectric column may be configured to be the same.

[0233] The integrated circuit may include a dielectric column that is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. In some embodiments, the first diameter of the dielectric column is greater than the second diameter.

[0234] In some embodiments, the integrated circuit may include a channel column whose shape is substantially cylindrical. The channel column is positioned around a dielectric column and is positioned around a pass gate electrode column. The ferroelectric column is positioned around the cylindrical channel column along its length.

[0235] In some embodiments, the shape of the channel column formed around the dielectric column in the first vertical structure is substantially cylindrical. The channel column may have a first diameter at the first end and a second diameter at the opposite second end. The first and second diameters of the channel column may be the same, or the first diameter may be larger than the second diameter.

[0236] In some embodiments, the channel column in the first vertical structure may have a substantially cylindrical shape with a uniform diameter along its entire length. Specifically, the channel column has a first diameter at a first end and a second diameter at the opposite second end, the first and second diameters being identical. This uniformly cylindrical channel column extends in the vertical structure parallel to the ferroelectric column and a plurality of horizontal gate electrode layers.

[0237] In some embodiments, the integrated circuit may include a substantially cylindrical channel column having a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter of the channel column is configured to be greater than the second diameter.

[0238] In some embodiments, the integrated circuit may have a ferroelectric column whose shape is substantially cylindrical. The ferroelectric column is arranged around the channel column along its length. The cylindrical ferroelectric column optionally has a first diameter at a first end and a second diameter at a second end, where the diameters may be the same, or the first diameter may be larger than the second diameter.

[0239] In some embodiments, the integrated circuit may include a ferroelectric column that is substantially cylindrical. The ferroelectric column may have a first diameter at a first end and a second diameter at a second end. Optionally, the first and second diameters may be the same, or the first diameter may be larger than the second diameter.

[0240] In some embodiments, the ferroelectric column of the first vertical structure is substantially cylindrical, having a first diameter at the first end and a second diameter at the second end. Optionally, the first and second diameters of the ferroelectric column are configured to be the same.

[0241] In some embodiments, the integrated circuit may have a ferroelectric column that is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end, where the first diameter is greater than the second diameter.

[0242] In some embodiments, the integrated circuit further comprises dielectric end columns positioned around the ends of the channel columns. These dielectric end columns are adjacent to the ends of the channel columns along their length and also adjacent to the ferroelectric columns.

[0243] In some embodiments, the integrated circuit further comprises drain-selection layers arranged parallel to a plurality of horizontal gate electrode layers. The drain-selection layers are positioned adjacent to dielectric end columns surrounding the ends of the channel columns. The dielectric end columns are adjacent to the ends of the length of the channel columns and adjacent to the ferroelectric columns in the first vertical structure.

[0244] In some embodiments, the integrated circuit further comprises a second dielectric end column positioned around another end of the channel column. This second dielectric end column is adjacent to another end of the channel column's length and is also adjacent to the ferroelectric column.

[0245] In some embodiments, the integrated circuit further comprises a source selection layer positioned parallel to a plurality of horizontal gate electrode layers and adjacent to a second dielectric end column surrounding the other end of the channel column. The source selection layer is positioned adjacent to the length end of the channel column and to the ferroelectric column.

[0246] In some embodiments, the integrated circuit further comprises a dielectric horizontal layer positioned adjacent to the end of the pass gate electrode column within the channel column. Specifically, the dielectric layer may be incorporated horizontally within the cylindrical channel column structure and positioned adjacent to the vertical end of the pass gate electrode column. This dielectric isolation layer helps define the extent of the pass gate region within the 3D-NAND string.

[0247] The integrated circuit may include a second vertical structure in addition to the first vertical structure. The first vertical structure comprises a pass gate electrode column, a dielectric column arranged around the pass gate electrode column, a channel column arranged around the dielectric column, and a ferroelectric column arranged around the channel column along its length. Each of the multiple horizontal gate electrode layers is arranged adjacent to the ferroelectric column at a predetermined distance from each other. The second vertical structure may be formed substantially identical to the first vertical structure, but may be arranged horizontally adjacent to the first vertical structure at a predetermined distance.

[0248] The integrated circuit may include a second vertical structure in addition to the first vertical structure described above. In some embodiments, this second vertical structure is formed to have substantially the same composition and dimensions as the first vertical structure. However, the second structure is positioned horizontally adjacent to the first vertical structure at a predetermined distance between the first and second vertical structures. By configuring two identical vertical structures in this parallel arrangement, it becomes possible to form certain circuit configurations, such as a dual-port 3D NAND structure having a pair of vertical structures.

[0249] The integrated circuit may include first and second vertical structures, the second vertical structure being formed to be substantially identical to the first vertical structure but positioned adjacent to the first vertical column at a predetermined horizontal distance. In some embodiments, these first and second vertical structures are configured to form a dual-port 3D NAND structure.

[0250] In some embodiments, the multiple horizontal gate electrode layers of the first vertical structure may be formed from at least one conductive material selected from the group consisting of silicides such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, TiSi2, CoSi2, and NiSi, metal alloys such as graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, AlCu, and TiW, and conductive polymers.

[0251] In some embodiments, the first vertically structured pass gate electrode column is formed from at least one of the following materials: silicides such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, TiSi2, CoSi2, and NiSi; metal alloys such as graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, AlCu, and TiW; and conductive polymers. The pass gate electrode column may be constructed using one or more of these conductive materials.

[0252] In some embodiments, the first vertical ferroelectric column is made of the following ferroelectric materials: perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), and zinc bismuth niobate. (Bi(Zn1 / 2Ti1 / 2)O3), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), lead magnesium niobate-lead titanate (PMN-PT), lead zirconate titanate lanthanum (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium oxides, hafnium oxide (HfO2), doped hafnium oxide, zirconium-doped hafnium oxide (HfZrO2), tungsten bronze structural materials, barium strontium niobate (BSN), barium lead niobate (PBN), potassium niobate tantalate (KTN), bismuth layered ferroelectric, bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectric, polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), P(VDF-TrFE) copolymer, Auribilius oxide phase, rare earth manganite, YMnO3, lanthanum-modified lead zirconate titanate (PLZT), nickel manganese oxide ( It is formed from at least one of the following: NiMnO3, relaxa ferroelectrics, magnesium lead niobate (PMN), scandium lead tantalate (PST), indium lead niobate (PIN), multiferroic materials, terbium manganite (TbMnO3), europium titanium oxide (EuTiO3), SbSI (antimony iodide sulfide), GeTe (germanium telluride), SnTe (tin telluride), thin-film ferroelectrics, PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, or PbTiO3 / SrTiO3.

[0253] In some embodiments, the first vertical channel column is made of the following materials: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), zinc gallium oxide (GZO), indium hafnium oxide (HIO), cadmium oxide (CdO), polysilicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-silicon), crystalline germanium (c-germanium), gallium arsenide (GaAs), indium phosphide (InP), and indium antimonide (InS b) The channel column is formed from at least one of the following: silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNT), methylammonium lead halide (CH3NH3PbX3, X=Cl, Br, I), cesium lead halide (CsPbX3, X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), skutterudite, rudolsden-popper phase, clathrate, perovskite oxide, and magnetic semiconductors. The selection of the channel column material can affect properties such as electron mobility, switching speed, and power consumption.

[0254] In some embodiments, the dielectric columns described herein include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO3), and varium titanate. Mustrontium (BST), lead zirconate titanate (PZT), bismuth ferrite (BiFeO3), magnesium oxide (MgO), cerium oxide (CeO2), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd2O3), dysprosium oxide (Dy2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), terbium oxide (Tb4O7), oxide Vanadium (V2O5), niobium oxide (Nb2O5), chromium oxide (Cr2O3), iron oxide (Fe2O3), molybdenum oxide (MoO3), tungsten oxide (WO3), ruthenium oxide (RuO2), rhodium oxide (Rh2O3), palladium oxide (PdO), silver oxide (Ag2O), cadmium oxide (CdO), tin oxide (SnO2), antimony oxide (Sb2O3), tellurium oxide (TeO2), iridium oxide (IrO2), platinum oxide (PtO2), gold oxide (A It is formed from at least one of the following: u2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth oxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxide, layered oxide, or composite transition metal oxide.

[0255] In some embodiments, one of a plurality of horizontal gate electrode layers and the first vertical structure may be configured to form a plurality of transistors. These transistors may include a first transistor as described herein. Specifically, the first vertical structure comprises a pass gate electrode column, a dielectric column arranged around the pass gate electrode column, a channel column arranged around the dielectric column, and a ferroelectric column arranged around the channel column along the length of the channel column. Each of the plurality of horizontal gate electrode layers is arranged adjacent to the ferroelectric column along the length of the ferroelectric column, at a predetermined distance from each other. Together, one of these horizontal gate electrode layers and the first vertical structure form a plurality of transistors, which may include a first transistor having the configuration described herein.

[0256] In some embodiments, the integrated circuit comprises a first vertical structure, which may include a vertical plug column. A source electrode column and a drain electrode column may be arranged adjacent to this vertical plug column. A channel column may be arranged around the vertical plug column, the source electrode column, and the drain electrode column. Furthermore, a ferroelectric column may be arranged around this channel column. The integrated circuit may also include a plurality of horizontal gate electrode layers, each arranged at a predetermined distance from one another. Each of these horizontal gate electrode layers may be arranged adjacent to the ferroelectric column along its length.

[0257] In some embodiments, the integrated circuit further comprises oxide / nitride / oxide stacks positioned adjacent to each of a plurality of horizontal gate electrode layers. The oxide / nitride / oxide stacks may provide electrical isolation between the gate electrode layers while allowing the layers to control channel formation in a vertical channel column structure.

[0258] In some embodiments, the vertical plug column of the integrated circuit has a first diameter at a first end and a second diameter at a second end. The first and second diameters may be the same or different.

[0259] In some embodiments, the vertical plug column of the first vertical structure has a first diameter at the first end and a second diameter at the second end. The first and second diameters may be configured to be the same.

[0260] In some embodiments, the vertical plug column in the first vertical structure has a first diameter at the first end and a second diameter at the second end, where the first diameter is larger than the second diameter.

[0261] In some embodiments, the vertical plug columns of the first vertical structure are configured to be solid rather than hollow. Specifically, the vertical plug columns involve continuous material filling rather than empty conduits. Forming the vertical plug columns in a solid configuration may provide certain advantages to the overall integrated circuit structure related to simplification of manufacturing or the integrity of adjacent components. However, other embodiments may utilize a hollow configuration for the vertical plug columns depending on specific design considerations.

[0262] In some embodiments, the integrated circuit may have a hollow vertical plug column. Specifically, the vertical plug column located adjacent to the source electrode column and drain electrode column in the first vertical structure may be hollow rather than solid. Forming a hollow vertical plug column structure allows for additional design flexibility.

[0263] In some embodiments, the integrated circuit further comprises a second vertical structure. The second vertical structure may be formed to be substantially identical to the first vertical structure, or it may be positioned adjacent to the first vertical structure at a predetermined horizontal distance. In certain embodiments, the first and second vertical structures may be configured to form a 3D AND structure or a 3D NOR structure.

[0264] In some embodiments, the integrated circuit further comprises a second vertical structure. The second vertical structure may be formed to be substantially identical to the first vertical structure, or it may be positioned adjacent to the first vertical structure at a predetermined horizontal distance.

[0265] In some embodiments, the integrated circuit may comprise a first vertical structure and a second vertical structure, the second vertical structure being formed to be substantially identical to the first vertical structure but positioned adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D AND structure.

[0266] In some embodiments, the integrated circuit may comprise a first vertical structure and a second vertical structure, the second vertical structure being formed to be substantially identical to the first vertical structure but positioned adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D NOR structure.

[0267] In some embodiments, the multiple horizontal gate electrode layers of the first vertical structure may be formed from at least one material selected from the group consisting of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

[0268] In some embodiments, the first vertically structured source electrode column is formed from at least one of the following: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, AlCu, and TiW, as well as conductive polymers.

[0269] In some embodiments, the integrated circuit further comprises a gate electrode column formed from at least one of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

[0270] In some embodiments, the first vertical ferroelectric column is made of perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), and zinc bismuth niobate (Bi(Zn1 / 2Ti1)). / 2)O3), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium oxides, hafnium oxide (HfO2), doped hafnium oxide, zirconium-doped hafnium oxide (HfZrO2), tungsten bronze structural materials, barium strontium niobate (BSN), nio Barium lead butate (PBN), potassium niobate tantalate (KTN), bismuth layered ferroelectric, bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectric, polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), P(VDF-TrFE) copolymer, Auribilius oxide phase, rare earth manganite, YMnO3, lanthanum-modified lead zirconate titanate (PLZT), nickel manganese oxide (NiMn It is formed from at least one of the following: O3, relaxa ferroelectrics, magnesium lead niobate (PMN), scandium lead tantalate (PST), indium lead niobate (PIN), multiferroic materials, terbium manganite (TbMnO3), europium titanium oxide (EuTiO3), SbSI (antimony iodide sulfide), GeTe (germanium telluride), SnTe (tin telluride), thin-film ferroelectrics, PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, and PbTiO3 / SrTiO3.

[0271] In some embodiments, the first vertical channel column contains indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), zinc gallium oxide (GZO), hafnium indium oxide (HIO), and cadmium oxide (CdO), polysilicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-silicon), crystalline germanium (c-germanium), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and silicon. It is formed from at least one of the following: concurbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNT), methylammonium lead halide (CH3NH3PbX3, X=Cl, Br, I), cesium lead halide (CsPbX3, X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), skutterudite, rudolsden-popper phase, clathrate, perovskite oxide, and magnetic semiconductors.

[0272] In some embodiments, the vertical plug column of the first vertical structure is composed of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO3), and varium titanate. Mustrontium (BST), lead zirconate titanate (PZT), bismuth ferrite (BiFeO3), magnesium oxide (MgO), cerium oxide (CeO2), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd2O3), dysprosium oxide (Dy2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), terbium oxide (Tb4O7), oxide Vanadium (V2O5), niobium oxide (Nb2O5), chromium oxide (Cr2O3), iron oxide (Fe2O3), molybdenum oxide (MoO3), tungsten oxide (WO3), ruthenium oxide (RuO2), rhodium oxide (Rh2O3), palladium oxide (PdO), silver oxide (Ag2O), cadmium oxide (CdO), tin oxide (SnO2), antimony oxide (Sb2O3), tellurium oxide (TeO2), iridium oxide (IrO2), platinum oxide (PtO2), gold oxide (A It is formed from at least one of the following: u2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth oxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxide, layered oxide, or composite transition metal oxide.

[0273] In some embodiments, the integrated circuit may comprise a plurality of transistors formed from one of the horizontal gate electrode layers and a first vertical structure, each relating to one of the transistors described herein. The first vertical structure may include components such as a vertical plug column, source and drain electrode columns, a channel column, and a ferroelectric column. The horizontal gate electrode layers may be arranged adjacent to the ferroelectric column at a predetermined distance from each other. By configuring the horizontal gate electrode layers and the first vertical structure in this manner, it is possible to form transistors having properties such as those described herein. [Brief explanation of the drawing]

[0274] Brief explanation of the drawing

[0275] These and other embodiments will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the drawings.

[0276] [Figure 1] This is a block diagram of an integrated circuit, which may be part of a semiconductor device such as a chiplet, according to embodiments of the present disclosure.

[0277] [Figure 2] Figure 1 shows a perspective view of an assembly having an integrated circuit mounted on a semiconductor device that is electrically connected to another device to form an assembly, according to an embodiment of the present disclosure.

[0278] [Figure 3] A block diagram showing the memory address space of the integrated circuit of Figure 1 is shown according to an embodiment of the present disclosure.

[0279] [Figure 4] A block diagram showing the memory address space having the signal interface of the integrated circuit of Figure 1 is shown according to an embodiment of the present disclosure.

[0280] [Figure 5]A diagram of an integrated circuit, which may be part of a semiconductor device such as a chiplet, is shown according to an embodiment of the present disclosure.

[0281] [Figure 6] Figure 1 shows a perspective view of an assembly having the integrated circuit mounted on a semiconductor device electrically connected to a system-on-chip, according to an embodiment of the present disclosure.

[0282] [Figure 7] A perspective view is shown of an assembly having a semiconductor device having an array of processing elements and a second semiconductor device having an array of microvolts.

[0283] [Figure 8] An assembly of a semiconductor device including several memory types is shown according to embodiments of this disclosure.

[0284] [Figure 9] An embodiment of the present disclosure shows an assembly of a semiconductor device including a semiconductor device having a system-on-a-chip and another semiconductor on which a microvolt is disposed.

[0285] [Figure 10] Embodiments of this disclosure show a semiconductor assembly incorporating a daisy-chain configuration of microvolts operably connected to a multiplexer and managed by counters for selection and acquisition of coordinated data.

[0286] [Figure 11] Embodiments of this disclosure show a semiconductor assembly incorporating a daisy-chain configuration of microvolts in multiple semiconductor devices operably connected to a multiplexer and managed by counters for selection and acquisition of coordinated data.

[0287] [Figure 12]According to an embodiment of the present disclosure, a three-dimensional (3D) memory column configured as a 3D-NOR or 3D-AND structure is shown, which has a series of ferroelectric field-effect transistors (FeFETs) with interconnected drain terminals linked to a common select line and individual gate terminals connected to respective read / write enable lines and all connected to a common bit line.

[0288] [Figure 13] According to an embodiment of the present disclosure, a three-dimensional (3D) memory column configured as a 3D-NAND structure composed of a vertical stack of ferroelectric field-effect transistors (FeFETs) is depicted.

[0289] [Figure 14] According to an embodiment of the present disclosure, a three-dimensional (3D) memory column configured as 3D-NAND with integrated pass gates is depicted.

[0290] [Figure 15] According to an embodiment of the present disclosure, a three-dimensional (3D) memory column 1500 is shown that can be configured as a 3D-NOR or 3D-AND structure with independent read / write enable capabilities.

[0291] [Figure 16] According to an embodiment of the present disclosure, a cross-sectional view of a 3D memory structure configured as a single-port 3D-NAND is shown.

[0292] [Figure 17] According to an embodiment of the present disclosure, a cross-sectional view of a 3D memory structure that is a dual-port 3D NAND arrangement is shown.

[0293] [Figure 18] According to an embodiment of the present disclosure, a 3D memory structure that can be configured as a 3D NOR vertical transistor memory array is shown.

[0294] [Figure 19]A planar FeFET is shown according to an embodiment of the present disclosure.

[0295] [Figure 20] The electrical characteristics of an embodiment of the FeFET are shown according to the embodiments of this disclosure. [Modes for carrying out the invention]

[0296] Modes for carrying out the invention

[0297] Figure 1 shows a block diagram of an integrated circuit 100 that can be packaged as a bondable chiplet (e.g., a bondable face-to-face chiplet) according to embodiments of the present disclosure. The integrated circuit (IC) 100 includes a group of modules 106, comprising modules 108, 110, 112, and 114. The IC 100 also features a shared write port 102 configured to write to the group of modules 106 using a write peripheral 104. Furthermore, the IC 100 includes read peripherals 116, 118, 120, and 122, as well as read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0298] The write port 102 may be configured to provide a single write address space for all of the module group 106, where each of modules 108, 110, 112, and 114 has its own dedicated read ports 124, 126, 128, and 130, respectively. The integrated circuit 100 may be packaged as part of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet or IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet may be electrically connected to another device by means of bonding, soldering, wafer-wafer bonding, face-face chiplet bonding, chiplet-wafer bonding, chiplet-interposer bonding, and / or together by an interposer or other interface connection technology. An interposer may not be used, one or more interposers may be used, or other interface connection technologies common to heterogeneous 3D system-in-package solutions may be used to electrically connect the chiplet to another device.

[0299] Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use a multicycle pipeline circuit. When bonded to another device (e.g., wafer, chiplet, chip, SOC, package, FPGA, etc.), the electrical contacts may be arranged in a manner that provides exclusive access to specific modules 108, 110, 112, 114. For example, a processing / computation element may have exclusive access to module 108 via read port 124, which may contain neural network weights in its register file. Similarly, different processing / computation elements may have exclusive read access to module 110 via read port 126, which may contain different register files. In this particular embodiment, this arrangement of electrical contacts ensures that each computing / processing element has the dedicated access it needs to efficiently perform its specific calculation, thereby providing a compact, modular, and expandable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to use the same resources in a row, which would slow down the overall processing speed. By providing dedicated access, the proposed chiplet ensures, in this particular embodiment, that each processing element can operate at its maximum capacity without interference from other computing elements.

[0300] The write peripheral 104 is a peripheral circuit responsible for processing and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts such that the chip is electrically connected (e.g., junctioned) to a chiplet of the integrated circuit, and as a result, the write port 102 is accessible via a shared write logic system that includes utilizing a shift register-based different voltage design, preferably a high-voltage design, having a shared write address and data component. This shared write logic system is designed to be accessed via a junction chip, another junction chiplet, and / or other circuitry in the same package as the integrated circuit 100. The shift register may allow the system to move data through a series of steps, each of which receives data from the previous step. By utilizing the shift register, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location where data is written to the chiplet.

[0301] In another embodiment, the interlock 132 may disable the read ports 124, 126, 128, and 130 while data is being written to the module group 106 via the write port 102. Similarly, the interlock 132 may disable the write port 102 when read operations are being performed on the read ports 124, 126, 128, and 130. The written data can then be simultaneously accessed by all processing elements that need to read the data via the respective read ports 124, 126, 128, and 130. This ensures that all processing elements have the most frequently used data available to them, regardless of other reads being performed simultaneously by other processing elements.

[0302] The circuit of the write peripheral device 104 includes a write driver. This unit receives the data to be written and converts the data into a suitable signal that can change the state of the memory cell. Depending on the type of memory technology used, the signal may include a voltage level, a current pulse, or other types of energy. The shared write logic system may be at a high voltage due to the specific voltage requirements of the die. The write driver needs to provide sufficient power to reliably change the state of the memory cell, but the write driver also needs to operate within suitable parameters to avoid causing damage or unnecessary consumption.

[0303] Also, the circuit of the write peripheral device 104 may feature a data buffer or a write buffer. This component temporarily stores the data to be written and enables the write operation to be performed at an optimal pace. By balancing the speed of the incoming data with the speed at which the memory cells can be written, the write buffer helps prevent data loss and optimizes system performance.

[0304] Also, in some embodiments, the write peripheral device 104 may include a write control unit that coordinates a series of operations in the write process. The write control unit generates control signals to activate the write driver at the appropriate time, controls the flow of data from the write buffer, and adjusts the timing of the write operation. By synchronizing these various tasks, the write control unit ensures an efficient and reliable write operation.

[0305] Also, the write peripheral device 104 may include a data encoding mechanism to improve reliability and data integrity. For example, before the data is written to the memory cells, the mechanism encodes the data in a way that enables potential errors to be detected and, in some cases, corrected when the data is read later. This can be useful in systems where data integrity has a higher priority, such as servers or scientific research devices.

[0306] Furthermore, the writing peripheral 104 may include a timing unit that functions as the heartbeat of the system, supplying a clock signal to synchronize the operation of various components of the system. In some systems, the timing unit may include components such as an oscillator, a clock generator, or a phase-locked loop. The timing unit may ensure that all operations occur at appropriate times relative to each other.

[0307] IC100 may be implemented as a face-to-face junction chiplet in which modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC100 may also feature dynamic allocation circuits for allocating memory blocks to the module group 106 based on the use of the module group 106 (for example, each module 108 may include dynamic allocation circuits that dynamically allocate a range of read locations for its respective processing elements).

[0308] IC100 features multiple clocks, each of which supplies a clock to a module of the multiple modules, providing each module with isolated timing relative to the other modules of the multiple modules. The module group 106 may be arranged in any topology known to those skilled in the art. The bit cell density can be up to 10 times denser than the embedded SRAM cells in the module group 106.

[0309] IC100 may be formed in a chiplet including a first side and a second side, the second side being configured to be bonded to a second semiconductor device. IC100 may include high-voltage writing logic adjacent to the first side of the chiplet. Decoder circuits, driver circuits, and register circuits may be formed in the silicon substrate portion of the chiplet, while the module group 106 is formed in the second layer portion of the chiplet. The second semiconductor device may comprise a plurality of processing elements. Each processing element includes an interface for communicating with each of the multiple modules in the module group 106 when the second semiconductor device is bonded to the chiplet.

[0310] Silicon substrates traditionally serve as the initial stage in IC manufacturing, focusing on the creation of active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to create the complex structures of transistors. These processes operate on a small scale. By applying photolithography, etching, and implantation techniques, it becomes possible to precisely define the transistor structure. The importance of silicon substrates lies in their ability to establish the basic building blocks necessary for signal processing, amplification, and control within the IC. This layer is sometimes referred to as the line front-end ("FEOL").

[0311] In the manufacturing process, a second layer may be added, which traditionally plays the role of interconnect manufacturing, facilitating electrical connections between various IC components. This stage has traditionally focused on creating passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The process for the second layer is typically different from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers, usually aluminum or copper, to construct a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are incorporated to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects that enable the routing and distribution of electrical signals throughout the IC. However, as described herein, circuits may also be utilized within this second layer (sometimes referred to as the back-end of the line ("BEOL")).

[0312] Alternative embodiments of IC100 may be implemented as a stacked die, monolithic design, TSV, or through-silicon electrode. In a stacked die design, several dies may be stacked on top of each other, with each die performing a different function such as memory and processing. The stacked dies may communicate through wire junctions, microbumps, or bumpless junctions. In a monolithic design, the various functions and modules of IC100 may be incorporated into a single die, forming a more compact and power-efficient design.

[0313] Furthermore, IC100 may include one or more interlocks 132 to prevent conflicts when reading or writing data. The module group 106 may be formed from various non-volatile or semi-volatile (e.g., very long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistors (FeFETs), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating-gate memory, and / or Schottky diodes.

[0314] The module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., a latch flip-flop) that ensures that stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, the module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0315] Module group 106 may utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein features a matrix of memory cells, each composed of a floating-gate transistor or a charge trap device. Module group 106 may also utilize wear-leveling techniques to extend the lifespan of the memory cells.

[0316] The module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. The FeRAM topology utilizes a ferroelectric material capable of maintaining a polarization state. In one such memory topology, in a particular embodiment, an FeFET may be used to program the ferroelectric material by holding state information. The ferroelectric material may be used to function as a memory bit cell by holding state information.

[0317] The module group 106 may utilize a phase-change memory (PCM) topology, which is a non-volatile memory technology that utilizes a reversible phase change of material to store data. The PCM topology may include any phase-change material, for example, a chalcogenide alloy or chalcogenide glass housed within the memory cell.

[0318] The module group 106 may utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistive switching phenomenon. The ReRAM topology may utilize a thin film material that exhibits a reversible change in resistance when an electrical stimulus is applied.

[0319] Module group 106 may utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a type of non-volatile memory that utilizes spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology may incorporate a magnetic tunnel junction (MTJ) structure and leverage spin-orbit interaction effects to write and read data. The magnetic tunnel junction may have a dielectric layer between the magnetic fixed layer and the magnetic free layer. Writing may be performed by switching the magnetization of the free magnetic layer by applying an in-plane current in an adjacent SOT layer. Reading may be performed by applying current to the magnetic tunnel junction. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write energy consumption.

[0320] Module group 106 may utilize a spin-transfer torque (STT) magnetic random-access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology may use a magnetic tunnel junction (MTJ) structure in which the magnetization orientation determines the stored data. Furthermore, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be modified, for example, using a spin-polarization current.

[0321] IC100 may include a single write peripheral 104 having its own dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock (not shown in Figure 1). Furthermore, the module group 106 may be organized into separate compartments, each having its own dedicated read peripheral 116, 118, 120, 122 having an independent clock.

[0322] Another possible embodiment of IC100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the packaging of IC100. Furthermore, in additional specific embodiments, IC100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) that processes data within the IC.

[0323] Figure 2 shows a perspective view of assembly 200 of the integrated circuit 212 of Figure 1, mounted on a chiplet 230 bonded to a second device 226 according to an embodiment of the present disclosure. The integrated circuit 212 is the circuit within the chiplet 230. The second device 226 may be a chiplet, a semiconductor wafer, a semiconductor package, a encapsulation circuit, etc. For example, the second device 226 may be an AI accelerator such that each processing unit has read access to one module (or a predetermined set) of the module group 236. In yet another embodiment, the second device 226 may be a network controller, where offload circuits exist to read data from each of the modules and process incoming / outgoing packets, etc. The assembly 200 includes a module group 236 having a plurality of modules, including a first module 232 and a second module 234. Figure 2 shows several modules, but for clarity only modules 232 and 234 have reference numbers. The integrated circuit 212 further includes a shared write port 222. The shared write port 222 is interfaced to the write peripheral device 202.

[0324] The second device 226 may write data to any module in the module group 236 using a shared write port 222 via an address and data bus along with a clock and enable signal, although other methods of writing data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc., may be used. Each module has a read port having a read address 218 (to send an address to module 234) and read data 214 (which is the read of data from module 232).

[0325] The module group 236 is formed in a chiplet 230 having two sides including a surface 228 that can be bonded to and complement the second device 226. The chiplet 230 may be formed by forming a circuit on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers may be in reverse order, and / or other layers may be added, removed, etc. The read address 218 and read data 220 are used to read the module 232.

[0326] The second device 226 may read data from module 232 using an address and data bus along with a clock and enable signal, but other methods for reading data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc. may be used.

[0327] All read ports (e.g., 218 and 222) are configured to be deactivated when a write operation is applied to the shared write port 222. The read ports may also be configured to handle reads simultaneously with each other. The shared write port 222 is configured to write to the address space, where it is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the multiple modules 236 includes an independent read port that reads simultaneously through its own independent read port relating to any of the multiple modules.

[0328] Each read port for each module may include contacts for a circuit found in the second device 226 for interface connection via metal contacts. Thus, there may be metal contacts on the upper layer 208 configured to interface with metal contacts on the surface 228 of the chiplet 230, and as a result, the metal contacts enable a read space having the same extent as the module read space of module 236. All of the read spaces of the module group 236 may have the same extent as one another (as described with reference to Figures 3 and 4).

[0329] In one embodiment, the read peripherals for the first module 232 are mounted on the silicon substrate 204 (sometimes referred to as the front end of the line). In the manufacturing process, a second layer 206 (sometimes referred to as the back end of the line) may then be built on top of the silicon substrate 204 (and any circuitry) and may include each memory bit cell. In an alternative embodiment, the read peripherals for the first module 232 are mounted on the second layer 206 and are located between the module group 236 and the surface 228 of the chiplet 230.

[0330] The module group 236 may be configured to process only write commands during reset. The write command may be a "slow write" command; that is, the module group 236 may have a write speed that is very low compared to the read speed of the module group 236. The write logic may be frozen (or disabled) when the module group 236 is used to read data. In some specific embodiments, the integrated circuit 212 provides the ability to allocate memory blocks to the module group 236 based on its use. In other embodiments, the memory address is fixed with the allocation. The integrated circuit 212 may be implemented as a face-to-face bonded chiplet 230. The face-to-face bond may be a bump-less wafer bond.

[0331] The module group 236 may have a single write peripheral 202. In another embodiment, each module of the module group 236 may have a dedicated write peripheral that utilizes a shared clock. In yet another embodiment, the module group 236 may also be organized into separate partitions, each having a partition with a dedicated read peripheral, where each dedicated read peripheral has an independent clock. The partitions may consist of one, two, or more modules of the module group 236.

[0332] The overall circuit architecture of the write peripheral 202 may include a set of different components, including a write driver, address decoder, sense amplifier, data input latch, data bus, and / or any combination thereof. The write driver or write buffer may be responsible for the task of transferring data to the memory cell. The write driver or write buffer may amplify the input signal to the memory cell to achieve an appropriate level. The address decoder may be used to interpret the memory address supplied as input to which data should be written. The address decoder may be used to select a target memory cell by activating specific rows and columns of the memory array linked to the address. The sense amplifier may be used to identify and amplify the signal from the memory cell during a read operation and to participate in refreshing the memory cell after data has been written during a write operation. The write operation is initiated by a write enable signal. When a write command is initiated, this signal causes the write driver and decoder to proceed with the write process. The data input latch may be used as a temporary storage unit to hold data that has been set to be written to memory until the write operation is implemented. A data bus with a transmit route may be used to facilitate the movement of data from the data input latch to the memory cell.

[0333] The write operation to the module group may be performed through a priority arbitration circuit that facilitates the access of modules in a predetermined order, and the shared write port 222 may be configured to write to a virtual address space mapped to a physical memory space. The integrated circuit 212 may include high-voltage write logic used in the write peripheral 202, and the second semiconductor device 226 may have multiple processing elements, each of which includes an interface for communicating with each module of the module group 236. Furthermore, the chiplet 230 may include an interface to the shared write port 222 on the second side, thereby interface-connecting to a complementary interface in the second semiconductor device 226.

[0334] Furthermore, the integrated circuit 212 may include a power gating circuit that selectively cuts off the power to the module 236 when it is not in use. In addition, the integrated circuit 212 may have a programming peripheral 202 for the module group 236 connected to dedicated I / O pads to enable data transfer outside the integrated circuit package.

[0335] The integrated circuit 212 may utilize multiple modules of a group of modules 234 that are grouped together. These modules may be synchronized with one another in certain embodiments. In some cases, all modules are synchronized, while in other examples, only specific modules are synchronized. For example, the circuitry in the second device 226 may need to be synchronized with a specific module when reading data from one of the modules in the module group 236.

[0336] To synchronize the modules, the integrated circuit 212 may use various timing techniques. In some cases, multiple clocks may be supplied to each module of the module group 236, thereby allowing each module to have isolated timing relative to the other modules in the group. This isolation ensures that any delay in one module does not affect the functionality of other modules. It should be noted that the clocks used may or may not need to be synchronized. In some cases, a common clock may be used to synchronize the modules. In yet another embodiment, the clock signal or signal(s) may be provided by a second device 226.

[0337] In alternative embodiments, other synchronization techniques, such as phase comparison of clock signals or synchronization methods of a phase-locked loop (PLL), may be used. Another embodiment for synchronizing modules in an IC may use synchronization of a delay-locked loop (DLL). In this method, a delay element is added to the clock signal path, and its output is compared with the input clock signal. A feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.

[0338] In another embodiment, the integrated circuit 212 may achieve synchronization between modules using a combination of different synchronization techniques. For example, some modules may use PLL synchronization, while others may use clock delay line or DLL synchronization depending on their specific requirements. Furthermore, the integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in case one method fails. For example, the integrated circuit 212 may use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the others can still maintain synchronization.

[0339] Figure 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0340] The write address space 316 consists of various units in which data, such as weights and / or instructions, can be stored. These units are referred to as memory addresses. The module group 302 includes several memory modules 304, 306, and 308. The write address space 316 can be distributed among the memory modules 304, 306, and 308 such that the write address space 316 extends from 0 to N*M-1. As shown in Figure 3, the module group 302 has N memory modules 304, 306, and 308, where N is a positive integer and each module has a memory size of M. The total number of unique write memory addresses in the write address space is N*M, which can be referred to by integers from 0 to N*M-1.

[0341] Starting at 0, the memory addresses in the write address space 316 are arranged sequentially up to N*M-1. In other words, the first address is 0, the last address is N*M-1, and there are a total of N*M addresses. This ordering can be linear (each address increasing by 1) or some other incidental designation pattern.

[0342] Write memory addressing can be implemented in various ways depending on the system architecture. One method used in a particular embodiment is to use a base register and a limit register. The base register holds the smallest valid physical write memory address, and the limit register specifies the size of the range. Thus, the base is added to the relative address to generate a logical address. In other embodiments, a memory addressing scheme may be used, where the base used is set to 0. Further write addressing techniques will be understood by those skilled in the art.

[0343] For any device writing to module group 302, each memory module may have a unique set of write memory addresses, and as a result, all memory addresses within module group 302 are unique with respect to data writing, for example, starting with 0 for the first module and ending with N*M-1 for the last module. In some embodiments, this allocation may depend on the memory management system of the devices writing data to modules 304, 306, and 308, which can range from a simple fixed partitioning scheme to a more complex dynamic partitioning model.

[0344] For example, in a simple linear model where each module (304, 306, or 308) has an address of the same size M, the first module 304 has write addresses 0 to M-1, the second module has write addresses M to 2M-1, the third module has write addresses 2M to 3*M-1, and so on. Therefore, the Nth module 308 has write addresses (N-1)*M to N*M-1.

[0345] Those skilled in the art may use other implementations of write memory addresses from 0 to N*M-1, which depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of programs executed in the system.

[0346] The module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 may have overlapping address spaces, contiguous address spaces, or address spaces with the same extent. The read address spaces 310, 312, and 314 may be independent of each other. The system includes three independent read address spaces labeled as read address spaces 310, 312, and 314. Each of these read address spaces is separate from the others, meaning that reads can be performed in each space without affecting the others.

[0347] The read address spaces 310, 312, and 314 may be defined as contiguous blocks of memory addresses, each having its own start and end addresses. In the module group 302, each read address space 310, 312, and 314 may have addresses in the range of 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0348] In one embodiment, a single processing unit may be allowed to interface with each of the read address spaces 310, 312, and 314, and simultaneous reads may be implemented as described herein. The independence of the read address spaces 310, 312, and 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.

[0349] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to embodiments of the present disclosure. The signals used in Figure 4 may be used in any embodiment described herein. However, those skilled in the art will understand that different signaling schemes may be used.

[0350] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus containing the address of the data to be written, a write data bus containing the data, and a write clock that causes the write (e.g., on the leading or trailing edge of a clock signal). The write occurs only if the write enable signal indicates that the write should occur. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In some embodiments, the write peripheral 411 may be on a chiplet 230, and in other embodiments, the write peripheral 411 is on a second device 226.

[0351] Module group 402 has modules 404, 406, and 408, each having its own read peripherals 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for transmitting a read address, a read data bus for receiving data, a read clock which is a clock used to control the timing of the output of digital data, and an output enable which is a prerequisite for the output of data. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In further embodiments, multibit or analog data storage may be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the chiplet 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the second device 226.

[0352] Figure 5 shows a diagram of an integrated circuit 500, which may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure. The integrated circuit 500 may be arranged in a semiconductor device such as a chiplet, having a silicon substrate 506 and a second layer 508. Within the integrated circuit 500, there may be array sections forming a module 502, where the memory bit cells 522 of a three-dimensional column array have components necessary for memory storage in a non-volatile memory, semi-volatile memory, or memory format as described herein.

[0353] Even if only a single module 502 is shown, the integrated circuit 500 may include a group of modules having multiple modules, such as a first module and a second module. The memory bit cell 522 is written to by shared write ports 512, 516, which include both a write address bus line 512 and a write data bus 516. These buses extend through a second layer 508 and may be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement the electrical contacts on the surface 518, enabling the second device to be electrically connected to the write address and data buses. The memory bit cell 522 can be read out by read ports 524, 526, which include a read address bus line 524 and a read data bus 526. Both of these buses may also extend through the second layer 508 to a second semiconductor device connected to the surface 518, which also has complementary electrical contacts that enable the second semiconductor device to be electrically connected to the read address and data buses.

[0354] Various types of memory technologies, such as a vertically connected fabric structure formed from non-volatile memory unit cells arranged in a three-dimensional column array 522, may be used for the memory bit cell 522. The memory bit cell 522 may utilize one or more of the following: crosspoint, 3D-NAND, 3D-NOR, 3D AND, and / or stacked planar layers.

[0355] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device (not shown in Figure 5) comprising another integrated circuit, which may be a system-on-chip or a field-programmable gate array. In some embodiments, the memory bit cell 522 may be formed from various non-volatile memory types such as FeFET, FeRAM, ReRAM, SOT, or STT. Furthermore, alternatively or optionally, the memory bit cell may be formed from a non-volatile memory unit cell having a two-terminal, three-terminal, or four-terminal device.

[0356] For example, the memory unit bit cell 522 may be formed from a ferroelectric material such as a ferroelectric tunnel junction, diode, capacitor, single-gate transistor, or dual-gate transistor. Alternatively, the memory unit bit cell 522 may be formed from a memristor material, such as at least one ReRAM, or a magnetic material, such as at least one spin-orbit torque device or at least one spin-transition torque device. Furthermore, the non-volatile memory unit cell 522 may also be formed from a phase-change material or an antiferroelectric material.

[0357] In some alternative embodiments, the non-volatile memory unit cell 522 may be formed from other types of materials, such as phase-change materials, antiferroelectric materials, or multi-bit PCM materials. The non-volatile unit cell may be formed using different structures, such as resistive random-access memory (RRAM) technology, magnetic random-access memory (MRAM) technology, or ferroelectric random-access memory (FRAM®) technology.

[0358] Furthermore, in some implementations, 3D NAND technology may be used to form the memory unit bit cell 522. For example, the memory unit bit cell 522 may be formed from stacked memory layers, where each layer contains multiple memory cells that can be accessed using a shared bit line. In such a case, read ports 524, 526 may be connected to bit lines, and write ports 512, 516 may be connected to word lines that control access to each layer.

[0359] In another embodiment, the 3D connected fabric structure may be constructed of stacked layers of NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates may be combined to optimize the functionality of the structure. In addition, the 3D connected fabric structure may be formed using through-silicon (TSV) technology, which enables vertical interconnection of different layers of the structure.

[0360] Furthermore, the non-volatile memory unit cell may include a two-terminal device, such as a capacitive or memristor device with or without an additional selector device such as a series diode; a three-terminal device, such as a floating-gate transistor or a transistor with an access gate; or a four-terminal device, such as a transistor with two access gates. The type and configuration of the non-volatile memory unit cell 522 may depend on the requirements of a particular application, including circuit speed, power consumption, and reliability. The memory unit cell may include, or may consist of, a single ferroelectric transistor or a 6T SRAM cell. The memory unit cell may also be a combination of many different devices, including, but not limited to, one or more of the transistors, memristors, capacitors, etc.

[0361] In some embodiments, ferroelectric materials may be used to form non-volatile memory unit cells 522. Ferroelectric materials may be implemented as thin-film devices, including, but not limited to, ferroelectric tunnel junctions, capacitors, single-gate transistors, or dual-gate transistors, or any other type of device.

[0362] In another embodiment, the non-volatile memory unit cell 522 may be formed from a memristor material, such as a metal oxide memristor (MOM), a conductive bridge RAM (CBRAM), or a valence-change memory (VCM), each offering different advantages in terms of power consumption, speed, durability, and so on.

[0363] Furthermore, in some embodiments, the non-volatile memory unit cell 522 may be formed from a magnetic material, such as a spin-orbit torque (SOT) device, a spin-transition torque (STT) device, or a perpendicular magnetic tunnel junction (p-MTJ).

[0364] In one embodiment, the module group may include a number of modules, each of which can be accessed through dedicated read ports 524, 526 having dedicated read peripherals 520, while sharing the same write ports 512, 516 and a shared write peripheral 510. The shared write ports 512, 516 may be configured to selectively write to one or more of the modules in the module group, including memory bit cells 522. Each module may have the same or different sizes, and different module sizes may be configured to optimize the use of the memory array in different operating scenarios, etc.

[0365] Furthermore, the integrated circuit 500 may be formed using different manufacturing processes and technologies, including but not limited to CMOS or bipolar CMOS-DMOS (BCD) processes, silicon on insulator (SOI) processes, FinFET processes, silicon germanium (SiGe) processes, and gallium arsenide (GaAs) processes.

[0366] In some embodiments, the memory bit cells 522 of the three-dimensional column array are configured as microvolts. Furthermore, or alternatively, each microvolt has a dedicated read peripheral 520 and a dedicated write peripheral 510, and the write peripheral 510 is a dedicated write peripheral rather than a shared write peripheral. That is, in some embodiments, each microvolt includes a dedicated write connection and a dedicated read connection, and a predetermined number (e.g., two or four) of microvolts may have dedicated write connections and dedicated read connections, each having its own dedicated peripheral, and so on.

[0367] Figure 6 shows a perspective view of assembly 600 having the integrated circuit of Figure 1 mounted on a semiconductor device such as a chiplet 230, which is electrically connected to a system-on-a-chip ("SOC") 610, according to an embodiment of the present disclosure. In this embodiment, the semiconductor device is a chiplet 230 that is electrically connected to a system-on-a-chip ("SOC") 610.

[0368] Referring to Figure 6, the SOC610 includes a silicon substrate 602 on which multiple processing elements are formed, including a processing element 606. The processing elements can communicate with each other through a network-on-chip ("NOC") 604, which is a communication fabric that directs data transfer between processing elements. The communication fabric can take various forms, including buses, switches, NOCs, etc. In the SOC610, the NOC 604 directs data traffic between various nodes (e.g., processing elements 606) and links that provide communication paths between nodes.

[0369] The processing elements, including processing element 606, may be any suitable type of processor capable of executing instructions, including a microprocessor, graphics processing unit (GPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC).

[0370] Furthermore, the SOC610 may comprise various modules, such as module 232, which are grouped together to provide memory functionality to assembly 600 as described herein. Modules in module group 236 may be connected to their respective processing elements to provide readable memory to each processing element. In some embodiments, the connection between modules (e.g., module 232) and processing elements (e.g., 606) may be achieved through interconnects in the silicon substrate 602.

[0371] After the circuit is formed on the silicon substrate 602, a second layer 608 may be placed on the substrate. The second layer 608 may be any suitable material, such as an insulating material, a metal, a dielectric, or an interconnect layer, and the second layer 608 may be bonded to the chiplet 230. Bonding may be performed using any suitable technique, including but not limited to adhesives, soldering, or welding.

[0372] In general, assembly 600 provides a means for integrating a chiplet 230, which may include the integrated circuit shown in Figure 1, into the SOC 610. The integration of the chiplet 230 offers various advantages, such as improved functionality, higher performance, and lower power consumption. Furthermore, the integration of the chiplet 230 into the SOC 610 can be achieved in various ways depending on the specific application and design objectives of the system.

[0373] Assembly 600 can incorporate various modifications and alterations to meet the specific requirements of the system. For example, the processing elements formed on the silicon substrate 602 can vary in number, type, and arrangement. Similarly, the modules in the module group 236 can vary in number, type, and function.

[0374] Furthermore, the second layer 608 may be modified to include additional functions. For example, the second layer 608 may include passive components such as resistors, capacitors, and inductors, or active components such as transistors or diodes. By incorporating these components into the second layer 608, the functionality and performance of the system can be further improved.

[0375] In another variation, assembly 600 may incorporate a heterogeneous integration technique, where the chiplet 230 is manufactured using a different technique than that used in SOC610. This technique allows for the optimal use of different manufacturing techniques for different parts of the system, resulting in improved performance and reduced power consumption.

[0376] Figure 7 shows a perspective view of an assembly 700 having a semiconductor device 707 having an array of processing elements 706 (in a grid of processing elements 706a,a~706n,n where the first subscript is the column and the second subscript is the row), and a second semiconductor device 709 having an array of microvolts 708. The array of microvolts 708 is in a grid of microvolts 708a,a~708n,n, where the first subscript is the column and the second subscript is the row. These subscripts may be arranged such that each subscript of the processing element 706 corresponds to each subscript of the microvolt 708. The microvolts 708 are modules of the type described herein, where the microvolts 708 are positioned, for example, vertically on each processing element 706. The semiconductor device 707 may be a chiplet. The semiconductor device 709 may also be a chiplet. Chiplets 707 and 709 may be joined together. Different layers 710 (for example, 710a to 710d may correspond) may be assigned to separate AI models (for example, parameters in a neural network such as a CNN or transformer model).

[0377] Assembly 700 is a comprehensive structure that houses the various components shown in Figure 7. Assembly 700 provides mechanical support and integration to the other elements, enabling them to function as an integrated system.

[0378] Assembly 700 includes two semiconductor devices, namely semiconductor device 707 and semiconductor device 709. Semiconductor device 707 includes an array of processing elements labeled 706a, a to 706n, n. Similarly, semiconductor device 709 includes an array of microvolts labeled 708a, a to 708n, n.

[0379] The subscripts a, a~n, n indicate that the processing elements 706 and microvolts 708 are arranged in a grid pattern, with the first subscript pointing to a column and the second subscript pointing to a row. This grid arrangement allows each processing element 706 to have a corresponding microvolt 708 positioned vertically above it. For example, processing element 706a,a has microvolts 708a,a above it, processing element 706b,b has microvolts 708b,b above it, and so on. The grid alignment allows for a dense clustering of processing components and storage components.

[0380] In some embodiments, semiconductor devices 707 and 709 are separate chiplets, which may be integrated into an integrated assembly 700 using packaging technology. The chiplet form factor allows for greater flexibility and customization during system assembly. This arrangement allows each processing element 706 to access its respective microvolt 708 located on top of each processing element 706 to retrieve relevant data, such as weights for a neural network or AI model. This may provide high-bandwidth and low-latency access to the data required for efficient processing.

[0381] Input data enters the system via the input DRAM memory 702. This data flows into the processing element 706, where it is locally manipulated using weights or parameters from vertically integrated microvolts 708. The processing results are output via the output DRAM memory 704. The input DRAM memory 702 consists of several individual DRAM modules labeled 702a, 702b, and 702c. The DRAM memory 702 can be any type of dynamic random access memory, including but not limited to DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM. The DRAM memory provides high-bandwidth data input capability to supply data, such as inference input or training data, to the processing pipeline.

[0382] In some embodiments, each individual DRAM module 702a, 702b, and 702c has a dedicated interface and data path to each processing element 706. For example, DRAM module 702a may supply data only to processing elements 706a,a, while DRAM module 702b may supply data only to processing elements 706b,b. This provides modular expandability, as additional DRAM modules can be added to supply more processing elements.

[0383] The number of input DRAM memory 702 and individual modules 702a to 702c may vary depending on the application requirements. For example, there may be 4, 8, 16, or more input DRAM modules. The capacity of each module may range from gigabytes to terabytes, depending on factors such as access speed, power, and cost budget.

[0384] High-speed interfaces such as DDR5, GDDR6, or HBM3 may be used to maximize data transfer bandwidth between the input DRAM memory 702 and the processing element 706 across the semiconductor device 707. A shared data bus, crossbar switch, or on-chip network may interconnect the group of DRAM modules 702 and the processing element 706.

[0385] In some implementations, the input DRAM modules 702 may be stacked or arranged in a multidimensional configuration to increase overall memory capacity and bandwidth while reducing latency and power consumption. A dedicated memory controller and scheduler may manage parallel data access across multiple input DRAM modules 702.

[0386] The input DRAM memory 702 meets the high-bandwidth data demands of the parallel processing elements 706, enabling fast and efficient data-intensive computations such as neural network inference. Each processing element 706 can directly access the necessary input data from its own dedicated DRAM module 702 without competing with other processors for data access.

[0387] In alternative embodiments, instead of, or in addition to, DRAM memories 702, 706, adjacent accelerator chiplets may communicate with semiconductor devices 707. That is, there may be a grid arrangement of assemblies 700 that communicate with each other to perform AI inference and / or AI training (e.g., transformer inference, CNN interference, ANN interference, etc.). In some embodiments, there may be clusters of semiconductor devices 707 that share banks or parts of DRAM memories 702 and / or 706. In some embodiments, input DRAM memory 702 and output DRAM memory 704 may be combined into the same DRAM memory.

[0388] Assembly 700 includes a semiconductor device 707 comprising an array of processing elements labeled 706a,a to 706n,n. Each processing element in the array may be configured to perform dedicated computation and data processing operations. For example, in some embodiments, processing elements may be optimized for artificial intelligence workloads such as neural network inference. In other cases, processing elements may be more focused on general-purpose capabilities. Ultimately, the capabilities of each processing element depend on the specific microarchitecture of that processing element, which can be tuned for specific applications as needed.

[0389] The processing element 706 may access nearby memory storage to obtain data to supply to the calculations of the processing element 706. This memory may be physically separate from the processing element array 706, as in the case of the microvolt 708 shown in Figure 7. The processing elements 706 and microvolts 708 are aligned such that each microvolt is positioned in a vertical configuration directly above its corresponding processing element. This close connectivity provides high data transfer rates between each volt-element pair.

[0390] From the perspective of physical implementation, the array of processing elements 706 resides within a semiconductor device 707. The semiconductor device 707 may, in some cases, be manufactured as a standalone chiplet using advanced packaging techniques. This modular chiplet can then be integrated with other components, such as a microvolt chiplet 709, through high-density interconnects. Some options include bumpless hybrid bonding, interposers, or even monolithic 3D integration. Ultimately, the combination of chiplets enables the creation of a robust heterogeneous system with an optimized die.

[0391] The specific number, design, and interconnect scheme of the processing elements 706 may vary between implementations of the assembly 700. For example, a simpler system might require only a 2x2 grid of elements, while a more advanced AI accelerator might feature a 32x32 array. Furthermore, the processing elements 706 themselves may have different memory access routes across the assembly. Point-to-point links, crossbar switches, or shared buses are possible connection structures. Such architectural decisions depend on the performance and area constraints to be met.

[0392] The second semiconductor device 709 is a separate device from the first semiconductor device 707. Like the first semiconductor device 707, the second semiconductor device 709 may also be implemented as a chiplet. The second semiconductor device 709 includes an array of microvolts 708 arranged in a grid from microvolts 708a,a to 708n,n.

[0393] As mentioned, the microvolts 708 in the second semiconductor device 709 are positioned vertically above the processing elements 706 in the first semiconductor device 707. Each microvolt 708 is aligned with respect to the processing element 706 below it, based on an index that identifies the position of each microvolt 708 in the grid, and corresponds to that processing element 706. For example, microvolts 708a,a are aligned vertically with respect to processing elements 706a,a, and correspond to processing elements 706a,a. This allows each processing element 706 to access the microvolts 708 above it.

[0394] Microvolt 708 functions as a memory structure to store things like the weights of an AI model that can be accessed by the underlying processing element 706 during operations such as neural network inference. Microvolt 708 may be optimized for very fast read times, with the exception of slower write times. This allows the processing element 706 to quickly access the weights and data required for its computations, while less frequently updated data can still be written at a slower pace.

[0395] In some embodiments, a second semiconductor device 709 containing an array of microvolts 708 is directly bonded to a first semiconductor device 707 having processing elements 706. This bonding aligns each microvolt 708 such that the corresponding processing element 706 for each microvolt 708 is located beneath it. An electroconductive interconnect between the devices allows each processing element 706 to communicate directly and upward with the respective microvolts 708 of each processing element 706 that overlaps it. This provides a compact, modular, and efficient system architecture.

[0396] The microvolt 708 may include multiple memory layers labeled 710a to 710b, each storing weights or data related to a different AI model. For example, layer 710a may contain weights related to model A, layer 710b may contain weights related to model B, and so on. The vertical stacking of these layers contributes to the high density and fast access time of the microvolt design.

[0397] Microvolt 708 can be implemented using a variety of memory technologies, including but not limited to SRAM, FeFET, ReRAM, SOT, and STT, which are optimized for fast read times to supply data to the processing element 706 with minimal latency. Certain embodiments may configure Microvolt 708 to have a read speed much faster than its write speed. Microvolt 708 may be implemented using any FeFET or memory structure described herein.

[0398] In some embodiments, each microvolt 708 may have a capacity of 4 to 128 kilobytes to store parameters or other data related to a machine learning model. The bit density per layer may exceed 0.4 gigabits per square millimeter. The compact size of the microvolt 708, which is less than 100 micrometers per side in one embodiment, or 12 micrometers x 12 micrometers in another embodiment, enables high-density integration of memory modules.

[0399] The array-based arrangement of the microvolts 708 can support high-throughput data processing by the assembly 700 by enabling simultaneous parallel data access by the processing elements 706. Furthermore, the one-to-one alignment of the microvolts 708 and processing elements 706 ensures that each processing element 706 has dedicated access to the data it needs without contention.

[0400] The microvolt 708 shares a semiconductor device interface provided by the second semiconductor device 709, which facilitates writing data from the input DRAM memory 702 to the microvolt 708. Reading data from the microvolt 708 to the processing element 706 and the output DRAM memory 704 is handled through dedicated paths between each vertically aligned pair of microvolts 708 and processing elements.

[0401] The microvolt memory layer 710 refers to multiple layers of microvolt memory stacked vertically within the second semiconductor device 709. As shown in Figure 7, there are four separate microvolt memory layers labeled 710a, 710b, 710c, and 710d. Each layer contains an array of microvolts, such as the array of microvolts 708 shown in the figure.

[0402] In one embodiment, the microvolt 708 may utilize a stacked 3D NAND architecture constructed from multiple layers of NAND memory arrays using charge-trap flash technology. Each microvolt 708 may include a dedicated set of word line drivers in the bottom layer to facilitate access to the above 3D NAND cell array, which is separated by alternating dielectric layers. The 3D NAND packaging configuration may be used to maximize density and throughput by leveraging vertical scaling.

[0403] In an alternative embodiment, the MicroVolt 708 employs a 3D NOR architecture consisting of multiple layers of NOR flash memory arrays. Each layer features a NOR string with a source-line and bit-line architecture, stacked on top of each other using vias. The 3D NOR arrangement optimizes random read access times for stored data.

[0404] Furthermore, the MicroVault 708 may employ a hybrid configuration with different types of volatile and / or non-volatile memory, such as a combination of FeRAM and ReRAM cells, organized into vertical subarrays. This heterogeneous 3D integration enables optimization of speed, durability, and retention within the same vault structure.

[0405] In certain embodiments, the MicroVolt 708 directly integrates processing logic, such as analog computation, into the memory array stack itself. This in-memory processing approach enables highly parallel and efficient in-situ data processing by placing basic computation operators within memory peripherals or bit cells.

[0406] Some implementations may utilize 2.5D or 3D stacking to integrate the MicroVolt 708 with other components such as logic, CPUs, GPUs, or application-specific accelerators. This dense packaging integration via technologies such as high-bandwidth memory cube architecture reduces data transfer latency and power consumption.

[0407] Furthermore, the microvolt 708 may employ a virtualization architecture that includes an external memory controller that handles the translation between the physical array configuration and dynamically allocated virtual memory domains. These virtual domains, mapped to the physical array, effectively create separate virtual vaults with flexible capacities that can be adjusted to the demands of the application.

[0408] In certain embodiments, the MicroVolt 708 is designed as a compute RAM (CRAM) with integrated processing capabilities within bit-cell peripherals to enable a highly parallel in-memory computing architecture. The gateless transistor structure integrated into the CRAM array facilitates efficient execution of bulk bit-level operations.

[0409] Some implementations place the microvolt 708 in a modular memory processing unit (MPU) structure that includes dedicated processing logic tailored for workloads such as AI inference. The MPU architecture connects the vault array to a vector processor via a high-speed interface such as HBM2, enabling low-latency data transfer.

[0410] Furthermore, the MicroVolt 708 may implement content addressability by integrating the comparison logic into the memory peripheral. This facilitates data retrieval or access based on content rather than explicit addresses, enabling robust pattern matching capabilities.

[0411] In certain embodiments, multiple microvolt dies may be stacked on top of a base logic die featuring something like a GPU or AI accelerator. This creates a dense, high-bandwidth heterogeneous system optimized for data-centric workloads while minimizing data movement.

[0412] The microvolt memory layer 710 may be manufactured using a three-dimensional integrated circuit manufacturing process to stack multiple dies or wafers containing arrays of microvolts 708 onto each other. Through-silicon vias (TSVs) or other vertical interconnect technologies may be employed to enable inter-layer communication.

[0413] In some embodiments, each microvolt memory layer 710 corresponds to a different artificial intelligence (AI) model or application. For example, layer 710a may store weights and parameters for AI model A, layer 710b may store weights and parameters for AI model B, and so on. This makes it possible to efficiently store multiple AI models within the same microvolt memory structure 708.

[0414] In some embodiments, the microvolt 708 may have a capacity ranging from 4 kilobytes to 128 kilobytes. In other embodiments, the capacity may be between 4 kilobytes and 16 kilobytes. Each microvolt may have lateral dimensions of less than 100 micrometers × 100 micrometers, while extending vertically to incorporate, in some implementations, more than 200 memory cell layers.

[0415] In some embodiments, the bit density per square millimeter per layer within the microvolt memory layer 710 may facilitate high-capacity storage with a small footprint. The layers may utilize non-volatile memory technologies such as FeFET, STT-MRAM, or ReRAM to retain data when power is lost.

[0416] During operation, the processing element 706 may access weights or parameters from the microvolt memory layer 710 to perform neural network inference or other machine learning calculations.

[0417] Various AI inference results may be sent to an output DRAM memory 704 comprising individual DRAM memory modules labeled 704a, 704b, and 704c. The output DRAM memory 704 is located adjacent to the array of microvolts 708 and the second semiconductor device 709. The output DRAM memory 704 may function as temporary data storage that can buffer output data acquired from the microvolts 708 until the output data is transmitted externally.

[0418] Each DRAM memory module 704a, 704b, and 704c may have similar or different storage capacities, depending on the design requirements. For example, in one embodiment, each module contains 16 megabits of storage. The DRAM storage cell utilizes a capacitor to hold data bits in the form of electric charge. Due to charge leakage, the DRAM memory requires periodic refresh cycles to maintain the integrity of the stored data. To enable simultaneous read and write operations across multiple modules, each DRAM module 704a, 704b, and 704c may have its own dedicated internal control circuits and I / O ports.

[0419] The data output from each microvolt 708 may be aggregated and buffered in the output DRAM memory 704 until it is transmitted to an external component via peripheral circuitry. Data buffering allows the transmission rate to be adjusted to meet the requirements of the external interface. Furthermore, buffering allows data processing operations, such as formatting, encoding, or encryption, to be performed by a second semiconductor device 709 before output.

[0420] In some embodiments, output DRAM modules 704a, 704b, and 704c are designed to provide high-density, low-cost transient data storage to support high-bandwidth parallel readouts from the array of microvolts 708. Optimizing these performance parameters enables efficient extraction of data from the microvolts to feed computational workflows hosted on external chips or devices. Specific implementations may utilize various types of DRAM, including asynchronous DRAM, synchronous DRAM, graphics DRM, and low-power DRM, tailored to the application. Overall, the output DRAM memory 704 facilitates seamless data movement from the integrated microvolts to external execution pipelines.

[0421] Figure 8 shows an assembly 800 of semiconductor devices 802, 804, 806, 808, 810, 812, and 814, including several memory types, according to embodiments of the present disclosure. Specifically, Figure 8 shows a preferred assembly 800 of semiconductor devices 802, 804, 806, 808, 810, 812, and 814 configured to provide a hierarchical memory structure. The assembly 800 is modular and expandable, allowing various combinations and numbers of semiconductor devices, which may be implemented as chiplets in certain embodiments, to be stacked to meet specific performance and density requirements.

[0422] Assembly 800 includes an application semiconductor 802 which may be a plurality of processing elements as described herein. A semiconductor device 814 containing an array of microvolts is located on semiconductor device 802. A semiconductor device 812 which may also contain an array of microvolts is located on semiconductor device 814. Semiconductor devices 810 and 808 which may be SRAM vault dies are located on semiconductor device 812. Semiconductor devices 806 and 804 which may be DRAM vault dies are located on semiconductor device 808. These vaults 816 may be arranged in a grid-like manner such that the vaults are subscripted 816a, a to 816n, n. Each of these vaults may contain a microvolt from semiconductor devices 804 and 812, an SRAM vault from semiconductor devices 810 and 808, and a DRAM vault from semiconductor devices 806 and 804.

[0423] A semiconductor device 802, comprising multiple processing elements, forms the base of assembly 800. These processing elements perform computational tasks to facilitate data flow within the system.

[0424] A semiconductor device 814 containing an array of microvolts is located directly above semiconductor device 802. The microvolts utilize field-effect transistors (FeFETs), which are known for their non-volatile properties and suitability for high-density memory applications. FeFET-based microvolts may be designed to support slower write operations with greater latency tolerance, while enabling high-speed read operations essential for rapid data acquisition during processing tasks such as AI inference. Similarly, a semiconductor device 812 containing an array of microvolts is stacked on top of semiconductor device 814. The presence of multiple layers of microvolts in semiconductor devices 814 and 812 exemplifies the scalable nature of the assembly, where additional memory capacity and functionality can be integrated through additional layers.

[0425] Further contributing to the memory hierarchy, semiconductor devices 810 and 808, positioned above semiconductor device 812, are described as an SRAM microvolt die. The SRAM provides high-speed access memory that can function as a cache or buffer for the underlying FeFET microvolt memory layer, which is slower but denser.

[0426] Semiconductor devices 806 and 804, indicated as DRAM vault dies, are located on assembly 800, and therefore on the memory structure. DRAM is typically used in main memory because, compared to SRAM, it is relatively fast and has a lower cost per bit, providing a balance between performance and cost.

[0427] The arrangement of the vaults 816 in a grid-like manner, subscripted as 816a, a to 816n, n, indicates that each processing element at a given location (a,b) in the semiconductor device 802 has dedicated access to the corresponding vertically aligned vaults of the microvolts and memory cells in the layer above. This vertical stacking and alignment ensures that data and control signals can be directly routed between the processing elements and their respective memory stacks, which is facilitated by interconnect technologies such as through-silicon electrodes (TSVs) and microbumps used in the 3D integrated circuit architecture of assembly 800.

[0428] The modular and expandable design of Assembly 800 allows for the integration of various combinations of semiconductor devices or chiplets into larger systems. The flexibility in the number and combination of stacks provides adaptability to tailor the assembly to different application requirements and performance demands. Each vault within Vault 816 in Assembly 800 exhibits a multi-die structure that contributes to the overall capacity and performance of the system.

[0429] Figure 9 shows an assembly of semiconductor devices, according to an embodiment of the present disclosure, which includes a semiconductor device having a system-on-chip 914 and another semiconductor 906 on which a microvolt is mounted. The assembly 900 integrates semiconductor devices 906 and 914, which can be mounted as separate chiplets that are bonded together. Semiconductor device 914 includes various components that facilitate the reading of data from the microvolt in semiconductor device 906, such as a read address register input interconnect 924, a read data register 922, and a read data register output interconnect 950. These components pass a read address to the microvolt in semiconductor device 906 and return the read data to semiconductor device 914.

[0430] Specifically, the read address enters the read address register 926 via the interconnect 924. The output of this register 962 is connected to another read address register 938 in semiconductor device 906 via the interconnect and bumpless junction, and the read address register 938 then addresses the target microvolt 936. Microvolt 936 outputs the read data to the read data register 942 via the interconnect 940, and the read data register 942 passes the data back to the read data register 922 in semiconductor device 914 via bumpless junctions 910, 918. This data can then be accessed externally via the read data register output interconnect 950. Furthermore, semiconductor devices 914 and 906 have interconnected through-silicon electrodes 916 and 944, which optionally enable communication with devices stacked on top of semiconductor device 906.

[0431] The semiconductor device 906 features various memory structures that provide data storage capabilities. This includes a microvolt 936 that provides high-density, low-latency data storage, along with other peripheral memory components such as a read data register 942 and a read address register 938 to facilitate data retrieval. The microvolt 936 resides in the BEOL portion of the chiplet, enabling dense 3D integration of the memory layer. In some implementations, the microvolt utilizes non-volatile memory technologies such as FeFET or STT-MRAM to retain data without power.

[0432] The semiconductor device 914 includes processing elements and data routing circuits for acquiring and manipulating data stored in the semiconductor device 906. Components such as the read address register 926 and the read data register 922 each handle the transmission of read addresses and the reception of data from the microvolt 936. The device 914 also includes interconnects 924, 950 and through-silicon electrodes 916 for communicating with the outside world.

[0433] The two devices 906 and 914 are integrated via fine-pitch interconnects such as bumpless hybrid junctions 908, 910, 918, 920, 930, and 932. This enables a direct data transfer path between the processing components in device 914 and the memory structure in device 906. Alignment during the junction ensures dedicated access; for example, the read data register output interconnect 950 in 914 directly links to the read data register 922 to receive the requested data.

[0434] The path for facilitating data flow during reading can be summarized as follows: The read address enters the read address register 926 in device 914 via interconnect 924. This is then transmitted to the read address register 938 in device 906 via the interconnect and bumpless junction, where the read address register 938 addresses microvolt 936. The request data is passed to the read data register 942 via interconnect 940, and then transferred back to the read data register 922 in 914 via the junction, where the request data becomes available externally via interconnect 950.

[0435] Assembly 900 exemplifies a modular, high-density architecture optimized for data-centric applications such as AI inference. Dense integration of processing and storage dies via advanced packaging techniques enables local data access with minimal latency and power consumption. Scalability is achieved by incorporating multiple chiplets, in this case devices 906 and 914. Assembly 900 presents a conceivable configuration suitable for high-performance computing systems with space constraints.

[0436] The through-silicon electrode (TSV) 916 is an electrical connection that passes vertically through the semiconductor device 914. The purpose of the TSV 916 is to provide a path for signals to travel to processing elements within the semiconductor device 914. This allows the device to be stacked and interconnected with other components in a vertical configuration. The TSV 916, along with other TSVs in the device, facilitates high-density 3D integration and heterogeneous stacking of multiple devices such as chiplets.

[0437] The TSV916 interacts with several other components in the system. Above semiconductor device 914, the TSV916 connects to an interconnect 912 that connects the TSV916 to a bumpless junction 918. This junction interfaces with a complementary bumpless junction 910 on the bottom side of semiconductor device 906 when the two devices are stacked. This allows signals to travel from device 914 through the TSV916 to device 906. The route continues so that signals travel through the interconnect 902 to the TSV944 in device 906. The TSV944 provides a vertical signal path to the top surface of device 906, where additional devices may be stacked. In the reverse direction, signals travel from the TSV944 down through device 906, up through the TSV916 and back down into device 914. Thus, the TSV916 provides bidirectional vertical communication across device boundaries.

[0438] Several possible variations exist for the implementation of the TSV916. Firstly, multiple TSVs arranged in an array can be used instead of a single via to increase throughput and redundancy. Secondly, the dimensions and materials of the TSVs can be optimized; for example, using denser materials such as tungsten, and smaller TSV diameters may be advantageous. Furthermore, interface circuit drive signals to the TSVs, such as interconnects 912 and 902, may employ variable line drivers to support different voltage levels or improved signal integrity. Further embodiments may include integrated monitoring circuits within the TSV916 to track metrics such as temperature and link utilization. In addition to electrical signals, alternative signal transmission schemes may be employed in further cases. For example, integrated silicon photonics that utilize modulated light to transmit data through the TSVs can enable very high bandwidth and low latency connections. Within these complex 3D integrated architectures, several means exist to further develop the capabilities of TSV-based vertical links such as the TSV916.

[0439] Several variations and alternatives exist for the implementation of interconnect 912. For example, different conductive materials, such as copper or aluminum, may be used to fabricate the paths forming the interconnect 912 to optimize conductivity or heat dissipation. Furthermore, interconnect 912 may feature redundant signal paths or self-healing capabilities using spare interconnect wires to improve reliability and resilience. Also, the bumpless joints 918 and 910 connecting devices 906 and 914 can be replaced with hybrid joints or other high-density bonding techniques such as through-silicon electrodes. In addition to simple digital logic, alternative signal transmission schemes, such as analog signal transmission or multi-level digital waveforms, may be employed in interconnect 912 to improve data transmission capability. The routing and dimensions of interconnect 912 may also be configured according to bandwidth requirements or circuit layout considerations. Overall, numerous structural and functional alternatives exist to make interconnect 912 to meet the demands of the application.

[0440] The bumpless joint 918 is an electrical connection located on the semiconductor device 914 between the interconnect 912 and the bumpless joint 910 of the semiconductor device 906. The bumpless joint 918 provides an electrical path for signals to travel between the semiconductor device 914 and any additional semiconductor devices, such as the semiconductor device 906, which are stacked on top of the assembly 900. Signals communicated at the bumpless joint 918 may include data signals, control signals, address signals, or any other signals required to coordinate the operation between multiple semiconductor devices.

[0441] Several possible variations exist for the bumpless joint 918. The number of individual joint locations can range from a few to several hundred, depending on the signal bandwidth requirements. Joining methods can utilize techniques such as direct bonding, plasma-activated bonding, adhesive bonding, or compression bonding. Hybrid bonding methods combining direct wafer joints with intermediate metal joints are also possible. The size and pitch of each joint location can vary, and pitches of less than 10 micrometers may be used to enable high-density connections. Redundant joints may provide backup paths. Shielding structures may surround the joints for noise immunity. Overall, numerous embodiments of the bumpless joint 918 can meet the demands for cost, reliability, and performance.

[0442] The bumpless junction 910 provides an interface for signal communication between semiconductor device 906 and semiconductor device 914. Specifically, the bumpless junction 910 of semiconductor device 906 is electrically connected to a complementary bumpless junction 918 of semiconductor device 914. This allows signals such as read / write data and addresses to be transmitted between the two devices. The bumpless nature of the junction enables low-profile, high-density interconnection.

[0443] The bumpless junction 910 interacts with other components in the system to facilitate data transfer operations. For writing, data enters the semiconductor device 914 via the through-silicon electrode 916, passing through the interconnect 912 and bumpless junction 918 before reaching the bumpless junction 910 of device 906. For reading, the address flows from the read address register 926 of device 914 through the interconnects 928, 930, and bumpless junction 932 to the read address register 938 in device 906. The read data then returns to device 914 through bumpless junctions 908 and 920. Thus, the bumpless junction 910 provides critical data and address routing between devices.

[0444] Possible modifications to the bumpless joint 910 include using different joint densities, materials, or electrical contact configurations to optimize performance. The joint may utilize alloying or doping techniques to improve conductivity. Furthermore, signal routing may be modified, for example, by using separate ports for input and output instead of a shared port. More bumpless joints may be added to increase bandwidth between devices. Shielding may be added around the joint to reduce interference. Overall, numerous modifications to the bumpless joint 910 are possible within the scope of electrically interconnecting multiple devices.

[0445] The through-silicon electrode (TSV) 944 is an electrical connection that passes vertically through the semiconductor device 906 from top to bottom. The purpose of the TSV 944 is to facilitate signal and data communication between the semiconductor device 906 and, optionally, any additional semiconductor devices stacked on top of the semiconductor device 906 in a 3D integrated circuit configuration. The TSV 944 enables high-density interconnection between multiple stacked semiconductor layers, providing an efficient means for data routing and signal transmission.

[0446] The TSV944 interfaces with peripheral circuits within the semiconductor device 906, enabling signals to be transmitted upward or downward depending on the system configuration. At one end, the TSV944 connects to a read data register 942 via an interconnect 946. The read data register 942 can transfer read data from the microvolt 936 to an external semiconductor device using the path of the TSV944. This enables efficient data offloading from on-chip memory. At the other end, the TSV944 continues to the top surface of the semiconductor device 906, where the TSV944 may interface with complementary contacts or interconnects in the junction semiconductor above the TSV944. This facilitates vertical transfer of signals and data along the assembly 900.

[0447] Numerous variations are possible in specific mounting configurations of the TSV944. The dimensions of the TSV944 can range from a few microns to tens of microns to accommodate pitch requirements. The TSV944 may be tapered, linear, or have a non-uniform cross-section. The TSV944 may utilize different conductive materials, including metals such as copper, tungsten, or alloys, as liner and fill. An insulating liner made of a material such as silicon dioxide can separate the conductive fill from the substrate. Furthermore, the contacts and interconnects connecting to the TSV944 can have a variety of layouts. Multiple TSVs may be arranged adjacent to each other in a high-density array configuration if necessary. Overall, numerous architectural optimizations in the design and manufacturing process of the TSV944 are possible within the scope of this disclosure.

[0448] Figure 10 shows a semiconductor assembly 1000 incorporating a daisy-chain configuration of microvolts 1036, 1058 operably connected to a multiplexer 1060 and managed by a counter 1062 for selection and acquisition of coordinated data, according to an embodiment of the present disclosure. The assembly 1000 is optionally designed to perform data processing tasks for applications such as artificial intelligence (AI) and machine learning where high-speed data access and processing are utilized.

[0449] Assembly 1000 comprises two main semiconductor devices, namely semiconductor device 1006 and semiconductor device 1014. Semiconductor device 1014 is described as including several interfaces and registers for data communication, including a read address input interconnect 1024. This interconnect 1024 facilitates the delivery of read addresses to read address register 1026, which temporarily holds the read address for data acquisition operations until the read address is sent to the corresponding microvolts 1036, 1058 in semiconductor device 1006.

[0450] In semiconductor device 1014, interconnect 1028 functions as a path through which read addresses from read address register 1026 are transferred to bumpless junction 1030. Bumpless junctions 1030 and 1032 represent a high-density, low-profile electrical connection between semiconductor device 1014 and semiconductor device 1006, ensuring the transmission of read addresses with minimal signal loss and physical space requirements.

[0451] Through interconnect 1034, the received address reaches read address register 1038 in semiconductor device 1006, which then instructs microvolt 1036 to output the requested read data. Microvolt 1036, memory storage unit, may include various memory technologies, such as FeFET and / or 3D-NAND structures, as described herein, to facilitate the storage and rapid retrieval of data.

[0452] The multiplexer 1060 selects the appropriate data stream from the outputs of multiple microvolts 1036 and 1058. Controlled by a counter 1062, which may operate according to a predetermined sequence or be driven by an external control signal, the multiplexer 1060 arbitrates between the outputs of microvolt 1036 and another microvolt designated as microvolt 1058. Microvolt 1058, like microvolt 1036 in terms of function and possible memory technology, provides an additional data source that the multiplexer 1060 selects.

[0453] When the desired data is selected by the multiplexer 1060, the data is temporarily stored in the read data register 1042, which is located within the semiconductor device 1006. This register 1042 functions as a buffer to hold data for the next processing or transmission. The read data is then routed to the bumpless junction 1008 via the interconnect 1004, thereby facilitating the transfer of data to the semiconductor device 1014.

[0454] The bumpless joints 1010 and 1018 facilitate the continuation of the data path through assembly 1000, ensuring data transfer from semiconductor device 1006 to semiconductor device 1014. When read data reaches semiconductor device 1014, the read data is transported via interconnect 1048 to a read data register, specifically read data register 1022, where the read data can be accessed by an external system such as an application-specific integrated circuit (ASIC) or system-on-a-chip (SoC) via read data register output interconnect 1050.

[0455] Furthermore, assembly 1000 includes through-silicon electrodes (TSVs) 1016 and 1044 that provide vertical electrical connections through semiconductor devices 1014 and 1006, respectively. These TSVs allow for the stacking of additional semiconductor devices or chiplets on top of assembly 1000, thus enabling vertical expansion of the system's capabilities. Interconnects 1012 and 1046 serve as horizontal paths for signals to travel to and from TSVs 1016 and 1044, respectively.

[0456] While the description presents a specific configuration, assembly 1000 may conform to various modifications and alternative embodiments. For example, the number and arrangement of microvolts, the specific type of memory technology employed within the microvolts, and the configuration of interconnect and junction areas may be adjusted to meet the requirements of different applications.

[0457] In some embodiments, semiconductor devices 1006 and 1014 may be designed to incorporate additional features such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or a power management circuit to optimize energy consumption. Thus, the detailed structure of Figure 10 serves as a basis for various advanced semiconductor systems that can be configured, each tailored to the specific needs of the intended application of the semiconductor system.

[0458] In the configuration of assembly 1000 as depicted in Figure 10, the microvolts, exemplified by microvolts 1036 and 1058, exhibit a daisy-chain configuration that enables an expandable and flexible memory architecture within the semiconductor device 1006. This daisy-chain is facilitated through a series of interconnection paths and controlled by the multiplexer 1060 in cooperation with the counter 1062.

[0459] Each microvolt, such as 1036 and 1058, is designed to hold and provide rapid access to data, which may take the form of stored charge, magnetic state, state of ferroelectric material, or other physical embodiments of binary information. The microvolts are interconnected such that the output of one microvolt can be routed to the input of another to create a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 1034 for microvolt 1036 and interconnect 1056 for microvolt 1058, which act as conduits for read data signals emanating from the microvolts.

[0460] The multiplexer 1060 manages the flow of data from this daisy-chain of microvolts. The multiplexer 1060 is designed with multiple inputs, each connected to the output of a microvolt via its respective interconnect. In the provided example, interconnect 1040 carries read data from microvolt 1036, and interconnect 1056 carries read data from microvolt 1058 to the multiplexer 1060. The multiplexer 1060 can select which inputs are connected to its outputs at any given time, and thus control which microvolt data is transferred to the read data register 1042.

[0461] Counter 1062 summarizes the operation of the multiplexer 1060. Counter 1062 may be a binary counter of sequential logic circuitry or any other form that generates a set of output states in response to a clock signal. Counter 1062 advances its state with each tick of a clock that may be provided by an external clock source or generated internally within the semiconductor device 1006. As counter 1062 advances, it outputs a control signal that instructs the multiplexer 1060 on which input to select.

[0462] For example, on the first clock pulse, counter 1062 may instruct multiplexer 1060 to connect the output from microvolt 1036 to the read data register 1042. On the next clock pulse, the counter may cycle through the available microvolts in a predetermined order, switching the connection to the output of microvolt 1058, and so on. The counter's sequence and timing may be configured based on the desired data access pattern and specific requirements regarding the current processing task.

[0463] This clock-driven adjustment enables efficient and organized data acquisition from microvolts of larger arrays in some cases. The adjustment ensures that each microvolt has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable and regular progression of states. This is particularly advantageous in systems where large amounts of data need to be processed in parallel, as the adjustment provides a systematic method for accessing and utilizing stored information.

[0464] Although Figure 10 shows only two microvolts, it should be noted that the daisy-chain mechanism described can be extended to accommodate any arbitrary number of microvolts. Additional microvolts can be added to the chain, each new microvolt connected to the multiplexer via additional input lines. The multiplexer 1060 and counter 1062 are scaled accordingly to manage the increased number of inputs while maintaining the same clock-driven continuous data acquisition process across the extended memory architecture.

[0465] MicroVolt's daisy-chain, along with a multiplexed counter-driven control system, exemplifies a modular and scalable approach to memory design in semiconductor devices. This approach allows for the customization of memory arrays, providing versatile solutions to the latest computing challenges and adapting to the capacity and performance demands of a wide range of applications, from embedded systems to large-scale data centers.

[0466] Figure 11 shows a semiconductor assembly 1100 incorporating a daisy-chain configuration of microvolts in multiple semiconductor devices 1106, 1116 operably connected to a multiplexer and managed by counters for selection and acquisition of coordinated data, according to an embodiment of the present disclosure.

[0467] This detailed description relates to Figure 11 of the accompanying drawings, which shows an embodiment of assembly 1100 as part of an integrated circuit. Assembly 1100 may be considered a hierarchical structure comprising a bottom semiconductor device 1122, an intermediate semiconductor device 1116, and an upper semiconductor device 1106 (each of which may be a chiplet). Each semiconductor device is configured to interface with others through a series of bumpless junctions, such as 1128, 1129, 1158, 1159, 1160, 1161, 1162, and 1163, which facilitate electrical connection without the addition of profiles of conventional bonding methods and thus enable compact and dense stacking of semiconductor layers.

[0468] The bottom semiconductor device 1122 includes a read address register 1126 which can be configured to store and communicate read addresses to microvolts arranged across the assembly 1100. The read address register 1126 communicates via an interconnect 1174 which acts as a conduit for signals directed to a bumpless junction 1128. The junction then engages with a bumpless junction 1129 of the intermediate semiconductor device 1116 and thus transfers the read address to the intermediate semiconductor device. The bottom semiconductor device 1122 also includes a read data register 1124 which can act as a repository for read data to be received. The read data is received via an interconnect 1176 which is connected to a bumpless junction 1158 that communicates with a bumpless junction 1159 of the intermediate semiconductor device 1116.

[0469] The intermediate semiconductor device 1116 functions as an intermediate layer within an assembly 1100 that houses microvolts such as microvolts 1132 and 1118, each of which may be designed to store data and provide rapid access to that data. These microvolts are linked to other components within the device via interconnects such as interconnects 1130 and 1134, which guide the flow of read addresses and read data, respectively. The intermediate semiconductor device 1116 also features a read address register 1146 that receives read addresses from interconnect 1130, and a read data register 1154 that collects read data from TSV 1152.

[0470] A multiplexer 1114 within the intermediate semiconductor device 1116 selects between various data streams. This multiplexer is controlled by a phase counter 1110 that determines the sequence of data selections based on inputs received from the upper semiconductor device 1106 via the TSV 1152. A read data register 1112 serves as a holding area for the selected data stream from the multiplexer 1114.

[0471] The upper semiconductor device 1106 features a phase counter 1102 and a read data register 1104 used to coordinate the data flow within the assembly 1100. The phase counter 1102, together with the multiplexer 1150, commands the output of read data from microvolts 1138 and 1164 based on the selected phase. The read data register 1104 captures the output from the multiplexer 1150, which is then relayed to the bumpless junction 1162 via the interconnect 1108 to facilitate communication with the intermediate semiconductor device 1116.

[0472] Assembly 1100 represents an integration of multiple microvolts across different semiconductor devices. For example, microvolt 1132 in intermediate semiconductor device 1116 may receive a read address from read address register 1146 via interconnect 1134 and path "1". Similarly, microvolt 1118 may receive a read address from the same register via interconnect 1156 and path "2". Microvolts 1138 and 1164 in upper semiconductor device 1106 receive read addresses from read address register 1142 via interconnect 1140 and paths "3" and "4", respectively, and read address register 1142 communicates with intermediate semiconductor device 1116 via TSV 1136 and bumpless junctions 1160 and 1161.

[0473] Each microvolt, such as 1132, 1118, 1138, and 1164, may optionally output read data to a multiplexer 1114 or 1150, where the data is then selected based on the configuration of the respective phase counters 1110 or 1102. The selected data is transmitted down to the assembly 1100 through the respective bumpless junctions and interconnects and is temporarily stored in read data registers 1112 or 1104 until it finally reaches the read data register 1124 of the bottom semiconductor device 1122. This arrangement enables synchronized reading of data from all microvolts, which may be essential in applications requiring parallel processing and high-speed data access.

[0474] TSVs such as 1136 and 1152 provide vertical connectivity across semiconductor devices, enabling the integration of additional layers or functions on top of an existing assembly 1100. These TSVs connect to various interconnects and bumpless joints that establish the necessary paths for signal transmission both within and between semiconductor devices.

[0475] In some embodiments, the microvolts within the assembly 1100 may include various memory technologies, such as 3D-NAND or 3D-NOR structures, and are arranged to facilitate parallel processing and efficient data acquisition. Each microvolt may include additional features to optimize energy consumption, such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or a power management circuit.

[0476] The data path 1 within assembly 1100 is a route through which read addresses and corresponding read data are transmitted across the assembly, specifically illustrating an instruction operation from a read address register 1126 located in the bottom semiconductor device 1122 to a read data register 1124 within the same device.

[0477] The process begins with a read address register 1126 holding a specific read address. This address is transmitted through an interconnect 1174, which acts as a channel for signals. The read address is then transmitted to a bumpless junction 1128, which is carefully designed to create a reliable electrical connection without the physical protrusions associated with conventional junction methods. This junction ensures a low-profile interface that maintains the compactness of the semiconductor stack.

[0478] The signal continues from the bumpless junction 1128, which engages with the bumpless junction 1129 of the intermediate semiconductor device 1116. The read address is carried forward by the interconnect 1130, which delivers the address to the read address register 1146 of the intermediate semiconductor device. The read address register 1146 then transmits the read address through the interconnect 1134, which is designated as path "1" and guides the signal to the microvolt 1132.

[0479] Upon receiving a read address, the microvolt 1132 accesses the requested data. This data is then output through the interconnect 1170 and directed to the multiplexer 1114. In some embodiments, the multiplexer 1114 acts as a selective switch that chooses between data streams based on a configuration determined by the phase counter 1110. This phase counter may be designed to cycle through a sequence that commands the timing and selection of data streams, ensuring that each microvolt is read in a coordinated manner.

[0480] Next, the selected data from the multiplexer 1114 is captured by a read data register 1112 that instantaneously holds the data. Then, the data is transmitted via an interconnect 1120 that carries the signal to a bumpless junction 1159. This junction, along with a bumpless junction 1158 in the bottom semiconductor device 1122, is part of an advanced electrical interconnect system that enables vertical and horizontal integration within the semiconductor stack.

[0481] Here, the signal in the form of read data traverses from bumpless joint 1159 to bumpless joint 1158 and is guided into interconnect 1176. This interconnect completes the connection to read data register 1124, which is configured to receive and hold the read data. Read data register 1124 may be provided to hold data for subsequent processing or external communication.

[0482] The data path 2 within assembly 1100 describes a route specifically designed to send a read address from the read address register 1126 in the bottom semiconductor device 1122 to the microvolt 1118 located in the intermediate semiconductor device 1116, and then transfer the read data back to the read data register 1124 in the bottom device.

[0483] The process begins at the read address register 1126, where the read address is held in preparation for transmission. This register is part of the control mechanism of the semiconductor device that aggregates data acquisition by illuminating a specific address to the memory unit. From the read address register 1126, the read address is transmitted through the interconnect 1174, which provides a secure and reliable path for electrical signals within the integrated circuit.

[0484] The read address continues from interconnect 1174 to bumpless junction 1128, which provides a seamless, low-profile connection to the intermediate semiconductor device 1116 via the corresponding bumpless junction 1129. These junctions are designed to maintain signal integrity during interlayer communication and to adapt to the requirements of modern semiconductor architectures.

[0485] The signal is then carried via interconnect 1130 to read address register 1146 in intermediate semiconductor device 1116. Read address register 1146 functions as a secondary store and hold register, and from read address register 1146, the read address is directed downwards to interconnect 1156 labeled as path "2", which terminates at microvolt 1118.

[0486] Upon receiving a read address, the microvolt 1118 accesses the corresponding data. This data acquisition process is facilitated by the microvolt's internal architecture, which may include an array of memory cells optimized for rapid access and data stability. The read data is output from the microvolt 1118 and proceeds through the interconnect 1172, which leads to the multiplexer 1114.

[0487] The multiplexer 1114 determines which data stream to transfer based on the input from the phase counter 1110. The phase counter 1110 operates in synchronization with the system clock or an external control signal, cycling through various states to control the selection process of the multiplexer 1114 in an accurate and predictable manner.

[0488] Here, the output of the multiplexer 1114, which carries the selected read data, is transmitted to the read data register 1112. This register functions as a buffer to temporarily store the read data. The read data is then transmitted to the bumpless joint 1159 via the interconnect 1120.

[0489] The bumpless joint 1159 forms an interface with the bumpless joint 1158 in the bottom semiconductor device 1122, where signals are transmitted downward through the assembly. The read data then travels across the interconnect 1176 to its final destination, namely the read data register 1124. The read data register 1124 captures the read data and holds it in preparation for further processing or transmission to an external circuit.

[0490] Data path 3 within assembly 1100 is another communication route that represents a data transfer sequence starting from the read address register 1126 in the bottom semiconductor device 1122, through various components, and finally proceeding to the microvolt 1138 in the upper semiconductor device 1106, and then returning to the read data register 1124 in the bottom device.

[0491] The sequence begins with a read address register 1126, which serves as the origin for the read address. Register 1126 securely holds the address until the address is transmitted through the interconnect 1174. The interconnect 1174 acts as a dedicated channel to ensure that the read address is accurately transmitted to the bumpless junction 1128. The bumpless junction 1128 facilitates the streamlined connection of the intermediate semiconductor device 1116 to the bumpless junction 1129, maintaining the integrity and compactness of the signal path.

[0492] Upon reaching the intermediate semiconductor device 1116, the read address is relayed to the read address register 1146 via the interconnect 1130. The read address register 1146 functions as a junction that further transmits the address signal through the through-silicon electrode (TSV) 1136. The TSV 1136 is a vertical interconnect that perforates the semiconductor substrate, providing a direct link from the intermediate semiconductor device 1116 to the upper semiconductor device 1106, and thus exemplifying the 3D integration capability of the semiconductor design.

[0493] The read address ascends from TSV1136 and appears at bumpless junction 1160 in the intermediate semiconductor device 1116. Bumpless junction 1160 is connected to bumpless junction 1161 of the upper semiconductor device 1106. The address signal is transmitted through interconnect 1140 to read address register 1142 in the upper device 1106.

[0494] When the read address register 1142 receives a read address, it directs a signal along the interconnect 1144. This path, labeled "3," leads the address to the microvolt 1138. The microvolt 1138, designed for data storage, retrieves the requested information according to the read address. The read data is output through the interconnect 1166, which supplies the data to the multiplexer 1150.

[0495] The multiplexer 1150 in the upper semiconductor device 1106 is managed by a phase counter 1102 that commands the selection of a data stream to be carried to the read data register 1104. The selected data stream is temporarily stored in the read data register 1104, where it awaits downstream transmission.

[0496] The read data exits the read data register 1104 via the interconnect 1108 connected to the bumpless junction 1162. The junction 1162 engages with the corresponding bumpless junction 1163 in the intermediate semiconductor device 1116 to transfer the read data to the TSV 1152.

[0497] The TSV1152 acts as a vertical conduit, allowing read data to traverse downward toward the intermediate semiconductor device 1116, where it is received by the read data register 1154. The read data register 1154 momentarily holds the read data until it is directed toward the multiplexer 1114 through the interconnect 1156.

[0498] A multiplexer 1114 in the intermediate semiconductor device 1116, adjusted by a phase counter 1110, selects appropriate data for output. The read data is then carried to a read data register 1112 where the read data is temporarily stored. After this, the read data proceeds to the bumpless junction 1159 via the interconnect 1120.

[0499] The bumpless joint 1159 forms an interface with the bumpless joint 1158 in the bottom semiconductor device 1122. The read data signal is then transported through the interconnect 1176 to the read data register 1124 in the bottom device, which is the final step in the read data signal's path.

[0500] The data path 4 within assembly 1100 is a path that facilitates the movement of read data from the read address register 1126 in the bottom semiconductor device 1122 to the microvolt 1164 located in the top semiconductor device 1106, and then back down towards the read data register 1124 in the bottom device.

[0501] This data path begins with a read address register 1126, which is responsible for holding and issuing the read addresses necessary for retrieving data from the microvolt. The read addresses are transmitted from register 1126 through the interconnect 1174, which is a path that maintains signal integrity and facilitates electrical communication.

[0502] From interconnect 1174, the read address is directed to bumpless junction 1128. This junction area creates an interconnect between the bottom semiconductor device 1122 and the intermediate semiconductor device 1116 through bumpless junction 1129. The design of this bumpless junction facilitates data transmission.

[0503] When a read address reaches the intermediate semiconductor device 1116, the read address is forwarded to the read address register 1146 by the interconnect 1130. This register functions as an intermediate, preparing the address for vertical escalation through the device stack. The address is then transmitted via the through-silicon electrode (TSV) 1136, which facilitates vertical integration by providing a direct electrical link through the semiconductor substrate.

[0504] After ascending TSV1136, the read address appears at bumpless junction 1160, which is aligned to connect to bumpless junction 1161 in the upper semiconductor device 1106. The read address then proceeds along interconnect 1140 to read address register 1142 located in the upper device.

[0505] The read address register 1142 functions to forward the read address to its final destination, namely the microvolt 1164, via the interconnect 1148 labeled as route "4". Upon receiving the read address, the microvolt 1164 retrieves the request data, which is then output through the interconnect 1168. This data is directed to the multiplexer 1150, which is under the control of the phase controller 1102.

[0506] The phase counter 1102 determines which data stream is selected by the multiplexer 1150, which then sends the read data to the read data register 1104. The read data register 1104 acts as a temporary repository that holds the data until it can be sent down through the device stack.

[0507] The data leaves the read data register 1104 and proceeds to the bumpless junction 1162 via the interconnect 1108. This junction maintains a connection to the bumpless junction 1163 in the intermediate semiconductor device 1116. The read data is then transferred to the TSV 1152, which carries the data vertically downward towards the read data register 1154 in the intermediate semiconductor device 1116.

[0508] The read data register 1154 temporarily holds the read data until it is supplied to the multiplexer 1114 via the interconnect 1156. The multiplexer 1114, regulated by the phase counter 1110, carries the appropriate data stream to the read data register 1112. This register functions as a staging area for the read data, which is then transmitted to the bumpless joint 1159 via the interconnect 1120.

[0509] The bumpless joint 1159 interfaces with the bumpless joint 1158 on the bottom semiconductor device 1122 to provide downward transmission of read data. The signal is then routed through the interconnect 1176 to the read data register 1124, where the data is made available for further processing or external communication.

[0510] Figure 12 shows a three-dimensional (3D) memory column 1200 configured as a 3D-NOR or 3D-AND structure, featuring a series of ferroelectric field-effect transistors (FeFETs) 1202 having interconnect drain terminals 1204 linked to a common selection line 1212, and individual gate terminals 1206 connected to a common bit line, each connected to a read / write enable line 1214 (e.g., 1214a for FeFET 1202a, all connected to a common bit line).

[0511] Accordingly, Figure 12 depicts a three-dimensional (3D) memory column designated as element 1200, which can be configured as a 3D-NOR or 3D-AND structure in various embodiments, providing flexibility in the application and use of the integrated circuit. This memory column is an assembly of multiple ferroelectric field-effect transistors (FeFETs) collectively referred to as FeFET 1202, where each FeFET is represented by elements such as 1202a, 1202b, 1202c, and 1202d, among others, which may be present in the array.

[0512] Within each FeFET, such as 1202a, there is a drain terminal 1204a. This drain terminal is part of the memory cell's output path and is connected to a common selection line 1212. In some embodiments, the common selection line 1212 functions as a control mechanism that enables the selection of a specific FeFET for data read or write operations.

[0513] For FeFET 1202a, the gate terminal of each FeFET exemplified by 1206a is individually connected to its respective read / write enable line, such as 1214a. This allows control of the FeFET state, enabling it to be either conductive (on) for reading or writing data, or non-conductive (off) for preventing data flow. The presence of individual read / write lines for each FeFET allows for precise control and operation of each memory cell.

[0514] Furthermore, each FeFET, such as 1202a, is provided with a source terminal, such as 1208a, connected to a common bit line 1210. The bit line 1210 provides a conduit through which data is written to or read from the FeFET. In some embodiments, this bit line may be shared across multiple memory columns, which can facilitate parallel processing and increased data throughput.

[0515] In accordance with various embodiments of this disclosure, the 3D memory column 1200 may incorporate additional elements and configurations to improve performance and functionality. For example, the 3D memory column 1200 may include insulating materials, conductive paths, and other structural components not explicitly shown in Figure 12, which are specific to the implementation of the 3D memory structure. Furthermore, the FeFET 1202 may exhibit variations in terms of material composition, structural dimensions, and electrical properties to contribute to a range of performance characteristics suitable for different applications.

[0516] Furthermore, the memory column 1200 may be incorporated into a larger memory array that forms part of a memory module or system. This array may be arranged in various configurations, such as rows and columns, to create a matrix that efficiently addresses the demands of high-density data storage. The memory column 1200 may also interface with other circuit elements and control logic that can manage the operation of the memory array, including data management protocols, error correction algorithms, and power optimization strategies.

[0517] In some embodiments, the memory column 1200 may be manufactured using advanced semiconductor manufacturing techniques such as photolithography, etching, deposition, and planarization processes. The selection of materials for the FeFET, including the ferroelectric material, semiconductor channel, and conductive element, may be based on desired electrical properties such as charge retention, switching speed, and energy efficiency.

[0518] The 3D memory column 1200, as shown in Figure 12, may include FeFETs such as 1202, manufactured from various materials that provide the electrical and physical properties necessary to achieve the desired function. For example, in some embodiments, the channel layer of each FeFET in FeFET 1202 may be composed of a material such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) such as zinc tin oxide or indium tungsten oxide (IWO). These materials are selected based on their electronic properties, such as carrier mobility and stability.

[0519] The ferroelectric material rigidly connected to the channel layer in each FeFET may include hafnium zirconium oxide (HfZrO2) or other transition metal oxides, perovskites, etc. These ferroelectric materials are selected for their ability to maintain a polarized state when an electric field is applied, and this ability is used for the non-volatile memory properties of the FeFET. The thickness, crystal structure, and stoichiometry of the ferroelectric material can be controlled to achieve the desired coercivity voltage, remanent polarization, and other electrical parameters for reliable data storage and retrieval.

[0520] The drain 1204 and source 1208 terminals of FeFET 1202 are connected to a common select line 1212 and a common bit line 1210, respectively. These common lines may be formed from conductive materials such as tungsten, titanium nitride, or other metals, and metal alloys that provide a low-resistance path for electrical signals. The configuration of these terminals and their respective common lines ensures that the FeFET can be effectively accessed and controlled during operation.

[0521] Each gate terminal of FeFET1202a, such as gate 1206, is connected to its respective read / write enable line, such as 1214a. The gate terminals help control the state of the FeFET, and the material chosen for these terminals may include a variety of conductive materials that can provide a reliable electrical interface with ferroelectric materials. The read / write enable line 1214 is designed to deliver a suitable voltage level to gate 1206 of FeFET1202 for switching between states.

[0522] The memory column 1200 as a whole is designed to support a range of operating parameters. In some embodiments, these parameters include, but are not limited to, an off-state current of less than 10^-8 amperes / cubic centimeter, an on-state current greater than 10^-7 amperes / cubic centimeter, and channel mobility maintained despite the presence of the ferroelectric layer. The thickness of the channel layer may be less than 30 nm to ensure high device density while being optimized to provide the memory functions required by the ferroelectric layer's properties, such as coercivity and remanent polarization.

[0523] In some embodiments, the FeFET1202 may include additional materials or dopants to improve the electrical properties of the FeFET1202. For example, dopants such as gallium (Ga), indium (In), or zinc (Zn) may be incorporated into the channel layer to modulate the carrier concentration or adjust the threshold voltage of the FeFET. Similarly, a ferroelectric layer may include dopants such as lanthanum (La) or niobium (Nb) to adjust the ferroelectric properties of the ferroelectric layer.

[0524] In other embodiments, the 3D memory column 1200 may be integrated into additional semiconductor devices and structures to form a complex memory system. This system can provide storage capacity and support various memory architectures.

[0525] Figure 13 depicts a three-dimensional (3D) memory column 1300 configured as a 3D-NAND structure consisting of a vertical stack of ferroelectric field-effect transistors (FeFETs) 1302, each having a source terminal 1304 and a drain terminal 1308. The source 1304 of each FeFET, such as 1304a for FeFET 1302a, is connected to the beginning of the bit line 1310 or to the drain of the preceding FeFET, as exemplified by source 1304b of FeFET 1302b, which is connected to the drain 1308a of FeFET 1302a. Each FeFET includes a gate 1306, such as 1306a for FeFET 1302a, which is connected to the respective read / write enable line, as indicated by 1314a for FeFET 1302a, according to embodiments of the present disclosure.

[0526] The 3D memory column 1300 is composed of a series of vertically stacked field-effect transistors (FeFETs) collectively identified as FeFET 1302. These transistors, including FeFET 1302a, 1302b, 1302c, 1302d, etc., are characterized by incorporating a ferroelectric material within their gate structure. Each FeFET in this series of memory columns contributes to the device's memory storage capacity.

[0527] In the described embodiment, each FeFET, such as FeFET 1302a, includes a source 1304a connected to a source terminal 1304, for example, a bit line 1310. The bit line 1310 acts as a conduit for electrical signals used to read from and write to a memory cell associated with FeFET 1302a. In scenarios where FeFET 1302a is not the bottom transistor in the column, the source 1304b of FeFET 1302a may be connected to the drain 1308a of the preceding FeFET, such as FeFET 1302a, to facilitate the series connection that defines the vertical NAND architecture.

[0528] Each FeFET within FeFET1302 further comprises a gate terminal 1306, exemplified by gate 1306a for FeFET1302a. This gate terminal 1306 is connected to the respective read / write enable line, exemplified by 1314a for FeFET1302a. The read / write enable line 1314a controls the state of the FeFET, either making the FeFET conduct or preventing current flow through the device, thereby enabling data writing or reading.

[0529] Furthermore, each FeFET in FeFET1302 typically includes a drain terminal 1308, such as drain 1308a for FeFET1302a, which is connected to the source of the next FeFET in a vertical stack. This arrangement ensures that the charge stored in the ferroelectric material of the gate can modulate the current flowing from source to drain, enabling data storage and retrieval.

[0530] The memory column 1300 in Figure 13 illustrates a memory architecture that can be used in a variety of applications, from portable electronic devices to enterprise-level data storage systems. In some embodiments, the ferroelectric material used in the FeFET may include various compositions such as hafnium oxide, zirconium oxide, or any combination thereof, which can be doped with elements such as lanthanum or yttrium to adjust the ferroelectric properties as needed.

[0531] In some variations, the 3D memory column 1300 may incorporate additional features that improve performance, reliability, or manufacturability. For example, the FeFET 1302 may include a protective layer to shield the ferroelectric material from environmental or process-induced damage. The column 1300 may also be integrated with other circuit elements such as capacitors or diodes to facilitate operations such as charge pumping or to provide additional functionality within the memory array.

[0532] The 3D memory column 1300 may be manufactured from various materials that provide specific electrical properties to improve device performance. In some embodiments, the channel layer of each FeFET may be formed from a material such as indium gallium zinc oxide (IGZO). Other materials for the channel layer may include amorphous oxide semiconductors (AOS) such as zinc tin oxide or aluminum zinc oxide.

[0533] The ferroelectric layer within the FeFET1302 may contain materials such as hafnium zirconium oxide (HfZrO2). The thickness and material composition of the ferroelectric layer can be controlled through methods such as atomic layer deposition (ALD) to achieve desired coercivity, remanent polarization, and durability characteristics. In some implementations, the coercivity of the ferroelectric layer may be adjusted to be between -3 volts and +3 volts to facilitate low-voltage operation of the memory device.

[0534] The source and drain terminals of the FeFET1302 may be made of a conductive material such as tungsten or titanium nitride. These materials may also be selected to optimize contact resistance with the channel layer, thereby reducing overall power consumption and improving the Ion / Ioff ratio of the device.

[0535] Furthermore, the FeFET1302 may be designed to exhibit specific electrical parameters. For example, the thickness of the channel layer may be less than 30 nm in some embodiments. In some embodiments, the channel layer may exhibit carrier concentrations of 10^17 to 10^20 / cubic centimeter, which can be adjusted through doping with elements such as gallium, indium, or zinc to modulate the electrical properties.

[0536] Furthermore, the memory cells formed by the FeFET 1302 within the 3D memory column 1300 may target operational parameters such as read and write latency, endurance, and energy consumption. For example, read and write operations may be performed with less than 10 picojoules of energy and within a time frame of less than 20 nanoseconds, contributing to the low-power and high-speed attributes of the memory column.

[0537] Furthermore, the 3D-NAND configuration of memory column 1300 may be designed to achieve a high off-state resistance to on-state resistance ratio (Roff / Ron), which is important for distinguishing between different data states and ensuring reliable data retention. This ratio may be approximately 10^3 or greater, which helps maintain a high signal-to-noise ratio during memory operation.

[0538] Furthermore, the FeFET 1302 in the memory column 1300 may be designed to maintain a high level of reliability with an endurance rating of 10^11 cycles or more, which guarantees the lifespan and durability of the memory device. This durability is complemented by the ability of the ferroelectric layer to maintain data retention for at least 1 minute at room temperature of 25°C.

[0539] Figure 14 depicts a three-dimensional (3D) memory column configured as a 3D-NAND with integrated pass gates according to an embodiment of the present disclosure. The figure shows a series of ferroelectric field-effect transistors (FeFETs) 1402, each gate-controlled by its respective gate terminal 1406 and including source 1404 and drain 1408 terminals connected to a read / write enable line 1414. The FeFETs are interconnected to form a vertical memory structure having a pass gate 1418 linked to the pass gate line 1416.

[0540] Therefore, Figure 14 includes a three-dimensional (3D) memory column designated as element 1400, which can be configured as a 3D-NAND structure with integrated path gates. This configuration allows for advanced control over individual memory cells within the 3D structure, potentially improving read / write operations and facilitating efficient memory management.

[0541] In detail, the 3D memory column 1400 comprises multiple ferroelectric field-effect transistors (FeFETs) collectively referred to as FeFET 1402. Each FeFET within the series 1402, such as 1402a, 1402b, 1402c, and 1402d, constitutes a memory cell of the 3D memory column 1400. These FeFETs are utilized for their ability to retain data in a non-volatile manner due to the ferroelectric properties of their gate material, which allows data retention without continuous power supply for a period of time.

[0542] Each FeFET in the series 1402 includes a source exemplified by source 1404a for FeFET 1402a. Source 1404 for each FeFET is connected to a bit line, indicated as bit line 1410 for FeFET 1402a, or to the drain of a preceding FeFET in the series. For example, source 1404b of FeFET 1402b is electrically connected to drain 1408a of FeFET 1402a. This series connection forms the basis of the daisy-chain configuration used in NAND architectures, enabling continuous access to the array of FeFETs.

[0543] Furthermore, each FeFET within FeFET1402 is equipped with a gate terminal, such as gate 1406a for FeFET1402a. The gates of the FeFETs are connected to the respective read / write enable lines of the FeFET, which are depicted as element 1414 in the diagram. For example, gate 1406a of FeFET1402a is affected by read / write enable line 1414a. This enable line controls the application of the appropriate voltage for reading and writing data.

[0544] Furthermore, each FeFET in the series of FeFET1402 includes a drain, such as drain 1408a for FeFET1402a. This drain is connected to the source of the next FeFET in the series, thus establishing the continuity of the column structure of the 3D memory stack.

[0545] In some embodiments, each FeFET in the FeFET 1402 incorporates a pass gate, for example, pass gate 1418a, connected to a pass gate line represented by 1416 in the figure. The pass gate line 1416 is a conductive path that provides an electrical signal to control the pass gate 1418 of the FeFET. Including a pass gate in the FeFET allows for improved isolation between memory cells in operation, thereby reducing interference and potentially improving the reliability of data storage and retrieval.

[0546] Furthermore, the 3D memory column 1400, as depicted in Figure 14, includes a diverse range of materials and parameters that can be used to optimize the performance of the 3D memory column 1400 in various embodiments. Each FeFET 1402 in the column can be manufactured using a variety of semiconductor materials. For example, the channel layer of the FeFET can be formed from a material such as indium gallium zinc oxide (IGZO).

[0547] The ferroelectric layer that defines the characteristics of the FeFET may consist of a material such as hafnium zirconium oxide (HfZrO2) or other perovskite material, the residual polarization of which is known. This property determines the data retention capability of the FeFET. The coercivity voltage of this layer, which affects the energy required to switch the polarization state, is another important parameter that can be adjusted according to the requirements of a particular application, ranging from -3 volts to 3 volts in one embodiment.

[0548] The source and drain terminals of the FeFET, including elements 1404 and 1408 respectively, may be made of a conductive material such as tungsten or titanium nitride. These materials provide a path for the current used for switching. Additionally, the read / write enable line 1414, which controls the gate 1406 of the FeFET, may be manufactured from a similar material to ensure consistent electrical characteristics throughout the device.

[0549] In terms of physical parameters, the thickness of the channel layer may be less than 30 nm. The electron mobility within the channel layer may be maintained at a predetermined level even when the layer thickness is less than 30 nm.

[0550] The pass gate 1418 may be manufactured using a low-resistance material to enable a rapid switchover time, which is advantageous when the memory column is frequently accessed during operation.

[0551] Figure 15 shows a three-dimensional (3D) memory column 1500 that may be configured as a 3D-NOR or 3D-AND structure having independent read / write enable capabilities according to embodiments of the present disclosure. This memory column comprises a series of vertically aligned FeFETs 1502, such as FeFETs 1502a, 1502b, 1502c, 1502d, each integrated with a source 1504 (e.g., source 1504a for FeFET 1502a) linked to its respective read enable line 1520 (e.g., read enable line 1520a for FeFET 1502a) and a gate 1506 (e.g., gate 1506a for FeFET 1502a) connected to a corresponding write enable line 1522 (e.g., write enable line 1522a for FeFET 1502a). All FeFETs in the column share a common bit line 1510 connected to the drain 1508 of the FeFET, enabling the column to perform coordinated memory operation.

[0552] Figure 15 presents a detailed depiction of a three-dimensional (3D) memory column 1500, which may be configured as a 3D-NOR or 3D-AND structure with independent read / write enable functions. This memory column is an assembly of field-effect transistors having a ferroelectric gate layer, typically referred to as FeFET 1502, where the gate layer is individually identified, for example, as 1502a, 1502b, 1502c, 1502d, etc., each representing a memory cell within the column.

[0553] In the illustrated embodiment, each FeFET 1502 includes a source 1504, such as source 1504a, which corresponds to FeFET 1502a. Source 1504 is designed to be electrically connected to a respective read enable line 1520, such as read enable line 1520a, which is dedicated to FeFET 1502a. The read enable lines 1520 function to selectively activate FeFET 1502 for read operations, thereby enabling the reading of stored data from the memory cell.

[0554] Furthermore, each FeFET 1502 includes a gate 1506, exemplified by gate 1506a for FeFET 1502a. Gate 1506 is connected to its respective write enable line 1522, such as the write enable line 1522a which is specific to FeFET 1502a. The write enable line 1522 functions to selectively activate FeFET 1502 for write operations, enabling the storage of data in the memory cell.

[0555] Furthermore, each FeFET 1502 includes a drain 1508, for example, a drain 1508a related to FeFET 1502a. The drain 1508 is connected to a common bit line 1510. The bit line 1510 acts as a conduit for transferring data between memory cells during read and write operations. The commonality of the bit line 1510 across multiple FeFETs 1502 means that data from any working memory cell can be routed through this shared path.

[0556] In some embodiments of the memory cell 1500, the configuration of the FeFET 1502 enables high-density memory cells stacked vertically within a compact footprint.

[0557] The ferroelectric material used in the gate 1506 of FeFET1502 may include various compositions, such as hafnium oxide-based materials that can be deposited using atomic layer deposition techniques. The ferroelectric properties of the material enable data retention, allowing the memory cell to maintain stored information even when power is not supplied.

[0558] The source 1504, gate 1506, and drain 1508 of each FeFET 1502 may be manufactured from a material that provides predetermined electrical performance. These materials may include metals such as tungsten, copper, or titanium nitride.

[0559] In some embodiments, the read enable line 1520 and the write enable line 1522 may be designed to minimize crosstalk and interference between adjacent lines. In some specific embodiments, a shielding layer or insulating material may be included to further isolate the signal paths.

[0560] Furthermore, the memory column 1500 described may be integrated within a larger semiconductor device, such as a processor or storage module. The memory column 1500 may form part of a system-on-a-chip (SoC) or be included in a multi-chip module (MCM), contributing to a data storage and retrieval system.

[0561] The materials constituting the FeFET 1502 within the memory column 1500 are selected to provide specific electrical and physical properties to optimize the performance of the integrated circuit. For example, the channel layer in each FeFET may be formed from advanced semiconductor materials such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) such as zinc tin oxide or cadmium oxide. These materials are selected for their superior electron mobility and stability.

[0562] The ferroelectric layer required for the FeFET1502 may be manufactured from a variety of ferroelectric materials exhibiting suitable polarization properties. Materials such as hafnium zirconium oxide (HfZrO2) or lead zirconate titanate (PZT) may be used. These materials may be doped with elements such as lanthanum, yttrium, or other suitable dopants to modify their ferroelectric properties, including coercivity, remanent polarization, and crystallization temperature. The thickness and material composition of the ferroelectric layer may be adjusted to achieve desired memory characteristics, such as write endurance and retention time, while ensuring the layer remains compatible with the overall semiconductor manufacturing process or other considerations.

[0563] The source 1504, gate 1506, and drain 1508 terminals of FeFET 1502 may be made of a conductive material such as tungsten, titanium nitride, nickel, or molybdenum. Connections to the read enable line 1520 and write enable line 1522 can be facilitated through conductive vias or contacts.

[0564] The read enable line 1520 and the write enable line 1522, together with the common bit line 1510, may be patterned using lithography techniques to achieve predetermined precision and alignment for proper function. These lines may be insulated from each other using dielectric materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), or low-k dielectrics to reduce parasitic capacitance and crosstalk.

[0565] Each element within the memory column 1500 may take into account factors such as line width, spacing, and aspect ratio to ensure manufacturability, functionality, and / or other objectives or characteristics. The materials and processes used in the configuration of the memory column 1500 are selected to ensure compatibility with standard semiconductor manufacturing techniques such as photolithography, etching, deposition, and annealing, while also enabling the integration of materials and structures.

[0566] The fabrication of the FeFET 1502 within the memory column 1500 may include deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) to create uniform and / or non-uniform layers.

[0567] Figure 16 shows a cross-sectional view of a 3D memory structure designated 1600 configured as a single-port 3D-NAND according to an embodiment of the present disclosure. The structure includes a first vertical structure 1608a and a second identical vertical structure 1608b, each comprising dielectric columns 1610a, 1610b, channel columns 1612a, 1612b arranged around the dielectric columns, and ferroelectric columns 1614a, 1614b arranged around the channel columns. A series of horizontal gate electrode layers 1606a-c are arranged adjacent to the ferroelectric columns along the length of the vertical structure, spaced apart from one another. The assembly further includes drain-selection layers 1602 and source-selection layers 1604, each having dielectric columns 1618a, 1618b and 1616a, 1616b at their respective ends, positioned at the interface with the vertical structure, illustrating a detailed complex design for high-density data storage.

[0568] Accordingly, Figure 16 provides a cross-sectional view of a three-dimensional (3D) memory structure designated 1600, configured as a single-port 3D-NAND architecture. This structure incorporates a pair of vertical structures 1608a and 1608b, which can be manufactured to be substantially identical, as indicated by the subscripts a and b of vertical structures 1608a and 1608b, respectively, demonstrating the potential for a modular and expandable memory array design.

[0569] Each vertical structure exemplified by the first vertical structure 1608a includes a dielectric column 1610a. The dielectric column may employ a variety of geometric forms, and the dielectric column may be cylindrical, substantially cylindrical, or feature curved. Furthermore, the dielectric column may exhibit a tapered form having different diameters at each end, exhibiting a design that narrows towards the top. Both solid and hollow configurations of the dielectric column are envisioned within the scope of this disclosure to provide design flexibility for different electrical and structural requirements.

[0570] The channel column 1612a, which is the location for charge carriers during device operation, surrounds the dielectric column 1610a. The channel column may also be described as cylindrical, substantially cylindrical, or feature curve, and / or, like the dielectric column, may exhibit a deformation in its diameter along its length.

[0571] The ferroelectric column 1614a, which extends along the length of the channel column, surrounds the channel column 1612a, but recedes at its ends, which may mean that the ferroelectric column 1614 does not extend to the full length of the channel column 1612a.

[0572] A series of horizontal gate electrode layers 1606a-c, positioned at predetermined distances from each other, intersect with the vertical structure. These layers play a role in controlling the operating state of the device by influencing the electric field within the ferroelectric column.

[0573] The drain selection layer 1602 is located on top of the 3D memory structure 1600, parallel to the horizontal gate electrode layer 1606. Where the drain selection layer 1602 contacts the vertical structures 1608a and 1608b, the end dielectric columns 1618a and 1618b are identifiable. These end dielectric columns 1618 interface with the channel column 1612 and the drain selection layer 1602, contributing to the isolation and control of charge carriers within the channel column. Because the end dielectric columns 1618 surround the channel column 1612 at different positions along its length, the end dielectric columns 1618 may contact the ferroelectric layer 1614.

[0574] Similarly, the source selection layer 1604 is located at the bottom of the structure 1600, again parallel to the horizontal gate electrode layer 1606. The corresponding end dielectric columns 1616a and 1616b are present where the source selection layer 1604 interfaces with the vertical structure and provide a similar function to the end dielectric column 1618 located near the drain selection layer 1602.

[0575] The layers of the horizontal gate electrode 1606 may be composed of conductive materials ranging from metals to metallic compounds, which can provide different work functions, conductivity, and compatibility with other materials in their structure. Similarly, the ferroelectric column 1614 may incorporate various ferroelectric materials, each having its own inherent polarization properties, coercivity, and dielectric constant, which may affect the memory retention and switching behavior of the device.

[0576] The material of the channel column 1612 may be selected based on the electronic properties of the material, such as carrier mobility and band gap, in order to achieve the desired levels of on-state and off-state current. The dielectric column 1610 provides the electrical insulation necessary to prevent leakage current and ensure proper functioning of the device.

[0577] The dielectric column for the first vertical structure, such as 1610a, may be composed of a material that provides insulating properties to mitigate any possible leakage current. The choice of dielectric material may be hafnium oxide (HfO2) or silicon dioxide (SiO2).

[0578] Surrounding the dielectric column, the channel column (1612a) has a channel material which can be selected from a wide range of semiconductor materials that provide a predetermined carrier mobility. For example, indium gallium zinc oxide (IGZO) may be used due to its IGZO electrical properties. The thickness of the channel layer may vary, and in some embodiments, thicknesses of less than 30 nm are considered. This thickness is selected to achieve a predetermined electrical performance. Ferroelectric columns such as 1614a may include a perovskite structure such as lead zirconate titanate (PZT).

[0579] The horizontal gate electrode layer, represented by 1606a-c, is composed of a conductive material that facilitates the application of an electric field to a ferroelectric column, such as tungsten or titanium nitride, which can be selected based on the electrical behavior of the conductive material. The selection of the gate electrode material also takes into account factors such as work function, thermal stability, and ease of integration with existing semiconductor manufacturing processes.

[0580] The drain-selection layer and source-selection layers 1602 and 1604 are incorporated to enable addressing of individual memory cells within the array, respectively. The materials used for these layers are selected based on their conductivity and compatibility with the channel and ferroelectric materials. The design of these layers may also incorporate considerations to reduce parasitic capacitance and ensure rapid data access.

[0581] Edge dielectric columns such as 1618a and 1616a provide electrical insulation at the edges of the channel column where the ferroelectric material is not extended.

[0582] Embodiments of the present disclosure within a 3D memory structure 1600 outline assemblies capable of providing data storage. The design allows for deformation in structural dimensions, such as the diameter of cylindrical columns, which may be uniform or tapered. Furthermore, options relating to solid or hollow configurations may be used.

[0583] Figure 17 shows a 3D memory structure which is a dual-port 3D NAND arrangement according to an embodiment of the present disclosure. The three-dimensional (3D) memory structure shown in Figure 17, referred to as 3D memory structure 1700, exemplifies a dual-port 3D NAND arrangement that provides memory functionality. This structure is characterized by two main vertical formations, designated as a first vertical structure 1708a and a second vertical structure 1708b, which may be identical or substantially identical, as indicated by the designating subscripts "a" and "b".

[0584] The first vertical structure 1708a includes a hollow or solid tapered pass gate electrode column 1718a having a substantially cylindrical shape. The pass gate electrode column 1718a may be made of titanium nitride and may have a larger diameter at the bottom end compared to the top end.

[0585] A dielectric column 1710a, which may be made of hafnium oxide, surrounds the pass gate electrode column 1718a. The dielectric column 1710a is substantially cylindrical in shape, slightly tapered with a slightly larger diameter at the top. The dielectric column 1710a provides electrical isolation between the pass gate electrode and the next layer.

[0586] A cylindrical channel column 1712a, which may be made of IGZO semiconductor material, is positioned around the dielectric column 1710a. The channel column 1712a is characterized by a curve along its length and has a uniform diameter throughout. The thickness of the channel column may be less than 30 nm.

[0587] The PZT ferroelectric column 1714a, which covers most of the length of the channel column 1712a, surrounds the channel column 1712a but recedes at the ends, leaving a portion of the channel column 1712a uncovered. The ferroelectric column 1714a is substantially cylindrical and contains lead, zirconium, and titanium as key basic components.

[0588] The vertical structures 1708a and 1708b traverse several horizontal gate electrode layers 1706a, 1706b, and 1706c, which may be made of tungsten and are positioned at fixed intervals to form an interconnected grid layout. These layers influence the electric field within the ferroelectric column 1714a during memory operation.

[0589] On the memory structure 1700, the drain-selection layer 1702 (e.g., titanium nitride) extends parallel to the horizontal gate electrode layer 1706. Where the drain-selection layer 1702 intersects with the vertical structures 1708a and 1708b, the end dielectric columns 1718a and 1718b are recognizable. These end columns (made of, for example, HfO2) contact the ferroelectric column 1714a at one end, surrounding the uncovered portion of the channel column 1712a and providing insulation.

[0590] Similarly, a source selection layer 1704 (made of, for example, tungsten) parallel to the electrode layer 1706 interfaces with the vertical structure at the bottom of the structure 1700. The end dielectric columns 1716a and 1716b are confirmed at their intersection and may surround the open ends of the channel columns 1712a and 1712b.

[0591] Within the hollow regions of the pass gate electrode columns 1718a and 1718b at the ends, thin dielectric horizontal layers 1720a and 1720b may be positioned near the bottom terminal (e.g., HfO2). These layers seal the bottom open end of the vertical hollow void.

[0592] Figure 18 shows a 3D memory structure 1800 that can be configured as a 3D NOR vertical transistor memory array. The 3D memory structure 1800 comprises a first vertical structure 1808a and an identical (or substantially identical) second vertical structure 1808b, which are arranged adjacent to each other.

[0593] The first vertical structure 1808a includes a vertical plug column 1802a that provides electrical connections to the lower portion of the 3D memory structure. The vertical plug column 1802a may have a uniform diameter along its entire length, or it may have a larger diameter at its lower end than at its upper end. In various embodiments, the plug column 1802a may be manufactured as a solid column or a hollow column.

[0594] The source electrode column 1804a and the drain electrode column 1816a are positioned adjacent to the vertical plug column 1802a. The source electrode column 1804a and the drain electrode column 1816a provide electrical connections to the source node and drain node of a vertical transistor formed along the vertical structure 1808a. The source electrode column 1804a and the drain electrode column 1816a may be composed of a variety of conductive materials, including, but not limited to, metal alloys such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, AlCu and TiW, and conductive polymers.

[0595] The channel column 1812a, which provides a semiconductor channel region for vertical transistors along the first vertical structure 1808a, surrounds the vertical plug column 1802a, the source electrode column 1804a, and the drain electrode column 1816a. The channel column 1812a contains indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), zinc gallium oxide (GZO), indium hafnium oxide (HIO), cadmium oxide (CdO), polysilicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon, crystalline germanium, gallium arsenide (GaAs), and phosphorus. The materials may be formed from materials including, but not limited to, indium phosphate (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT, polythiophene, PPV, graphene, carbon nanotubes (CNT), methylammonium lead halide, cesium lead halide, lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), and other semiconductor materials.

[0596] A ferroelectric column 1814a, which provides a gate dielectric for vertical transistors along the first vertical structure 1808a, surrounds the channel column 1812a. The ferroelectric column 1814a contains perovskite oxide, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), and bismuth titanate ( Bi4Ti3O12), bismuth zinc niobate (Bi(Zn1 / 2Ti1 / 2)O3), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), PMN-PT, PLZT, neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium oxide (HfO2) and other hafnium-based oxides such as doped hafnium oxide, and tungsten The bronze structural material, barium strontium niobate (BSN), lead barium niobate (PBN), potassium niobate tantalate (KTN), bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectrics such as PVDF, TrFE, and P(VDF-TrFE) copolymer, the Auribilius oxide phase, YMnO3 and Lan The materials may include, but are not limited to, rare earth manganese such as tan-modified PLZT, nickel manganese oxide (NiMnO3), relaxa ferroelectrics such as PMN, PST, and PIN, multiferroic materials such as TbMnO3 and EuTiO3, SbSI, GeTe, SnTe, PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, and PbTiO3 / SrTiO3.

[0597] The 3D memory structure 1800 further comprises a plurality of horizontal gate electrode layers 1806, including layers 1806a, 1806b, 1806c, etc. The horizontal gate electrode layers 1806 are arranged at regular intervals along the vertical structure 1808 and provide gate electrodes to vertical transistors. The gate electrode layers 1806 may be formed from materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, AlCu and TiW metal alloys, and conductive polymers.

[0598] Each of the horizontal gate electrode layers 1806 may be surrounded by an oxide / nitride / oxide (ONO) stack 1810, such as 1810a surrounding the gate electrode layer 1806a, to provide insulation between gate electrodes.

[0599] The second vertical structure 1808b in the 3D memory structure 1800 is identical in composition to the first vertical structure 1808a. The two vertical structures 1808a and 1808b are arranged horizontally adjacent to each other with spacing that allows for the integration of the gate electrode layer 1806 and the ONO stack 1810. Together, the first and second vertical structures 1808a and 1808b, along with the horizontal gate electrode layer 1806, can be configured as a 3D NOR memory architecture.

[0600] Figure 19 shows an embodiment of a planar FeFET 1900. The FeFET 1900 comprises a substrate 1910 on which various layers and components are formed. The substrate 1910 may be made of silicon or other suitable semiconductor material. A layer of TiN 1912 is disposed on the substrate 1910. The TiN layer 1912 may function as an electrode and may be deposited by sputtering or other suitable deposition techniques.

[0601] The HZO1908 layer is placed on substrate 1910 and TiN layer 1912. HZO1908 contains hafnium, zirconium, and oxygen and may exhibit ferroelectric properties. HZO1908 may be deposited by ALD, CVD, PVD, or other suitable deposition methods and may have a thickness in the range of 5 nm to 50 nm. Functioning as a ferroelectric layer, HZO1908 enables non-volatile data storage in FeFET1900.

[0602] The IWO1906 layer is conformally deposited on HZO1908. IWO1906 contains indium, tungsten, and oxygen. IWO1906 can be deposited by sputtering or other preferred techniques and may have a range of thicknesses. The IWO1906 layer functions as a controlled oxide layer in FeFET1900.

[0603] The drain contact 1904 and source contact 1914 are formed on a layer of IWO1906. The drain contact 1904 and source contact 1914 may contain metals such as copper, aluminum, or alloys thereof, and can be deposited by PVD, CVD, or other preferred methods. The drain contact 1904 and source contact 1914 enable electrical connection to the FeFET 1900. The drain contact 1904 and source contact 1914 may have a thickness in the range of 50 nm to 500 nm.

[0604] During operation, the voltages applied to the drain 1904, source 1914, and TiN gate contact 1912 can control the ferroelectric polarization of the HZO1908 layer. The polarization state can be used to store information in a non-volatile manner, enabling memory storage capabilities. The IWO1906 layer helps improve switching speed and the durability of the FeFET1900. Overall, the layered structure shown in Figure 19 enables the FeFET1900 to be suitable for non-volatile memory applications.

[0605] Figure 20 shows the transfer characteristics of a ferroelectric FET (FeFET) device, illustrating the relationship between the gate voltage (V_GS) on the x-axis and the resulting drain current (I_D) on the y-axis. Figure 20 may also show characteristics of an FeFET as disclosed herein. The x-axis ranges from -1V to 1V, while the y-axis displays current values ​​on a logarithmic scale from 10^-12 A / μm to 10^-4 A / μm.

[0606] The two separate curves represent the drain current behavior of the FeFET under clockwise (CW) and counterclockwise (MW) polarization. The blue curve (CW) starts at approximately 10^-11 A / μm at -1V, shows a sharp increase around -1V, and reaches a value just over 10^-5 A / μm at 1V. This demonstrates the sharp increase in drain current exhibited by the FeFET under forward bias in the clockwise polarization state.

[0607] Conversely, the red curve (MW) starts at approximately 10^-11 A / μm at -1V and increases more gradually as MW approaches 0V. Per 1V, MW then approaches and follows the blue curve above 1V. This demonstrates equivalent drain current behavior under reverse bias conditions, regardless of polarization state.

[0608] In particular, the separation between the red and blue curves is several orders of magnitude in the negative voltage range near -1V. This substantial difference in off-state current highlights the non-volatile memory effect achievable with the FeFET, depending on the polarization direction of the FeFET. This large memory window is explicitly shown in the green box labeled "Large Memory Window" in the upper left.

[0609] The additional important details provided include the dimensions of the FeFET device, with a specified width / length ratio of 1 μm / 50 μm. The drain voltage is also fixed at 0.05 V. Certain points along the curve are annotated, such as "MW@5e-7A / μm=1V" on the red MW curve, indicating a 1V memory window with a drain current of 5 × 10^-7 A / μm. Another marked point is "CW@-0.5V=1 × 10^6" on the blue CW curve, highlighting a clockwise current value of 1 × 10^-6 A / μm with a gate voltage of -0.5 V.

[0610] In summary, Figure 20 comprehensively depicts the bidirectional transfer characteristics of the FeFET device, highlighting the large memory window achievable through polarization switching, and provides detailed voltage, current, and dimensional specifications to fully convey the measurement conditions and transistor performance. The paired curves effectively compare clockwise and counterclockwise operating modes across the entire gate voltage range.

[0611] Various alternatives and modifications can be conceived by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to include all such alternatives, modifications, and variations. Furthermore, while some embodiments of this disclosure are shown in the drawings and / or described herein, this disclosure is not intended to be limited thereto, as this disclosure is broad in the scope of what the art makes possible, and the specification is intended to be read similarly. Therefore, the above description should not be construed as a limitation, but merely as an example of a particular embodiment. Those skilled in the art will conceive of other modifications within the scope and spirit of the claims appended herein. Other elements, steps, methods, and techniques that differ slightly from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0612] The embodiments shown in the drawings are presented solely to demonstrate specific examples of the present disclosure. The drawings described are illustrative and non-limiting. In the drawings, for illustrative purposes only, the sizes of some elements may be exaggerated and not depicted to a particular scale. Furthermore, elements shown in the drawings with the same number may be identical or similar elements, depending on the context.

[0613] When the term “equipped with” is used herein and in the claims, the term does not exclude other elements or steps. When an indefinite or definite article is used with a single noun, for example, “a,” “an,” or “the,” this includes multiple such nouns unless specifically stated otherwise. Therefore, the term “equipped with” should not be interpreted as being limited to the items enumerated therein, and since the term does not exclude other elements or steps, the scope of the expression “a device comprising items A and B” should not be limited to a device consisting only of components A and B. This expression means to the present disclosure that A and B are merely related components of a device.

[0614] Furthermore, the terms “First,” “Second,” “Third,” and similar terms, whether used in the specification or in the claims, are provided to distinguish similar elements and are not necessarily provided to describe a sequential or chronological order. Terms used in this manner are interchangeable under appropriate circumstances (unless otherwise expressly disclosed), and it should be understood that embodiments of the disclosure described herein may operate in sequences and / or arrangements other than those described or shown herein.

[0615] Each of the characteristics and examples described herein, as well as any combination thereof, can be said to be included by this disclosure. Accordingly, this disclosure covers the following non-limiting numbered embodiments:

[0616] 1. An integrated circuit comprising: a plurality of microvolts, each of which is spaced apart from the others and adjacent to a first surface, the plurality of microvolts including a first microvolt; and a plurality of junction areas, each of which is located on the first surface adjacent to one of the plurality of microvolts, the plurality of junction areas including a first junction area that operably communicates with the first microvolt.

[0617] 2. The integrated circuit according to embodiment 1, wherein the first junction area includes a plurality of junctions, each of which operably communicates with the first microvolt.

[0618] 3. The integrated circuit according to embodiment 2, wherein the multiple joints are bumpless joints.

[0619] 4. An integrated circuit according to any one of embodiments 1 to 3, wherein the first microvolt has a capacity between 4 kilobytes and 1 megabyte.

[0620] 5. An integrated circuit according to any one of embodiments 1 to 4, wherein the first microvolt has a capacity between 4 kilobytes and 128 kilobytes.

[0621] 6. An integrated circuit according to any one of embodiments 1 to 5, wherein the first microvolt has a capacity between 4 kilobytes and 16 kilobytes.

[0622] 7. An integrated circuit according to any one of embodiments 1 to 6, wherein the first microvolt has dimensions of less than 256 micrometers × less than 256 micrometers and extends a predetermined distance in the vertical direction.

[0623] 8. An integrated circuit according to any one of embodiments 1 to 7, wherein the first microvolt has dimensions of 32 micrometers × 32 micrometers and extends a predetermined distance in the vertical direction.

[0624] 9. The integrated circuit according to embodiment 8, wherein the vertical dimensions correspond to at least eight memory layers.

[0625] 10. An integrated circuit according to any one of embodiments 1 to 9, wherein the bit density of the first microvolt is greater than 0.2 gigabits / square millimeter for each layer of the microvolt.

[0626] 11. An integrated circuit according to any one of embodiments 1 to 10, wherein the first microvolt is located at the back end of the die line.

[0627] 12. The integrated circuit according to embodiment 1, further comprising an SRAM volt arranged adjacent to the first microvolt.

[0628] 13. The integrated circuit according to embodiment 12, wherein the first junction area operably communicates with an SRAM vault.

[0629] 14. The integrated circuit according to embodiment 12, further comprising a second junction area located on the first surface and operably communicating with an SRAM vault.

[0630] 15. The integrated circuit according to embodiment 12, wherein a plurality of microvolts are formed on a first die, an SRAM volt is formed on a second die, and the first and second dies are joined together.

[0631] 16. The integrated circuit according to embodiments 1 to 15, further comprising a DRAM volt adjacent to a microvolt.

[0632] 17. The integrated circuit according to embodiment 16, wherein the first junction area operably communicates with a DRAM vault.

[0633] 18. The integrated circuit according to embodiment 16, further comprising a second junction area located on the first surface and operably communicating with a DRAM vault.

[0634] 19. The integrated circuit according to embodiment 16, wherein a plurality of microvolts are formed on a first die, a DRAM volt is formed on a third die, and the first and second dies are rigidly fixed together.

[0635] 20. The integrated circuit according to Embodiment 1, further comprising a read address register operably connected to a first junction area, the read address register being configured to hold a read address and communicate with a first microvolt.

[0636] 21. The integrated circuit according to embodiment 1 or 20, further comprising a read data register operably connected to the first microvolt, configured to receive and hold read data from the first microvolt.

[0637] 22. The integrated circuit according to embodiment 21, wherein a read data register is operably connected to a first junction area to transmit read data to the first junction area.

[0638] 23. The integrated circuit according to embodiment 21, wherein the read data register is operably connected to a second junction area to transmit read data to a second junction area of ​​a plurality of junction areas.

[0639] 24. An integrated circuit according to any one of embodiments 21 to 23, further comprising a second read data register configured to operably communicate with a read data register and to receive and hold read data from the read data register.

[0640] 25. An integrated circuit according to embodiment 24, dependent on embodiment 22, wherein a second read data register is located on a die having a second face, the second face including a read data junction area operably connected to a first junction area of ​​the first face.

[0641] 26. An integrated circuit according to embodiment 24, dependent on embodiment 23, wherein a second read data register is located on a die having a second face, the second face including a read data junction area operably connected to a second junction area of ​​the first face.

[0642] 27. An integrated circuit according to any one of embodiments 1 to 26, further comprising a second read data register located on a die different from the die having a plurality of microvolts.

[0643] 28. An integrated circuit according to any one of embodiments 1 to 27, further comprising a second read address register located on a die different from the die containing a plurality of microvolts.

[0644] 29. The integrated circuit according to embodiment 1 or 20, further comprising a second read address register.

[0645] 30. The integrated circuit according to embodiment 29, further comprising a second bonding area on the second surface.

[0646] 31. The integrated circuit according to embodiment 30, wherein the second read address register is configured to receive and hold a read address and to transmit the read address to the read address register via the second face.

[0647] 32. The integrated circuit according to embodiment 31, wherein the second surface and the first surface are joined together.

[0648] 33. An integrated circuit according to any one of embodiments 1 to 32, further comprising a through-silicon electrode operably connected at a first end to a third surface, wherein the third surface is opposite to the first surface.

[0649] 34. The integrated circuit according to embodiment 33, further comprising an interconnect connected to a first face and a second end of a through-silicon electrode.

[0650] 35. The integrated circuit according to embodiment 1, further comprising a second microvolt that operably communicates with a first junction area.

[0651] 36. The integrated circuit according to embodiment 35, further comprising a multiplexer operably connected to the first microvolt to receive first read data from the first microvolt, the multiplexer operably connected to the second microvolt to receive second read data from the second microvolt, and the multiplexer configured to select between the first read data and the second read data for output.

[0652] 37. The integrated circuit according to embodiment 36, further comprising a counter configured to communicate operably with a multiplexer and to sequentially read out first read data and second read data.

[0653] 38. The integrated circuit according to embodiment 36 or 37, further comprising a read data register configured to receive and internally hold first read data or second read data.

[0654] 39. The integrated circuit according to embodiment 38, further comprising a second junction area on the first face, wherein a read data register is connected to the second junction area to transmit held first read data or second read data from a multiplexer to the second junction area.

[0655] 40. An integrated circuit according to any one of embodiments 1 to 39, further comprising an assembly including a first die having a plurality of microvolts.

[0656] 41. An integrated circuit according to any one of embodiments 1 to 40, further comprising an assembly including a first die having a plurality of microvolts, including a first microvolt and a second microvolt.

[0657] 42. The integrated circuit according to embodiment 40 or 41, further comprising a second die having a read address register and a read data register, wherein the first die is bonded to the second die.

[0658] 43. The integrated circuit according to embodiment 42, wherein the first die includes a second bonding area on a first face, the second die includes a third bonding area and a fourth bonding area, the first bonding area of ​​the first die is connected to the third bonding area of ​​the second die, and the second bonding area of ​​the first die is connected to the fourth bonding area of ​​the second die.

[0659] 44. The integrated circuit according to embodiment 43, wherein the read address register is operably connected to a third junction area to communicate read data to the third junction area.

[0660] 45. The integrated circuit according to embodiment 43 or 42, wherein a read data register is operably connected to a fourth junction area to receive read data from a fourth junction area of ​​a second die.

[0661] 46. ​​An integrated circuit according to any one of embodiments 41 to 45, wherein the first die includes a second read address register configured to receive and hold a read address, and the second read address register is configured to transmit the read address to a first microvolt and a second microvolt.

[0662] 47. The integrated circuit according to embodiment 45, wherein the first die further comprises a multiplexer configured to select between the output of a first microvolt and the output of a second microvolt.

[0663] 48. The integrated circuit according to embodiment 47, further comprising a second junction area on a second face of a first die, wherein the interconnect connects the second junction area to the input of a multiplexer, and the multiplexer is configured to select between the output of a first microvolt, the output of a second microvolt, and transmission from the junction area.

[0664] 49. The integrated circuit according to embodiment 47 or 48, further comprising a phase counter configured to control a multiplexer.

[0665] 50. The integrated circuit according to embodiment 47 or 48, further comprising a third address register configured to receive and hold the output of a multiplexer.

[0666] 51. The integrated circuit according to embodiment 49, wherein a third address register is operably connected to a second junction area of ​​the first die.

[0667] 52. An integrated circuit according to any one of embodiments 42 to 50, further comprising a read address register and a through-silicon electrode (TSV) connected to a second face of the die.

[0668] 53. An integrated circuit according to any one of embodiments 42 to 51, further comprising a second through-silicon electrode (TSV) connected to a second bonding area of ​​the first die and a second read data register on a second surface.

[0669] 54. The integrated circuit according to embodiment 1, wherein the multiplexer is configured to select one of a plurality of microvolts.

[0670] 55. The integrated circuit according to embodiment 54, wherein the phase counter is configured to control the selection of a multiplexer.

[0671] 56. The integrated circuit according to embodiment 1, further comprising through-silicon electrodes (TSVs) operably connected to a first and second surface of a die having a plurality of microvolts.

[0672] 57. The integrated circuit according to embodiment 1, wherein the through-silicon electrode is configured to facilitate communication between a second die connected to a first die having a plurality of microvolts.

[0673] 58. The integrated circuit according to Embodiment 1, wherein the first microvolt comprises at least one column of a 3D-NOR formed from a plurality of transistors, each transistor comprising a gate connected to a read-write enable, a source connected to a bit line, and a drain connected to a select line.

[0674] 59. The integrated circuit according to Embodiment 1, wherein the first microvolt comprises a column of 3D-NAND formed from a plurality of transistors, each transistor having a gate connected to a read / write enable line, a source connected to a bit line, and a drain connected to the source of a second transistor.

[0675] 60. The integrated circuit according to Embodiment 1, wherein the first microvolt comprises a column of 3D-NAND having a pass gate formed from a plurality of transistors, each transistor having a gate connected to a read / write enable line, a source connected to a bit line, a drain connected to the source of a second transistor, and a pass gate connected to all of the plurality of transistors.

[0676] 61. The integrated circuit according to Embodiment 1, wherein the first microvolt comprises a column of 3D-NOR transistors having independent read and write enable lines, each transistor comprising a source connected to a bit line, a drain connected to a read enable line, and a gate connected to a write enable line.

[0677] 62. An integrated circuit according to any one of embodiments 1 to 61, wherein the plurality of microvolts include a thermal management layer configured to dissipate heat generated by the microvolts during operation.

[0678] 63. The integrated circuit according to embodiment 62, wherein the thermal management layer comprises a material having high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene.

[0679] 64. An integrated circuit according to any one of embodiments 1 to 63, further comprising a hardware-based encryption module operably connected to at least one microvolt for securing data written to or read from a microvolt.

[0680] 65. An integrated circuit according to any one of embodiments 1 to 64, further comprising a power management circuit configured to adjust the voltage and current supplied to a plurality of microvolts based on the operating status.

[0681] 66. The integrated circuit according to embodiment 65, wherein the power management circuit includes a low-power mode that reduces the power supply to the microvolts during periods of inactivity.

[0682] 67. An integrated circuit according to any one of embodiments 1 to 66, further comprising a signal conditioning circuit operably connected to a plurality of microvolts to improve the integrity of the data transfer signal.

[0683] 68. The integrated circuit according to embodiment 67, wherein the signal conditioning circuit comprises a filter, an amplifier, or an error correction encoder.

[0684] 69. An integrated circuit according to any one of embodiments 1 to 68, further comprising a diagnostic module configured to monitor the health and performance of a microvolt and report indicators to an external controller.

[0685] 70. The integrated circuit according to embodiment 69, wherein the diagnostic module is capable of performing a self-test against a microvolt and generating an alert if a malfunction is detected.

[0686] 71. An integrated circuit according to any one of embodiments 1 to 70, wherein each microvolt includes a built-in self-healing mechanism capable of isolating and bypassing a faulty memory cell.

[0687] 72. The integrated circuit according to embodiment 71, wherein the self-repair mechanism utilizes redundancy in the form of spare memory cells that can be dynamically allocated to replace a faulty cell.

[0688] 73. An integrated circuit according to any one of embodiments 1 to 73, wherein the microvolts are arranged in a matrix configuration to enable parallel processing and data acquisition.

[0689] 74. The integrated circuit according to embodiment 73, wherein the matrix configuration includes row and column decoders to facilitate access to individual microvolts.

[0690] 75. An integrated circuit according to any one of embodiments 1 to 74, further comprising a flexible substrate that enables the integrated circuit to be adapted to a non-planar surface.

[0691] 76. The integrated circuit according to embodiment 75, wherein the flexible substrate comprises a material selected from the group consisting of polyimide, PEEK, liquid crystal polymer, and flexible glass.

[0692] 77. An integrated circuit according to any one of embodiments 1 to 76, wherein the first microvolt is configured to operate as cache memory for a processor.

[0693] 78. The integrated circuit according to embodiment 77, wherein the cache memory operates in one of the following modes: write-through, write-back, write-around, or a combination thereof.

[0694] 79. An integrated circuit according to any one of embodiments 1 to 78, wherein the first microvolt is part of a redundant array of independent memory elements for error correction and data recovery.

[0695] 80. An integrated circuit according to any one of embodiments 1 to 79, wherein the first microvolt includes a crossbar switch architecture to facilitate data routing between memory cells.

[0696] 81. The integrated circuit according to embodiment 80, wherein the crossbar switch architecture enables non-blocking data transfer within the integrated circuit.

[0697] 82. An integrated circuit according to any one of embodiments 1 to 81, wherein the first microvolt includes a dedicated readout peripheral.

[0698] 83. An integrated circuit according to any one of embodiments 1 to 82, wherein the first microvolt includes a dedicated read port.

[0699] 84. An integrated circuit according to any one of embodiments 1 to 83, wherein the first microvolt includes a dedicated writing peripheral.

[0700] The first microvolt is an integrated circuit according to any one of embodiments 1 to 84, including a dedicated writing port.

[0701] 86. A method comprising forming an integrated circuit according to any one of embodiments 1 to 85.

[0702] 87. A method of using an integrated circuit, which includes using an integrated circuit described in any one of embodiments 1 to 85.

Claims

1. A plurality of microvolts, each of the plurality of microvolts being spaced apart from each other and adjacent to a first surface, the plurality of microvolts including the first microvolt, A plurality of bonding areas, each of the plurality of bonding areas is located on the first surface adjacent to one of the plurality of microvolts, and the plurality of bonding areas includes a first bonding area that operably communicates with the first microvolt, An integrated circuit comprising:

2. The integrated circuit according to claim 1, wherein the first junction area includes a plurality of junctions, each of which operably communicates with the first microvolt.

3. The integrated circuit according to claim 2, wherein the plurality of joints are bumpless joints.

4. The integrated circuit according to claim 1, further comprising an SRAM volt disposed adjacent to the first microvolt.

5. The integrated circuit according to claim 4, wherein the first junction area operably communicates with the SRAM vault.

6. The integrated circuit according to claim 4, further comprising a second junction area disposed on the first surface and operably communicating with the SRAM vault.

7. The integrated circuit according to claim 4, wherein the plurality of microvolts are formed on a first die, the SRAM volts are formed on a second die, and the first die and the second die are joined together.

8. The integrated circuit according to claim 1, further comprising a read address register operably connected to the first junction area, wherein the read address register is configured to hold a read address and transmit the read address to the first microvolt.

9. The integrated circuit according to claim 1, further comprising a read data register operably connected to the first microvolt, configured to receive and hold read data from the first microvolt.

10. The integrated circuit according to claim 9, wherein the read data register is operably connected to the first junction area to transmit the read data to the first junction area.

11. The integrated circuit according to claim 9, wherein the read data register is operably connected to the second junction area to transmit read data to the second junction area of ​​the plurality of junction areas.

12. The integrated circuit according to claim 1, further comprising a second read address register.

13. The integrated circuit according to claim 12, further comprising a second bonding area located on the second surface.

14. The integrated circuit according to claim 13, wherein the second read address register is configured to receive and hold the read address and to transmit the read address to the read address register via the second plane.

15. The integrated circuit according to claim 14, wherein the second surface and the first surface are joined together.

16. The integrated circuit according to claim 1, further comprising a second microvolt that operably communicates with the first junction area.

17. The integrated circuit according to claim 16, further comprising a multiplexer operably connected to the first microvolt to receive first read data from the first microvolt, the multiplexer operably connected to the second microvolt to receive second read data from the second microvolt, and the multiplexer configured to select between the first read data and the second read data for output.

18. The integrated circuit according to claim 17, further comprising a counter configured to communicate operably with the multiplexer and to sequentially read the first read data and the second read data.

19. The integrated circuit according to claim 17, further comprising a read data register configured to receive in order to internally hold the first read data or the second read data.

20. The integrated circuit according to claim 19, further comprising a second junction area disposed on the first surface, wherein the read data register is connected to the second junction area to transmit held first read data or second read data from the multiplexer to the second junction area.

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