Method and system for the testability of known good dies for face-to-face bonded chiplets

Abstract

A known method for fabricating a good stack and related systems are disclosed. The method comprises forming a first semiconductor device having an interface logic having a plurality of interconnects electrically connected to the surface of a first semiconductor device. The method also comprises activating an interconnect loopback configured to receive a first interconnect of the plurality of interconnects and to communicate electrically back to the interface logic via the interconnect loopback. The method electrically connects a test signal to the first interconnect of the plurality of interconnects and tests the return signal returned from the interconnect loopback, thereby testing the path from the first interconnect of the plurality of interconnects back to the interface logic via the interconnect loopback.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed on August 11, 2023, entitled "INTEGRATED CIRCUIT HAVING MEMORIES AND A SHARED WRITE PORT", identified by docket number P23 - 133 - US - PSP, the entire content of which is incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed on November 27, 2023, entitled "METHOD AND SYSTEM FOR KNOWN - GOOD - DIE TESTABILITY OF FACE - TO - FACE BONDED CHIPLETS", the entire content of which is incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed on November 27, 2023, entitled "SYSTEM AND METHOD FOR HAVING CORRECT - BY - CONSTRUCTION TIMING CLOSURE", the entire content of which is incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed on March 20, 2024, entitled "ASSEMBLY HAVING A FACE - TO - FACE BONDED CHIPLET", identified by docket number P24 - 052 - US - PSP, the entire content of which is incorporated herein by reference.

[0005] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed on 23 April 2024, identified by reference number P24-081-US-PSP, entitled “INTEGRATED CIRCUIT HAVING MICROVAULT MEMORIES,” the entire contents of which are incorporated herein by reference.

[0006] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed on 23 April 2024, identified by reference number P24-082-US-PSP, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS,” the entire contents of which are incorporated herein by reference.

[0007] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed on 23 July 2024, identified by reference number P24-135-US-PSP, entitled “SYSTEM, METHOD, AND APPARATUS FOR WAFER-SCALE MEMORY,” the entire contents of which are incorporated herein by reference. [Background technology]

[0008] Technical field This disclosure relates to an integrated circuit. More specifically, this disclosure relates to an integrated circuit that allows testing for known-good-die when bonding chiplets face-to-face.

[0009] Description of related technologies A chiplet refers to a small chip designed to function as a single entity while utilizing advanced packaging technology. This miniaturized chip is created by dividing a larger chip into several smaller chips, each possessing a unique function or capability. The concept, stemming from the semiconductor industry, requires overcoming the physical limitations of traditional monolithic chip designs and achieving higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality. [Overview of the project] [Problems that the invention aims to solve]

[0010] Chiplets are derived from different architectures such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways according to the requirements of a specific application. One of the advantages of the chiplet approach is that different chiplets from different manufacturers can be mixed and matched to create custom solutions that meet specific computing requirements. Because chiplets can be upgraded or replaced without requiring a complete system redesign, this approach also enables shorter time to market, reduced development costs, and increased flexibility.

[0011] Chiplets can be used in a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chiplets are expected to play a crucial role in future computing and are thought to unlock new possibilities for creating more powerful and / or advanced electronic devices. [Means for solving the problem]

[0012] Summary of the Invention

[0013] A known method for fabricating a good stack involves forming a first semiconductor device having an interface logic having multiple interconnects electrically connected to the surface of the first semiconductor device. An interconnect loopback is then activated, designed to receive signals from the first interconnect among the multiple interconnects and to communicate electrically back to the interface logic via the loopback. A test signal is electrically connected to the first interconnect, and the return signal from the interconnect loopback is tested to evaluate the path from the first interconnect back to the interface logic via the loopback.

[0014] In one embodiment, the method includes activating an interconnect loopback by loading a test signal into a buffer. In this method, activation of the interconnect loopback can be achieved by activating a tristate buffer connected to either the interconnect loopback itself or a first interconnect among a plurality of interconnects. This serves as an optional feature of the method.

[0015] The method may optionally include bonding a first semiconductor device to a second semiconductor device to improve performance and functionality. Boundary scan may be used as an optional feature to test the electrical connections between multiple interconnects of the first semiconductor device and multiple complementary interconnects of the second semiconductor device.

[0016] In one embodiment, the method may include joining complementary interface logic of a second semiconductor device having a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device. In addition, the method may include connecting a plurality of interconnects of the first semiconductor device to a set of complementary interconnects of the second semiconductor device. The method may also include performing a boundary scan to test the connectivity of the complementary interface logic to the interface logic, which is an optional feature that can enhance the effectiveness and accuracy of the overall process.

[0017] In the method, the operation of electrically connecting a test signal to a first interconnect among a plurality of interconnects may optionally include directly applying the test signal to the first interconnect among a plurality of interconnects. In the method, the process of electrically connecting a test signal to a first interconnect among a plurality of interconnects may optionally include applying the test signal to an interconnect loopback. In one embodiment of the method, at least one conductive junction is located on the surface of a first semiconductor device, and the first interconnect among a plurality of interconnects functions as a conductive path configured to electrically connect the conductive junction to interface logic. In addition, the interconnect loopback may include another conductive path configured to electrically connect to interface logic.

[0018] The method may include an additional step of buffering a test signal according to a clock, which is an optional feature that may be adopted in the process. In the method, the optional feature includes buffering a return signal according to a clock guideline. In the method, the interface logic includes an external interface connected to a first interconnect among a plurality of interconnects, which functions as an optional feature for improved functionality. In the method, the interface logic includes an external interface connected to an interconnect loopback, which provides an optional feature for better communication and interaction within the system.

[0019] The method may include an interconnect loopback featuring a comparator designed to compare a test signal with a return signal to determine the integrity of the signal. In the method, the interconnect loopback may also include a delay circuit configured to introduce a controlled delay in the return signal, enabling testing of the timing characteristics of a first interconnect among a plurality of interconnects. In the method described, an additional optional feature is to dynamically adjust the test signal based on a predetermined test pattern to enhance its effectiveness. In one embodiment of the method, test data is loaded in series with a boundary canceller to generate a test signal on a first interconnect among a plurality of interconnects. The return signal is then sampled into a second boundary canceller, and the return signal is shifted. In the method, there is also an optional feature that includes comparing the sampled return signal with an expected return signal.

[0020] In the described method, an optional feature is that the first interconnect among a plurality of interconnects is a read-address interconnect. In this case, the test signal is a read address, and the return signal is a return read address returned from the first interconnect among the plurality of interconnects via an interconnect loopback. In one embodiment of the method, the return read address is applied to the read data output bus of the interface logic of a first semiconductor device to enhance the functionality of the entire process. In the method, additional steps may include signaling a register clock signal to the interface logic and buffering the return read address in a register. In the aforementioned method, an optional feature is that the return read address is tested by examining the output of a register.

[0021] As previously described, the method may include an interconnect loopback featuring at least one buffer. This buffer is specifically designed to selectively connect the interconnect loopback to a first interconnect among a plurality of interconnects, providing improved functionality and flexibility in the system. In the method, the first interconnect from the plurality of interconnects may be a clock interconnect, the test signal may be a clock signal, and the return signal may be a return clock signal returned from the first interconnect via the interconnect loopback. This configuration serves as an optional feature within the method.

[0022] In the method, an optional feature includes applying a return clock signal to the read data output bus of the interface logic of a first semiconductor device. In embodiments of the method, a register clock signal is signaled to the interface logic, and the return clock signal is buffered in the register. In the method, an optional step includes testing the return clock signal in the register to ensure its proper function and accuracy. In one embodiment, the method includes an interconnect loopback, which includes at least one tristate buffer configured to selectively connect the interconnect loopback to a first interconnect of a plurality of interconnects. In embodiments of the method, the first interconnect of a plurality of interconnects functions as a read data interconnect, the test signal represents read test data, and the return signal constitutes return read test data sent back from the first interconnect via the interconnect loopback. The method includes an optional feature that applies the read test data returned to the read data output bus of the interface logic of a first semiconductor device. In embodiments of the method, the method may further include signaling a register clock signal to the interface logic and buffering return read test data in the register, providing optional features that enhance the efficiency of the method. Optional features of the method include testing the return read test data by examining the output of the register.

[0023] In the method, the interconnect loopback includes at least one tristate buffer that can selectively connect the interconnect loopback to a first interconnect among a plurality of interconnects. In an embodiment of the method, the first interconnect among the plurality of interconnects functions as a write clock interconnect. In this case, the test signal corresponds to the write clock signal, and the return signal is the returned write clock signal sent back from the first interconnect via the interconnect loopback. In a method for coordinating data transfer in a system having at least two semiconductor devices, an optional feature includes applying the write clock signal to the read data output bus of the interface logic of the first semiconductor device. In an embodiment of the method, there are additional steps of signaling the interface logic with a register clock signal and buffering the returned write clock signal in the register.

[0024] In this method, the operation of testing the returned write clock signal may optionally be performed by examining the output of a register. In an embodiment of this method, the first interconnect of a plurality of interconnects functions as a write address interconnect. In this case, the test signal is designed to define a write address, and the return signal constitutes the returned write address that comes back from the first interconnect of the plurality of interconnects via an interconnect loopback. In this method, an optional feature includes applying the returned write address to the read data output bus of the interface logic of the first semiconductor device. In this method, an optional feature includes signaling the interface logic with a register clock signal and buffering the returned write address in a register.

[0025] In an embodiment of the method, the operation of testing the returned write address includes examining the output of a register. In the method, a first interconnect among a plurality of interconnects may be a write data interconnect, where a test signal defines write test data and a return signal consists of the returned write test data returned from the first interconnect via an interconnect loopback. This setup functions as an optional feature of the method. In an embodiment of the method, the returned write test data is applied to a read data output bus of interface logic of a first semiconductor device. In the method, optional features include signaling a register clock signal to interface logic and buffering the returned write test data in a register. In the method as mentioned, the operation of testing the returned write test data may include examining the output of a register. This is an optional feature that may be employed to ensure the accuracy and functionality of test data.

[0026] The stack system may include a first semiconductor device including interface logic having a plurality of interconnects electrically connected to a surface of the first semiconductor device. This device also has an interconnect loopback designed to receive a first interconnect from the plurality of interconnects and communicate back to the interface logic via the loopback. Additionally, there is a test signal connection electrically communicating with the first interconnect and a return signal connection for testing a path from the test signal connection, through the first interconnect and the interconnect loopback, back to the interface logic and ultimately to the return signal connection.

[0027] The system includes a first semiconductor device, and an optional feature of this system is the presence of a second semiconductor device bonded to the first semiconductor device. In an embodiment, the system includes a second semiconductor device characterized by a plurality of complementary interconnects bonded to a plurality of interconnects of the first semiconductor device. This configuration enables the first and second semiconductor devices to provide a boundary scan chain for testing the electrical connection between their respective interconnects, ensuring proper functionality and performance.

[0028] As previously explained, the system may also include complementary interface logic on the second semiconductor device. This complementary interface logic is characterized by a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device. In this embodiment, the plurality of interconnects from the first semiconductor device are connected to the plurality of complementary interconnects on the second semiconductor device. The system includes interface logic and complementary interface logic designed to provide boundary scan for testing the connectivity between them. This boundary scan is an optional feature that can be utilized in certain embodiments for improved functionality.

[0029] In the system, interface logic and complementary interface logic may be connected together to form an integrated boundary scan that implements boundary scan as an optional feature. The system includes a first semiconductor device, which further includes a buffer connected to a test signal from an interconnect loopback. In the system, the first semiconductor device may optionally include a tristate buffer designed to drive a test signal on the interconnect loopback. In one embodiment of the system, a test signal connection is electrically connected to the first interconnect and provides a means for efficient communication between different components of the system. The system may include a test signal connection electrically connected to the interconnect loopback, which functions as an optional feature. In one embodiment of the system, the first interconnect functions as a conductive path that electrically connects a conductive junction on the surface of the first semiconductor device to the interface logic. In addition, the interconnect loopback, which is also a conductive path, is electrically connected to the interface logic and the conductive junction.

[0030] In one embodiment of the system, the interface logic includes an external interface connected to the first interconnect. In another embodiment of the system, the interface logic includes an external interface connected to an interconnect loopback, providing additional functionality and flexibility to the user. In one embodiment of the system, there is an interconnect loopback feature that includes a comparator. This comparator is configured to compare a test signal with a return signal to determine the integrity of the signal. In the system described, the interconnect loopback may include a delay circuit specifically designed to add a controlled delay to the return signal. This feature serves to test the timing characteristics of the first interconnect.

[0031] The system may include a test signal connector designed to dynamically adjust test signals according to a predetermined test pattern. This provides flexibility and adaptability in the test process and offers optional features for improved system performance. In one embodiment, the system includes a boundary cancellation that generates test signals on a first interconnect and a second boundary cancellation configured to sample return signals. The system also includes a comparator designed to compare the sampled return signals with expected return signals, providing optional features for improved performance. In one embodiment, the system includes a first interconnect, which is a read-address interconnect. This interconnect allows the test signal connection to receive read addresses from system components. Furthermore, the return signals are designed to be returned read addresses that are sent back to the first interconnect via an interconnect loopback, ensuring proper functioning and communication within the system. The system includes an additional feature, a read-data output bus designed to receive the returned read addresses.

[0032] The system may also include, as an additional optional feature, a register configured to buffer the read address returned in the register clock signal. The system further includes a comparator configured to test the returned read address output by the register, providing an optional feature for improved functionality. In one embodiment of the system, a first interconnect functions as a clock interconnect, where the test signal is a clock signal and the return signal is the clock signal returned from the first interconnect via an interconnect loopback. The system includes a read data output bus designed to receive the clock signal returned from the interface logic. The system further includes a register designed to buffer the returned clock signal when it receives the register clock signal. This additional feature provides an optional improvement for better performance and efficiency. The system includes a comparator designed to compare the returned clock signal stored in the register with a predetermined value, providing an additional optional feature for improved functionality. The system includes a first interconnect, which is a read data interconnect, and a test signal connection configured to receive read test data.

[0033] In addition, the return signal in the system may be read test data returned from the first interconnect via an interconnect loopback, and functions as an optional feature. The system features an optional component including a read data output bus designed to receive the returned read test data. The system may also feature an additional register clock signal connection to the interface logic and registers designed to buffer the returned read test data based on a clock signal received via the register clock signal connection. This optional enhancement may improve the system's data processing capability for more efficient operation. The system includes an additional feature, a comparator designed to test the returned read test data against a predetermined value.

[0034] As previously described, the system may optionally include at least one tristate buffer. This tristate buffer is designed to selectively connect an interconnect loopback to a first interconnect among several interconnects present in the system. In one embodiment of the system, the first interconnect is a write clock interconnect, the test signal is a write clock signal, and the return signal is the write clock signal returned from the first interconnect via the interconnect loopback. The system may include a read data output bus designed to receive the write clock signal returned from the interface logic. The system further includes an optional feature comprising a register clock signal connector and a register. This register is configured to buffer the returned write clock signal in response to the register clock signal from the register clock signal connector. The system includes an optional feature, a comparator, designed to compare the returned write clock signal with a predetermined value. This allows the system to analyze performance and potential inconsistencies within the clock signals being used. In one embodiment of the system, the first interconnect operates as a write address interconnect, where the test signal is the write address and the return signal corresponds to the returned write address received from the first interconnect via the interconnect loopback.

[0035] The system includes an additional feature, a read-data output bus designed to receive write addresses returned from the interface logic. This read-data output bus complements the system's functionality and enhances its performance. The system may optionally include a register clock signal connector and registers designed to buffer the returned write addresses when they receive register clock signals from the register clock signal connector. The system further includes, according to some embodiments, comparators designed to compare the outputs generated by the registers with predetermined values. In one embodiment, the system includes a first interconnect among a plurality of interconnects that function as a write data interconnect, a test signal having write test data, and a return signal in the form of write test data returned from the first interconnect via an interconnect loopback. The system includes a read-data output bus designed to receive write test data returned from the interface logic, adding an optional feature for enhanced functionality. The system includes a register clock signal interface and registers. The registers are designed to buffer the returned write test data when they receive register clock signals via the register clock signal interface. This feature is optional and may be present in some embodiments of the system. The system described may further include a comparator configured to compare the output of a register with a predetermined value, providing optional features to the user.

[0036] One method of manufacturing includes forming a first semiconductor device according to various possible embodiments, providing different options and approaches to semiconductor production. A method of forming a stack of semiconductor devices includes stacking a first semiconductor device, designed according to one of some possible embodiments, on top of another semiconductor device. In a method of forming a stack of semiconductor devices, the first semiconductor device is provided according to one of a number of possible embodiments. Another semiconductor device is then bonded to the first semiconductor device to result in a stack configuration. A method of using a semiconductor device may include providing a first semiconductor device based on a particular embodiment and testing one of a plurality of interconnects of the device as part of this process. A possible method of designing a semiconductor device includes creating a digital representation of the interface logic in the first semiconductor device and utilizing one of the various embodiments previously described to achieve this formation. The method may also include an optional step of forming a photomask from the digital representation to improve the overall process. A system includes a first semiconductor device designed with features from one of the various embodiments, the first semiconductor device providing means for testing one of a plurality of interconnects. [Brief explanation of the drawing]

[0037] Brief explanation of the drawing

[0038] These and other embodiments will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the drawings.

[0039] [Figure 1] This is a block diagram of an integrated circuit, which may be part of a semiconductor device such as a chiplet, according to embodiments of the present disclosure.

[0040] [Figure 2]Figure 1 shows a perspective view of an assembly having the integrated circuit mounted on a semiconductor device that is electrically connected to another device to form an assembly, according to an embodiment of the present disclosure.

[0041] [Figure 3] A block diagram showing the memory address space of the integrated circuit of Figure 1 is shown according to an embodiment of the present disclosure.

[0042] [Figure 4] A block diagram showing the memory address space having the signal interface of the integrated circuit of Figure 1 is shown according to an embodiment of the present disclosure.

[0043] [Figure 5] The diagram shows two semiconductor devices, such as two chiplets, that automatically test the connectivity and integrated connectivity of a read interconnect within a semiconductor device, according to an embodiment of the present disclosure.

[0044] [Figure 6] The diagram shows two semiconductor devices, such as two chiplets, that automatically test the connectivity and integrated connectivity of a write interconnect within a semiconductor device, according to an embodiment of the present disclosure.

[0045] [Figure 7] A flowchart illustrating a method for testing semiconductor devices, joining two semiconductor devices together, and performing integration testing after joining, according to embodiments of this disclosure, is shown. [Modes for carrying out the invention]

[0046] Modes for carrying out the invention

[0047] Figure 1 shows a block diagram of an integrated circuit 100 that can be packaged as a bondable chiplet (e.g., a bondable face-to-face chiplet) according to embodiments of the present disclosure. The integrated circuit (IC) 100 includes a group of modules 106, comprising modules 108, 110, 112, and 114. The IC 100 also features a shared write port 102 configured to write to the group of modules 106 using a write peripheral 104. Furthermore, the IC 100 includes read peripherals 116, 118, 120, and 122, as well as read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0048] The write port 102 may be configured to provide a single write address space for all of the module group 106, where each of modules 108, 110, 112, and 114 has its own dedicated read ports 124, 126, 128, and 130, respectively. The integrated circuit 100 may be packaged as part of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet or IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet may be electrically connected to another device by means of bonding, soldering, wafer-wafer bonding, face-face chiplet bonding, chiplet-wafer bonding, chiplet-interposer bonding, and / or together by an interposer or other interface connection technology. An interposer may not be used, one or more interposers may be used, or other interface connection technologies common to heterogeneous 3D system-in-package solutions may be used to electrically connect the chiplet to another device.

[0049] Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use a multicycle pipeline circuit. When bonded to another device (e.g., wafer, chiplet, chip, SOC, package, FPGA, etc.), the electrical contacts may be arranged in a manner that provides exclusive access to specific modules 108, 110, 112, 114. For example, a processing / computation element may have exclusive access to module 108 via read port 124, which may contain neural network weights in its register file. Similarly, different processing / computation elements may have exclusive read access to module 110 via read port 126, which may contain different register files. In this particular embodiment, this arrangement of electrical contacts ensures that each computing / processing element has the dedicated access it needs to efficiently perform its specific calculation, thereby providing a compact, modular, and expandable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to use the same resources in a row, which would slow down the overall processing speed. By providing dedicated access, the proposed chiplet ensures, in this particular embodiment, that each processing element can operate at its maximum capacity without interference from other computing elements.

[0050] The write peripheral 104 is a peripheral circuit responsible for processing and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts such that the chip is electrically connected (e.g., junctioned) to a chiplet of the integrated circuit, and as a result, the write port 102 is accessible via a shared write logic system that includes utilizing a shift register-based different voltage design, preferably a high-voltage design, having a shared write address and data component. This shared write logic system is designed to be accessed via a junction chip, another junction chiplet, and / or other circuitry in the same package as the integrated circuit 100. The shift register may allow the system to move data through a series of stages, each of which receives data from the previous stage. By utilizing the shift register, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location where data is written to the chiplet.

[0051] In another embodiment, the interlock 132 may disable the read ports 124, 126, 128, and 130 while data is being written to the module group 106 via the write port 102. Similarly, the interlock 132 may disable the write port 102 when read operations are being performed on the read ports 124, 126, 128, and 130. The written data can then be simultaneously accessed by all processing elements that need to read the data via the respective read ports 124, 126, 128, and 130. This ensures that all processing elements have the most frequently used data available to them, regardless of other reads being performed simultaneously by other processing elements.

[0052] The circuitry of the writing peripheral 104 includes a write driver. This unit receives the data to be written and converts the data into a suitable signal that can change the state of the memory cell. Depending on the type of memory technology used, the signal may include a voltage level, a current pulse, or other type of energy. The shared write logic system may be high voltage due to the specific voltage requirements of the chiplet. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within parameters suitable to avoid causing damage or unnecessary wear.

[0053] Furthermore, the circuitry of the writing peripheral device 104 may feature a data buffer or a write buffer. This component temporarily stores the data to be written, enabling the write operation to be performed at a predetermined pace. By balancing the rate of incoming data with the rate at which the memory cell can be written, the write buffer helps prevent data loss and optimizes system performance.

[0054] Furthermore, in some embodiments, the writing peripheral device 104 may include a write control unit that coordinates a series of operations in the writing process. This write control unit generates control signals to activate the write driver at the appropriate time, controls the flow of data from the write buffer, and adjusts the timing of the write operation. By synchronizing these various operations, the write control unit ensures efficient and reliable writing operations.

[0055] Furthermore, the writing peripheral 104 may include a data encoding mechanism to improve reliability and data integrity. For example, before data is written to the memory cell, the mechanism encodes the data in a manner that allows potential errors to be detected and, in some cases, corrected when the data is read later. This may be useful in systems where data integrity is a higher priority, such as servers or scientific research devices.

[0056] Furthermore, the writing peripheral 104 may include a timing unit that functions as the heartbeat of the system, supplying a clock signal to synchronize the operation of various components of the system. In some systems, the timing unit may include components such as an oscillator, a clock generator, or a phase-locked loop. The timing unit may ensure that all operations occur at appropriate times relative to each other.

[0057] IC100 may be implemented as a face-to-face junction chiplet in which modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC100 may also feature dynamic allocation circuits for allocating memory blocks to the module group 106 based on the use of the module group 106 (for example, each module 108 may include dynamic allocation circuits that dynamically allocate a range of read locations for its respective processing elements).

[0058] IC100 features multiple clocks, each of which supplies a clock to a module of the multiple modules, providing each module with isolated timing from the other modules of the multiple modules. The module group 106 may be arranged in any topology known to those skilled in the art. The bit cell density can be up to 10 times denser than the embedded SRAM cells in the module group 106.

[0059] IC100 may be formed in a chiplet including a first side and a second side, the second side being configured to be bonded to a second semiconductor device. IC100 may include high-voltage writing logic adjacent to the first side of the chiplet. Decoder circuits, driver circuits, and register circuits may be formed in the silicon substrate portion of the chiplet, while the module group 106 is formed in the second layer portion of the chiplet. The second semiconductor device may comprise a plurality of processing elements. Each processing element includes an interface for communicating with each of the multiple modules in the module group 106 when the second semiconductor device is bonded to the chiplet.

[0060] Silicon substrates traditionally serve as the initial stage in IC manufacturing, focusing on the creation of active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to create the complex structures of transistors. These processes operate on a small scale. By applying photolithography, etching, and implantation techniques, it becomes possible to precisely define the transistor structure. The importance of silicon substrates lies in their ability to establish the basic building blocks necessary for signal processing, amplification, and control within the IC. This layer is sometimes referred to as the line front-end ("FEOL").

[0061] In the manufacturing process, a second layer may be added, which traditionally plays the role of interconnect manufacturing, facilitating electrical connections between various IC components. Interconnects may be, but are not limited to, wires, conductive paths, waveguides, signal paths, logic paths, digital paths, buses, and ports. This stage has traditionally focused on creating passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The process for the second layer typically differs from that used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers, typically aluminum or copper, to construct a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are incorporated to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects that enable the routing and distribution of electrical signals throughout the IC. However, as described herein, circuits may also be utilized within this second layer (sometimes referred to as the back-end of the line ("BEOL").

[0062] Alternative embodiments of IC100 may be implemented as a stacked die, monolithic design, TSV, or through-silicon electrode. In a stacked die design, several dies may be stacked on top of each other, with each die performing a different function such as memory and processing. The stacked dies may communicate through wire junctions, microbumps, or bumpless junctions. In a monolithic design, the various functions and modules of IC100 may be incorporated into a single die, forming a more compact and power-efficient design.

[0063] Furthermore, IC100 may include one or more interlocks 132 to prevent conflicts when reading or writing data. The module group 106 may be formed from various non-volatile or semi-volatile (e.g., very long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistors (FeFETs), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating-gate memory, and / or Schottky diodes.

[0064] The module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., a latch flip-flop) that ensures that stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, the module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0065] The module group 106 may utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. In one particular embodiment, the flash memory topology disclosed herein features a matrix of memory cells, each composed of a floating-gate transistor or a charge trap device. The module group 106 may also utilize wear-leveling techniques to extend the lifespan of the memory cells.

[0066] The module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. The FeRAM topology utilizes a ferroelectric material capable of maintaining a polarization state. In one such memory topology, in a particular embodiment, an FeFET may be used to program the ferroelectric material by holding state information. The ferroelectric material may be used to function as a memory bit cell by holding state information.

[0067] The module group 106 may utilize a phase-change memory (PCM) topology, which is a non-volatile memory technology that utilizes a reversible phase change of material to store data. The PCM topology may include any phase-change material, for example, a chalcogenide alloy or chalcogenide glass housed within the memory cell.

[0068] The module group 106 may utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistive switching phenomenon. The ReRAM topology may utilize a thin film material that exhibits a reversible change in resistance when an electrical stimulus is applied.

[0069] Module group 106 may utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a type of non-volatile memory that utilizes spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology may incorporate a magnetic tunnel junction (MTJ) structure and leverage spin-orbit interaction effects to write and read data. The magnetic tunnel junction may have a dielectric layer between the magnetic fixed layer and the magnetic free layer. Writing may be performed by switching the magnetization of the free magnetic layer by applying an in-plane current in an adjacent SOT layer. Reading may be performed by applying current to the magnetic tunnel junction. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write energy consumption.

[0070] Module group 106 may utilize a spin-transfer torque (STT) magnetic random-access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology may use a magnetic tunnel junction (MTJ) structure in which the magnetization orientation determines the stored data. Furthermore, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be modified, for example, using a spin-polarization current.

[0071] IC100 may include a single write peripheral 104 having its own dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock (not shown in Figure 1). Furthermore, the module group 106 may be organized into separate compartments, each having its own dedicated read peripheral 116, 118, 120, 122 having an independent clock.

[0072] Another possible embodiment of IC100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the packaging of IC100. Furthermore, in additional specific embodiments, IC100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) that processes data within the IC.

[0073] Figure 2 shows a perspective view of assembly 200 of the integrated circuit 212 of Figure 1, mounted on a chiplet 230 bonded to a second device 226 according to an embodiment of the present disclosure. The integrated circuit 212 is the circuit within the chiplet 230. The second device 226 may be a chiplet, a semiconductor wafer, a semiconductor package, a encapsulation circuit, etc. For example, the second device 226 may be an AI accelerator such that each processing unit has read access to one module (or a predetermined set) of the module group 236. In yet another embodiment, the second device 226 may be a network controller, where offload circuits exist to read data from each of the modules and process incoming / outgoing packets, etc. The assembly 200 includes a module group 236 having a plurality of modules, including a first module 232 and a second module 234. Figure 2 shows several modules, but for clarity only modules 232 and 234 have reference numbers. The integrated circuit 212 further includes a shared write port 222. The shared write port 222 is interfaced to the write peripheral device 202.

[0074] The second device 226 may write data to any module in the module group 236 using a shared write port 222 via an address and data bus along with a clock and enable signal, although other methods of writing data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc., may be used. Each module has a read port having a read address 218 (to send the address to module 234) and read data 220 (which is the read of data from module 232).

[0075] The module group 236 is formed in a chiplet 230 having two sides including a surface 228 that can be bonded to and complement the second device 226. The chiplet 230 may be formed by forming a circuit on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers may be in reverse order, and / or other layers may be added, removed, etc. The read address 218 and read data 220 are used to read the module 232.

[0076] The second device 226 may read data from module 232 using an address and data bus along with a clock and enable signal, but other methods for reading data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc. may be used.

[0077] All of the read ports 220 are configured to be deactivated when a write operation is applied to the shared write port 222. The read ports 220 may also be configured to handle reads from each other simultaneously. The shared write port 222 is configured to write to the address space, where it is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the multiple modules 236 includes an independent read port that reads simultaneously through its own independent read port relating to any of the multiple modules.

[0078] Each read port for each module may include contacts for a circuit found in the second device 226 for interface connection via metal contacts. Thus, there may be metal contacts on the upper layer 208 configured to interface with metal contacts on the surface 228 of the chiplet 230, and as a result, the metal contacts enable a read space having the same extent as the module read space of module 236. All of the read spaces of the module group 236 may have the same extent as one another (as described with reference to Figures 3 and 4).

[0079] In one embodiment, the read peripherals for the first module 232 are mounted on the silicon substrate 204 (sometimes referred to as the front end of the line). In the manufacturing process, a second layer 206 (sometimes referred to as the back end of the line) may then be built on top of the silicon substrate 204 (and any circuitry) and may include each memory bit cell. In an alternative embodiment, the read peripherals for the first module 232 are mounted on the second layer 206 and are located between the module group 236 and the surface 228 of the chiplet 230.

[0080] The module group 236 may be configured to process only write commands during reset. The write command may be a "slow write" command; that is, the module group 236 may have a write speed that is very low to the read speed of the module group 236. The write logic may be frozen (or disabled) when the module group 236 is used to read data. In some specific embodiments, the integrated circuit 212 provides the ability to allocate memory blocks to the module group 236 based on its use. In other embodiments, the memory address is fixed with the allocation. The integrated circuit 212 may be implemented as a face-to-face bonded chiplet 230. The face-to-face bond may be a bump-less wafer bond.

[0081] The module group 236 may have a single write peripheral 202. In another embodiment, each module of the module group 236 may have a dedicated write peripheral that utilizes a shared clock. In yet another embodiment, the module group 236 may also be organized into separate partitions, each having a dedicated read peripheral, where each dedicated read peripheral has an independent clock. The partitions may consist of one, two, or more modules of the module group 236.

[0082] The overall circuit architecture of the write peripheral 202 may include a set of different components, including a write driver, address decoder, sense amplifier, data input latch, data bus, and / or any combination thereof. The write driver or write buffer may be responsible for the task of transferring data to the memory cell. The write driver or write buffer may amplify the input signal to the memory cell to achieve an appropriate level. The address decoder may be used to interpret the memory address supplied as input to which data should be written. The address decoder may be used to select a target memory cell by activating specific rows and columns of the memory array linked to the address. The sense amplifier may be used to identify and amplify the signal from the memory cell during a read operation and to participate in refreshing the memory cell after data has been written during a write operation. The write operation is initiated by a write enable signal. When a write command is initiated, this signal causes the write driver and decoder to proceed with the write process. The data input latch may be used as a temporary storage unit to hold data that has been set to be written to memory until the write operation is implemented. A data bus with a transmit route may be used to facilitate the movement of data from the data input latch to the memory cell.

[0083] The write operation to the module group may be performed through a priority arbitration circuit that facilitates the access of modules in a predetermined order, and the shared write port 222 may be configured to write to a virtual address space mapped to a physical memory space. The integrated circuit 212 may include high-voltage write logic used in the write peripheral 202, and the second semiconductor device 226 may have multiple processing elements, each of which includes an interface for communicating with each module of the module group 236. Furthermore, the chiplet 230 may include an interface to the shared write port 222 on the second side, thereby interface-connecting to a complementary interface in the second semiconductor device 226.

[0084] Furthermore, the integrated circuit 212 may include a power gating circuit that selectively cuts off the power to the module 236 when it is not in use. In addition, the integrated circuit 212 may have a programming peripheral 202 for the module group 236 connected to dedicated I / O pads to enable data transfer outside the integrated circuit package.

[0085] The integrated circuit 212 may utilize multiple modules of a group of modules 234 that are grouped together. These modules may be synchronized with one another in certain embodiments. In some cases, all modules are synchronized, while in other examples, only specific modules are synchronized. For example, the circuitry in the second device 226 may need to be synchronized with a specific module when reading data from one of the modules in the module group 236.

[0086] To synchronize the modules, the integrated circuit 212 may employ various timing techniques. In some cases, multiple clocks may be supplied to each module of the module group 236, thereby allowing each module to have timing isolated from the other modules in the group. This isolation ensures that any delay in one module does not affect the functionality of other modules. It should be noted that the clocks used may or may not need to be synchronized. In some cases, a common clock may be used to synchronize the modules. In yet another embodiment, the clock signal or signal(s) may be provided by a second device 226.

[0087] In alternative embodiments, other synchronization techniques, such as phase comparison of clock signals or synchronization methods of a phase-locked loop (PLL), may be used. Another embodiment for synchronizing modules in an IC may use synchronization of a delay-locked loop (DLL). In this method, a delay element is added to the clock signal path, and its output is compared with the input clock signal. A feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.

[0088] In another embodiment, the integrated circuit 212 may achieve synchronization between modules using a combination of different synchronization techniques. For example, some modules may use PLL synchronization, while others may use clock delay line or DLL synchronization depending on their specific requirements. Furthermore, the integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in case one method fails. For example, the integrated circuit 212 may use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the others can still maintain synchronization.

[0089] Figure 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0090] The write address space 316 consists of various units in which data, such as weights and / or instructions, can be stored. These units are referred to as memory addresses. The module group 302 includes several memory modules 304, 306, and 308. The write address space 316 can be distributed among the memory modules 304, 306, and 308 such that the write address space 316 extends from 0 to N*M-1. As shown in Figure 3, the module group 302 has N memory modules 304, 306, and 308, where N is a positive integer and each module has a memory size of M. The total number of unique write memory addresses in a particular write address space is N*M, which can be referred to by integers from 0 to N*M-1.

[0091] Starting at 0, the memory addresses in the write address space 316 are arranged sequentially up to N*M-1. In other words, the first address is 0, the last address is N*M-1, and there are a total of N*M addresses. This ordering can be linear (each address increasing by 1) or some other incidental designation pattern.

[0092] Write memory addressing can be implemented in various ways depending on the system architecture. One method used in a particular embodiment is to use a base register and a limit register. In a particular embodiment, the base register holds the smallest valid physical write memory address, and the limit register specifies the size of the range. Thus, the base is added to the relative address to generate a logical address. In other embodiments, a memory addressing scheme may be used, where the base used is set to 0. Further write addressing techniques will be understood by those skilled in the art.

[0093] For any device writing to module group 302, each memory module may have a specific set of write memory addresses, and as a result, all memory addresses within module group 302 are specific with respect to data writing, for example, starting with 0 for the first module and ending with N*M-1 for the last module. In some embodiments, this allocation may depend on the memory management system of the devices writing data to modules 304, 306, and 308, which can range from a simple fixed partitioning scheme to a more complex dynamic partitioning model.

[0094] For example, in a simple linear model where each module (304, 306, or 308) has an address of the same size M, the first module 304 has write addresses 0 to M-1, the second module has write addresses M to 2M-1, the third module has write addresses 2M to 3*M-1, and so on. Therefore, the Nth module 308 has write addresses (N-1)*M to N*M-1.

[0095] Those skilled in the art may use other implementations of write memory addresses from 0 to N*M-1, which depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of programs executed in the system.

[0096] The module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 may have overlapping address spaces, contiguous address spaces, or address spaces with the same extent. The read address spaces 310, 312, and 314 may also be independent of each other. The system includes three independent read address spaces labeled as read address spaces 310, 312, and 314. Each of these read address spaces is separate from the others, meaning that reads can be performed in each space without affecting the others.

[0097] The read address spaces 310, 312, and 314 may be defined as contiguous blocks of memory addresses, each having its own start and end addresses. In the module group 302, each read address space 310, 312, and 314 may have addresses in the range of 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0098] In one embodiment, a single processing unit may be allowed to interface with each of the read address spaces 310, 312, and 314, and simultaneous reads may be implemented as described herein. The independence of the read address spaces 310, 312, and 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.

[0099] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to embodiments of the present disclosure. The signals used in Figure 4 may be used in any embodiment described herein. However, those skilled in the art will understand that different signaling schemes may be used.

[0100] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus containing the address of the data to be written, a write data bus containing the data, and a write clock that causes the write (e.g., on the leading or trailing edge of a clock signal). The write occurs only if the write enable signal indicates that the write should occur. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In some embodiments, the write peripheral 411 may be on a chiplet 230, and in other embodiments, the write peripheral 411 is on a second device 226.

[0101] Module group 402 has modules 404, 406, and 408, each having its own read peripherals 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for transmitting a read address, a read data bus for receiving data, a read clock which is a clock used to control the timing of the output of digital data, and an output enable which is a prerequisite for the output of data. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In further embodiments, multibit or analog data storage may be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the chiplet 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the second device 226.

[0102] Figure 5 illustrates a stack 500 consisting of two semiconductor devices 562 and 502 that can be joined together. The first semiconductor device 562 may be an application chiplet, and the second semiconductor device 502 may be a memory chiplet. The application chiplet 562 includes circuitry to facilitate interconnect testing before joining by using interconnect loopbacks 522, 532, and 542. The first semiconductor device 562 has several test signal connections 580, 582, and 550 that can be used to test the path by examining how signals are returned through one of the return signal connections 558, 554, and 584, respectively. These connections may be connected to external circuitry outside of the boundary cancellation and / or interface logic 548. The tristate buffer 544 may have an enable connection 586 that can control whether the tristate buffer 544 is active or inactive.

[0103] The stack 500 can facilitate the design and integration of a second semiconductor device 502 (e.g., a system-on-a-chip (SoC) or application chiplet) and a first semiconductor device 562 (e.g., a co-chiplet), and more specifically, it can facilitate application design methods for known good dies to facilitate independent testing.

[0104] In some embodiments, the first and second semiconductor devices 562, 502 are joined together in a final stage. Therefore, to achieve independently verified chiplets, the disclosed method is to provide a thin interface module (e.g., interface logic 548) on the first semiconductor device 562 (e.g., application SoC base die), where inputs and outputs may be held in registers at the clock edge. By doing so, application designers can focus on ensuring the independent effectiveness of each semiconductor device.

[0105] With the thin interface logic 548 in place, the application designer's responsibility is primarily to interface with the thin interface logic 548 according to the specifications. By following this approach, the design complexity associated with the integration of cochiplets can be effectively managed, leading to improved efficiency and reliability.

[0106] Independent testing of semiconductor devices 562, 502 may be used to minimize yield losses in the post-integration stage. For example, in a 3D memory fab, each memory chiplet may be manufactured, individually tested to identify known good dies, and then placed in stock. The testing process utilizes serial scan-based built-in self-test (BIST) technology to ensure thorough testing and verification of the memory chiplets. During the placement and routing stage, interface logic 548 is placed by a placement tool, and custom scripts can facilitate vertical routing such as loopbacks 522, 532, 542 and junctions 518, 524, 536. The rest of the design can then be fully routed to establish complete connectivity. Subsequently, an application wafer for the first semiconductor device 562 may be manufactured with the top layer metal junctions 518, 524, 536.

[0107] The first semiconductor device 562 (e.g., as a fully manufactured application wafer) may be tested using pass-through interface logic, which allows for a comprehensive evaluation of the functionality and performance of the application device. Optionally, wafer-level testing may also be performed to further ensure the quality and reliability of the first semiconductor device 562 (e.g., an application chiplet). Through this testing phase, the objective is to identify any defects or problems that may affect the functionality or integration of the device.

[0108] During the hybrid package integration stage, a known high-performance second semiconductor device 502 (e.g., a memory chiplet) obtained from previous tests can be face-to-face bonded with a known high-performance first semiconductor device 562 (e.g., an application chiplet). This bonding process facilitates a secure and reliable connection between the semiconductor devices 502 and 562 (e.g., the memory chiplet and the application chiplet). Furthermore, selective bonding of semiconductor devices at the wafer level can improve post-packaging yield, thereby reducing potential yield losses and improving overall production efficiency.

[0109] The first semiconductor device 562 includes interface logic 548 to facilitate communication with external circuits and external semiconductor devices. The interface logic 548 also includes interconnect loopbacks 522, 532, 542 for testing connectivity between the interface logic 548 and conductive pads (or junctions) 518, 526, 536 located on the surface of the first semiconductor device 562. These connections can be tested before (or after in some embodiments) bonding with another device. The conductive pad 518 of the first semiconductor device 562 may be electrically connected to the conductive pad 516 of the second semiconductor device 502. In addition, the conductive pad 526 of the first semiconductor device 562 may be electrically connected to the conductive pad 528 of the second semiconductor device 502. And the conductive pad 526 of the first semiconductor device 562 may be electrically connected to the conductive pad 538 of the second semiconductor device 502.

[0110] The interface logic 548 includes a plurality of input or output interfaces to other circuits (not shown) within the first semiconductor device 562, and includes a read address input 564, a read clock input 560, and a read data output 546 (each of which may have boundary cancellation to facilitate boundary scan testing). The read clock input 560 is connected to a read clock interconnect 520 that extends to the face of the first semiconductor device 562 and terminates with a conductive pad 518. In addition, the conductive pad 518 is connected to an interconnect loopback 522 which is connected to a buffer 556. The buffer 556 is further connected to a read clock output 558 which should have the same value as the read clock input 560 of the interface logic 548 if the circuit integrity is sound. Therefore, the buffer 556 can connect and / or amplify the signal from the interconnect loopback 522 so that the value of the output to the read clock output 558 can be checked when an external circuit applies a clock signal to the read clock input 560, and the integrity of the path from the interface logic 548 to the conductive pad 518 and finally back to the read clock output 558 can be tested.

[0111] Similarly, interface logic 548 includes a read address interconnect 524 connected to a read address input 564. The read address interconnect 524 extends to the face of the first semiconductor device 562 and is connected to a conductive pad 526. An interconnect loopback 532 is connected to the conductive pad 526 and linked to a buffer 522, allowing testing of the read address output 554 by an external test circuit. Although only one connection is shown, those skilled in the art will know how to extend this to parallel data lines (e.g., eight interconnects, eight conductive pads, eight interconnect loopbacks, eight buffers, etc.) to form an 8-bit address space. Any other number of bits or address size may be used.

[0112] Next, regarding the read address interconnect 524, we consider that the test signal is the read address and the return signal is the return read address obtained from the interconnect loopback 522. The return read address 532 is applied to the read data output bus 546 of the interface logic 548, and may be amplified or connected by the buffer 552 and tested, etc.

[0113] The interconnect loopbacks 522, 532, and 542 in interface logic 548 may include additional components such as comparators and delay circuits to ensure signal integrity and test timing characteristics. The test may also include dynamically adjusting the test signals based on a predetermined test pattern, thereby enabling comprehensive testing and verification of the interconnect.

[0114] For the clock interconnect 520, the test signal is the clock signal, and the return signal is the return clock signal received from the interconnect loopback 532. Similarly, the return clock signal may be applied to the read data output bus of the interface logic 548, buffered in a register, and tested, etc.

[0115] For the read data interconnect 534, the test signal represents the test data applied via the read data input connector 550, which can be amplified by the tristate buffer 544, and the return signal is the return test data received via the read data output connector 584 from the test data applied to the interconnect loopback 542. The test data may be received and / or output to the bus of the interface logic 548, buffered in a register, and tested, etc.

[0116] When the first semiconductor device 562 and the second semiconductor device 502 are joined together, their respective conductive pads (518, 516), (526, 528), and (536, 538) are electrically connected to each other. This enables the transfer of electrical signals between the first and second semiconductor devices 562 and 502.

[0117] The second semiconductor device 502 includes an interface logic 568 comprised of various interconnects (each of which may include a boundary cancellation for testing). This interface logic 568 includes a read clock interconnect 514 that receives a read clock signal from the first semiconductor device 562, a read address interconnect 530 that receives a read address from the first semiconductor device 562, and a read data interconnect 540 that transmits data from the memory cell to the first semiconductor device 562 via a read data output 504. That is, read data from the memory cell 504 is sent through the interface logic 568 to the read data interconnect 540. Similarly, the read address interconnect 530 is sent through the interface logic 568 to the read address 508 used to access the memory cell. The read clock interconnect 514 is a clock transmitted to the memory cell and / or internal logic, thereby allowing the interface logic to buffer the read data when presented to the read data interconnect 540.

[0118] The interface logic 568 may also utilize a serial test data input 510, a test clock 512, and a serial test data output 566 to perform boundary scan. These components enable the interface logic 568 to test the connectivity of the interconnect and verify the integrity of the signals. The interface logic 548 also includes boundary cancellation, including a serial test data input 570 and a serial test data output 574. Optionally, a separate clock, such as the test clock 574, may be used instead of the read clock 560. However, in some embodiments, the boundary cancellation may use the read clock 560. Thus, the connectivity of the first semiconductor device 562 from the interface logic 548 to the second semiconductor device 502 can be tested, and the integrity of the connectivity between them can be ensured.

[0119] Boundary scan is a test technique used to verify the connectivity and integrity of interconnects within semiconductor devices. Therefore, boundary scan may be used to ensure connectivity compatibility when testing the connectivity between the interface logic 548 of a first semiconductor device 562 and the interface logic 568 of a second semiconductor device 502. Any, all, or some of the inputs and / or outputs for the interface logics 548, 568 may include boundary cancellation to control, modify, or test any, all, or some of the inputs and / or outputs.

[0120] Boundary scan testing can be performed by forming a boundary scan chain and connecting the boundary cancellations within each interface logic 548, 568 in a daisy-chain configuration. This forms a serial shift register arrangement, enabling controlled shifting of test data and return data through the boundary scan chain.

[0121] The boundary cancellation within interface logics 548 and 568 provides control and capture functions for manipulating and observing test data and return data within the boundary scan chain via the connected device. This ensures reliable testing of connectivity between the interface logic 548 of the first semiconductor device 562 and the interface logic 568 of the second semiconductor device 502. Thus, through boundary scan testing, the interconnect between the two interface logics 548 and 568 can be thoroughly investigated and verified, ensuring that the connectivity is suitable and functions as intended. The boundary cancellation within each interface logic 548 and 568 allows for precise control over test data and return data, enabling comprehensive analysis and evaluation of connectivity between the two semiconductor devices.

[0122] During testing, various test patterns and data can be loaded into the boundary cancel through the serial test data input 570 of the interface logic 548 of the first semiconductor device 562 and / or the serial test data input 510 of the interface logic 568 of the second semiconductor device 502. These test patterns simulate different input scenarios and conditions, allowing for the investigation of various connection scenarios between the two interface logics. The loaded test data is then shifted through the boundary scan chain using test clocks 512 and 574. Note that the clocks may be coupled, synchronized, and / or other clocks may be used. In each clock cycle, the test data propagates through the serially connected boundary cancel, progressing one cell at a time to the next. This shifting process allows the test data to traverse the interconnect between the two interface logics 548 and 568, verifying the connectivity and integrity of the interconnect. This enables subsequent analysis and comparison with expected return data. By comparing the sampled return data with the expected value, the completeness of connectivity between the two interface logics 548 and 568 can be accurately evaluated.

[0123] Furthermore, at specific points in the boundary scan chain, return data from the interface logic 548 of the first semiconductor device 562 and / or the serial test data input 510 of the interface logic 568 of the second semiconductor device 502 are sampled for additional boundary cancellation. These boundary cancellations capture and retain the return data for further analysis and comparison.

[0124] Figure 6 shows two semiconductor devices 662, 602, such as two chiplets, that automatically test the connectivity and integrated connectivity of the write interconnects 620, 624, 634 within the semiconductor device according to embodiments of the present disclosure. The first semiconductor device 662 has several test signal connections 680, 682, 684 that can be used to test the path by examining how signals are returned through one of the return signal connections 658, 654, 650, respectively. In some embodiments, the write interconnects 620, 624, 634 may be integrated with the read interconnects 520, 524, 534 of Figure 5 on the same interface logic.

[0125] As shown in Figure 6, the stack 600 of two semiconductor devices 662 and 602 consists of an application chiplet (first semiconductor device 662) and a memory chiplet (second semiconductor device 602). The application chiplet 662 includes interconnect loopbacks 622, 632, and 642 for pre-bond interconnect testing. Interface logic 648 within the application chiplet includes interconnect loopbacks 622, 632, and 642 to facilitate communication with external circuits and to test connectivity with conductive pads 618, 626, and 636.

[0126] The interface logic 648 includes input / output interfaces for connectivity to the write address 624, write clock 620, and write data 634 of the first semiconductor device 662. These interfaces, along with interconnect loopbacks 622, 632, and 642, allow for testing of connectivity between the interface logic 648 and the conductive pads (or junctions) 618, 626, and 636 before bonding. In addition, the conductive pads 618, 626, and 636 of the first semiconductor device 662 can be electrically connected to the conductive pads 616, 628, and 638 of the second semiconductor device 602 so that the interface logic 648 can provide connectivity to the memory write function found within the second semiconductor device 602.

[0127] The interface logic 648 consists of interconnects such as a write clock interconnect 620 connected to the write clock input 660 and terminated with a conductive pad 618. It also includes an interconnect loopback 622 and a buffer 656. The integrity of the circuit can be tested by applying a clock signal to the write clock input 660 and comparing it with the write clock output 658.

[0128] Similarly, interface logic 648 includes a write address interconnect 624 connected to write address input 664 and terminated with conductive pad 626. An interconnect loopback 632 connected to buffer 652 enables testing of write address 664.

[0129] The interconnect loopbacks 622, 632, and 642 may include additional components such as comparators and delay circuits to ensure signal integrity and test timing characteristics. Test signals and return signals for testing may include the write address 624, the write data 634, and the write clock signal 620. The connectivity and integrity of the interconnect can be verified by applying these signals through the interconnect loopbacks and comparing them to expected values.

[0130] When the first semiconductor device 662 and the second semiconductor device 602 are joined together, their respective conductive pads (618, 616), (626, 628), and (636, 638) are electrically connected, enabling the transfer of electrical signals between them.

[0131] The second semiconductor device 602 has its own interface logic 668, which includes an interconnect for a write clock 614, a write address 630, and write data 640. Write data applied to the write data interconnect 634 is sent through the interface logic 668 to write data 604, which is used to write to the memory cell addressed by the write address 608 in the write clock 606. The write clock interconnect 614 can receive clock signals to control writing to the memory cell and internal logic.

[0132] Interface logic 668 also incorporates components for boundary scan, such as serial test data input 610, test clock 612, and serial test data output 666. Boundary scan allows testing the connectivity of the interconnect and verifying the integrity of signals between interface logics 648 and 668 of two semiconductor devices.

[0133] Boundary scan testing involves forming a boundary scan chain by connecting boundary cancellations in a daisy-chain configuration within each interface logic 648, 668. This enables controlled shifting of test data and return data through the boundary scan chain. Boundary cancellations provide control and capture functions for manipulating and observing test data and return data within the boundary scan chain. This enables reliable testing of connectivity between interface logics 648 and 668. Some or all of the inputs and / or outputs of interface logics 648, 668 may include boundary cancellations to facilitate reading, writing, or recording test data as known to a person skilled in the art.

[0134] During testing, test patterns and data are loaded into boundary cancel via serial test data inputs 610 and 670 of interface logic 668 and 648. These test patterns simulate different input / output scenarios, allowing for the investigation of various connection scenarios between the two interface logics 668 and 648. The loaded test data is then shifted through the boundary scan chain using test clocks 612 and 674. In each clock cycle, the test data propagates through boundary cancel to verify the connectivity and integrity of the interconnect.

[0135] The return data from the interface logic is sampled for additional boundary cancellations within the boundary scan chain for analysis and comparison. By comparing the sampled return data with the expected value, the completeness of connectivity between the two interface logics can be accurately assessed.

[0136] Figure 7 shows a flowchart of a method 700 for testing a semiconductor device 562 (or 662), bonding two semiconductor devices 502, 562 (or 602, 662) together, and performing an integrated test after bonding, according to an embodiment of the present disclosure.

[0137] Method 700 includes operations 702 to 716. Operation 702 forms a first semiconductor device 562 (or 662) having interface logic 548 (or 648) with a plurality of interconnects 520, 524, 534 (or 620, 624, 634) electrically connected to the surface of the first semiconductor device 562 (or 662). Operation 704 activates an interconnect loopback (one or more of 522, 532, or 542 (or 622, 632, or 642)) connected to one or more of the interconnects (520, 524, or 534 (or 620, 624, or 634)) from the plurality of interconnects 520, 524, 534 (or 620, 624, 634). Operation 706 electrically connects a test signal to an interconnect (one or more of 520, 524, or 534 (or 620, 624, or 635)). The test signal may include, but is not limited to, a read address, read data, data, a clock signal, a read clock signal, etc. The test signal may be input to interface logic 548, 568 (or 648, 668) via a serial test data input, a read data input, a read address input, or an external connection to interface logic 548, 568 (or 648, 668). The test signal may include registers, buffers, tristate logic, clocks, comparators, delays, test patterns, etc., as disclosed herein or known to a person skilled in the art. Operation 708 tests the return signals returned from the interconnect loopback (one or more of 522, 532, or 542 (or 622, 632, or 642)) to test the path from interface logic 548 (or 648) back to interface logic 548 (or 648) via the interconnect (one or more of 520, 524, or 534 (or 620, 624, or 634)) and the interconnect loopback (one or more of 522, 532, or 542 (or 622, 632, or 642)).The return test signals may include registers, buffers, tristate logic, clocks, comparators, delays, test patterns, etc., as disclosed herein or known to a person skilled in the art. Any of the test signals may be output to a connection on interface logic 548, 568 (or 648, 668) and / or to a read data output, serial test data output, read address output, read data output, etc.

[0138] Decision 710 determines whether the test indicates that the semiconductor device is of satisfactory quality. If the test does not indicate that the semiconductor device is of satisfactory quality, the semiconductor is rejected in 712. If the test indicates that the semiconductor device is of satisfactory quality, the semiconductor passes and proceeds to operation 714.

[0139] Operation 714 connects the first semiconductor device 562 to the second semiconductor device 502 (or 602). Operation 716 connects the interface logic 568 (or 668) of the second semiconductor device 502 (or 602) to the interface logic 548 (or 648) of the first semiconductor device 562 (or 662) by connecting a plurality of interconnects 514, 530, 540 (or 614, 630, 640) of the second semiconductor device 502 (or 602) to a plurality of interconnects 520, 524, 534 (or 620, 624, 634) of the first semiconductor device 562 (or 662). The junction may be formed via conductive pads 516, 528, 538, 518, 526, 536 (or 616, 628, 638, 618, 626, 636) on the surfaces of the first and second semiconductor devices 502, 562 (or 602, 662). Operation 718 performs a boundary scan to test the electrical connectivity between multiple interconnects 520, 524, 534 (or 620, 624, 634) of the first semiconductor device 562 (or 662) and multiple interconnects 514, 530, 540 (or 614, 630, 640) of the second semiconductor device 502 (or 602). Operation 720 performs a boundary scan to test the connectivity of complementary interface logic (e.g., 568 or 668) to interface logic (e.g., 548 or 648). Any boundary scan may use registers, buffers, tristate logic, clocks, comparators, delays, test patterns, boundary cancellations, etc., as disclosed herein or known to a person skilled in the art.

[0140] Decision 722 determines whether the semiconductor device passes the boundary scan test. If the semiconductor device fails the boundary scan test, the semiconductor is rejected in 724. If the semiconductor device passes the boundary scan test, the semiconductor device is considered a known good device 726.

[0141] Various alternatives and modifications can be conceived by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to include all such alternatives, modifications, and variations. Furthermore, while some embodiments of this disclosure are shown in the drawings and / or described herein, this disclosure is not intended to be limited thereto, as this disclosure is broad in the scope of what the art makes possible, and the specification is intended to be read similarly. Therefore, the above description should not be construed as a limitation, but merely as an example of a particular embodiment. Those skilled in the art will conceive of other modifications within the scope and spirit of the claims appended herein. Other elements, steps, methods, and techniques that differ slightly from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0142] The embodiments shown in the drawings are presented solely to demonstrate specific examples of the present disclosure. The drawings described are illustrative and non-limiting. In the drawings, for illustrative purposes only, the sizes of some elements may be exaggerated and not depicted to a particular scale. Furthermore, elements shown in the drawings with the same number may be identical or similar elements, depending on the context.

[0143] When the term “equipped with” is used herein and in the claims, the term does not exclude other elements or steps. When an indefinite or definite article is used with a single noun, for example, “a,” “an,” or “the,” this includes multiple such nouns unless specifically stated otherwise. Therefore, the term “equipped with” should not be interpreted as being limited to the items enumerated therein, and since the term does not exclude other elements or steps, the scope of the expression “a device comprising items A and B” should not be limited to a device consisting only of components A and B. This expression means in this disclosure that A and B are merely related components of a device.

[0144] As used herein, the term “stack” may mean connecting, joining, fixing, bonding, electrically connecting, physically connecting, signaling, optically connecting, or otherwise interfaced one or more devices to each other in any direction such that they are fixed together on any dissimilar or homogeneous surfaces between them.

[0145] Furthermore, the terms “First,” “Second,” “Third,” and similar terms, whether used in the specification or in the claims, are provided to distinguish similar elements and are not necessarily provided to describe a sequential or chronological order. Terms used in this manner are interchangeable under appropriate circumstances (unless otherwise expressly disclosed), and it should be understood that embodiments of the disclosure described herein may operate in sequences and / or arrangements other than those described or shown herein.

[0146] Each of the characteristics and examples described above, as well as any combination thereof, can be said to be included by this disclosure. Accordingly, this disclosure includes the following non-limiting numbered aspects:

[0147] 1. A method for fabricating a known good stack, the method comprising: forming a first semiconductor device having interface logic having a plurality of interconnects electrically connected to the surface of a first semiconductor device; activating an interconnect loopback configured to receive a first interconnect of the plurality of interconnects and to communicate electrically back to the interface logic via the interconnect loopback; electrically connecting a test signal to the first interconnect of the plurality of interconnects; and testing a return signal returned from the interconnect loopback, thereby testing the path from the first interconnect of the plurality of interconnects back to the interface logic via the interconnect loopback.

[0148] 2. The method according to aspect 1, wherein the interconnect loopback is activated by loading a test signal into a buffer.

[0149] 3. The method according to embodiment 1, wherein the interconnect loopback is activated by activating a tristate buffer connected to the interconnect loopback and a first interconnect among a plurality of interconnects.

[0150] 4. The method according to embodiment 1, further comprising bonding a first semiconductor device to a second semiconductor device.

[0151] 5. The method according to embodiment 4, further comprising using boundary scan to test the electrical connections between a plurality of interconnects of a first semiconductor device and a plurality of complementary interconnects of a second semiconductor device.

[0152] 6. The method according to embodiment 4, further comprising joining complementary interface logic of a second semiconductor device having a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device, and connecting a plurality of interconnects of the first semiconductor device to a plurality of complementary interconnects of the second semiconductor device.

[0153] 7. The method according to aspect 6, further comprising performing a boundary scan to test the connectivity of complementary interface logic to the interface logic.

[0154] 8. The method according to embodiment 1, wherein the operation of electrically connecting a test signal to a first interconnect among a plurality of interconnects includes applying a test signal to a first interconnect among a plurality of interconnects.

[0155] 9. The method according to embodiment 1, wherein the operation of electrically connecting a test signal to a first interconnect among a plurality of interconnects includes applying a test signal to an interconnect loopback.

[0156] 10. The method according to embodiment 1, wherein at least one conductive junction is located on the surface of a first semiconductor device, the first interconnect of a plurality of interconnects is a conductive path configured to electrically connect at least one conductive junction to an interface logic, and an interconnect loopback is another conductive path configured to electrically connect to the interface logic.

[0157] 11. The method according to embodiment 1, further comprising buffering a test signal according to a clock.

[0158] 12. The method according to embodiment 1, further comprising buffering the return signal according to the clock.

[0159] 13. The method according to embodiment 1, wherein the interface logic includes an external interface connected to a first interconnect among a plurality of interconnects.

[0160] 14. The method according to embodiment 1, wherein the interface logic includes an external interface connected to an interconnect loopback.

[0161] 15. The method according to embodiment 1, wherein the interconnect loopback further includes a comparator configured to compare a test signal with a return signal to determine the integrity of the signal.

[0162] 16. The method according to embodiment 1, further comprising a delay circuit configured to introduce a controlled delay in the return signal in order to test the timing characteristics of a first interconnect among a plurality of interconnects.

[0163] 17. The method according to embodiment 1, further comprising dynamically adjusting a test signal based on a predetermined test pattern.

[0164] 18. The method according to aspect 1, further comprising: loading test data in series into a boundary canceller to generate a test signal on a first interconnect of a plurality of interconnects; sampling a return signal into a second boundary canceller; and shifting the return signal.

[0165] 19. The method according to embodiment 18, further comprising comparing a sampled return signal with an expected return signal.

[0166] 20. The method according to Embodiment 1, wherein the first interconnect of a plurality of interconnects is a read-address interconnect, the test signal is a read-address, and the return signal is a return read-address returned from the first interconnect of the plurality of interconnects via an interconnect loopback.

[0167] 21. The method according to embodiment 20, further comprising applying a return read address to the read data output bus of the interface logic of the first semiconductor device.

[0168] 22. The method according to embodiment 20, further comprising signaling a register clock signal to interface logic and buffering a return read address in a register.

[0169] 23. The method according to aspect 22, wherein the operation to test the return read address includes testing the output of a register.

[0170] 24. The method according to embodiment 20, wherein the interconnect loopback includes at least one buffer configured to selectively connect the interconnect loopback to a first interconnect among a plurality of interconnects.

[0171] 25. The method according to embodiment 1, wherein the first interconnect of the plurality of interconnects is a clock interconnect, the test signal is a clock signal, and the return signal is a return clock signal returned from the first interconnect of the plurality of interconnects via an interconnect loopback.

[0172] 26. The method according to embodiment 25, further comprising applying a return clock signal to the read data output bus of the interface logic of the first semiconductor device.

[0173] 27. The method according to embodiment 25, further comprising signaling a register clock signal to interface logic and buffering a return clock signal in a register.

[0174] 28. The method according to embodiment 27, further comprising testing the return clock signal in a register.

[0175] 29. The method according to embodiment 25, wherein the interconnect loopback includes at least one tristate buffer configured to selectively connect the interconnect loopback to a first interconnect among a plurality of interconnects.

[0176] 30. The method according to Embodiment 1, wherein the first interconnect of a plurality of interconnects is a read data interconnect, the test signal defines read test data, and the return signal is the return read test data returned from the first interconnect of the plurality of interconnects via the interconnect loopback.

[0177] 31. The method according to embodiment 30, further comprising applying read test data returned to the read data output bus of the interface logic of the first semiconductor device.

[0178] 32. The method according to embodiment 30, further comprising signaling a register clock signal to interface logic and buffering return read test data in a register.

[0179] 33. The method according to aspect 32, wherein the operation to test the return read test data includes testing the output of a register.

[0180] 34. The method according to embodiment 30, wherein the interconnect loopback includes at least one tristate buffer configured to selectively connect the interconnect loopback to a first interconnect among a plurality of interconnects.

[0181] 35. The method according to Embodiment 1, wherein the first interconnect of the plurality of interconnects is a write clock interconnect, the test signal defines the write clock signal, and the return signal is the write clock signal returned from the first interconnect of the plurality of interconnects via the interconnect loopback.

[0182] 36. The method according to embodiment 35, further comprising applying a write clock signal to the read data output bus of the interface logic of the first semiconductor device.

[0183] 37. The method according to embodiment 35, further comprising signaling a register clock signal to interface logic and buffering a write clock signal returned in a register.

[0184] 38. The method according to aspect 37, wherein the operation to test the returned write clock signal includes testing the output of a register.

[0185] 39. The method according to Embodiment 1, wherein the first interconnect of the plurality of interconnects is a write address interconnect, the test signal defines the write address, and the return signal is the write address returned from the first interconnect of the plurality of interconnects via the interconnect loopback.

[0186] 40. The method according to embodiment 39, further comprising applying a written address returned to the read data output bus of the interface logic of the first semiconductor device.

[0187] 41. The method according to aspect 39, further comprising signaling a register clock signal to interface logic and buffering the write address returned in a register.

[0188] 42. The method according to aspect 41, wherein the operation to test the returned write address includes testing the output of a register.

[0189] 43. The method according to Embodiment 1, wherein the first interconnect of the plurality of interconnects is a write data interconnect, the test signal specifies write test data, and the return signal is the write test data returned from the first interconnect of the plurality of interconnects via the interconnect loopback.

[0190] 44. The method according to embodiment 43, further comprising applying written test data returned to the read data output bus of the interface logic of the first semiconductor device.

[0191] 45. The method according to aspect 43, further comprising signaling a register clock signal to interface logic and buffering write test data returned in a register.

[0192] 46. ​​The method according to aspect 45, wherein the operation to test the returned write test data includes testing the output of a register.

[0193] 47. A stack system comprising a first semiconductor device, the first semiconductor device comprising: an interface logic having a plurality of interconnects electrically connected to the surface of the first semiconductor device; an interconnect loopback configured to receive the first interconnect from the plurality of interconnects and to communicate electrically back to the interface logic via the interconnect loopback; a test signal connection unit that communicates electrically with the first interconnect; and a return signal connection unit for testing a path from the test signal connection unit, through the first interconnect, back to the interface logic via the interconnect loopback, and to a return signal connection unit.

[0194] 48. The system according to embodiment 47, further comprising a second semiconductor device bonded to a first semiconductor device.

[0195] 49. The system according to embodiment 48, wherein the second semiconductor device includes a plurality of complementary interconnects joined to a plurality of interconnects of the first semiconductor device, and the first and second semiconductor devices are configured to provide a boundary scan chain for testing the electrical connections between the plurality of interconnects of the first semiconductor device and the plurality of complementary interconnects of the second semiconductor device.

[0196] 50. The system according to embodiment 48, further comprising complementary interface logic on a second semiconductor device, the complementary interface logic having a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device, and the plurality of interconnects of the first semiconductor device being connected to the plurality of complementary interconnects of the second semiconductor device.

[0197] 51. The system according to embodiment 50, wherein the interface logic and complementary interface logic are configured to provide boundary scans for testing connectivity between the interface logic and the complementary interface logic.

[0198] 52. The system according to embodiment 51, wherein the interface logic and complementary interface logic are connected together to form an integrated boundary scan in order to implement a boundary scan.

[0199] 53. The system according to embodiment 47, wherein the first semiconductor device further includes a buffer connected to a test signal from an interconnect loopback.

[0200] 54. The system according to embodiment 47, further comprising a tristate buffer configured to drive a test signal over an interconnect loopback, the first semiconductor device.

[0201] 55. The system according to embodiment 47, wherein the test signal connection section is electrically connected to the first interconnect.

[0202] 56. The system according to embodiment 47, wherein the test signal connection section is electrically connected to the interconnect loopback.

[0203] 57. The system according to embodiment 47, wherein the first interconnect is a conductive path configured to electrically connect a conductive junction on the surface of a first semiconductor device to an interface logic, and the interconnect loopback is a conductive path electrically connected to the interface logic and the conductive junction.

[0204] 58. The system according to embodiment 47, wherein the interface logic includes an external interface connected to a first interconnect.

[0205] 59. The system according to embodiment 47, wherein the interface logic includes an external interface connected to an interconnect loopback.

[0206] 60. The interconnect loopback system according to embodiment 47, comprising a comparator configured to compare a test signal with a return signal to determine the integrity of the signal.

[0207] 61. The system according to embodiment 47, wherein the interconnect loopback includes a delay circuit configured to introduce a controlled delay in the return signal in order to test the timing characteristics of the first interconnect.

[0208] 62. The system according to embodiment 47, wherein the test signal connection unit is configured to dynamically adjust the test signal based on a predetermined test pattern.

[0209] 63. The system according to embodiment 47, further comprising a boundary cancellation configured to generate a test signal on a first interconnect, and a second boundary cancellation configured to sample a return signal.

[0210] 64. The system according to embodiment 63, further comprising a comparator configured to compare a sampled return signal with an expected return signal.

[0211] 65. The system according to Embodiment 47, wherein the first interconnect is a read-address interconnect, the test signal connection is configured to receive a read-address, and the return signal is configured to be a read-address returned from the first interconnect via an interconnect loopback.

[0212] 66. The system according to embodiment 65, further comprising a read data output bus configured to receive a returned read address.

[0213] 67. The system according to embodiment 65, further comprising one register configured to buffer a read address returned in one register clock signal.

[0214] 68. The system according to embodiment 67, further comprising a comparator configured to test the returned read address output by a register.

[0215] 69. The system according to aspect 47, wherein the first interconnect is a clock interconnect, the test signal is a clock signal, and the return signal is a clock signal returned from the first interconnect via an interconnect loopback.

[0216] 70. The system according to embodiment 69, further comprising a read data output bus configured to receive a clock signal returned from the interface logic.

[0217] 71. The system according to embodiment 69, further comprising a register configured to buffer the returned clock signal upon receiving a register clock signal.

[0218] 72. The system according to embodiment 71, further comprising a comparator configured to compare a clock signal returned in a register with a predetermined value.

[0219] 73. The system according to aspect 47, wherein the first interconnect is a read data interconnect, the test signal connection is configured to receive read test data, and the return signal is read test data returned from the first interconnect via the interconnect loopback.

[0220] 74. The system according to embodiment 73, further comprising a read data output bus configured to receive returned read test data.

[0221] 75. The system according to embodiment 73, further comprising a register clock signal connection unit to interface logic, and a register configured to buffer returned read test data in a clock signal received via the register clock signal connection unit.

[0222] 76. The system according to embodiment 75, further comprising a comparator configured to test the returned read test data against a predetermined value.

[0223] 77. The system according to embodiment 73, further comprising at least one tristate buffer configured to selectively connect an interconnect loopback to a first interconnect among a plurality of interconnects.

[0224] 78. The system according to aspect 47, wherein the first interconnect is a write clock interconnect, the test signal is a write clock signal, and the return signal is a write clock signal returned from the first interconnect via an interconnect loopback.

[0225] 79. The system according to embodiment 78, further comprising a read data output bus configured to receive a write clock signal returned from the interface logic.

[0226] 80. The system according to embodiment 78, further comprising a register clock signal connector and a register configured to buffer a returned write clock signal in response to a register clock signal from the register clock signal connector.

[0227] 81. The system according to embodiment 80, further comprising a comparator configured to compare the returned write clock signal with a predetermined value.

[0228] 82. The system according to Embodiment 47, wherein the first interconnect is a write address interconnect, the test signal is a write address, and the return signal is a write address returned from the first interconnect via an interconnect loopback.

[0229] 83. The system according to embodiment 82, further comprising a read data output bus configured to receive a write address returned from interface logic.

[0230] 84. The system according to embodiment 82, further comprising a register clock signal connection unit and a register configured to buffer a write address returned based on a register clock signal received from the register clock signal connection unit.

[0231] 85. The system according to embodiment 84, further comprising a comparator configured to compare the output of a register with a predetermined value.

[0232] 86. The system according to aspect 47, wherein the first interconnect is a write data interconnect, the test signal contains write test data, and the return signal is the write test data returned from the first interconnect via the interconnect loopback.

[0233] 87. The system according to embodiment 86, further comprising a read data output bus configured to receive write test data returned from interface logic.

[0234] 88. The system according to embodiment 86, further comprising a register clock signal interface and a register configured to buffer returned write test data when a register clock signal is received via the register clock signal interface.

[0235] 89. The system according to embodiment 88, further comprising a comparator configured to compare the output of a register with a predetermined value.

[0236] 90. A manufacturing method comprising forming a first semiconductor device according to any one of embodiments 47 to 89.

[0237] 91. A method for forming a stack of semiconductor devices, the method comprising stacking a first semiconductor device according to any one of embodiments 47 to 89 on another semiconductor device.

[0238] 92. A method for forming a stack of semiconductor devices, the method comprising providing a first semiconductor device according to any one of embodiments 47 to 89, and joining another semiconductor device to the first semiconductor device.

[0239] 93. A method for using a semiconductor device, the method comprising providing a first semiconductor device according to any one of embodiments 47 to 89, and testing one of a plurality of interconnects.

[0240] 94. A method for designing a semiconductor device, the method comprising forming a digital representation of an interface logic in a first semiconductor device according to any one of embodiments 47 to 89.

[0241] 95. The method according to embodiment 94, further comprising forming a photomask of a digital representation.

[0242] 96. A system comprising a first semiconductor device according to any one of embodiments 47 to 89, having means for testing one interconnect among a plurality of interconnects.

Claims

1. A method for creating a known good stack, To form a first semiconductor device having an interface logic having a plurality of interconnects electrically connected to the surface of the first semiconductor device, Activating the interconnect loopback, which is configured to receive a first interconnect among multiple interconnects and to electrically return and communicate to the interface logic via the interconnect loopback, The test signal is electrically connected to the first interconnect among the plurality of interconnects, Test the return signal returned from the interconnect loopback, thereby testing the path from the first interconnect among the plurality of interconnects back to the interface logic via the interconnect loopback, Methods that include...

2. The method according to claim 1, wherein the interconnect loopback is activated by loading the test signal into a buffer.

3. The method according to claim 1, wherein the interconnect loopback is operated by operating a tristate buffer connected to either the interconnect loopback or the first interconnect among the plurality of interconnects.

4. The method according to claim 1, further comprising bonding the first semiconductor device to a second semiconductor device.

5. The method according to claim 4, further comprising using boundary scan to test the electrical connections between the plurality of interconnects of the first semiconductor device and the complementary plurality of interconnects of the second semiconductor device.

6. The complementary interface logic of the second semiconductor device is joined, having a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device. Connecting the plurality of interconnects of the first semiconductor device to the complementary plurality of interconnects of the second semiconductor device, The method according to claim 4, further comprising:

7. The method according to claim 6, further comprising performing a boundary scan to test the connectivity of the complementary interface logic to the interface logic.

8. The method according to claim 1, wherein the operation of electrically connecting the test signal to the first interconnect among the plurality of interconnects includes applying the test signal to the first interconnect among the plurality of interconnects.

9. The method according to claim 1, wherein the operation of electrically connecting the test signal to the first interconnect among the plurality of interconnects includes applying the test signal to the interconnect loopback.

10. At least one conductive junction is located on the surface of the first semiconductor device, The first interconnect among the plurality of interconnects is a conductive path configured to electrically connect the at least one conductive junction to the interface logic, The method according to claim 1, wherein the interconnect loopback is another conductive path configured to be electrically connected to the interface logic.

11. The method according to claim 1, further comprising buffering the test signal according to a clock.

12. The method according to claim 1, further comprising buffering the return signal in accordance with a clock.

13. The method according to claim 1, wherein the interface logic includes an external interface connected to the first interconnect among the plurality of interconnects.

14. The method according to claim 1, wherein the interface logic includes an external interface connected to the interconnect loopback.

15. The method according to claim 1, further comprising a comparator configured to compare the test signal with the return signal to determine the integrity of the signal.

16. It is a stack system, The first semiconductor device comprises a first semiconductor device, and the first semiconductor device is An interface logic having a plurality of interconnects electrically connected to the surface of the first semiconductor device, An interconnect loopback configured to receive a first interconnect from the plurality of interconnects and to electrically communicate back to the interface logic via the interconnect loopback, A test signal connection unit that electrically communicates with the first interconnect, A return signal connection unit for testing the path from the test signal connection unit, through the first interconnect, back to the interface logic via the interconnect loopback, and to the return signal connection unit, A system that includes this.

17. The stack system according to claim 16, further comprising a second semiconductor device bonded to the first semiconductor device.

18. The stack system according to claim 16, wherein the second semiconductor device comprises a plurality of complementary interconnects joined to the plurality of interconnects of the first semiconductor device, and the first and second semiconductor devices are configured to provide a boundary scan chain for testing the electrical connections between the plurality of interconnects of the first semiconductor device and the plurality of complementary interconnects of the second semiconductor device.

19. The stack system according to claim 16, further comprising complementary interface logic on the second semiconductor device, the complementary interface logic having a plurality of complementary interconnects electrically connected to the surface of the second semiconductor device, the plurality of interconnects of the first semiconductor device being connected to the plurality of complementary interconnects of the second semiconductor device.

20. The stack system according to claim 19, wherein the interface logic and the complementary interface logic are configured to provide a boundary scan to test connectivity between the interface logic and the complementary interface logic.

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