Apparatus and method for controlled waveform shaping

Abstract

In specific examples, methods and circuit-based devices involve selectively engaging (e.g., activating and / or deactivating) multiple resonant isolated DC-DC converter cells ("converter cells") using logic circuits. Selective engagement of each converter cell involves combining the output signals from the converter cells to generate an aggregated (e.g., high-voltage) output signal with a customized waveform shape based on the selective engagement. In more specific examples, due to the inherent fast response of the converter cells, nanosecond-level pulsing and customized high-voltage waveforms are achieved by controlling the precise on-or-off timing of the DC-DC converter cells on a nanosecond scale and the voltage of each converter cell.

Description

Background Art

[0001] Background Aspects of the present disclosure generally relate to the field of power conversion for supplying power to a load at a relatively high voltage. Examples of loads in such situations include many existing and new applications that operate based on a high-voltage power source where the input voltage therefrom is the same as or exceeds 1 kV (kilovolt). In many applications, a high-voltage power converter preferably supplies power in the range of tens of kV (e.g., 10 - 100 kV). Exemplary high-voltage applications in this context include, inter alia, medical, environmental, security, aerospace, and semiconductor industry applications.

[0002] Using plasma processing in the semiconductor manufacturing industry as one such technology type, it is understood that the advancement of this industry has led to a requirement to synthesize a specially adjusted voltage waveform that exhibits a customized (or any controllable) waveform shape, such as (a) very short rise and fall times (e.g., tens of ns), (b) very high peak voltages (e.g., tens of kV), (c) a voltage that rises or falls with a constant controllable slope. For example, in semiconductor manufacturing, such a unique voltage waveform enables direct control of the ion energy distribution function (IEDF) in the substrate during plasma processing. The goal of the pulse generator that generates these waveforms includes high efficiency for minimizing cooling requirements and electrical costs, as well as a compact form factor for reducing the storage requirements of power equipment. Meeting these stringent needs and goals often results in solutions that sacrifice one or more performance metrics, leading to large-sized systems, systems with high cooling requirements due to low efficiency, or both.

[0003] The above problems and other problems have presented challenges for power conversion for semiconductor plasma processing and various other applications.

Summary of the Invention

Means for Solving the Problems

[0004] Overview of various forms and examples The various examples / embodiments presented in this disclosure cover issues such as those addressed above and / or others that may become apparent from the following disclosures. For example, some of these disclosed embodiments cover methods and devices that use or leverage a stacked arrangement of resonant isolated DC-DC converter cells ("converter cells"), each having its own output terminal, to generate an aggregated output signal by having the output signals generated by each converter cell cooperate at the output terminals to combine and generate a customized waveform shape within the aggregated output signal with high precision (e.g., nanosecond timing) via control of the converter cells.

[0005] In certain specific examples, including methods and / or apparatus, aspects of the present disclosure include a plurality of resonant isolation converter cells and logic circuits for controlling the converter cells. Each converter cell may have a respective output terminal configured to cooperate in coupling the output signals each converter cell generates at the output terminal. A logic circuit (e.g., a programmable or fixed logic circuit such as a programmable logic device (PLD) or a microcomputer circuit) controls the converter cells by selectively engaging (e.g., activating and / or deactivating) each of the converter cells to generate output signals having customized waveform shapes based on such selective engagement.

[0006] In the relevant methods of the present disclosure, a specific implementation includes selectively engaging (including at least one of activated and deactivated) each of a plurality of resonant isolated DC-DC converter cells via a logic circuit, and combining the output signals from each output terminal of the converter cells to generate an output signal having a waveform shape customized based on the selective engagement.

[0007] More specific exemplary embodiments of the present disclosure can be constructed based on the exemplary methods and / or apparatus described above. In one such exemplary embodiment, a set of time-tuned gate drive signals is provided or generated to control the input ports of converter cells, which includes setting or adjusting the timing and signal level of each time-tuned gate drive signal for selective engagement to adjust each respective output voltage generated by each of the converter cells, and the step of coupling the output signals in response to selective engagement. Consistent with another such exemplary embodiment, the logic circuit performs activation and deactivation via input signals provided to the converter cells by controlled timing on the order of nanoseconds and each respective voltage of each of the converter cells, where changing the timing of the input signals causes one or more changes in waveform shape. Furthermore, in yet another exemplary embodiment, the waveform shape is controlled according to timing control (e.g., with an accuracy of nanoseconds or tens of nanoseconds) in which the activation of one or more converter cells is delayed to achieve a desired form of waveform shape.

[0008] In a specific alternative example that can be further constructed based on the embodiments described above, the method and apparatus are intended to control the generation of waveform shapes via selective activation and deactivation to realize a design specification that includes one or more combinations of (a) short and / or fall times of about nanoseconds, (b) high peak voltages of about kV, and (c) waveform shapes that are controllable by at least one of a voltage rise with a constant controllable gradient or a voltage fall with a constant controllable gradient.

[0009] Other exemplary embodiments may be constructed based on the embodiments described above. One such embodiment involves the activation and / or deactivation of a converter cell controlled by a logic circuit based on stored or configured information useful for realizing a desired pulse waveform shape and its characteristics, the stored or configured information provided by at least one of a storage setting, a configured logic circuit, and a feedback signal acquired or determined during the operation of the device. Another such embodiment involves the converter cell and the logic circuit cooperating and selectively engaging to generate a pulse waveform having a tuned bias voltage having a short positive pulse followed by a negative linear ramp. In specific examples, the tuned pulse voltage waveform is provided to a semiconductor processing load to bring a desired narrow ion energy distribution within a plasma chamber. In this context, the pulse voltage waveform is characterized, for example, by a maximum pulse voltage, rise and / or fall times, voltage and / or current ramps. According to exemplary embodiments of the present disclosure, a tuned pulsed voltage waveform is generated having a maximum pulsed voltage in the range of 10 kV to several kV, a rise time in the range of 10 nanoseconds (ns) to 100 ns, and a negative linear ramp lasting up to several microseconds (μsec).

[0010] Further exemplary embodiments that can be constructed based on the above embodiments include an isolation circuit comprising an inverter circuit and a transformer in one or more of the converter cells. The inverter circuit includes control gates from which each gate control signal is generated. The output of the inverter is connected to the primary side of the transformer. The secondary side of the transformer supplies power to the rectifier stage. The combination of the inverter stage, transformer stage and rectifier stage constitutes a single DC-DC converter cell. The logic circuit controls the generation of waveform signals for each of the converter cells by increasing or decreasing the frequency of the gate control signals or the pulse width of the gate control signals relative to the steady state, in order to drive the inverter circuit.

[0011] Other exemplary embodiments include mitigating or eliminating signal overshoot of the output signal at the output terminals of a converter cell. One or more converter cells include an inverter circuit having control gates for receiving their respective gate control signals, and the logic circuit generates the waveform shape by generating their respective gate control signals at an initial higher switching frequency for operating the converter cell (within the frequency used for steady-state operation) in order to mitigate or eliminate such signal overshoot in the output signal at the output terminals. In the relevant embodiments, mitigation or elimination of overshoot is achieved by starting the switching frequency of the inverter's gate signals at a relatively high frequency and then reducing this frequency to reduce the overshoot (without further adjustment of one or more switching frequencies used to operate the converter cell, if necessary). In certain relevant examples (alone or in combination with the relevant embodiments above), proper timing and / or sequencing of gate signals across different converter cells is also used to reduce overshoot of the combined output voltage signal (i.e., the output of the entire stack).

[0012] Another exemplary aspect of the present disclosure uses a stack of converter cells having multiple DC rails isolated from each other by one or more voltage isolation barriers to provide operating power at different voltage levels to each of the cells. Each cell has its own input port referencing a different voltage level.

[0013] Further specific examples of the above methods and devices include one or more of the converter cells comprising an inverting stage, an isolation stage, and a rectifier stage. The design selection of the inverting and rectifier stages involves the cell topology, the selection of active power devices with appropriate voltage and current ratings, and the tuning of component values. An exemplary circuit for the inverting stage may include a circuit having a resonant switch-mode push-pull topology that allows for adjustment of the output voltage by phase-shifting the configuration inverter.

[0014] In yet another specific example, the disclosure covers systems and methods for generating nanosecond-scale high-voltage pulses having customized (sometimes called optional) controlled waveform shapes, short rise and / or fall times, and potentially inherently small volume and mass. In relevant exemplary embodiments, a customized and controllable high output voltage is generated by stacking the outputs of a group of highly miniaturized, optimized, and isolated individual resonant DC-DC converter cells in series and connecting the resulting stacked output across a desired load. The output voltage can be implemented in various ways, such as the sum of the individual output voltages of each cell, or as a collection of specific (or all) individual output voltages of each cell, which can be derived for different purposes (e.g., to achieve capped voltage and / or current levels). The input to the DC-DC converter is a DC voltage rail which may be provided by a front-end AC / DC converter, another DC-DC converter, or some other DC voltage source.

[0015] In some exemplary system types, the disclosure relates to a system including a load having a plurality of converter cells (each, for example, each including an inverter stage, an isolation stage, and a rectifier stage, as illustrated herein) configured such that their respective outputs are coupled at output terminals, and a logic circuit controls the converter cells by selectively engaging each of the converter cells and generating output signals having waveform shapes customized to the load according to such selective engagement via control signals used to drive the FETs of the inverters of the cells.

[0016] In some examples, this disclosure covers apparatus and methods for controlling such systems (e.g., as described above) by implementing feedforward and / or feedback modes for controlling each output of a converter cell. The feedback mode may be implemented by monitoring the level at the output of the converter cell (e.g., via a controller and / or associated circuitry shown by the lower block in Figure 1) to precisely adjust the operation of the converter cell. For example, such a system may be used in feedforward mode to selectively engage the converter cell based on an operating zone in the current-voltage space, and the system then uses closed-loop feedback to adjust the frequency, duty cycle, and phase shift to reach a desired output voltage. As a more specific example of implementation, the feedforward mode and / or feedback mode can be implemented in various ways, including learning and / or predicting which parameters to set for the converter cells (and which or how many converter cells to engage) to ensure signal generation in the initial course mode and / or for subsequent fine-tuning, by combining a power-related parameter (e.g., voltage and / or current) measurement circuit that monitors the output and / or aggregated or combined output of the converter cells via the associated circuit in Figure 1 implemented as a threshold level comparator, with data pre-stored in a lookup table, or by evaluating current and / or past measurements by an algorithm execution data processing calculation circuit.

[0017] In some exemplary embodiments, multiple DC-DC converter stacks can be connected in parallel to provide a higher current level to the load. Each stack is optimized to supply a certain amount of current with high efficiency. For specific output current requirements, stacks can be added in parallel as needed to meet load requirements, with each stack supplying up to its rated current. In certain exemplary circuits according to this disclosure, the stacks are substantially identical and share substantially equal current among them to avoid loss of efficiency, overload, overheating, or all of the above.

[0018] In some embodiments, multiple DC-DC converter cells may be connected in series or parallel to achieve a fast transient response of the output waveform, and / or the DC-DC converter cells may be designed to have substantially identical characteristics, including output voltage / power, switching frequency, transient response, and voltage isolation requirements. In other embodiments, DC-DC converter cells may be designed to be different in the stack to have different output voltage / power, different switching frequencies, different transient responses, different voltage isolation requirements, etc. Also, due to the isolated nature of the DC-DC cells in the type of system shown in Figure 1, each cell may be connected to provide a voltage waveform that may be positive or negative relative to a reference node in the system. Note that at the bottom of Figure 1, arrows are shown pointing to a controller block to represent such logic circuits that retrieve data from external circuits as needed (e.g., a database stored in a memory circuit such as the lookup table disclosed above, and / or configuration parameters for executing the algorithm disclosed above). The arrows in Figure 1, as with other figures herein, are partially shown with dashed lines, which indicate that the embodiments shown are arbitrary in the non-limiting examples of the illustration.

[0019] The DC-DC converters in exemplary embodiments of this disclosure may be tuned to achieve soft switching (e.g., zero-voltage switching) of active power devices in order to minimize switching losses and maintain high efficiency. Resonant DC-DC converter cells can take advantage of high switching frequencies of power devices (in different examples, several MHz to tens of MHz, tens of MHz to hundreds of MHz, and below and above such ranges), and thus significantly reduce the size requirements of internal energy storage devices, including capacitors, inductors, and transformers. The switching frequency of the DC-DC converter may be further tuned to meet specific rise or fall time targets or to adjust the output voltage of the converter.

[0020] DC-DC converter cells can be designed to handle bidirectional energy flow so that the energy stored at the output can be reused and returned to the input when driving a capacitive load.

[0021] In some embodiments, the system output waveform may be configured as unipolar, and in other embodiments, the system output waveform may be configured as bipolar. When driving a capacitive load, a bipolar pulse centered at 0 requires half the energy compared to a unipolar pulse to achieve the same inter-peak voltage across the capacitive load.

[0022] In some embodiments, the DC rail providing input to the DC-DC converters may be a fixed DC voltage rail common to all converters. In other embodiments, the input voltage rail may be an adjustable DC voltage common to all converters. In other embodiments, the input voltage rail to each converter may be different from the input voltage rails of other converters, and may be fixed or adjustable.

[0023] In some embodiments, selective engagement of converter cells includes selectively activating, selectively deactivating, and / or selectively setting or adjusting the timing and tune of the converter cells by gate control signals that drive the inverter. By selectively activating and / or deactivating in this way, each DC-DC converter can be turned on or off as needed, which can be used as part of one exemplary technique for coarsely varying the output voltage level in discrete steps. For a given required output voltage, the more DC-DC cells stacked in series there are, the smaller the discrete steps can be, and the less precise the need for output voltage control becomes. The main advantage of on / off control in this context is the ability of the pulse generation system to step from low voltage levels (e.g., tens of volts) to much higher voltage levels (e.g., tens of kV) or vice versa, on a much faster time scale (e.g., tens of nanoseconds) than is possible with other techniques for output voltage control. Furthermore, the individual on and / or off (sometimes "on / off") control of each converter in a given group of series-stacked converters can also be timed so that one or more converters are delayed relative to others in order to achieve a desired output voltage waveform shape.

[0024] In certain cases, multiple DC-DC converter cells can be switched on or off in a controlled sequence while a control setpoint is changed to minimize overshoot or undershoot of the output waveform (the setpoint being the point at which an electrical circuit or cell is activated or deactivated). Such multiple DC-DC converter cells can also operate at synchronous switching frequencies but have different phases to achieve output ripple cancellation.

[0025] In some embodiments, the DC-DC converter cell can include a push-pull resonant power inverter stage, and the adjustment of the output voltage of one or more DC-DC converters can be achieved by phase-shifting two push-pull branches within the inverter stage. In a specific exemplary circuit according to the present disclosure, the range in which the phase shift is utilized is limited to provide only a small adjustment of the output voltage so as not to affect the DC-DC conversion efficiency.

[0026] In some embodiments, to further improve the transient response of the output waveform (e.g., rise time, fall time, etc.), additional switching stages such as a half-bridge, full-bridge, pull-down switch, or pull-up switch can be cascaded after the output of each individual DC-DC converter cell or a plurality of DC-DC converter cells.

[0027] Exemplary embodiments of the present disclosure can include a measurement and control module that is responsible for (a) relaying signals from various sensors within the system such as, by way of example, output voltage, output current, individual stack current, etc., (b) processing the received signals, and (c) providing appropriate commands to the DC-DC converters and output switching stages. The control module can also include information regarding the shape and its characteristics of the desired pulse waveform.

[0028] In some embodiments, a method for controlling the system includes receiving an output voltage and a corresponding output current setpoint, identifying an operating region or "zone" within the current-voltage space, and adjusting the DC-DC converter cell configuration according to a pre-assigned configuration for each region. Such a configuration can include several activated DC-DC cells connected in series, several activated cells connected in parallel, an operating frequency, an input voltage, a duty cycle, and / or a phase shift within an individual DC-DC cell. The pre-assigned configuration can be stored at an appropriate memory location within the system controller, such as using a look-up table or other means.

[0029] In some embodiments, the setpoint may be provided to the system controller via an analog voltage signal supplied to the system, or a digital signal represented by several bits may be transmitted to the controller via serial communication including RS232, RS485, parallel communication, Ethernet®, Universal Asynchronous Receiver-Transmitter (UART), or as a value encoded in the form of pulse width modulation.

[0030] In some embodiments, once the DC-DC cell configuration is determined based on the operating region in the current-voltage space, the system can transition to a closed-loop control mode, where the operating frequency, input voltage, or both are dynamically adjusted to achieve a desired output voltage or current.

[0031] In other embodiments, if the DC-DC cell configuration is determined based on the operating region in the current-voltage space, the operating frequency of the DC-DC cell may be determined by a simple or adaptive feedforward method in which the frequency is selected based on a pre-assigned frequency table. Such a table may include operating frequencies or input voltages at various combinations of desired output voltages and corresponding current setpoints.

[0032] In some embodiments, a single frequency table may be pre-assigned to all regions within the current-voltage space. In other embodiments, a unique pre-assigned frequency table may be used for each region within the current-voltage operating space. One or more frequency tables may be pre-entered during system characterization by manual entry, automated population by one or more scripts while the system is being trained at a target load, or by other means.

[0033] In other embodiments, a method for controlling the system includes receiving an output voltage and a corresponding output current setpoint; determining the number of stacks to be activated; dynamically increasing or decreasing the number of DC-DC cells connected in series so that the measured output voltage is within a threshold of a desired output voltage; and dynamically adjusting the operating frequency, duty cycle, and / or phase shift within the individual DC-DC cells.

[0034] In the embodiments described above and / or other embodiments, the system can operate to generate repetitive pulses. A method for controlling such a system may first include selecting a DC-DC cell configuration, including, among other things, the operating region, frequency, and duty cycle, for a given pulse, based on the last known configuration from a preceding pulse. The system can then transition to a closed-loop mode in which the operating frequency and region can be adjusted so that the output converges to a desired operating point.

[0035] In some embodiments, methods for controlling the rise time, fall time, overshoot, or combination thereof of the output waveform may include frequency ramping, thereby smoothly adjusting the operating frequency to achieve desired transient behavior. Furthermore, some embodiments may utilize frequency stepping, such as within a pulse, to smoothly adjust the output voltage level, and certain exemplary embodiments of this disclosure may be suitable for a variety of applications, including plasma processing in semiconductor manufacturing. For example, advanced plasma etching systems require a tuned bias voltage waveform having a short positive pulse followed by a negative linear ramp. This type of bias voltage waveform can provide a narrower ion energy distribution (so that it can be compared, for example, to a more conventional sinusoidal waveform), with a maximum pulse voltage reaching tens of kV, a rise time of less than 100 ns, and / or a negative linear ramp lasting several microseconds. Certain specific exemplary embodiments of this disclosure may also provide the ability to adjust voltage levels, pulse widths, and ramp times to accommodate a wide range of semiconductor etching recipes.

[0036] In yet another embodiment that can be used alone and / or in combination with the exemplary power converters of the above type, the Disclosure relates to a transformer core, the transformer core comprising a primary winding and one or more secondary windings shaped to mitigate or minimize eddy current losses, and a multilayer printed circuit board (PCB), the PCB comprising a plurality of layers for fixing traces for the primary winding and a plurality of layers for fixing traces for the secondary winding, and comprising vias through specific traces to minimize winding losses and facilitate thermal conductivity, the PCB, primary winding and secondary winding being vertically stacked in cooperation between a plurality of specific layers of the PCB to facilitate magnetic coupling between the primary and secondary windings.

[0037] The above description is not intended to describe every aspect, embodiment, or implementation of the present disclosure. It should be understood that such embodiments (and related aspects) can be combined unless otherwise specified. The following drawings and detailed description also illustrate the above and various other aspects and embodiments. [Brief explanation of the drawing]

[0038] Various exemplary embodiments, including experimental examples, can be better understood by considering the following detailed descriptions relating to the accompanying drawings of each invention.

[0039] [Figure 1] Figure 1 is a block diagram of a system according to an exemplary embodiment of the present disclosure that can generate nanosecond high-voltage pulses having a customized (arbitrary) waveform shape. The figure shows a power stage block comprising a DC-DC converter block forming a plurality of stacks, an optional switching stage cascaded with the DC-DC block, and a controller (and associated circuitry) block.

[0040] [Figure 2A]Figures 2A to 2D are schematic diagrams of exemplary implementations of a switching stage. Figure 2A is an exemplary implementation using a pull-up switch that may be used to achieve fast output voltage charging across the load.

[0041] [Figure 2B] Figure 2B shows an exemplary implementation of a switching stage using pull-down switches, which may be used to achieve high-speed output voltage discharge within a series stack and / or across a load.

[0042] [Figure 2C] Figure 2C shows an exemplary implementation of a switching stage using a half-bridge structure with both pull-up and pull-down switches, which can be used to achieve high-speed output voltage charging or discharging within a series stack and / or across a load.

[0043] [Figure 2D] Figure 2D shows an exemplary implementation of a switching stage using a full-bridge structure with pull-up and pull-down switches that can be used to achieve both high-speed output voltage charging or discharging, as well as voltage polarity within the series stack and / or across the load.

[0044] [Figure 3] Figure 3 is a flowchart illustrating one method of controlling the system to achieve a desired output voltage pulse waveform.

[0045] [Figure 4] Figure 4 shows a plot illustrating an example where the current-voltage space is divided into regions or zones.

[0046] [Figure 5] Figure 5 shows a plot of an example where the current-voltage space is divided into regions or zones that are not necessarily rectangular.

[0047] [Figure 6]Figure 6 is a flowchart illustrating how the system is controlled by activating DC-DC cells in feedforward mode based on operating zones in the current-voltage space and using closed-loop feedback to adjust frequency, duty cycle, and phase shift to reach the desired output voltage.

[0048] [Figure 7] Figure 7 is a flowchart showing how to control the system shown in Figure 1.

[0049] [Figure 8] Figure 8 is a flowchart illustrating another method of controlling the system in Figure 1 using feedback.

[0050] [Figure 9] Figure 9 is a flowchart illustrating a method for controlling the system when a desired pulse is repeated over time.

[0051] [Figure 10] Figure 10 shows a schematic diagram of an exemplary load having substantially capacitive components that can be driven using the type of system shown in Figure 1. This load is typically found in semiconductor processing bias power supply applications. The exemplary simulated system uses this load model in the exemplary plot of the presented voltage waveforms.

[0052] [Figure 11] Figure 11 is a plot of the system's exemplary output voltage as a function of time, illustrating an example of the system's ability to generate high-voltage pulse waveforms with nanosecond rise and fall times and adjustable pulse width.

[0053] [Figure 12]Figure 12 is a plot of the system's exemplary output voltage as a function of time, which illustrates an example of the system's ability to generate high-voltage pulse waveforms with nanosecond rise and fall times and an adjustable slope during the fall time, as is commonly required in several semiconductor processing applications.

[0054] [Figure 13A] Figures 13A to 13C show scope shots illustrating the possibility of adjusting the rise or fall time gradient between consecutive pulses by timing the turn-on and turn-off of cells in a predetermined sequence. [Figure 13B] Figures 13A to 13C show scope shots illustrating the possibility of adjusting the rise or fall time gradient between consecutive pulses by timing the turn-on and turn-off of cells in a predetermined sequence. [Figure 13C] Figures 13A to 13C show scope shots illustrating the possibility of adjusting the rise or fall time gradient between consecutive pulses by timing the turn-on and turn-off of cells in a predetermined sequence.

[0055] [Figure 14A] Figures 14A and 14B show scope shots demonstrating the adjustability of pulse peak voltage levels by timing the cell turn-on and turn-off in a predetermined sequence to obtain a customized voltage waveform. [Figure 14B] Figures 14A and 14B show scope shots demonstrating the adjustability of pulse peak voltage levels by timing the cell turn-on and turn-off in a predetermined sequence to obtain a customized voltage waveform.

[0056] [Figure 15]Figure 15 is a plot of the system's exemplary output voltage as a function of time, illustrating an example of the system's ability to generate high-voltage pulse waveforms with nanosecond rise and fall times, as well as tunable inflection points (starting points for controlled slope duration of the waveform), as is commonly required in several semiconductor processing applications.

[0057] [Figure 16] Figure 16 is a plot of various exemplary output voltages of the system as a function of time, which demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series stacks in parallel) on the overall waveform shape of an exemplary pulse. In this example, 16 cells were stacked in series, and some of these stacks were placed in parallel to obtain the desired total number of cells.

[0058] [Figure 17] Figure 17 is a plot of various exemplary output voltages of the system as a function of time, which demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series stacks in parallel) on the achievable rise time of an exemplary pulse. The plot is zoomed in near the rise edge for further clarity. In this example, 16 cells were stacked in series, and some of these stacks were placed in parallel to obtain the desired total number of cells.

[0059] [Figure 18] Figure 18 is a plot of various exemplary output voltages of the system as a function of time, which demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series stacks in parallel) on the achievable fall time of an exemplary pulse. The plot is zoomed in near the fall edge for further clarity. In this example, 16 cells were stacked in series, and some of these stacks were placed in parallel to obtain the desired total number of cells.

[0060] [Figure 19] Figure 19 plots the rise time, fall time, and estimated bill of materials (BOM) cost of the power stage as a function of the total number of DC-DC converter cells used. In this example, 16 cells were stacked in series, and some of these stacks were placed in parallel to obtain the total number of cells shown on the x-axis.

[0061] [Figure 20] Figures 20A and 20B show scope shots illustrating exemplary pulse fall time adjustment by sloping the operating frequency.

[0062] [Figure 21] Figure 21 shows a scope shot illustrating the use of frequency stepping for smooth voltage level adjustment within a pulse.

[0063] [Figure 22A] Figures 22A and 22B show scope shots illustrating the use of in-pulse frequency adjustment to compensate for input voltage rail fluctuation effects using feedforward. [Figure 22B] Figures 22A and 22B show scope shots illustrating the use of in-pulse frequency adjustment to compensate for input voltage rail fluctuation effects using feedforward.

[0064] [Figure 23] Figure 23 is a schematic diagram of one of many methods for implementing a converter cell, in which a control block drives the converter cell by engaging with an inverter using gate control signals.

[0065] [Figure 24] Figure 24 shows a control block (e.g., a logic circuit) that sends control signals to selectively engage with specific cells within and between stacked arrangements of converter cells in order to control output overshoot in the output signals of the converter cells.

[0066] [Figure 25A] Figures 25A, 25B, and 25C show alternative block diagrams of each method for supplying power to a stacked arrangement of converter cells, where Figure 25A has input signals to converter cells that refer to a single pair of power rails in common, and Figures 25B and 25C have different configurations, each having input signals to specific converter cells that refer to different sets of power rails. [Figure 25B] Figures 25A, 25B, and 25C show alternative block diagrams of each method for supplying power to a stacked arrangement of converter cells, where Figure 25A has input signals to converter cells that refer to a single pair of power rails in common, and Figures 25B and 25C have different configurations, each having input signals to specific converter cells that refer to different sets of power rails. [Figure 25C] Figures 25A, 25B, and 25C show alternative block diagrams of each method for supplying power to a stacked arrangement of converter cells, where Figure 25A has input signals to converter cells that refer to a single pair of power rails in common, and Figures 25B and 25C have different configurations, each having input signals to specific converter cells that refer to different sets of power rails.

[0067] [Figure 26A] Figures 26A and 26B show cross-sectional views of corresponding planar transformers, both applicable to one or more transformer-based implementations of the converter cell shown in Figure 1. Figure 26A shows vias distributed across the planar winding on different layers (e.g., to improve thermal issues), while Figure 26B shows a typical planar winding. [Figure 26B] Figures 26A and 26B show cross-sectional views of corresponding planar transformers, both applicable to one or more transformer-based implementations of the converter cell shown in Figure 1. Figure 26A shows vias distributed across the planar winding on different layers (e.g., to improve thermal issues), while Figure 26B shows a typical planar winding.

[0068] [Figure 27] Figure 27 is an exploded view of a PCB planar transformer that can be used with one or more of the converter cells shown in the system of Figure 1. [Modes for carrying out the invention]

[0069] The various embodiments described herein are suitable for modifications and alternative forms, which are shown as examples in the drawings and described in detail. However, it should be understood that the intent is not to limit this disclosure to the specific embodiments described. Rather, the intent is to cover all modifications, equivalents, and alternative forms that fall within the scope of this disclosure, including the forms defined in the claims. Furthermore, the term “example” as used throughout this application is illustrative and not limiting.

[0070] Detailed explanation Aspects of this disclosure are considered applicable to a wide variety of different types of apparatus, systems, and methods, including devices that are at least partially characterized by generating nanosecond-scale high-voltage pulses having customized waveform shapes (e.g., closely including one or more peaks and / or short rise and fall times). Aspects of this disclosure have proven particularly useful for powering equipment used in plasma processing in the semiconductor manufacturing industry. While this disclosure is not necessarily limited to such aspects and / or specifically to the field of plasma processing, understanding the specific examples in the following description can be inferred from discussions in such specific contexts.

[0071] Accordingly, the following description includes various specific details to illustrate the specific examples presented herein. However, it should be apparent to those skilled in the art that one or more other examples and / or variations thereof may be carried out without all the specific details given below. In other examples, well-known features are not described in detail so as not to obscure the description of the examples herein. For the sake of clarity, the same meaning and / or reference number may be used in different figures to refer to the same element or additional instances of the same element. Also, while aspects and features may be shown in individual figures in some cases, it will be understood that features from one figure or embodiment can be combined with features from another figure or embodiment, even if the combination is not explicitly shown or described as such.

[0072] Illustrative embodiments of this disclosure relate to power supplies and / or power conversion methods and circuit-based devices, including the use of logic circuits for selectively engaging (e.g., activating and / or deactivating) a plurality of resonant isolated DC-DC converter cells. The selective engagement of each converter cell involves combining the output signals from the converter cells to generate an aggregated (e.g., high-voltage) output signal having a waveform shape customized based on the selective engagement. In more specific examples, the inherent fast response of the converter cells allows for nanosecond-level pulsing and customized high-voltage waveform formation by controlling the on or off timing of the DC-DC converter cells and the voltage of each converter cell. In certain specific exemplary embodiments, the selective engagement includes operating at least a subset of the converter cells over a frequency set of one or more sufficiently high switching frequencies in the high frequency range (e.g., about 1 MHz to 100 MHz) for at least several cycles of the frequency set to manipulate the waveform shape of a fractional portion of the output signal at the output terminals of the converter cells (e.g., individual portions corresponding to a small proportion of the entire cycle, such as significantly less than a quarter or an eighth).

[0073] In accordance with the embodiments described above, such manufactured devices or methods of such manufacture may include embodiments presented and claimed in U.S. Provisional Patent Application No. 63 / 518,883, filed on 11 August 2023, to which priority is claimed. To the extent permitted, such subject matter is incorporated by reference in general, and in its entirety, to the extent that further embodiments and examples (such as experimental and / or more detailed embodiments) may be useful for supplementation and / or clarification.

[0074] To a more specific example, this disclosure covers methods and, alternatively, devices, including the ability to generate precisely controlled pulsed voltage waveforms with unique and challenging characteristics, such as in modern industrial applications where this is increasingly necessary. These characteristics include waveforms of pulse characteristics, including rise and fall times on a nanosecond timescale, with the ability to control high voltages of tens of kilovolts, as well as other voltage waveform features such as gradient, pulse width, and pulse repetition rate. Embodiments described herein provide customized waveform high-voltage pulse generation systems that meet such requirements in a variety of applications, including plasma processing in semiconductor manufacturing.

[0075] In such plasma processing applications, plasma etching, for example, offers the advantages of anisotropic etching through energy ion bombardment of the substrate, which is useful for etching small, high-aspect-ratio features in wafer processing. Many plasma etching systems use a sinusoidal bias voltage supply to control the ion energy. Due to the time-varying nature of sinusoidal waveforms, the ion flux impacting the wafer substrate typically has a bimodal, broad ion energy distribution function (IEDF). This is not ideal when smaller, higher-aspect-ratio etching features are required for state-of-the-art semiconductor technologies that require a very narrow IEDF. A tuned bias voltage waveform with a short positive pulse followed by a negative linear ramp can provide a narrower ion energy distribution compared to a conventional sinusoidal waveform. Depending on the specific type of plasma etching application, the optimal maximum pulse voltage may be over 10kV with a rise time of less than 100 nanoseconds and a negative linear ramp lasting several microseconds. It is also desirable that the plasma etching tool has the ability to adjust the voltage level, pulse width, and negative ramp time to accommodate a wide range of etching recipes. For these reasons, having a pulse generation system with such capabilities allows for precise control over the shape of the IED on the substrate surface, thereby enabling precise control over features on that substrate.

[0076] Figure 1 is a block diagram of a type of system for generating high-voltage nanosecond pulses and customized waveforms, comprising two stages, namely a power stage and a controller stage (and possibly a controller and measurement stage), according to an example of the present disclosure. Another important aspect of the operation of the pulse generator system according to the present disclosure is (a) the ability to generate the required high voltage, (b) the ability to rapidly adjust the output voltage level from very low / high voltage to very high / low voltage, and (c) the ability to precisely correct the output voltage level over time according to a ramp waveform, sawtooth waveform, triangle waveform, and / or other predetermined pattern.

[0077] As shown in Figure 1, the power stage comprises a modular array of isolated DC-DC converters. These converters in the array are supplied from a DC voltage source (e.g., a front-end AC / DC converter, another DC-DC converter, or another power supply) and function as power building blocks to achieve desired output voltages and currents in a specific application. Similarly, in the specific exemplary circuits of this disclosure, the converters may be identical in terms of components and architecture, or the converters may be designed to differ (within the array) in respect to these, for example, having different output voltages / powers, different switching frequencies, different transient responses, and / or different isolation requirements. Multiple converters may be stacked in series to achieve a higher desired output voltage or to speed up the transient response of the output waveform. Each converter has an output voltage V cell and output current I cell Optimized to generate, and therefore when M of these converters are connected in series, the resulting voltage generated across the series stack is MV cell Similarly, multiple stacks can be connected in parallel to provide a desired output current higher than the rated current of each individual converter stack. Specifically, if N converter stacks are connected in parallel, the resulting current supplied to the load will be NI cell Therefore, in this way, a suitable combination of M × N converters can be selected to satisfy the target load voltage, current, or rise time. In certain exemplary circuits of this disclosure, the stacks are designed to share current equally among them as feasible (and may be substantially identical if necessary). In certain other exemplary circuits of this disclosure, the stacks are not substantially identical, and the system still functions correctly, but it may be useful to mitigate thermal issues (e.g., conventional cooling mechanisms such as vias in traces, vias in PCBs, heat sinks, and / or fans). Such thermal issues arise because a stack conducting a higher current than other stacks can become overloaded, potentially leading to reduced efficiency, overheating, or both.

[0078] In certain examples, a controller block (including, for example, associated circuits such as measuring circuits, sensors, comparators, and / or CPU-based circuits as needed, as shown at the bottom of Figure 1) is used to selectively engage (e.g., activate) DC-DC cells and couple the cell outputs in series. This series arrangement is not necessarily limited but can accommodate series stacks of specific converter cells, such as series stacks with a wide range of converter cells, including 2-3 converter cells at the bottom and up to 30 or more converter cells at the top.

[0079] In relation to the appropriate selection of M and N, the design selection of individual DC-DC converter cells is of equal importance. Each cell includes an inverting stage, an isolation stage, and a rectifier stage. The design selection of the inverting and rectifier stages includes the cell topology, the selection of active power devices with appropriate voltage and current ratings, and the tuning of component values. Exemplary circuits for the inverting stage may include resonant switch-mode push-pull topologies that allow for adjustment of the output voltage by phase-shifting the constituent inverter. These may include, among other things, push-pull variations of resonant class D, class E, class F, or Φ2 topologies. In certain applications, switch-mode designs that utilize zero-voltage switching (ZVS) of the active device may be used for optimal efficiency and to mitigate losses. Furthermore, in certain designs, high switching frequencies (e.g., several MHz to tens of MHz, or several MHz to hundreds of MHz or more) are used to minimize energy storage, volume, and weight requirements. Non-push-pull switch-mode resonant variations can also be used when inverter phase shifting within the DC-DC converter cell is not required for output voltage control. For rectification, a similar resonant topology can be used, and the rectifying components may consist of semiconductor switches or diodes.

[0080] Power stage isolation between the inverter stage and the rectifier stage can be achieved using a separate standalone transformer with appropriate voltage standoff ratings across the primary and secondary windings. In other exemplary implementations, the primary and secondary windings of the transformer are integrated into the inverter and rectifier stages, respectively. Appropriate voltage isolation between the windings can be provided by controlling the spacing between the primary and secondary windings, by introducing one or more high-voltage standoff materials (e.g., polyimide film, coating, etc.) between the windings, or both. As one of many examples in this context, one can refer to U.S. Patent No. 11,228,252, which discloses a planar PCB transformer as an isolation stage between an inverter circuit and a DC-DC rectifier circuit, and Figures 1, 2A, 2B, and 4A–4C illustrate planar PCB transformers providing inductive isolation to each of several multilayer DC-DC converters.

[0081] The inverter and rectifier stages may be designed to allow bidirectional energy flow to and from the load. This can be useful in cases such as when the load consists of an energy storage element (for example, when it is substantially a capacitive load). The power stage can return the stored energy to the input by receiving appropriate control signals to reverse the energy flow. For example, in applications requiring repeated charging and discharging of a capacitive load, the energy returned to the input prevents energy from being lost and dissipated as heat, thereby improving system efficiency and reducing the need for additional thermal management.

[0082] The power stage may also include additional switching stages (e.g., half-bridge, full-bridge, pull-down switches, pull-up switches, etc.) connected across the outputs of each DC-DC converter, as needed, as shown in Figure 1, each of these switches rated up to the maximum expected voltage at the converter output. Alternatively or additionally, specific exemplary embodiments of the present disclosure have one or more switching stages connected across the outputs of multiple DC-DC converter cells or systems (i.e., across the load), each of these switches rated up to the maximum expected voltage depending on the node. In these and other embodiments disclosed herein, additional switching stages may be incorporated to further improve the rise and / or fall times of the output waveform. Figures 2A–2D show schematic diagrams of exemplary embodiments of such switching stages, including voltage pull-up using a series semiconductor switch (Figure 2A), voltage pull-down using a shunt semiconductor switch (Figure 2B), both pull-up and pull-down using a half-bridge configuration of the switch (Figure 2C), and all of the above having the ability to swap the output voltage polarity using a full-bridge configuration (Figure 2D). As one of many examples of switching stages / power supplies in this context, one can refer to U.S. Patent No. 11,978,611 (for example, a switching-mode power supply with a controller that generates drive control signals for engaging with high-power (FET) switching components, as described throughout and disclosed with Figure 2). It should be understood that these are merely exemplary embodiments of switching stages and should not be considered limiting. Thus, those skilled in the art will understand that other implementation forms are possible, among other possibilities, such as using multiple switches instead of a single switch.

[0083] Due to the isolated nature of the DC-DC cells in the type of system shown in Figure 1, the system can be configured to provide an output voltage waveform that can be positive or negative relative to a reference node in the system. Therefore, the system can also be configured to provide an output voltage waveform that can be unipolar or bipolar. It should be noted that when the system is driving a capacitive load, a bipolar pulse centered at zero requires half the energy compared to a unipolar pulse to achieve the same pulse voltage differentially across the capacitor.

[0084] A controller block, as shown at the bottom of Figure 1, is typically required to achieve the system's control objectives and to ensure the accurate and safe operation of all system components, including the power stage. Specifically, this stage acquires various measurements from the power stage as needed, processes these measurements, and provides the power stage with the necessary control signals to achieve the desired output waveform shape and voltage level.

[0085] This stage may include measured and controlled signals present on both sides of the isolation barrier of the power stage. Various methods can be used for these signals to cross the isolation barrier. These include, but are not limited to, the use of galvanic isolation, capacitive isolation, or optical isolation, such as transformers. Such methods are applicable to both analog and digital measured and controlled signals.

[0086] Various control methods may be suitable for the type of high-voltage customized pulse generation system disclosed in Figure 1. In various examples, multiple means of voltage, current, and / or power control are implemented as needed. Rapid changes in voltage, power, and / or current are possible by enabling and disabling the inverter stages of individual DC-DC converter cells. By configuring the system with many series / parallel strings of cells, relatively precise control of the output is possible while allowing each cell to operate near its optimal conversion efficiency. Enabling and disabling DC-DC cells (sequentially and / or selectively) in this manner may be beneficial when relying on a variable input DC bus voltage where the control bandwidth and / or transient response may be limited.

[0087] Due to the resonant characteristics of DC-DC cells, frequency can be used as a way to control the system's output. Voltage, current, and power can be tuned by changing the basic DC-DC conversion frequency. Frequency can also be tuned to optimize the transient response and achieve the desired waveform when moving from one operating point to another. Frequency can be tuned to optimize conversion efficiency or to minimize losses in various components within the power stage.

[0088] In inverters using a complementary "push-pull" design, the phase shift of the gate signals of a single cell, which typically operate with a relative phase of 180 degrees, can control the amplitude of the voltage signal driving the cell's rectifier. Thus, this phase control can make it possible to adjust the voltage, current, and / or power contributions of individual inverters. In certain examples, also according to this disclosure, the range over which the gate signal phase shift is utilized is limited to provide only small adjustments to the output voltage (e.g., less than P%, where P is greater than 0 and less than 5, 10, or 15) so as not to adversely affect the DC-DC conversion efficiency. The phase of each DC-DC cell can also be adjusted relative to each other to reduce or substantially cancel out the voltage and / or current ripple experienced by the load, and / or to enable reduced output filtering and a better dynamic response.

[0089] The inverter's gating duty cycle can be used to optimize cell conversion efficiency. Dynamic adjustments during changes in the operating point can be used to adjust the transient response.

[0090] The input DC voltage to the resonant DC-DC converter cell can be adjusted to control the unit's output voltage to achieve a specific voltage target or to optimize the performance of a specific operating point. While a single variable DC bus is possible to power all DC-DC converter cells, subgroups of cells, such as series and / or parallel strings, and even individual DC-DC cells, may have their own variable DC voltage rails to add adjustability and flexibility to the system. An example of this technique is disclosed in relation to Figures 25B and 25C.

[0091] Feedback can be based on measured voltage, current, and power, as well as the derivatives of these signals and the calculated load impedance. Where a repeating or pulsed output signal is required, the system can "learn" from the previous pulse and adjust the next pulse by measuring and analyzing telemetry data at discrete time intervals within the pulse. Thus, control parameters can be adjusted not simply as a result of pure feedback, but by defining the trajectory in an adaptive feedforward manner. The power supply can store these control parameters in system memory as needed. Various sets of control parameters can be acquired by training the system over a series of loads and stored in appropriate memory within the system, such as a lookup table (LUT) or other means. Similarly, such sets of control parameters may be transferred to system memory from an external device (e.g., a computer) based on prior knowledge and characteristics of the system. Figure 3 shows a flowchart of the exemplary control strategy described above for achieving a desired output waveform.

[0092] In many examples of this disclosure, the operating output voltage-current space can be divided into regions or zones (e.g., as shown in Figures 4 and 5), and different sets of control parameters, such as the number of DC-DC cells to be activated in series or parallel, can be pre-assigned to each region. In certain exemplary embodiments of this disclosure, the operating current-voltage space is divided into rectangular regions. Such division can, for example, allow for a simple selection of the number of DC-DC cells to be activated in series or parallel, and more cells can be activated in series if more voltage is desired for the same output current, as shown in Table 1 below, and more cells can be activated in parallel if more current is desired for the same output voltage. [Table 1]

[0093] Figure 4 shows that such regions are rectangular, but in other cases they do not necessarily have to be rectangular. For example, it may be desirable to assign activation to series or parallel DC-DC cells based on output voltage, current, power, efficiency, losses, or any combination thereof, resulting in many possible shapes of regions, including irregular shapes. One example is shown in Figure 5, which shows a combination of rectangular and non-rectangular regions (at low voltage / current). In these examples, each region corresponds to the assignment of activated series or parallel cells, but may also correspond to the selection of other control parameters, including operating frequency, duty cycle, input voltage, or phase shift within the DC-DC cells.

[0094] By utilizing these domains, various exemplary methods for controlling the system are given. Figure 6 shows a flowchart illustrating one such method. The first step involves the controller receiving a desired output voltage setpoint and a desired output current setpoint (these may be derived, for example, from desired output voltage and load impedance values). Based on these desired setpoints, the system then determines the operating domain and acquires a pre-allocated number of series and parallel enabled DC-DC cells (for example, stored in system memory) in feedforward mode. The system then enables these cells at an initial operating frequency which can be predefined specifically for each domain or identically for all domains. The system can then enter a closed-loop mode in which one or more of the cell switching frequency, duty cycle, or phase shift are dynamically adjusted so that the output voltage converges to the desired setpoint. For example, in many applications of this disclosure, it has been found that in certain examples, the output voltage can be converged to the desired setpoint by entering a closed-loop mode in relation to dynamically adjusting the cell switching frequency.

[0095] Figure 7 shows another exemplary method of the system in Figure 1 in which a parallel stack can be configured based on a corresponding output current setpoint. The method in Figure 7 uses coarse closed-loop voltage feedback to set the number of cells to be activated in series, and another closed-loop feedback for precise control of specific output signal parameters. The coarse closed-loop voltage feedback is performed first, and the selective engagement of the cells involves discrete activation and deactivation of DC-DC cells to coarsely achieve an output voltage within a predetermined threshold δ from a given desired output voltage setpoint. Once that is achieved, the system enters closed-loop mode, and the system can control certain signal parameters such as frequency, duty cycle, and / or phase shift (e.g., by adjustment and / or resetting) to achieve relatively precise output voltage control compared to the threshold δ.

[0096] Another example of a control method applicable to the system in Figure 1 is shown in Figure 8, which involves input voltage fluctuation and feedback control. More specifically, Figure 8 shows a block diagram illustrating how such a system can be controlled by using coarse closed-loop voltage feedback for selective engagement to set the number of cells to be activated in series, and another closed-loop feedback for precise control by adjusting the DC voltage rail at the cell inputs. In other words, in addition to the closed-loop mode for coarse control by enabling / disabling cells, precise control adjustment can be achieved by adjusting the input DC voltage to the converter cells. Depending on the rate at which the input voltage can be changed, this technique in Figure 8 may be beneficial when output voltage convergence to a desired setpoint can occur on a slower time scale than is possible with closed-loop based on the cell switching frequency, such as within a few pulse cycles.

[0097] In many cases, it may be necessary to generate a pulsed voltage waveform that repeats over time at a certain repetition rate. Some applications may require a narrow pulse width (e.g., a few microseconds or tens of microseconds), which makes it difficult to achieve stabilization to a desired voltage setpoint in the first pulse. In such cases, a control method more suitable for pulsed applications can be utilized that allows the system to "learn" from previous pulses, and thus allows the system to reuse the system configuration from previous pulses. The system can then start from those system parameters and then adjust the cell parameters, such as the cell switching frequency (or duty cycle, or phase shift, or a combination thereof), until the desired output voltage is reached or the cell parameters exceed a predetermined boundary. In this case, the system can adjust the number of cells to be activated and repeat the adjustment of the cell parameters. This process can be repeated until the desired output voltage is achieved. Figure 9 shows an example of one such control method, where, at the start of a new pulse, the controller retrieves the desired voltage and corresponding current setpoint at the end of the last pulse, and other system configuration parameters (for powering the load), from a memory database (e.g., in the controller in Figure 1). In various exemplary embodiments, this data acquisition may include specified (or some) of the activated series and parallel DC-DC cells, operating frequency, duty cycle, phase shift, and / or other control parameters as needed (exemplary such control parameters are disclosed throughout this disclosure).

[0098] It should be understood that the disclosed subject matter is not limited in its application to implementation details and the arrangement of components described in the description or shown in the drawings. Other embodiments of the disclosed subject matter are possible and can be implemented and carried out in various ways.

[0099] To demonstrate the usefulness of the type of system shown in Figure 1, an exemplary system is designed and simulated for a typical semiconductor processing bias load model. An example of such a circuit model commonly used in semiconductor bias applications is shown in Figure 10. The components can take on a wide range of values, and Table 2 below shows the selected component values ​​for the load circuit model in the simulation described later. The experimental examples in this disclosure demonstrate how the system can be used to synthesize a desired bias voltage waveform with adjustable waveform parameters including on-time, fall slope, and inflection point. Such examples also show how the rise and fall times change as the total number of DC-DC converter cells in the system scales. [Table 2]

[0100] Referring to Table 2, "j" refers to the number of 16-cell stacks connected in parallel. For example, to achieve a total of 128 cells in the system, 8 of the 16-cell stacks are connected in parallel, so the value of j is assigned to 8, and so on.

[0101] According to various examples of this disclosure, the output waveform can be adjusted by a controller (also known as a logic circuit), for example, as described above. Figure 11 shows an example of an output voltage waveform with different pulse widths (i.e., on-times). The pulse on-time is arbitrarily adjustable. In this example, the pulse width was adjusted by adjusting the timing and number of activated DC-DC cells.

[0102] Figure 12 shows an example of an output voltage waveform with different falling slopes between portions of the waveform after a predetermined on-time has ended. The controllability of the rising or falling slope of the voltage between such portions of the waveform is highly desirable in several applications, such as some semiconductor manufacturing processes. In the system disclosed herein, the slope can be adjusted in real time by controlling the output voltage to track a series of control setpoints. As previously mentioned, multiple control means can be used to achieve this, and in this simulation example, the system was simulated in an open-loop configuration, and waveforms with different slopes were generated by controlling the number of enabled DC-DC cells over time.

[0103] Figure 15 shows another simulated demonstration example where the output voltage waveform exhibits different inflection points, which are the moments that indicate the start of the controlled slope portion of the waveform described above. The inflection points can be adjusted by controlling the output voltage during the fall time. In this figure, inflection point 1 appears as a wave-like plot that begins just before 0.5 μs (microseconds) before it merges with the delayed inflection point (inflection point 2).

[0104] From these demonstrations (particularly Figure 15 disclosed herein), it can be concluded that the system can indeed adjust specific aspects of the waveform shape and adapt the output voltage on a timescale of tens of nanoseconds.

[0105] Another important aspect of the specific examples of this disclosure is scalability to a larger number of stacked converters. As disclosed herein, exemplary stacked converter configurations can vary widely depending on the scalability of the architecture. In the experimental efforts leading to this disclosure, modifications of the simulation examples demonstrate the trade-offs in scaling to a larger total number of converters while using the same DC-DC cell design. The exemplary systems herein include examples based on successful experimental and / or proof-of-concept efforts (simulations and / or prototype embodiments) supporting this disclosure, used over a relatively large range of total DC-DC cell numbers (e.g., 360 total cells, or around 100 or several hundred cells, such as 128 to 1024 total cells in some specific examples), with pulse rise times measured (5% to 95% and 10% to 90%) and fall times measured (in the range of 5% to 95%). Figure 16 shows the overall shape of the voltage waveforms for a selected number of DC-DC cells. Note that the plotted lines on the right side of Figure 16 are drawn from top to bottom, in the same order as the legend. It can be seen that the more cells there are, the shorter the rise and fall times generally become. Figure 17 shows a magnified view near the pulse rise edge. Note that the vertical plot lines in Figure 17 are drawn in the same order as in the legend when viewed from right to left. Figure 18 shows a magnified view near the pulse fall edge. Note that the plot lines on the right side of Figure 18 are drawn from top to bottom in the same order as in the legend. In all the examples above, 16 DC-DC cells were stacked in series, and some of these stacks were arranged side by side to achieve the total number of cells shown. The extent to which more cells in the system affect the rise and fall times of a given output voltage pulse depends on the exact implementation of the system, including the switching stage shown in Figure 1.

[0106] The cost estimate for the bill of materials (BOM) can also be calculated for each choice of number of DC-DC cells. In one example of such estimation, the results shown in Figure 19 show that the cost of the BOM increases linearly as the total number of converters in the system increases. The results also show a significant decrease in the rise and fall times of the output voltage pulses as the number of cells increases to approximately 384. However, beyond that number, the effect diminishes as the BOM cost increases rapidly and the rise or fall times do not decrease significantly. It should be noted that, although not shown in Figure 19, another benefit of increasing the number of cells is the reduction in the discrete step size of the output voltage (e.g., as a percentage of the total output voltage) as a result of enabling or disabling individual converters.

[0107] Therefore, at least in part from exemplary simulated demonstrations, there is generally an optimal total number of cells that should be used for a given cell design and given output waveform requirements.

[0108] Also according to certain specific exemplary embodiments of the present disclosure, Figure 23 is a schematic diagram of one of many methods for implementing a converter cell (including an inverting stage, an isolation stage, and a rectifier stage). Figure 23 also shows, at the bottom of the figure, a timing diagram relating to the use of an optional control block (e.g., a logic circuit) that drives the converter cell by transmitting a gate control signal to engage with an inverter, in which the gate control signal (or simply “gate signal”) is operated to minimize the transient drain voltage and / or for a short rise time of the output signal at the output terminal of the converter cell.

[0109] In more general situations, a control block may include or refer to a logic circuit arranged in cooperation with multiple resonant isolated DC-DC converter cells in a device, each having an output terminal of a converter cell configured to couple (or aggregate) the output signals generated by each converter cell at its output terminal. The logic circuit is used to selectively engage (e.g., selectively activate and / or deactivate) each of the converter cells to generate an output signal having a customized waveform shape based on selective engagement. In a more specific example, the control block and associated timing diagram in Figure 23 can be used to show how the transient portion of a pulse waveform can be easily and efficiently controlled to more closely follow a desired waveform shape. As an example, such desired waveform shapes and associated controls are described above in relation to Figures 6–9, 11, 13A–13C, and 20A–20B.

[0110] In certain other examples of this disclosure, the gate signal (to the right of the controller in Figure 23) can be generated and / or manipulated (e.g., tuned) by the controller and intervening circuitry or components (not shown) to affect one or more aspects of the switching behavior, such as the operating frequency, frequency modulation, and switching stress and output performance (rise time, overshoot, etc.) with respect to duty cycle control. Some of these converter examples in this disclosure are designed to operate when frequency has an inverse relationship with output voltage and current capability. The open-loop rise time also depends on frequency, as there are tuned reactive elements in the DC-DC cell design. In this general case, shorter rise times can be achieved by operating at lower frequencies during the initial rise. Similarly, slower response and reduced overshoot can be achieved by operating at higher initial frequencies.

[0111] In such examples using an inverter based on a Class E design in which the drain nodes (D1 and D2 of each FET shown in Figure 23) are unclamped, precise control of the gate drive signal may be important, for example, to mitigate or prevent overvoltage and / or limit power loss. According to one aspect of this disclosure, the controller generates gate drive signals for gates G1 and G2 in Figure 23 to reduce the initial voltage spike on the drain. In a more specific example, this is achieved by setting the width of the first gate pulse to about half of the later value (in different more specific examples, "about half" is within 5-10%, 10-15%, and possibly 20-25%). This is because there is no initial input inductor Lf current or load current, so fewer volts-seconds are required to reach the steady-state turn-off condition. The same principle can be applied to adjust subsequent gate pulses to track transient inverter and load conditions.

[0112] The timing diagram for the gate drive signals is shown at the bottom of Figure 23. Referring to the illustrative schematic diagram at the top of Figure 23, the horizontal axis shows the relative timing of the control voltages and corresponding drain voltages (D1 and D2) presented to the gates (G1 and G2), and the left side of the timing diagram shows such pulse-width manipulated control signals to achieve a low drain voltage (e.g., shown at the bottom of the timeline in Figure 23).

[0113] According to another optional aspect of this disclosure, the controller generates gate drive signals to control the signal transition timing (e.g., shorter rise time) at the outputs of the converter cells (Vo+ and Vo- in Figure 23). Generally, the duty cycle of the gate drive signals in such FET-based circuits is constrained by the efficiency for a given operating frequency and load. However, if efficiency is not as critical as rise time or other behavior, or for specific tuning and operating conditions, the output can be shaped by varying the duty cycle. In this case, a typical process is to increase the duty cycle for the purpose of causing the inverter to generate a higher peak drain voltage (and thus hard switching) or to overcome distortion from a low impedance load. The same timing diagram is used to represent the gate drive signals and corresponding drain voltages (D1 and D2) for achieving shorter rise times at the outputs of the converter cells.

[0114] Therefore, in consideration of the foregoing, the examples of the present disclosure concern achieving a lower drain voltage in an example using such an inverter and controlling the transition time at the output of a converter cell. In such an example, the converter cell is one of a stack of DC-DC converter cells, each having outputs connected in series to provide an aggregated output voltage based on the output voltage contributions from each output of a selected converter cell among the converter cells activated to generate an output voltage. Each converter cell, in such an example, includes an inverter circuit, an isolation circuit, and a rectifier circuit. The inverter circuit has a gate for receiving a gate drive (control) signal from a controller and an isolation circuit (e.g., including a transformer) for passing the output signal from the inverter circuit to the rectifier circuit, which is connected to the output terminals to provide a combined (or aggregated) output signal with each activated converter cell contributing its respective contribution. The controller is used to generate and / or control the gate drive signals of the FETs in the inverter, controlling the generation of gate drive (control) signals for each of the selected converter cells to be activated by at least one of an increase or decrease in the frequency or pulse width of the gate drive (control) signal compared to a steady state.

[0115] In a more specific example of this type, the controller controls the generation of waveform signals by setting the successive gate pulse widths of the waveform signals to have an initial lower gate pulse width with respect to the subsequent gate pulse width, which is substantially reduced with respect to the initial gate pulse width, or by generating a waveform signal at an initial higher frequency with respect to the steady state to achieve a shorter rise time at the output of the inverter circuit, or by generating a waveform signal at an initial higher frequency with respect to the steady state to achieve a slower response and reduced overshoot at the output of the inverter circuit, and / or

[0116] In other specific examples of this type (which may be carried out alone or in the manner described above), the initial gate pulse width is reduced by approximately half the subsequent gate pulse width, with a certain margin of error, and in more specific examples where the inverter circuit has a drain node (e.g., the drain node is unclamped or otherwise), the controller is configured to control the generation of the waveform signal by setting the successive gate pulse width to mitigate or reduce the initial voltage spike on the drain.

[0117] Other aspects of this disclosure include the use of such controllers to control the signal overshoot of the output signal provided by a stack composed of such DC-DC converters. In addition to controlling such signal overshoot, this type of selective engagement may be used to control rise time, shaping, and efficiency as needed (e.g., as disclosed herein in connection with the description of Figures 13A-13C and 14A-14B). Figure 24 shows a control block (e.g., a logic circuit) that transmits a control signal to selectively engage with specific cells within and between stack arrangements of converter cells in order to control the output overshoot of the output signal at the output terminals of the converter cells. In this regard, a specific exemplary system configured and selectively engaged while converter cells are arranged in series and / or parallel branch as stack cells may be intended to configure the power cells to operate within a load range available by frequency control. However, cells may also be used to control the shaping of transient responses (other than frequency control) and to optimize efficiency. This can be achieved, for example, by staggering the turn-on of different series cells, thereby reducing the overshoot to the same extent as in the case of a single series cell (but this increases the rise time). By turning on additional cells or branches during the rise time, additional current can be supplied to the output capacitance, shortening the rise time and allowing adjustments to limit the impact of overshoot. By turning off branches after the initial transient, the cell operating point can be shifted to a more efficient location, reducing system or per-cell losses.

[0118] Depending on the DC-DC cell design, the activation line may be processed to asynchronously modulate the gate drive signal to the inverter or to internally control the turn-on transient. The line may also be modulated at a much lower frequency to blend with the activation frequency and a common operating frequency, or to perform PWM control. In certain exemplary implementations, this technique may not generally optimize the control input efficiently, but advantageously, it provides some intermediate levels without phase shift. Since the cell's open-loop response depends on the operating frequency, activation control may be most effective when combined with appropriate frequency selection. Furthermore, the controller can use frequency or open-loop response information to adjust the activation sequence and timing.

[0119] According to further examples of the present disclosure, control of signal overshoot may be achieved by using a controller that generates enable and / or disable signals for a circuit including a stack of DC-DC converter cells, each output connected in series to provide an aggregated output voltage based on each output. The controller, including logic circuits, is configured to mitigate or eliminate output overshoot in the aggregated output voltage by selectively activating specific cells among a selection of cells in the stacked cell DC-DC converter. In more specific embodiments, the controller sequentially controls cells by selective enable and disable, selectively controlling the activation of cells to give each activated cell a delay in its contribution to the aggregated output voltage, or selectively controlling the activation and deactivation of cells by adjusting or modulating the frequency of one or more particular activated cells. In other specific examples, and as previously stated, mitigation or elimination of output overshoot in the aggregated output voltage is achieved, at least primarily, by initiating a specific set of gate drive signals with one or more higher initial switching frequencies and then reducing the frequency (without subsequently adjusting one or more frequencies as necessary), and / or by selectively adjusting one or more voltage setpoints that characterize a subset of cells, or by selectively adjusting one or more output voltages generated by a subset of cells.

[0120] A further aspect of this disclosure involves the use of different power rails to reduce isolation barrier requirements for high-speed converters by reducing voltage stress. Figures 25A–25C show alternative block diagrams of each method for powering a stacked arrangement of converter cells, each cell including an isolation stage as shown within each cell. Figure 25A shows one method in which the input signals to the converter cells refer to a single pair of power rails in common, which does not necessarily favor such a reduction in isolation barrier requirements. However, Figure 25B shows an alternative method in which the input signals to a particular converter cell refer to a different set of power rails. In particular, Figure 25B shows multi-stepping of levels provided by the power rails referenced by each converter cell.

[0121] More specifically, the power rail configuration in Figure 25A can be considered a default series connection of cells for higher output voltages, with the inputs remaining in parallel and the outputs connected in series. This approach has limitations in scaling to higher output voltages because the isolation barrier must be reliable up to the full pulse output voltage. The thickness increases to meet the need for isolation barriers, thereby decreasing the magnetization inductance of the transformer and increasing the leakage inductance (doubly decreasing the coupling coefficient). Compared to the approach in Figure 25B, this reduces the efficiency, power density, and response speed of the DC-DC cells because they must be designed around excessive parasitic elements. Also, thicker insulation increases costs.

[0122] The method in Figure 25B, as an alternative design, circumvents these problems by fabricating multiple high-voltage isolated DC rails to power the cell inputs. Thus, although the outputs are still connected in series, the inputs can reference intermediate voltages in the stack, and the isolation barrier stress is limited to a portion of the total output voltage. In the example shown in Figure 25B, having four isolated input rails reduces the isolation barrier requirement to approximately one-eighth. Because dielectric thickness does not necessarily increase linearly with voltage, the required barrier thickness can be reduced significantly more than the voltage stress. This allows for the use of more efficient, compact, and cost-effective cells to generate the required output voltage. A drawback of this method in certain implementations is the use of an additional isolation conversion step (and associated conversion circuits or one or more intermediate power supplies to supply operating power at different voltage levels, as shown in Figure 25B), although this type of converter has different requirements than cells, which can make it easier and / or more advantageous. For example, during operation and while supplying power to the DC rail, the control bandwidth is not critical, and an energy storage device can be connected to its output to supply the peak input power required by the load, so in some cases, the operation only needs to provide the average power requirement. In addition to smaller transformers to support the average power requirement rather than the peak power requirement, the isolation barrier capacity can be further reduced without directly sacrificing cell speed (as in the case of the single-step method in Figure 25A). This reduces the effective output load of the power supply, thereby reducing rise time and stored energy.

[0123] Each stack of DC-DC cells in Figure 25A can be compared to the stack in Figure 25B by the following more specific exemplary embodiment. Referring to the stack of DC-DC cells in Figure 25A, and looking from the bottom cell to the top cell, the isolation voltages of the cells in this more specific example are as follows: (1 / 8)*Vout; (2 / 8)*Vout[=(1 / 4)*Vout]; (3 / 8)*Vout; (4 / 8)*Vout[=(1 / 2)*Vout]; (5 / 8)*Vout; (6 / 8)*Vout[=(3 / 4)*Vout]; (7 / 8)*Vout; and (8 / 8)*Vout[=Vout]. Referring to the cell stack in Figure 25B for this more specific example, for the rightmost group of eight DC-DC cells, each cell has an isolation voltage of (1 / 8)*Vout. Each of the four middle DC-DC cells on the left side of Figure 25B has an isolation voltage as follows, starting from the bottom cell and going upwards: (1 / 8)*Vout; (3 / 8)*Vout; (5 / 8)*Vout; and (7 / 8)*Vout. In a specific example of the general configuration in Figure 25B, if the output voltage is a pulsed DC voltage, the group of four cells must withstand only a pure DC voltage, while the group of eight cells (in both drawings) must withstand a pulsed DC voltage.

[0124] In consideration of the foregoing, aspects of the present disclosure cover various examples for reducing isolation barrier requirements for such high-speed converters. In one such example, a power converter includes a stack of DC-DC converter cells ("converter cells") having respective outputs connected in series to provide an aggregated output voltage based on their respective outputs, and a plurality of DC rails isolated from each other by one or more voltage isolation barriers to provide operating power at different voltage levels to each of the converter cells. By accessing each of the plurality of DC rails, the converter cells have respective input ports referencing different voltage levels.

[0125] Figure 25C shows one or more alternative exemplary multi-stage configurations to those shown in Figure 25B. The configuration in Figure 25C is up to 3 / 4Vout 1 / 4V with a separate DC-DC stage for isolation out This shows the reduced DC pulse DC insulation stress.

[0126] In a more specific example, multiple DC rails are supplied with operating power at high voltages corresponding to different voltage levels (for example, for an output of about 10kV, the range may be about 1kV to about 9kV). In such a specific example, each of one or more voltage isolation barriers can at least partially isolate the voltage associated with directly adjacent DC rails as a function of the material thickness and voltage difference between directly adjacent DC rails, and / or one or more voltage isolation barriers are configured to limit the stress on a portion of the aggregated output voltage on one or more voltage isolation barriers of directly adjacent DC rails. In some of these examples, each cell may include a transformer-based isolation stage with large voltage differences on the primary and secondary sides of each voltage isolation barrier.

[0127] Therefore, the above discloses examples of different types of processes and apparatus (e.g., systems, devices, etc.) that use stacked arrangements of converter cells to generate custom waveform shapes in the output signal corresponding to the aggregation of individual output signals from each converter cell. Through the selective engagement of each converter cell, the output signals from the converter cells are combined to generate an aggregated (e.g., high-voltage) output signal having a customized waveform shape based on the selective engagement. A particular, more specific example leverages the intrinsic fast response time of the converter cells by using nanosecond-level pulsing for precise control over the cells to coordinate the high-voltage waveformization of the aggregated output signal derived from the DC-DC converter cells.

[0128] Further aspects of the present disclosure relate to exemplary configurations for primary and secondary windings of a planar transformer-based isolation stage as part of a PCB (printed circuit board), for example, integration with the inverter circuit and rectifier stage of a converter cell. As exemplary embodiments of such a planar transformer-based isolation stage, Figures 26A and 26B are diagrams showing corresponding cross-sectional views of the planar transformer, each applicable to one or more transformer-based implementations of the converter cell shown in Figure 1, with Figure 26A showing vias distributed throughout the planar winding on different layers (e.g., to improve thermal issues), and Figure 26B showing a normal planar winding. Figure 27 is an exploded view of a PCB planar transformer that can be used with one or more of the converter cells shown for the system in Figure 1 (e.g., showing a PCB planar transformer with an architecture common to all such converter cells).

[0129] In the exemplary configurations of Figures 26A, 26B, and 27, the transformer is implemented with primary and secondary windings mounted using planar traces within the PCB layer. While these exemplary configurations are not limited to being used with one or more of the circuits shown for the system in Figure 1, they have been found to be advantageous in terms of small form factor (e.g., minimum PCB area), voltage isolation, and other parameters that favor the operation of the system in Figure 1.

[0130] In relation to each of the exemplary configurations in Figures 26A and 26B, the transformer has a primary winding and one or more secondary windings (e.g., both are helical windings) integrated with a multilayer PCB, and the windings are shaped to minimize eddy current losses. The PCB has layers mounted to fix traces for the primary and secondary windings and includes vias through specific traces to minimize winding losses and promote thermal conductivity. Furthermore, the PCB, primary winding, and secondary winding are stacked vertically in cooperation to facilitate magnetic coupling between the primary and secondary windings.

[0131] In more specific examples based on the above examples, such configurations may be implemented to realize advantages that depend on a particular design, PCB space constraints, and power and thermal requirements and / or constraints. In some of these examples, several (X) layers fix the traces for the primary winding and another number (Y) layers fix the traces for the secondary winding, where X and Y are integers. In each of the examples in Figures 26A and 26B, X is 4 and Y is 2. In Figures 26A and 26B, the different numbers and arrangements of vias are partially defined by the traces for the primary and secondary windings to minimize winding losses and promote thermal conductivity. The primary and secondary windings may have corresponding portions internally with different widths in the parts closest to each other to minimize eddy current losses, or may have corresponding portions in the parts closest to each other where the trace width gradually decreases toward the center of the winding to minimize eddy currents. Furthermore, at least one of the primary and secondary windings may have portions that are narrower closer to the center of the winding, with traces closer to the outer edge of the winding and traces that are wider closer to the center of the winding. To minimize parasitic capacitance between the primary and secondary windings, the primary and secondary windings may also be arranged cooperatively with minimal overlap. In different examples, the primary and secondary windings may be helical windings or other windings of various forms and shapes (e.g., square, rectangular windings and / or combinations of shapes such as helical, square and / or rectangular).

[0132] In a related example, the PCB includes at least one insulating material between each set of traces arranged to cooperate to provide magnetic coupling, or multiple insulating material types to provide at least two levels of insulating protection, respectively, including high-voltage insulating protection closest to the transformer and another insulating protection, the high-voltage insulating protection being closest to the transformer than the other insulating material types and providing a higher degree of voltage insulating protection than the insulating protection provided by the other insulating material types.

[0133] In relation to specific examples of this disclosure, the figures and descriptions characterized above are provided to help illustrate specific embodiments (and possibly advantages) that may be used to manufacture such structures and devices. For example, the flowcharts in Figures 3, 6, 7, 8, and 9 are presented to illustrate methods and / or uses by specific techniques, including the operation of the system in Figure 1 (for example, each flowchart shows one or more blocks that can be used alone or in combination with other embodiments). To be useful in a particular implementation, such structures and devices may include exemplary structures and devices described in relation to one or more relevant embodiments (for example, by modifying and / or combining the examples of this disclosure) as described in the patent documents referenced above (including the above-mentioned U.S. Provisional Application and U.S. Patents 11,228,252 and 11,978,611). Each of these patent documents is incorporated by reference to the specific subject matter generally discussed herein, to the specific subject matter mentioned herein, and to the extent that further aspects and examples (such as experimental and / or more detailed embodiments) may be useful in supplementing and / or clarifying aspects of the present disclosure, including exemplary types of signals, circuits, loads, etc.

[0134] Those skilled in the art will also recognize various terms used in this disclosure by their obvious meanings. For example, this specification can describe and / or illustrate embodiments useful for implementing examples by various semiconductor materials / circuits, which can be indicated by or as terms referring to circuits, such as blocks, modules, stacks, devices, systems, units, stages, controllers, and / or other circuit types. Also, in connection with such descriptions, where appropriate in the orientation of a particular circuit polarity, the term “source” can interchangeably refer to the source and / or drain in the case of a transistor structure. Such semiconductors, semiconductor materials (including parts of semiconductor structures), circuit elements, and / or associated circuits can be used together with other embodiments of this disclosure to illustrate how a particular example can be implemented in form, or structure, steps, functions, operations, activities, etc. It should also be noted that terms illustrating orientations such as up / down, left / right, upper / lower, and upward / downward may be used herein to refer to the relative positions of elements, such as those shown in the figures. It should be understood that terms are used for convenience of notation only, and in actual use, the disclosed structures may be oriented differently from those shown in the figures. Therefore, such terminology should not be interpreted restrictively.

[0135] Based on the above description and examples, those skilled in the art will readily recognize that various modifications and changes can be made to various embodiments without strictly adhering to the exemplary embodiments and uses illustrated and described herein. For example, a method illustrated in the figures may include steps performed in various orders, or fewer or more steps, while retaining one or more aspects of the embodiments of this specification. Such modifications will not deviate from the true spirit and scope of the various aspects of this disclosure, including the aspects described in the claims.

Claims

1. It is a device, A plurality of resonant isolated DC-DC converter cells ("converter cells"), each of the plurality of converter cells having an output terminal configured to cooperate in coupling the output signals generated by each converter cell at the output terminal, A logic circuit, wherein the logic circuit controls the converter cell by selective engagement, which includes at least one of activation and deactivation ("selective engagement") of the converter cell, thereby generating an output signal having a waveform shape customized based on the selective engagement. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the logic circuit activates and deactivates the converter cell via an input signal provided to the converter cell at a controlled timing of approximately nanoseconds used when activating and deactivating the converter cell, and changing the timing of the input signal causes one or more changes in the waveform shape.

3. The apparatus according to claim 1, wherein the waveform shape is controlled according to timing control such that one or more delays are introduced for the activation of one or more of the converter cells in order to realize a desired form of the waveform shape.

4. The apparatus according to claim 1, wherein the waveform shape is controlled via selective activation and deactivation to realize a design specification that includes one or more combinations of (a) a short time and / or fall time of about nanoseconds, (b) a high peak voltage of about kV, and (c) the waveform shape being controllable by at least one of a voltage rise with a constant controllable gradient or a voltage fall with a constant controllable gradient.

5. The apparatus according to claim 1, wherein the activation and deactivation are controlled by the logic circuit based on stored or configured information useful for realizing a desired pulse waveform shape and its characteristics, the stored or configured information is provided by at least one of a stored setting, a configured logic circuit, and a feedback signal acquired or determined during the operation of the apparatus.

6. The apparatus according to claim 1, wherein the waveform shape is defined by pulses generated from a combined set of output signals driven by each of the converter cells.

7. The apparatus according to claim 1, wherein the waveform shape is easily modified by a waveform definition control parameter that includes one or more of the following: voltage, current, power, derivatives of the voltage, the current, and the power, and load impedance.

8. The apparatus according to claim 1, wherein the waveform shape is set or adjusted via feedback based on a control parameter including one or more of the following: voltage, current, power, derivatives of the voltage, the current, and the power, and load impedance.

9. The apparatus according to claim 1, further comprising a measurement and control circuit for implementing one or more combinations of: (a) a signal relayed from various sensors configured to monitor parameters derived from one or more of the converter cells, including at least one of output voltages, output currents, and individual currents from a stacked arrangement of the converter cells; (b) processing the signal derived from the monitored parameters derived from one or more of the converter cells; and (c) providing the converter cells with commands to cause the converter cells to perform a particular operation of a corresponding converter cell among the converter cells.

10. The apparatus according to claim 1, wherein the converter cell and the logic circuit are configured to cooperate in generating pulses for plasma processing in semiconductor manufacturing.

11. The apparatus according to claim 1, wherein the converter cell and the logic circuit are configured to cooperate in generating a pulse waveform having a tuned bias voltage, accompanied by a short positive pulse followed by a negative linear ramp, and having a maximum pulse voltage in the range of 10 kV to a maximum of several kV, a rise time in the range of 10 ns to a maximum of 100 ns, and a negative linear ramp lasting up to a maximum of several microsecs.

12. The apparatus according to claim 1, wherein the converter cell and the logic circuit are configured to cooperate in generating the output signal having the waveform shape as an adjustable pulse waveform in which a plurality of parameters from voltage level, pulse width, and ramp time can be adjusted.

13. The apparatus according to claim 1, wherein at least some of the converter cells are arranged in a stack to facilitate a fast time in transitioning to a peak voltage level, and the stacks are connected in parallel to provide an increased current level to a load driven by the output signal having the waveform shape customized based on the selective engagement.

14. The apparatus according to claim 1, wherein the converter cells are arranged in a stack, and each stack is configured to supply up to a certain amount of current to achieve a certain level of efficiency, and is arranged in parallel and / or optimized.

15. The apparatus according to claim 1, wherein the converter cells are arranged in a stack, and each of the stacks has a common architecture and consumes current according to the common architecture, thereby avoiding one of two or more combinations of reduced efficiency, overload, and overheating.

16. The apparatus according to claim 1, wherein the selective engagement can connect the output of the converter cell in series with respect to a series stack of a particular converter cell among the converter cells, in parallel with respect to a parallel arrangement of a particular converter cell among the converter cells, or in series with a particular converter cell among the converter cells in a series stack and in parallel with a particular other converter cell among the converter cells corresponding to a parallel arrangement.

17. The apparatus according to claim 1, wherein the selective engagement allows the output of the converter cell to be coupled in series with a specific converter cell among the converter cells in a series stack and in parallel with a specific other converter cell among the converter cells corresponding to a parallel arrangement, and the respective output signals are coupled at the output terminals to generate the customized waveform shape via a coupled output signal having output current and output voltage according to design limits or specified load requirements.

18. The apparatus according to claim 1, wherein each of the converter cells has a common circuit architecture and operating characteristics that include a plurality of the following: output voltage or power, switching frequency, transient response, selective activation timing, and voltage isolation requirements.

19. The apparatus according to claim 1, wherein at least one of the converter cells is designed to have one or more different operating characteristics from another of the converter cells, the one or more different operating characteristics include at least one of a different output voltage, a different output power, a different switching frequency range, a different transient response, and a different voltage isolation.

20. The apparatus according to claim 1, wherein at least one of the converter cells has a different circuit architecture from the other of the converter cells.

21. The apparatus according to claim 1, further comprising an inverter circuit and a rectifier circuit, wherein each of the converter cells implements isolation by integrating primary and secondary windings into the inverter circuit and the rectifier circuit.

22. The apparatus according to claim 1, further comprising a switching circuit coupled to one or more of the converter cells, wherein the converter cells are cascaded with the switching circuit to affect the corresponding of the respective output signals by one or a combination of high-speed pull-up, pull-down, and polarity swap operations.

23. The apparatus according to claim 1, wherein each of the output terminals of the converter cell is configured to provide a unipolar or bipolar output voltage over a load that is mainly capacitive.

24. The apparatus according to claim 1, wherein the output signal has a waveform shape customized to generate a shaped ion energy distribution on the surface of the substrate.

25. The apparatus according to claim 1, wherein the output signal has a waveform shape customized to generate a shaped ion energy distribution of single energy on the surface of the substrate.

26. The apparatus according to claim 1, wherein the output signal has a waveform shape customized to generate a shaped ion energy distribution on the surface of a semiconductor wafer.

27. The apparatus according to claim 1, further comprising an RF plasma source, wherein the output signal has a waveform shape customized to produce a shaped ion energy distribution at least partially defined by the RF plasma source.

28. The apparatus according to claim 1, wherein the output signal has a waveform shape customized to generate a shaped ion energy distribution in which ions are generated along with the generation of plasma and accelerated by the converter cell configured as a single power source.

29. The apparatus according to claim 1, wherein the logic circuit controls the converter cell by generating and manipulating a gate drive signal with respect to at least one of phase, timing, and voltage level in order to cause the generation of the output signal.

30. The apparatus according to claim 1, wherein the converter cell is configured to provide at least one of supplying power to a load and absorbing power from a load.

31. The inverter circuit further includes a converter and a rectifier circuit including each of the converter cells, the converter is A primary winding and one or more secondary windings shaped to mitigate or minimize eddy current losses, Multilayer printed circuit boards (PCBs) and Includes, The apparatus according to claim 1, wherein the multilayer printed circuit board (PCB) includes a plurality of layers for fixing traces for the primary winding and a plurality of layers for fixing traces for the secondary winding, and includes vias through specific traces of the traces to minimize winding losses and promote thermal conductivity, and the PCB, the primary winding and the secondary winding are laminated in cooperation perpendicularly with one or more insulating layers between specific layers of the plurality of layers of the PCB to isolate the secondary winding from the primary winding in order to promote magnetic coupling between the primary winding and the secondary winding.

32. The apparatus according to claim 1, wherein the logic circuit is used to facilitate a coarse closed-loop voltage feedback including a specific converter cell among the converter cells, and another closed-loop feedback for precise control of a specific output signal parameter provided by a selected converter cell.

33. The apparatus according to claim 1, wherein one or more of the converter cells include an inverter circuit having a control gate for receiving a respective gate control signal (in response to the logic circuit), an isolation circuit including a transformer, and a rectifier circuit, and the logic circuit controls the generation of the waveform signal of each of the converter cells by increasing or decreasing the frequency of the gate control signal or the pulse width of the gate control signal with respect to a steady state.

34. The apparatus according to claim 1, wherein the selective engagement further includes controlling at least one of the converter cells by coarse adjustment, followed by fine adjustment, in addition to activation and deactivation.

35. The apparatus according to claim 1, wherein at least one of the converter cells includes or is electrically coupled to a Class E amplifier.

36. The apparatus according to claim 1, wherein one or more of the converter cells include an inverter circuit having a control gate for receiving a respective gate control signal, the logic circuit generates the waveform shape by generating the output signal via an initial low frequency of the gate control signal with respect to the frequency used in steady-state operation, and facilitates the fast or optimized transition time of the output signal to reach its peak.

37. The apparatus according to claim 1, wherein one or more of the converter cells include an inverter circuit having a control gate for receiving a respective gate control signal, and the logic circuit generates the waveform shape by generating the respective gate control signals by setting consecutive gate pulse widths within the respective gate control signals through the generation of an initial gate pulse width which is substantially reduced with respect to the subsequent gate pulse width.

38. The apparatus according to claim 37, wherein the initial gate pulse width is approximately half of the subsequent gate pulse width within a 15% error range.

39. The apparatus according to claim 1, wherein one or more of the converter cells include an inverter circuit having drain nodes and control gates for receiving respective gate control signals, and the logic circuit generates the waveform shape by setting consecutive gate pulse widths to mitigate or reduce initial voltage spikes in one or more of the drain nodes.

40. The apparatus according to claim 1, wherein one or more of the converter cells include an inverter circuit having a control gate for receiving a respective gate control signal, and the logic circuit generates the waveform shape by generating the respective gate control signals at an initial higher frequency for operating the converter cells with respect to the frequency used in steady-state operation, in order to mitigate or eliminate signal overshoot occurring in the output signal.

41. The apparatus according to claim 40, wherein the mitigation or elimination of the overshoot is achieved, at least primarily, without adjusting the one or more switching frequencies used to operate the converter cell after reducing the one or more switching frequencies from the initial higher frequencies.

42. The apparatus according to claim 1, wherein the logic circuit sequentially controls the converter cell by at least one of selective activation and selective deactivation.

43. The apparatus according to claim 1, wherein the logic circuit controls the converter cells by selectively controlling the activation of the converter cells, thereby causing a delay in each of the contributions of the activated converter cells to the output signal coupled at the output terminals.

44. The apparatus according to claim 1, wherein the logic circuit selectively controls at least one of the converter cells by adjusting or modulating one or more switching frequencies of at least one of the converter cells.

45. The apparatus according to claim 1, wherein the logic circuit mitigates or eliminates output overshoot of the output signal coupled at the output terminal by selectively adjusting one or more voltage setpoints that characterize one or more of the converter cells.

46. The apparatus according to claim 1, wherein the logic circuit mitigates or eliminates output overshoot of the output signal coupled at the output terminal by selectively adjusting one or more output voltages generated by one or more of the converter cells.

47. It is a method, Selective engagement ("selective engagement") which includes activating and deactivating each of a plurality of resonant isolated DC-DC converter cells ("converter cells") via a logic circuit, The output signals from each output terminal of the converter cell are combined to generate an output signal having a waveform shape customized based on the selective engagement. Methods that include...

48. The method of claim 47, further comprising providing a set of time-adjusted gate drive signals to the control input port of the converter cells, which includes setting or adjusting the timing and signal level of each of the time-adjusted gate drive signals for selective engagement in order to adjust each respective output voltage generated by each of the converter cells, and combining the output signals in response to the selective engagement.

49. The method according to claim 47, wherein the selective engagement includes operating at least a subset of the converter cells via a frequency set of one or more sufficiently high switching frequencies within the frequency range of 1 MHz to 100 MHz, and manipulating the waveform shape of a fractional portion of the output signal at the output terminal of the converter cell over at least several cycles of the frequency set.

50. The method according to claim 47, wherein the portion corresponds to a segment of the waveform shape immediately after the waveform shape reaches an upper or lower peak, and selectively adjusts one or more output voltages generated by one or more of the converter cells.

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