Manufacturing method and storage device

Abstract

This application discloses a method for manufacturing a memory device and a memory device. The method for manufacturing a memory device includes providing a semiconductor substrate, the semiconductor substrate comprising the steps of: forming a plurality of first grooves from the hard mask layer toward an active region of the substrate, a portion of the plurality of first grooves located in a storage region, the other portion of the plurality of first grooves located in a drawout region, and the first grooves in the substrate being defined as substrate grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the substrate grooves, a portion of the semi-floating gate being in contact with the substrate, and the other portion of the semi-floating gate being separated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in each of the plurality of first grooves, forming a control gate in the first groove of the storage region, and forming a lead wire of a memory unit in the first groove of the drawout region. The drawout region of this application can be in contact with the outside, and the problem of voltage drop caused by a large embedded gate resistance is solved.

Description

Technical Field

[0001] <Cross - reference to Related Applications> This application claims priority from a Chinese patent application with the application number 202311044576.3 filed on August 16, 2023, and the entire content of this Chinese patent application is incorporated herein by reference into this application.

[0002] This application relates to the field of semiconductor technology, and particularly to a manufacturing method of a memory device and a memory device.

Background Art

[0003] In the application process of integrated circuits, since the contact area between each material layer affects the power consumption of the device, the performance of various devices (especially memory devices) is affected by the contact area between each material layer.

[0004] In the actual operation process, the developers of this application found that in the current semiconductor device manufacturing method, especially in the manufacturing of memory devices teeth , it always results in insufficient coupling between the control gate and the semi - floating gate. As a result, the operating voltage of the memory device increases, the power consumption also increases, and it affects the performance of the memory device.

Summary of the Invention

[0005] According to various embodiments of this application, a manufacturing method of a memory device and a memory device are provided.

[0006] This application provides a manufacturing method of a memory device. The manufacturing method of the memory device includes the step of providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a hard mask layer on the substrate, and the hard mask layer from in the active region of the substrate TowardsThe process includes the steps of forming a plurality of first grooves, where a portion of the plurality of first grooves is located in a storage area and the other portion of the plurality of first grooves is located in a drawout area, wherein the first grooves in the substrate are defined as base grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the base grooves, wherein a portion of the semi-floating gate is in contact with the substrate and the other portion of the semi-floating gate is separated from the substrate by the gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in each of the plurality of first grooves, wherein a portion of the first gate layer in the first groove of the storage area is removed to form a control gate of a storage unit, and the first gate layer in the first groove of the drawout area is left as a lead line of the storage unit, the lead line is connected to the control gates of a plurality of the storage units in the same row.

[0007] In another embodiment, the present application provides a memory device comprising a substrate, a substrate groove, a semi-floating gate, an intergate insulating film, and a first gate layer. The substrate groove extends from one side surface of the substrate to the substrate Inside The substrate is extended, and a portion of the plurality of substrate grooves is arranged in a storage area, and the other portion of the plurality of substrate grooves is arranged in a draw-out area, where a gate insulating layer is installed on the inner wall of the bottom of the substrate groove, and the semi-floating gate is filled into the bottom of the substrate groove, where a portion of the semi-floating gate is separated from the substrate by the gate insulating layer, and the other portion of the semi-floating gate is in contact with the substrate, and the inter-gate dielectric layer covers the semi-floating gate, and the first gate layer is installed on the inter-gate dielectric layer, where the first gate layer of the storage area constitutes the control gate of the storage unit in the storage device, and the first gate layer of the draw-out area is a lead line, and the lead line is connected to the control gates of a plurality of storage units in the same row.

[0008] Details of one or more embodiments of this application are described in the accompanying drawings and the following description. Other features, purposes, and advantages of this application will become apparent from the specification, drawings, and claims. [Brief explanation of the drawing]

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings that may be used in the description of the embodiments are briefly described below. Clearly, the drawings in the following description represent only a few embodiments of this application. Those skilled in the art can obtain other drawings from these without any creative effort. [Figure 1] This is a flowchart of one embodiment of the method for manufacturing a storage device as described in this application. [Figure 2a] This is a schematic diagram of the structure of a semiconductor substrate in the first direction according to one embodiment of the present invention. [Figure 2b] This is a schematic diagram of the structure of a semiconductor substrate in a second direction according to one embodiment of the present invention. [Figure 3a] This is a schematic diagram of the structure in the first direction of an embodiment in which a second groove is formed in the substrate according to this application. [Figure 3b] This is a schematic diagram of the second direction of an embodiment in which a second groove is formed in the substrate according to the present application. [Figure 4a] This is a schematic diagram of the structure in the first direction of an embodiment that forms a shallow trench isolation structure in this application. [Figure 4b] This is a schematic diagram of the second direction of an embodiment that forms a shallow trench isolation structure in this application. [Figure 5a] This is a schematic diagram of the structure in the first direction of an embodiment that forms the second well region in this application. [Figure 5b] This is a schematic diagram of the structure in the second direction of an embodiment that forms the second well region in this application. [Figure 6a] This is a schematic diagram of the structure in the first direction of an embodiment for forming the filling coating layer of this application. [Figure 6b]This is a schematic diagram of the structure in a second direction of an embodiment for forming the filling coating layer of this application. [Figure 7a] This is a schematic diagram of the structure in the first direction of an embodiment in which the first groove is formed in this application. [Figure 7b] This is a schematic diagram of the second direction of the embodiment in which the first groove is formed in this application. [Figure 8a] This is a schematic diagram of the structure in the first direction of an embodiment for filling the second gate material in this application. [Figure 8b] This is a schematic diagram of the second orientation of an embodiment for filling the second gate material in this application. [Figure 9a] This is a schematic diagram of the structure in the first direction of one embodiment that forms a contact window in this application. [Figure 9b] This is a schematic diagram of the second structural view of one embodiment of the contact window forming in this application. [Figure 10a] This is a schematic diagram of the structure in the first direction of an embodiment for filling the third gate material in this application. [Figure 10b] This is a schematic diagram of the second direction of the structure of an embodiment for filling the third gate material in this application. [Figure 11a] This is a schematic diagram of the structure in the first direction of an embodiment in which the second gate material, the third gate material, and a portion of the first insulating layer are removed from the first groove of the present application. [Figure 11b] This is a schematic diagram of the structure in a second direction of an embodiment in which a portion of the second gate material, third gate material, and first insulating layer are removed from the first groove of the present application. [Figure 12a] This is a schematic diagram of the structure in a first direction of one embodiment that forms the first separation portion of the present application. [Figure 12b] This is a schematic diagram of the structure in the second direction of one embodiment forming the first separation portion of this application. [Figure 13a] This is a schematic diagram of a first direction structure of another embodiment in which a shallow trench isolation structure is continuously lowered to form the first separation portion of the present application. [Figure 13b]It is a structural schematic diagram in the second direction of another embodiment for continuously lowering the shallow trench isolation structure to form the first isolation portion of this application. [Figure 14a] It is a structural schematic diagram in the first direction of an embodiment for forming a gate dielectric layer in this application. [Figure 14b] It is a structural schematic diagram in the second direction of an embodiment for forming a gate dielectric layer in this application. [Figure 15a] It is a structural schematic diagram in the first direction of an embodiment for coating the first gate material in this application. [Figure 15b] It is a structural schematic diagram in the second direction of an embodiment for coating the first gate material in this application. [Figure 16a] It is a structural schematic diagram in the first direction of an embodiment for removing a part of the first gate material in this application. [Figure 16b] It is a structural schematic diagram in the second direction of an embodiment for removing a part of the first gate material in this application. [Figure 17a] It is a structural schematic diagram in the first direction of an embodiment for forming the second insulating layer in this application. [Figure 17b] It is a structural schematic diagram in the second direction of an embodiment for forming the second insulating layer in this application. [Figure 18a] It is a structural schematic diagram in the first direction of an embodiment for removing a part of the first insulating layer and the filling coating layer of this application. [Figure 18b] It is a structural schematic diagram in the second direction of an embodiment for removing a part of the first insulating layer and the filling coating layer of this application. [Figure 19] It is a top view of the memory device of this application. [Figure 20a] It is a structural schematic diagram in the first direction of an embodiment for forming a spacer in this application. [Figure 20b] It is a structural schematic diagram in the second direction of an embodiment for forming a spacer in this application. [Figure 21a] It is a structural schematic diagram in the first direction of an embodiment for forming a contact plug in the interlayer dielectric layer of this application. [Figure 21b]This is a schematic diagram of the second orientation of an embodiment in which a contact plug is formed in the interlayer dielectric layer in this application. [Modes for carrying out the invention]

[0010] The technical solutions of the embodiments of this application will be described clearly and completely below with reference to the drawings of the embodiments of this application. Clearly, the embodiments described are only a part of, and not all, of, the embodiments of this application. All other embodiments that a person skilled in the art can obtain based on the embodiments of this application without requiring inventive work are all within the scope of protection of this application.

[0011] In current memory device manufacturing processes, particularly those involving embedded gate structures formed by semi-floating gates, the high resistance of the embedded gates leads to voltage drop problems. As a result, the coupling between the control gate and the semi-floating gate is often insufficient, leading to high operating voltage and power consumption in the memory device, which affects its performance.

[0012] Therefore, a method for manufacturing a storage device is provided. This allows the lead lines of the lead area to be external circuit and Electrically This allows for contact, solving the problem of voltage drop caused by the high embedded gate resistance of the control gate, while simultaneously lowering the operating voltage of the memory device and reducing power consumption.

[0013] Referring to Figure 1, Figure 1 is a flowchart of one embodiment of the method for manufacturing a storage device in this application.

[0014] As shown in Figure 1, the method for manufacturing a storage device according to this application includes the following:

[0015] Step (S11) provides a semiconductor substrate, the semiconductor substrate including the substrate and a hard mask layer placed on the substrate.

[0016] The semiconductor substrate in step (S11) is as shown in Figures 6a and 6b, and the operation process of one embodiment of step (S11) is as follows.

[0017] A substrate is provided, and a first dielectric layer and a second dielectric layer are sequentially formed on the substrate.

[0018] Here, the substrate may be any suitable substrate known in the art, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), other III / V compound semiconductors, multilayer structures made of these semiconductors, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI).

[0019] Referring to Figures 2a and 2b, Figure 2a is a schematic diagram of the structure of a semiconductor substrate according to one embodiment of this application, viewed from a first direction, and Figure 2b is a schematic diagram of the structure of a semiconductor substrate according to one embodiment of this application, viewed from a second direction.

[0020] Specifically, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are formed sequentially on the substrate 100.

[0021] In some embodiments, the first dielectric layer 200 may be an oxide layer such as a silicon oxide layer. The second dielectric layer 300 may be a nitride layer such as a silicon nitride layer.

[0022] A second groove is formed from the second dielectric layer toward the substrate, where the second groove is spaced apart along the first direction and extends along the second direction.

[0023] Here, the first direction is the extension direction of the word line (wordline, WL), i.e., the first direction is the X direction, and the second direction is the extension direction of the bit line (bitline, BL), i.e., the second direction is the Y direction, i.e., the first and second directions are orthogonal to each other in the same horizontal plane.

[0024] Referring to Figures 3a and 3b, Figure 3a is a schematic diagram of the structure in the first direction of an embodiment for forming a second groove in a substrate according to this application, and Figure 3b is a schematic diagram of the structure in the second direction of an embodiment for forming a second groove in a substrate according to this application.

[0025] As shown in Figure 3a, in the first direction, a second groove 101 is formed from the second dielectric layer 300 toward the substrate 100. In the second direction, the first dielectric layer 200 and the second dielectric layer 300 are sequentially formed on the substrate 100.

[0026] In some embodiments, the multiple second grooves 101 are distributed sequentially and at intervals along a first direction (X direction), and the bottom of the second grooves is higher than the bottom of the substrate 100, i.e., the second grooves 101 extend into a portion of the substrate 100.

[0027] A separation material is filled into the second groove to form a shallow trench isolation structure, and ion implantation is performed to form a first well region within the substrate.

[0028] Referring to Figures 4a and 4b, Figure 4a is a schematic diagram of the structure in the first direction of an embodiment forming a shallow trench isolation structure in this application. Figure 4b is a schematic diagram of the structure in the second direction of an embodiment forming a shallow trench isolation structure in this application.

[0029] As shown in Figure 4a, in the first direction, a separation material is filled into the second groove 101 to form a shallow trench isolation structure 102, and then ion implantation is performed on the substrate 100 to form a first well region 110 on the substrate 100. Here, the shallow trench isolation structure 102 penetrates to the first well region 110, and the bottom of the shallow trench isolation structure 102 is higher than the bottom of the first well region 110 and lower than the top of the first well region 110. As shown in Figure 4b, in the second direction, ion implantation is performed on the substrate 100 to form a first well region 110 on the substrate 100.

[0030] In some embodiments, the lowest point of the first well region 110 is higher than the lowest point of the substrate 100, and the highest point of the first well region 110 is lower than the highest point of the substrate 100, that is, the first well region 110 is located within the substrate 100.

[0031] In some embodiments, a portion of the shallow trench isolation structure 102 is located within the substrate 100, a portion of the shallow trench isolation structure 102 protrudes from the substrate 100, thereby defining the substrate into multiple active areas (AA), and the shallow trench isolation structure 102 extends along a second direction and is spaced apart along a first direction.

[0032] After forming the shallow trench isolation structure 102, the second dielectric layer 300 is removed, and a portion of the shallow trench isolation structure 102 is exposed.

[0033] Ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer, thereby forming a second well region 120 on the side of the substrate 100 adjacent to the first dielectric layer 200. Here, the doping type of the second well region 120 is different from the doping type of the first well region 110.

[0034] As shown in Figures 5a and 5b, Figure 5a is a schematic diagram of the structure in the first direction of an embodiment forming the second well region in this application, and Figure 5b is a schematic diagram of the structure in the second direction of an embodiment forming the second well region in this application.

[0035] As shown in Figure 5a, in the first direction, the second dielectric layer 300 is removed, exposing a part of the shallow trench isolation structure 102, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer, forming a second well region 120 on the side of the substrate 100 adjacent to the first dielectric layer 200. As shown in Figure 5b, in the second direction, the second dielectric layer 300 is removed, exposing the first dielectric layer 200, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer, forming a second well region 120 on the side of the substrate 100 adjacent to the first dielectric layer 200, where the second well region 120 is located on top of the first well region 110.

[0036] In some embodiments, the doping type of the first well region 110 and the doping type of the second well region 120 are different, that is, the doping types of the first well region 110 and the second well region 120 are reversed. For example, the first well region 110 is an N-type doped well region, and the second well region 120 is a P-type doped well region. Conversely, the first well region 110 is a P-type doped well region, and the second well region is an N-type doped well region.

[0037] A filling and coating layer is formed on the first dielectric layer, and the first dielectric layer and the filling and coating layer constitute a hard mask layer 400. Here, the filling and coating layer is filled between two adjacent shallow trench isolation structures 102 and covers the shallow trench isolation structures 102, and may be a multilayer structure or a single layer structure.

[0038] Here, if the filling coating layer has a multilayer structure, the filling coating layer may include a filling layer 410 and a first protective layer 420. In this case, the filling layer 410 is formed on the first dielectric layer 200, where the filling layer 410 is filled between two adjacent shallow trench isolation structures 102, and the first protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structures 102. Alternatively, if the filling coating layer has a single-layer structure, for example, it may be a silicon nitride layer, which is filled between two shallow trench isolation structures 102 and formed on the shallow trench isolation structures 102. In this case, the first dielectric layer 200 is also part of the hard mask layer 400.

[0039] As shown in Figures 6a and 6b, Figure 6a is a schematic diagram of the structure in the first direction of an embodiment for forming a hard mask layer in this application, and Figure 6b is a schematic diagram of the structure in the second direction of an embodiment for forming a hard mask layer in this application.

[0040] As shown in Figure 6a, in the first direction, a packing layer 410 is formed on the first dielectric layer 200, and the packing layer 410 is filled between two adjacent shallow trench isolation structures 102. Furthermore, a first protective layer 420 is formed on the packing layer 410 and the shallow trench isolation structures 102. Here, the packing layer 410 and the first protective layer 420 constitute a packed coating layer, and the first dielectric layer 200, the packing layer 410, and the first protective layer 420 constitute a hard mask layer 400. As shown in Figure 6b, in the second direction, a packing layer 410 is formed on the first dielectric layer 200, and further, a first protective layer 420 is formed on the packing layer 410.

[0041] In some embodiments, the packed layer 410 may be a packed layer of polycrystalline material, and the first protective layer may be an ON structure composed of a nitride layer and an oxide layer, for example, an ON structure protective layer consisting of a silicon nitride layer and a silicon oxide layer.

[0042] In step (S12), a plurality of first grooves are created in the active region of the substrate from the hard mask layer, with some of the plurality of first grooves located in the storage region and other parts of the plurality of first grooves located in the draw-out region, where the portion of the first grooves in the substrate is defined as the substrate groove, as shown in Figures 7a and 7b.

[0043] Here, the first groove is installed at intervals in the second direction.

[0044] As shown in Figures 7a and 7b, Figure 7a is a schematic diagram of the structure in the first direction of an embodiment for forming the first groove in this application. Figure 7b is a schematic diagram of the structure in the second direction of an embodiment for forming the first groove in this application.

[0045] A hard mask layer 400 has a plurality of first grooves 103 formed toward the active region of the substrate 100, with a portion of the first grooves 103 located in the storage region and another portion located in the drawer region. In the first direction, the first grooves 103 are separated by a shallow trench isolation structure 102, and in the second direction, the plurality of first grooves 103 are spaced apart.

[0046] As shown in Figure 7a, in the first direction, a portion of the hard mask layer 400 installed in the shallow trench isolation structure 102 between two adjacent first grooves 103 is removed, exposing a portion of the shallow trench isolation structure 102, and a first groove 103 is formed in the active region between the shallow trench isolation structures 102. As shown in Figure 7b, in the second direction, the hard mask layer 400 forms a plurality of first grooves 103 that are spaced apart toward the active region of the substrate 100.

[0047] In some embodiments, the first groove 103 penetrates the first protective layer 420, the packing layer 410, the first dielectric layer 200, and the second well region 120 in sequence, i.e., penetrates the hard mask layer 400 and the second well region 120, i.e., the bottom of the first groove 103 is in contact with the first well region 110, thereby exposing the first well region 110 by the first groove 103.

[0048] In step (S13), a gate insulating layer and a semi-floating gate are formed at the bottom of the substrate groove, with a portion of the semi-floating gate in contact with the substrate and the other portion of the semi-floating gate separated from the substrate by the gate insulating layer. This is shown in Figures 13a and 13b.

[0049] Here, the bottom of the substrate groove is the first slot segment 1031, that is, the first slot segment 1031 is the bottom region of the substrate groove where the semi-floating gate is formed.

[0050] One embodiment of step (S13) includes forming a gate insulating layer, a second gate, and a third gate at the bottom of a substrate groove. Here, the second gate and the substrate are separated by the gate insulating layer, the third gate is in direct contact with the substrate, and the second and third gates cooperate to constitute a semi-floating gate of a storage unit in a storage device. The specific operation process includes forming a first insulating layer on the inner wall of the substrate groove, filling the first groove with second gate material, removing a portion of the second gate material and a portion of the first insulating layer to form a contact window, and forming the third gate material above the contact window.

[0051] Referring to Figures 8a and 8b, Figure 8a is a schematic diagram of the structure in the first direction of the embodiment for filling the second gate material in this application. Figure 8b is a schematic diagram of the structure in the second direction of the embodiment for filling the second gate material in this application.

[0052] As shown in Figure 8a, in the first direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and the first insulating layer 104 can be formed on the exposed substrate using a thermal oxidation process, and a second gate electrode material 105 is filled into the first groove 103, and the second gate material 105 covers the first groove 103. As shown in Figure 8b, in the second direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a second gate material 105 is filled into the first groove 103, so that the second gate material 105 is flush with the hard mask layer 400, i.e., flush with the first protective layer 420.

[0053] In some embodiments, the second gate material 105 may be a polycrystalline material such as polysilicon, and after filling with the second gate material 105, the second gate material 105 is chemically and mechanically polished so that it is coplanar with the first protective layer 420.

[0054] In some embodiments, as shown in Figure 8a, when a first insulating layer 104 is formed on the inner wall of the first groove 103 and a second gate material 105 is filled into the first groove 103, the second gate material 105 also covers the shallow trench isolation structure 102.

[0055] A portion of the second gate material 105 and the corresponding portion of the first insulating layer 104 within the first groove 103 are removed to form a contact window, where at least a portion of the first insulating layer within the first slot segment is removed.

[0056] Referring to Figures 9a and 9b, Figure 9a is a schematic diagram of the structure in the first direction of an embodiment forming a contact window in this application, and Figure 9b is a schematic diagram of the structure in the second direction of an embodiment forming a contact window in this application.

[0057] As shown in Figure 9b, in the second direction, a portion of the second gate material 105 in the first groove 103 and a portion of the corresponding first insulating layer 104 are removed, and a portion of the second gate material 105 in the first slot segment 1031 in the substrate groove and a portion of the first insulating layer 104 are removed, forming a contact window with the substrate 100. As shown in Figure 9a, in the first direction, the structure shown in Figure 8a is maintained.

[0058] Here, the substrate groove includes a first slot segment 1031 and a second slot segment 1032, the second slot segment 1032 being located above the first slot segment 1031, i.e., the first slot segment 1031 being the bottom region of the first groove 103, the first slot segment 1031 being used to position the second and third gates, and the second slot segment 1032 being used to position the first gate layer.

[0059] In some embodiments, the removal method can be photolithography or etching.

[0060] The third gate material is filled into the empty area of ​​the first groove 103, that is, the third gate material is formed in the contact window. Here, the third gate material in the first slot segment 1031 is in contact with the substrate through the contact window.

[0061] Referring to Figures 10a and 10b, Figure 10a is a schematic diagram of the structure in the first direction of the embodiment for filling the third gate material in this application, and Figure 10b is a schematic diagram of the structure in the second direction of the embodiment for filling the third gate material in this application.

[0062] As shown in Figure 10a, in the first direction, the structure shown in Figure 9a is maintained. As shown in Figure 10b, in the second direction, after removing a portion of the second gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103, an empty area of ​​the first groove 103 is formed, and the empty area of ​​the first groove 103 is filled with the third gate material 106, i.e., the third gate material 106 is formed in the contact window, and after filling, chemical mechanical polishing is performed to flatten the surface after filling. Since at least a portion of the first insulating layer 104 in the first trench segment 1031 is removed to form a contact window, the third gate material 106 in the first trench segment 1031 can contact the substrate 100 through the contact window, for example, it can contact the second well area 120.

[0063] The third gate material may be formed using an epitaxial or deposition process. In one embodiment, the third gate material is formed by an epitaxial process, thereby at least basis Contact with the board Third gate material It is a single-crystal material.

[0064] After filling with the third gate material 106, the second gate material 105, the third gate material 106, and a portion of the first insulating layer 104 in the first groove 103 are removed, leaving the second gate material 105, the third gate material 106, and the first insulating layer 104 at the bottom of the substrate groove (i.e., the first slot segment 1031). Here, the second gate material 105, the third gate material 106, and the first insulating layer 104 remaining in the first slot segment 1031 become the second gate 1051, the third gate 1061, and the gate insulating layer, respectively. Referring to Figures 11a and 11b, Figure 11a is a schematic diagram of the structure in the first direction of an embodiment in this application in which the second gate electrode material, the third gate electrode material, and a portion of the first insulating layer are removed from the first groove. Figure 11b is a schematic diagram of the structure in the second direction of an embodiment in this application in which the second gate material, the third gate material, and a portion of the first insulating layer are removed from the first groove.

[0065] As shown in Figure 11b, in the second direction, the second gate material 105, the third gate material 106, and a portion of the first insulating layer 104 in the first groove 103 are removed, while the second gate material 105, the third gate material 106, and the first insulating layer 104 in the first slot segment 1031 are left intact. The second gate material 105 remaining in the first slot segment 1031 is designated as the second gate 1051, the third gate material 106 remaining in the first slot segment 1031 is designated as the third gate 1061, and the first insulating layer 104 remaining in the first slot segment 1031 is designated as the gate insulating layer 1041. Here, the bottom of the substrate groove where the second gate 1051, the third gate 1061, and the gate insulating layer 1041 remain is the first slot segment 1031.

[0066] In some embodiments, when performing the step of removing the second gate material 105, the third gate material 106, and a portion of the first insulating layer 104 within the first groove 103, a portion of the second gate material 105 covering the shallow trench isolation structure 102 is simultaneously removed, thereby leaving a portion of the shallow trench isolation structure 102 exposed.

[0067] As shown in Figure 11a, in the first direction, a portion of the second gate material 105 covering the shallow trench isolation structure 102 is simultaneously removed, and the shallow trench isolation structure 102 remains exposed.

[0068] The height of the shallow trench isolation structure is reduced to form the first separation section.

[0069] In another embodiment, a first insulating layer 104 is formed on the inner wall of the substrate groove, a sacrificial material is formed on the first insulating layer 104, and the sacrificial material fills the first groove 103. The sacrificial material and a portion of the first insulating layer 104 are removed to form a contact window on the side wall of the first slot segment 1031 of the substrate groove. The remaining sacrificial material is removed and gate material is filled in. The gate material and a portion of the first insulating layer 104 in the first groove 103 are removed to form a semi-floating gate and a gate insulating layer in the first slot segment 1031.

[0070] Here, the remaining gate material is a semi-floating gate, the remaining first insulating layer is a gate insulating layer, a portion of the semi-floating gate is in contact with the substrate through a contact window, and the other portion of the semi-floating gate and the substrate are separated through the gate insulating layer.

[0071] The sacrificial material is, for example, a silicon-rich composite material or another suitable dielectric material. Here, the gate material remaining in the first slot segment 1031 is a semi-floating gate, and the first insulating layer 104 remaining in the first slot segment 1031 is a gate insulating layer.

[0072] The following process will use the example where the semi-floating gate includes a second and a third gate.

[0073] Referring to Figures 12a and 12b, Figure 12a is a schematic diagram of the structure in the first direction of the embodiment forming the first separation portion in this application, and Figure 12b is a schematic diagram of the structure in the second direction of the embodiment forming the first separation portion in this application.

[0074] As shown in Figure 12a, in the first direction, based on Figure 11a, the exposed portion of the shallow trench isolation structure 102 is removed, that is, the height of the shallow trench isolation structure 102 is reduced, so that the height of the shallow trench isolation structure 102 is less than or equal to the height of the half-floating gate, forming the first separation section. As shown in Figure 12b, in the second direction, the structure of Figure 11b can be maintained.

[0075] In some embodiments, when the height of the shallow trench isolation structure 102 is reduced to form a first separation section, the remaining shallow trench isolation structure 102 can be made coplanar with the half-floating gate and can also be made into the first separation section.

[0076] Referring to Figures 13a and 13b, Figure 13a is a schematic diagram of the structure in the first direction of another embodiment in this application in which the shallow trench isolation structure is continuously reduced to form the first separation section. Figure 13b is a schematic diagram of the structure in the second direction of another embodiment in this application in which the shallow trench isolation structure is continuously reduced to form the first separation section.

[0077] As shown in Figure 13a, in the first direction, based on Figure 12a, a portion of the shallow trench isolation structure 102 is removed, the height of the shallow trench isolation structure 102 is made lower than the height of the half-floating gate, and the remaining portion of the shallow trench isolation structure 102 is made into the first separation section. As shown in Figure 13b, in the second direction, the first protective layer 420 can be removed.

[0078] In some embodiments, the removal process may first use wet etching followed by dry etching.

[0079] Step (S14): A gate-inter-gate dielectric layer and a first gate layer are formed in multiple first grooves. A portion of the first gate layer in the first groove of the storage region is removed to form the control gate of the storage unit. The first gate layer in the first groove of the extraction region is left as an extraction line for the storage unit, and the extraction line is connected to the control gates of multiple storage units in the same row. This is shown in Figures 16a and 16b.

[0080] The operation process of one embodiment of step (S14) is as follows, and includes forming an intergate dielectric layer, where the intergate dielectric layer covers at least the semi-floating gate.

[0081] Referring to Figures 14a and 14b, Figure 14a is a schematic diagram of the structure in the first direction of an embodiment for forming the intergate dielectric layer in this application. Figure 14b is a schematic diagram of the structure in the second direction of an embodiment for forming the intergate dielectric layer in this application.

[0082] As shown in Figure 14a, in the first direction, an intergate dielectric layer 500 is formed based on Figure 13a, and the intergate dielectric layer 500 covers the semi-floating gate in the first separation portion and the first slot segment 1031, forming a tooth-like structure and increasing the bonding area between the semi-floating gate and the control gate. As shown in Figure 14b, in the second direction, an intergate dielectric layer 500 is formed, thereby covering the portion of the first groove 103 on the semi-floating gate consisting of the second gate 1051 and the third gate 1061, and covering the hard mask layer 400 remaining between the two adjacent first grooves.

[0083] The intergate dielectric layer is coated with a first gate material, and any excess first gate material is removed until it is flush with the highest point of the first groove, i.e., the first gate material is flush with the highest point of the first groove.

[0084] Referring to Figures 15a and 15b, Figure 15a is a schematic diagram of the structure in the first direction of an embodiment for covering the first gate material in this application. Figure 15b is a schematic diagram of the structure in the second direction of an embodiment for covering the first gate material in this application.

[0085] As shown in Figure 15a, in the first direction, based on Figure 14a, the intergate dielectric layer 500 is covered with the first gate material 600, and any excess first gate material 600 is removed so that the first gate material 600 is flush with the highest point of the first groove 103. As shown in Figure 15b, in the second direction, based on Figure 14b, the intergate dielectric layer 500 is covered with the first gate material 600, and any excess first gate material 600 is removed so that the first gate material 600 is coplanar with the highest point of the first groove 103.

[0086] Part of the first gate material in the first groove 103 of the memory area ofThe remaining first gate material is removed until it does not rise above the highest point of the substrate groove, and the first gate material in the first groove 103 of the draw-out region is left as the first gate layer of the draw-out region and serves as the draw-out line of the storage unit, and the remaining first gate material is used as the first gate layer of the storage region to form the control gate of the storage unit.

[0087] Referring to Figures 16a and 16b, Figure 16a is a schematic diagram of the structure in the first direction of an embodiment in which a portion of the first gate material is removed in this application. Figure 16b is a schematic diagram of the structure in the second direction of an embodiment in which a portion of the first gate material is removed in this application.

[0088] As shown in Figure 16b, in the second direction, based on Figure 15b, a portion of the first gate material 600 in the first groove 103 of the storage area is removed to form an empty area 1033. In one embodiment, the highest point of the remaining first gate material 600 is less than or equal to the highest point of the base groove, and the remaining first gate material 600 becomes the first gate layer 610, that is, the height of the control gate of the storage area is less than or equal to the height of the base groove.

[0089] To more completely represent the device structure, the left side of the dashed line in Figure 16b is a cross-sectional view in which an empty region 1033 is formed in the second direction, and is a cross-sectional view in the direction of the memory region Y1 in Figure 19 below. The right side of the dashed line in Figure 16b is a cross-sectional view in which the first gate material 600 remains in the first groove 103 in the second direction, and the remaining first gate material 600 is used as the contact region of the control gate, i.e., the pull-out region, and is a cross-sectional view in the direction of the pull-out region Y2 in Figure 19 below. As shown in Figure 16b, the first gate material 600 above the substrate groove of the memory region is removed, and the first gate layer 610 is formed. As shown in Figure 16a, an empty region 620 is formed when viewed from the first direction.

[0090] A second insulating layer 700 is formed in the empty area 1033 of the first groove 103 and in the first gate material remaining in the first separation section.

[0091] Referring to Figures 17a and 17b, Figure 17a is a schematic diagram of the structure in the first direction of an embodiment for forming the second insulating layer in this application. Figure 17b is a schematic diagram of the structure in the second direction of an embodiment for forming the first groove of the second insulating layer in this application.

[0092] As shown in Figure 17a, in the first direction, a second insulating layer 700 is formed in the empty area 620 of the first gate material 600, based on Figure 16a. As shown in Figure 17b, in the second direction, a second insulating layer 700 is formed in the empty area 1033 of the first groove 103, based on Figure 16b, and chemical mechanical polishing is performed to flatten the surface. The material of the second insulating layer 700 is, for example, silicon oxide.

[0093] In some embodiments, in the second direction (the Y2 direction in Figure 19 below), the first gate material in the first groove 103 of the row in the drawer region is completely left. Here, the first gate material 600 left in the first groove 103 of the row in the drawer region serves as a connection point for the control gate in the storage unit, and the first gate layer 610 in the storage region and the outside world circuit It is used to establish a connection with [the specified entity].

[0094] In some embodiments, in the first direction, at least one first groove in the subsequent drawout area for each predetermined number of first grooves is shielded, leaving a portion of the first gate material 600 in the first groove 103 of the drawout area. Here, in the first direction, the first gate material 600 left in the first groove of the same row serves as the connection point for all control gates in the storage unit of that row, and in the storage area of ​​the same row Control gate and external circuit It is used to achieve connection with the outside. The gate contact region, i.e., the drawout region, may be formed at a fixed distance BL, for example, every 32 rows BL, thereby allowing the first gate layer 610 to connect to the outside via the gate contact region. circuit It is connected to this.

[0095] In some embodiments, the removal of all hard mask layers in the memory device is further included, where the second isolation portion is the portion of the shallow trench isolation structure 102 other than the exposed first isolation portion.

[0096] Referring to Figures 18a, 18b, and 19, Figure 18a is a schematic diagram of the structure in the first direction of an embodiment in which the hard mask layer is removed in this application, Figure 18b is a schematic diagram of the structure in the second direction of an embodiment in which the hard mask layer is removed in this application, and Figure 19 is a top view of the memory device in this application.

[0097] As shown in Figure 19, in the first direction, it can be divided into two type regions. Here, X1 is the first type region in the first direction, and Figure xa is a cross-sectional view of the first type region in the first direction, with the first separation part located in the first type region X1 in the first direction. X2 is the second type region in the first direction, with the second separation part located in the second type region X2 in the first direction. In the second direction, it can be divided into three type regions. Here, Y1 is the first type region in the second direction, i.e., the memory region, and the left side of the dashed line in Figure xb is a cross-sectional view of the first type region in the second direction, Y2 is the second type region in the second direction, and the right side of the dashed line in Figure xb is a cross-sectional view of the second type region in the second direction, i.e., the extraction region, and the third gate material in the second type region in the second direction is a contact region to the outside circuit It can be connected to Y3, which is a cross-sectional view of the third type region in the second direction, i.e., a cross-sectional view of the STI, and belongs to the memory region.

[0098] In the first direction, the first insulating layer 104 and hard mask layer 400 on the second separation portion of the shallow trench isolation structure in the second type region of the first direction are removed, and Figure 18a is a cross-sectional view of the first type region in the first direction, that is, the first insulating layer 104 and hard mask layer 400 do not exist on the first separation portion. As shown in Figure 18b, in the second direction, the region between two adjacent substrate grooves and the first insulating layer 104 and hard mask layer 400 on the second separation portion of the shallow trench isolation structure 102 in the second direction are removed.

[0099] multiple The first separation portion and multiple The second separation portion alternately in the Y3 direction. Distribution The second insulating layer and the third gate material, which are placed and remain in the substrate groove, are located in a second direction with different X-axis coordinates.

[0100] Spacer It forms.

[0101] Referring to Figures 20a and 20b, Figure 20a is in this application Spacer Figure 20b is a schematic diagram of the structure in the first direction of an embodiment forming the [object], and Figure 20b is the [object] of this application. Spacer This is a schematic diagram of the second direction of an embodiment that forms the structure.

[0102] As shown in Figure 20a, in the first direction, the structure is as shown in Figure 18a. As shown in Figure 20b, in the second direction, on both sides of the second insulating layer 700 and / or the first gate material 600 remaining in the substrate groove Spacer 800 is formed, that is, on both sides of the second insulating layer 700 left in the substrate groove of the memory area Spacer 800 is formed, as shown to the left of the dashed line in Figure 20b. On both sides of the first gate 610 in the base groove of the drawout region Spacer 800 is formed, as shown to the right of the dashed line in Figure 20b.

[0103] Referring to Figures 21a and 21b, Figure 21a shows the interlayer dielectric layer in this application. Contact plug Figure 21b is a schematic diagram of the structure in the first direction of an embodiment forming the interlayer dielectric layer in this application. Contact plug This is a schematic diagram of the second direction of an embodiment that forms the structure.

[0104] As shown in Figures 21a and 21b, the interlayer dielectric layer 900 is formed on the entire upper surface of the memory device, and the interlayer dielectric layer 900 covers the aforementioned structure. Contact plug 910 is formed within the interlayer dielectric layer 900, thereby Contact plug910 can be connected to all control gates of the same row of memory units.

[0105] In some embodiments, ion implantation is performed to form source and drain regions on the substrate on both sides of the first groove 103. The first dielectric layer 200 is removed, and the source region, drain region and Outlet wiring A metal silicide layer 210 is formed in the source region and drain region. Contact plug It can be installed.

[0106] This application further relates to a storage device, and as shown in Figures 21a, 21b, and 19, the cross-sectional view of the first class region X1 in the first direction is defined as the first cross-sectional view of the storage device in the first direction, and the cross-sectional views of the first class region Y1 in the second direction and the second class region Y2 in the second direction are defined as the second cross-sectional view of the storage device in the second direction, where the left side of the dashed line is the cross-sectional view of the first class region Y1 in the second direction, and the right side of the dashed line is the cross-sectional view of the second class region Y2 in the second direction.

[0107] The memory device includes a substrate, a substrate groove, a semi-floating gate, an inter-gate dielectric layer, and a first gate layer.

[0108] The substrate groove extends from one side surface of the substrate 100 to the substrate 100, and there are multiple substrate grooves, with a portion of the substrate groove located in the storage area and the other portion located in the drawer area, where a gate insulating layer 1041 is installed on the inner wall of the bottom of the substrate groove, as shown in Figure 21b.

[0109] The semi-floating gate is filled into the bottom of the substrate groove, a portion of the semi-floating gate is separated from the substrate 100 by the gate insulating layer 1041, and the other portion of the semi-floating gate is in contact with the substrate 100.

[0110] Here, the substrate groove includes a first slot segment and a second slot segment. The bottom of the substrate groove where the second gate 1051, the third gate 1061, and the gate insulating layer 1041 remain is the first slot segment, and the second slot segment is positioned above the first slot segment.

[0111] The intergate dielectric layer 500 covers the semi-floating gate.

[0112] The first gate layer 610 is installed on the intergate dielectric layer 500. Here, the first gate layer of the memory region constitutes the control gate of the memory unit within the memory device, the first gate layer of the extraction region becomes an extraction line, and the extraction line is connected to the control gates of multiple memory units in the same row.

[0113] In some embodiments, a shallow trench isolation structure 102 is formed on the substrate 100. multiple The shallow trench isolation structures are installed at intervals along the first direction, and Each shallow trench isolation structure is It extends along the second direction. Here, each The shallow trench isolation structure is alternately Placed multiple First separation unit and multipleThe shallow trench isolation structure 102 includes a second isolation section, the first isolation section is located within the substrate, and the second isolation section is installed protruding from the substrate. As shown in Figure 21a, in the first type region X1 in the first direction, the shallow trench isolation structure 102 is formed on the substrate, i.e., the height of the shallow trench isolation structure is lower than the height of the substrate, and in the second type region X2 in the first direction, the height of the shallow trench isolation structure is higher than the height of the substrate, thereby isolating the storage units in the storage device. The shallow trench isolation structure 102 is installed at intervals along the first direction and extends along the second direction, as shown in Figure 19. In the first type region X1 in the first direction, the shallow trench isolation structure 102 includes a first isolation section, which is formed between two adjacent substrate grooves in the first direction, and the highest point of the first isolation section in the third direction is lower than the highest point of the substrate grooves in the third direction. In the second type region X2 in the first direction, the shallow trench isolation structure 102 includes a second separation portion, and the highest point of the second separation portion in the third direction is higher than the highest point of the base groove in the third direction, i.e. multiple First separation unit and multiple The second separation section is alternately The first separation section is installed within the substrate, and the second separation section is installed protruding from the substrate. The third direction is vertical.

[0114] In some embodiments, the semi-floating gate includes a second gate 1051 and a third gate 1061, where the second gate 1051 is separated from the substrate 100 by a gate insulating layer 1041, and the third gate 1061 is in direct contact with the substrate 100. An intergate dielectric layer 500 covers the second gate 1051 and the third gate 1061.

[0115] In some embodiments, the intergate dielectric layer 500 also covers the first separation portion.

[0116] In some embodiments, at least the third gate in contact with the substrate is made of a single-crystal material.

[0117] In some embodiments, the first gate layer 610 includes a first portion of the first gate filled in a substrate groove and a second portion of the first gate located on a first separation portion. In a second direction, the first portions of the first gate in two adjacent substrate grooves are separated from each other, i.e., the control gates in two adjacent substrate grooves are separated from each other. In a first direction, the control gates in two adjacent substrate grooves are connected to each other by the first gate layer on the first separation portion between them.

[0118] In some embodiments, the height of the control gate is less than or equal to the height of the substrate groove, and the first gate layer further includes at least one third portion of the first gate, i.e., a lead line, which serves as a connection point, i.e., the height of the first gate layer in the substrate groove of the lead region is greater than the height of the substrate groove, and serves as a connection point between the control gate and the external circuit It is used to achieve connection with [the other component]. The control gate and the lead wire are connected via the first gate layer on the first separation section.

[0119] In the first direction, at least one corresponding lead line is provided for each predetermined number of control gates, and the lead line serves as a connection point between the control gates in the same row and the external circuit It is used to establish a connection with [the specified entity].

[0120] In some embodiments, the storage device has a second insulating layer, Spacer 800, interlayer dielectric layer 900 and Contact plug Further includes 910. The second insulating layer is the first of the substrate grooves in the memory area. Control gate Covering, Spacer 800 is Memory area Second insulating layer 700 and / or Outlet wiring in the outlet area Located on both sides, that is, on both sides of the second insulating layer of the memory area Spacer A is provided, and on both sides of the first gate layer of the drawout region Spacer A layer is formed. The interlayer dielectric layer 900 is on the substrate 100. The The 2nd insulating layer 700 and / or the 1st gate layer are covered. Contact plug 10 is located in the interlayer dielectric layer 900, where, Contact plug910 is connected to the first gate layer in the substrate groove of the drawout region.

[0121] In some embodiments, Contact plug 910 can also be connected to source and drain regions defined by substrate grooves.

[0122] In this application, a method for manufacturing a memory device includes providing a semiconductor substrate, the semiconductor substrate including a substrate and a hard mask layer placed on the substrate, forming a plurality of first grooves from the hard mask layer toward the active region of the substrate, a portion of the plurality of first grooves located in a storage region, and the other portions of the plurality of first grooves located in a drawout region, where the portion of the first grooves in the substrate is defined as a substrate groove, forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, a portion of the semi-floating gate in contact with the substrate, and the other portion of the semi-floating gate and the substrate separated by the gate insulating layer, forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves, removing a portion of the first gate layer in the first groove of the storage region to form a control gate of a memory unit, leaving the first gate layer in the first groove of the drawout region as a lead line of the memory unit, and the lead line connecting the control gates of a plurality of memory units in the same row. circuit This allows for contact with the control gate, solving the problem of voltage drop caused by the high embedded gate resistance of the control gate, while simultaneously lowering the operating voltage of the memory device and reducing power consumption.

[0123] The above describes embodiments of the present application and does not limit the scope of the patent of this application. Any equivalent structural or process transformations performed using the contents of the specification and drawings of this application, or any other related technical applications that are directly or indirectly applied, are similarly included within the scope of the patent protection of this application. [Explanation of Symbols]

[0124] 100 circuit boards 101 Second groove 102 Shallow trench isolation structure 103 1st groove 1031 First slot segment 1032 Second Slot Segment 1033 Free space 104 First insulating layer 1041 Gate Insulation Layer 105 Second Gate Material 1051 Gate 2 106 Third Gate Material 1061 Gate 3 200 First Dielectric Layer 210 Metal silicide layer 300 Second dielectric layer 400 Filling coating layer 410 Filled bed 420 First protective layer 500 Intergate dielectric layer 600 First Gateway Materials 610 First Grid Gate Layer 620 free spaces 700 2 insulating layers 800 Spacer 900 Intermittent Dielectric Layer 910 Contact plug

Claims

1. A step of providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a hard mask layer installed on the substrate, The hard mask layer forms a plurality of first grooves in the active region of the substrate, wherein a portion of the plurality of first grooves is located in the storage region, and the other portion of the plurality of first grooves is located in the draw-out region, and the first grooves in the substrate are defined as substrate grooves. A step of forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, wherein a portion of the semi-floating gate is in contact with the substrate, and the other portion of the semi-floating gate is separated from the substrate by the gate insulating layer, The steps include forming intergate dielectric layers and first gate layers in a plurality of first grooves, removing a portion of the first gate layer in the first groove of the storage region to form the control gate of the storage unit, leaving the first gate layer in the first groove of the extraction region as the extraction wiring of the storage unit, and connecting the control gates of a plurality of storage units in the same row. A method for manufacturing a storage device, including the method described above.

2. The method for manufacturing a storage device according to claim 1, wherein the height of the control gate is less than or equal to the height of the groove in the substrate.

3. The step of providing a semiconductor substrate is, A substrate is provided, and a first dielectric layer and a second dielectric layer are formed on the substrate. The second groove is formed from the second dielectric layer toward the substrate, wherein the second groove is spaced apart along the first direction and extends along the second direction. The second groove is filled with a separation material to form a shallow trench isolation structure, and ion implantation is performed on the substrate to form a first well region within the substrate. Removing the second dielectric layer to expose a part of the shallow trench isolation structure, The first dielectric layer is used as a barrier layer to perform ion implantation on the substrate to form a second well region on one side of the substrate, wherein the second well region is located above the first well region, and the doping type of the second well region is different from that of the first well region. A filling coating layer is formed on the first dielectric layer, and the first dielectric layer and the filling coating layer constitute the hard mask layer, wherein the filling coating layer is filled between two adjacent shallow trench isolation structures and covers the shallow trench isolation structures. A method for manufacturing a storage device according to claim 1, including the method described in claim 1.

4. The step of forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove is: A first insulating layer is formed on the inner wall of the substrate groove, a sacrificial material is formed on the first insulating layer, and the first groove is filled with the sacrificial material. The sacrificial material and a portion of the first insulating layer are removed to form a contact window, The remaining sacrificial material is removed, and the gate material is filled into the first groove. The method involves removing the gate material and a portion of the first insulating layer to form a semi-floating gate and a gate insulating layer at the bottom of the substrate groove, wherein the remaining gate material is the semi-floating gate, the remaining first insulating layer is the gate insulating layer, a portion of the semi-floating gate is in contact with the substrate via the contact window, and the other portion of the semi-floating gate is separated from the substrate by the gate insulating layer. A method for manufacturing a storage device according to claim 1, including the method described in claim 1.

5. The method for manufacturing a storage device according to claim 1, wherein the step of forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove comprises forming a gate insulating layer, a second gate and a third gate at the bottom of the substrate groove, wherein the second gate and the substrate are separated by the gate insulating layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to form a semi-floating gate of a storage unit in the storage device.

6. Forming a gate insulating layer, a second gate, and a third gate at the bottom of the substrate groove is, A first insulating layer is formed on the inner wall of the substrate groove, and a second gate material is filled into the first groove. A contact window is formed by removing a portion of the second gate material and a portion of the first insulating layer, and a third gate material is formed in the contact window. The method involves removing a portion of the second gate material, the third gate material, and the first insulating layer, leaving the second gate material, the third gate material, and the first insulating layer in the first slot segment of the substrate groove, wherein the remaining second gate material, the third gate material, and the first insulating layer become the second gate, the third gate, and the first insulating layer, respectively. A method for manufacturing a storage device according to claim 5, including the method described in claim 5.

7. The method for manufacturing a memory device according to claim 5, wherein at least the portion of the third gate that contacts the substrate is formed of a single crystal material.

8. A shallow trench isolation structure is provided within the substrate, wherein a portion of the shallow trench isolation structure is provided within the substrate, and the other portion of the shallow trench isolation structure is exposed from the substrate, and the shallow trench isolation structure is arranged at intervals along a first direction and extends along a second direction. A method for manufacturing a storage device according to claim 1, wherein after forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, a part of the shallow trench isolation structure is removed to form a first separation portion, and the height of the shallow trench isolation structure remaining in the first separation portion is less than or equal to the height of the semi-floating gate.

9. The steps of forming intergate dielectric layers and first gate layers in the plurality of first grooves, removing a portion of the first gate layer in the first groove of the storage region to form the control gate of the storage unit, and leaving the first gate layer in the first groove of the extraction region as the extraction wiring of the storage unit are as follows: The process involves forming the intergate dielectric layer, wherein the intergate dielectric layer covers at least the semi-floating gate. The intergate dielectric layer is covered with a first gate material, wherein the first gate material is flush with the highest point of the first groove. The method involves removing a portion of the first gate material in the first groove of the storage region until the remaining first gate material is below the highest point of the base groove, and leaving the first gate layer in the first groove of the drawer region as the drawer wiring of the storage unit, wherein the remaining first gate material becomes the first gate layer of the storage region, thereby forming the control gate of the storage unit. A method for manufacturing a storage device according to claim 1, including the method described in claim 1.

10. A method for manufacturing a storage device according to claim 9, wherein, in a first direction, for each predetermined number of first grooves, at least one of the first grooves in the draw-out area is shielded, leaving a portion of the first gate material in the first groove of the draw-out area, wherein, in the first direction, the first gate material left in the first groove of the same row serves as a connection point for all control gates in the storage unit of that row, thereby connecting the first gate layer in the storage area of ​​the same row to the outside world.

11. The method for manufacturing the aforementioned storage device is: A second insulating layer is formed in the empty area of ​​the first groove in the memory area, Removing the aforementioned hard mask layer, Forming separation barriers on both sides of the second insulating layer and / or the first gate material, Forming an interlayer dielectric layer, A connecting column is formed in the interlayer dielectric layer, and the connecting column is connected to the first gate material in the extraction region. A method for manufacturing a storage device according to claim 9, including the method described in claim 9.

12. A memory device comprising a substrate, a substrate groove, a semi-floating gate, an inter-gate dielectric layer, and a first gate layer, The substrate grooves extend from the side surface of the substrate toward the substrate, with some of the substrate grooves located in a storage area and other parts of the substrate grooves located in a drawer area, where a gate insulating layer is provided on the inner wall of the bottom of the substrate grooves. The semi-floating gate is filled into the bottom of the substrate groove, where a portion of the semi-floating gate is separated from the substrate by the gate insulating layer, and the other portion of the semi-floating gate is in contact with the substrate. The semi-floating gate is covered with the inter-gate dielectric layer, The first gate layer is provided in the intergate dielectric layer, and in the memory region, the first gate layer constitutes a control gate of a memory unit in the memory device, and in the drawer region, the first gate layer constitutes a drawer line, and the drawer line is connected to the control gates of a plurality of memory units in the same row, in a memory device.

13. The storage device according to claim 12, wherein the semi-floating gate includes a second gate and a third gate, the second gate being separated from the substrate by the gate insulating layer, and the third gate being in contact with the substrate.

14. The storage device according to claim 13, wherein at least the contact region between the third gate and the substrate is formed of a single-crystal material.

15. The storage device according to claim 12, wherein the shallow trench isolation structure is formed on the substrate, the shallow trench isolation structure is spaced apart along a first direction and extends along a second direction, the shallow trench isolation structure includes a spaced-apart first isolation portion and a second isolation portion, the first isolation portion is located within the substrate and the second isolation portion protrudes from the substrate.

16. The storage device according to claim 15, wherein the control gate and the lead wire are connected via the first gate layer on the first separation section.

17. The storage device according to claim 12, wherein the height of the control gate is less than or equal to the height of the substrate groove, and the height of the first gate layer in the substrate groove of the drawout region is greater than the height of the substrate groove and is used as a connection point to enable the first gate layer to connect to the outside world.

18. The storage device according to claim 12, wherein in a first direction, at least one corresponding lead line is provided for each of a preset number of control gates, and the lead line is used to connect to an external point, thereby enabling the control gates in the same row to connect to the outside.

19. The memory device further includes a second insulating layer, an isolation barrier, an interlayer dielectric layer, and connecting pillars. The first gate layer of the substrate groove in the memory region is covered with the second insulating layer. The separation barrier is arranged on both sides of the second insulating layer and / or the first gate layer remaining in the substrate groove, The substrate, the second insulating layer remaining in the substrate groove, and / or the first gate layer are covered with the interlayer dielectric layer. The storage device according to claim 12, wherein the connecting column is arranged in the interlayer dielectric layer, and thereafter the connecting column is connected to the first gate layer of the drawout region.

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