Display panels and display devices

Abstract

The present invention provides a display panel and a display device. The display panel includes a plurality of pixel circuits (100), an insulating material layer (ISL), a plurality of pixel electrodes (E1), an emissive function layer (EML), and a separation structure (600). The insulating material layer (ISL) is located on the plurality of pixel circuits and includes a plurality of organic insulating layers, each organic insulating layer includes an organic material. The pixel electrodes are located on the plurality of organic insulating layers and are connected to one pixel circuit. The emissive function layer (EML) includes a common layer (CL), and the separation structure (600) has protruding parts that extend from the organic insulating layer below it. The separation structure (600) has a (PR), or the separation structure itself has a protruding portion (PR), the separation structure (600) is arranged to block the common layer (CL) at the protruding portion (PR), the separation structure (600) is located between adjacent pixel electrodes (E1), includes an inorganic material, the separation structure (600) is located on at least a portion of an organic insulating layer, and the separation structure (600) and the plurality of pixel electrodes (E1) are separated by at least a portion of an organic insulating layer, which is advantageous for improving the display effect and avoids crosstalk.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, organic light emitting diode (OLED) display devices have become current research focuses and the direction of technological development for various manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-luminescence and wide viewing angle.

[0003] At present, organic light emitting diode display devices are widely applied in various electronic products ranging from small electronic products such as smart bracelets, smart watches, smart phones and tablet computers to large electronic products such as notebook computers, desktop computers and televisions. Accordingly, market demand for active matrix organic light emitting diode display devices is also strong. Summary of the Invention Problem to be Solved by the Invention

[0004] Embodiments of the present disclosure provide a display panel and a display device. Means for Solving the Problem

[0005] Embodiments of the present disclosure provide a display panel comprising a base substrate, a plurality of pixel circuits, an insulating material layer, a plurality of pixel electrodes, a light-emitting functional layer, and a separation structure, wherein the plurality of pixel circuits are located on the base substrate, the insulating material layer is located on the side of the plurality of pixel circuits away from the base substrate and comprises a plurality of organic insulating layers, each of the plurality of organic insulating layers comprises an organic material, the pixel electrodes are located on the side of the plurality of organic insulating layers away from the base substrate and are connected to one of the plurality of pixel circuits, and the light-emitting functional layer comprises a common layer, the base of the common layer The orthographic projection on the plate overlaps with the orthographic projection of the plurality of pixel electrodes on the base substrate, at least a portion of the common layer is located on the side of the plurality of pixel electrodes away from the base substrate, the separation structure has a protrusion that protrudes from the organic insulating layer below it, or has a protrusion itself, the separation structure is positioned so as to block the common layer at the protrusion, the separation structure is located between adjacent pixel electrodes, comprises an inorganic material, the separation structure is located on at least a portion of the organic insulating layer, and the separation structure and the plurality of pixel electrodes are separated by at least a portion of the organic insulating layer.

[0006] For example, the organic insulating layer located below the separation structure has grooves or first through holes in the protruding portion.

[0007] For example, the organic insulating layer located above the separation structure has a second through-hole in the protruding portion, and the first through-hole and the second through-hole are in communication with each other.

[0008] For example, the display panel further includes a pixel definition layer, the pixel definition layer having a plurality of first openings, each of which is arranged to expose one of the plurality of pixel electrodes, and the pixel definition layer further has a second opening, the second opening communicating with the second through-hole.

[0009] For example, the orthographic projection of the second opening on the base substrate overlaps with the orthographic projection of the separation structure on the base substrate.

[0010] For example, the separation structure has a protrusion in the groove or the first through hole.

[0011] For example, the groove or first through-hole is elongated, the separation structure includes two separation parts in the groove or first through-hole, each of the two separation parts forms two protrusions, the two protrusions are located within the groove or first through-hole and on opposite sides of the elongated groove or first through-hole.

[0012] For example, the display panel further includes a common electrode, at least a portion of which is located on the side of the light-emitting functional layer away from the base substrate, and the plurality of pixel electrodes, the light-emitting functional layer, and the common electrode constitute a plurality of light-emitting elements.

[0013] For example, an isolation structure surrounding a single light-emitting element may include multiple isolation substructures.

[0014] For example, the plurality of separation substructures include at least two separation substructures located on opposite sides of the light-emitting region of the light-emitting element.

[0015] For example, the distance between at least one of the plurality of isolated substructures and the two adjacent light-emitting elements is not equal.

[0016] For example, the light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the light-emitting region of the first light-emitting element is smaller than the light-emitting region of the second light-emitting element, the light-emitting region of the second light-emitting element is smaller than the light-emitting region of the third light-emitting element, and the separation structure includes a first separation structure and a second separation structure, wherein the first separation structure is located on the outer periphery of the light-emitting region of the first light-emitting element, and the second separation structure is located on the outer periphery of the light-emitting region of the second light-emitting element.

[0017] For example, the first separation structure includes two first separation substructures located on opposite sides of the light-emitting region of the first light-emitting element, the second separation structure includes four second separation substructures, the four second separation substructures are arranged surrounding the light-emitting region of the second light-emitting element, two of the four second separation substructures are located on opposite sides of the light-emitting region of the second light-emitting element, and the other two second separation substructures are located on opposite sides of the light-emitting region of the second light-emitting element.

[0018] For example, the light-emitting region of the first light-emitting element is surrounded by two first isolation substructures and two second isolation substructures located in the notches of the first isolation substructures.

[0019] For example, the light-emitting region of the third light-emitting element is surrounded by four first isolation substructures and two second isolation substructures.

[0020] For example, the common electrode is not divided in the separation structure.

[0021] For example, the first light-emitting element is arranged to emit green light, the second light-emitting element is arranged to emit red light, and the third light-emitting element is arranged to emit blue light.

[0022] For example, the separation structure does not come into contact with the plurality of pixel electrodes.

[0023] For example, the separation structure includes a passivation layer, the passivation layer is arranged to form the protrusion, the inorganic material includes an inorganic nonmetallic material, and the inorganic material is an insulating material.

[0024] For example, the inorganic material includes a metallic material, and the separation structure includes a first sublayer, a second sublayer, and a third sublayer that are stacked and arranged in sequence, wherein the first sublayer is closer to the base substrate than the third sublayer, and the third sublayer protrudes outward relative to the second sublayer to form the protruding portion.

[0025] For example, the plurality of organic insulating layers include a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer that are sequentially disposed, the first organic insulating layer is closer to the base substrate than the third organic insulating layer, and in a direction perpendicular to the base substrate, the isolation structure is located on at least a portion of the first organic insulating layer and located under at least a portion of the third organic insulating layer.

[0026] For example, the display panel further includes a first connection electrode and a second connection electrode, the pixel circuit includes a transistor, the first connection electrode is located on the first organic insulating layer and connected to the transistor through a via hole penetrating the first organic insulating layer, the second connection electrode is located on the second organic insulating layer and connected to the first connection electrode through a via hole penetrating the second organic insulating layer, and the pixel electrode is located on the third organic insulating layer and connected to the second connection electrode through a via hole penetrating the third organic insulating layer.

[0027] For example, the insulating material layer further includes an inorganic insulating material layer, the inorganic insulating material layer is located between the transistor and the first organic insulating layer, and the first connection electrode also penetrates the inorganic insulating material layer.

[0028] For example, the display panel has a bending region.

[0029] For example, the display panel has a hole region, a plurality of isolation structures are disposed, and at least a part of the plurality of isolation structures are located in a frame region close to the hole region.

[0030] Embodiments of the present disclosure further provide a display device, including any one of the above display panels.

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. Obviously, the drawings described below are only related to some embodiments of the present disclosure, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] [Figure 1] Figure 1 is a schematic diagram of a light-emitting element. [Figure 2] Figure 2 is a cross-sectional view of the display panel. [Figure 3] Figure 3 is a cross-sectional view of the display panel. [Figure 4] Figure 4 is a plan view of the display panel. [Figure 5] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 6] Figure 6 is a magnified view of a portion of Figure 5. [Figure 7] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 8] Figure 8 is a magnified view of a portion of Figure 7. [Figure 9] Figure 9 is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 10] Figure 10 is a cross-sectional view of several display panels according to embodiments of the present disclosure. [Figure 11] Figure 11 is a cross-sectional view of several display panels according to embodiments of the present disclosure. [Figure 12] Figure 12 is a cross-sectional view of several display panels according to embodiments of this disclosure. [Figure 13] Figure 13 is a cross-sectional view of several display panels according to embodiments of this disclosure. [Figure 14] Figure 14 is a cross-sectional view of several display panels according to embodiments of this disclosure. [Figure 15A] Figure 15A is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 15B] Figure 15B is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 16A] Figure 16A is a schematic diagram of the area division of a display panel according to an embodiment of the present disclosure. [Figure 16B] Figure 16B is a schematic diagram of the area division of another display panel according to an embodiment of the present disclosure. [Figure 17]Figure 17 is a schematic diagram of the area division of another display panel according to an embodiment of the present disclosure. [Figure 18] Figure 18 is a cross-sectional view of several display panels according to embodiments of this disclosure. [Figure 19] Figure 19 is a cross-sectional view of several display panels according to embodiments of the present disclosure. [Figure 20] Figure 20 is a cross-sectional view of several display panels according to embodiments of this disclosure. [Figure 21] Figure 21 is a cross-sectional view of several display panels according to embodiments of the present disclosure. [Modes for carrying out the invention]

[0033] To further clarify the purpose, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. As will be obvious, the embodiments described are a part of the embodiments of this disclosure, not all of them. All other embodiments obtained by a person skilled in the art without requiring any creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by those skilled in the art. The terms “First,” “Second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similar terms such as “Includes” or “Incorporates” mean that the element or component listed before the term covers the elements or components and equivalents listed after the term, but do not exclude other elements or components. Similar terms such as “Connected” or “Linked” are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect.

[0035] With the continuous development of display technology, people's pursuit of display quality is also increasing. To further reduce power consumption, extend service life, and achieve high brightness, one light-emitting layer of the OLED display panel's light-emitting element is replaced with two light-emitting layers, the charge generation layer (CGL) is increased between the two light-emitting layers, and N-type doped charge generation layers and P-type doped charge generation layers (N / P-CGL) are used as a heterojunction. The two light-emitting device structures are connected in series to form a double-layer design, constituting a Tandem structure. Tandem structure display panels realize the series connection of double light-emitting devices, significantly reducing the light-emitting current of the light-emitting elements under the same light intensity, extending the service life of the light-emitting elements, and are advantageous for the development and mass production of new technologies for long-life applications such as automotive. Tandem structure display devices have advantages such as long lifespan, low power consumption, and high brightness.

[0036] Figure 1 is a schematic diagram of a light-emitting element. Figure 1(a) is a schematic diagram of a typical light-emitting element. Figure 1(b) is a schematic diagram of a light-emitting element having a tandem structure. As shown in Figure 1(b), the charge generation layers (CGLs) between light-emitting elements with different tandem structures are connected.

[0037] Figure 1 shows the pixel electrode E1, common electrode E2, hole transport layer HTL, electron transport layer ETL, photocoupling layer CPL, increased permeability layer ARL, P-type doped charge generation layer P-CGL, N-type doped charge generation layer N-CGL, light emission layer R, light emission layer G, and light emission layer B. As shown in Figure 1, the hole transport layer HTL includes hole transport layer HTL-1 and hole transport layer HTL-2. As shown in Figure 1, the electron transport layer ETL includes electron transport layer ETL-1 and electron transport layer ETL-2.

[0038] As shown in Figure 1, the light-emitting layer R includes two sublayers containing light-emitting material R1 and light-emitting material R2, respectively; the light-emitting layer G includes two sublayers containing light-emitting material G1 and light-emitting material G2, respectively; and the light-emitting layer B includes light-emitting material B1 and light-emitting material B2. Light-emitting materials R1 and R2 are two different materials that emit red light, light-emitting materials G1 and G2 are two different materials that emit green light, and light-emitting materials B1 and B2 are two different materials that emit blue light.

[0039] Figure 1 shows the light-emitting functional layer EML located between the pixel electrode E1 and the common electrode E2, which includes a common layer CL and a local layer LL. The local layer LL includes light-emitting layers R, G, and B. The common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3. As shown in Figure 1, the first common layer CL1 includes a hole transport layer HTL-1, the second common layer CL2 includes an electron transport layer ETL-1, a charge generation layer N-CGL, a charge generation layer P-CGL, and a hole transport layer HTL-2, and the third common layer CL3 includes an electron transport layer ETL-2.

[0040] For example, the common layer CL may be fabricated using an aperture mask, and the local layer LL may be fabricated using a fine metal mask, but is not limited to these.

[0041] Figure 2 is a cross-sectional view of the display panel. As shown in Figure 2, the display panel includes a plurality of sub-pixels SP. Figure 2 shows sub-pixel SP1 and pixel SP2. It includes a plurality of pixel circuits 100 and a plurality of light-emitting elements 200. As shown in Figure 2, the pixel circuit 100 includes transistors T1 and T2. Figure 2 shows light-emitting elements EM1 and EM2. For example, the light-emitting elements 200 include, but are not limited to, organic light-emitting diodes.

[0042] The inventors focused on the following: In high-resolution products, the common layer CL, such as the charge generation layer, is shared by multiple subpixels. The doping concentration of the charge generation layer is high, the charge generation layer has strong conductivity, and the charge generation layers of the light-emitting functional layers of adjacent subpixels are connected. Therefore, layers with high conductivity in the common layer CL, such as the charge generation layer, are prone to causing crosstalk between adjacent subpixels, affecting the image quality of the product and thus having a serious impact on display quality.

[0043] For example, crosstalk between adjacent subpixels refers to a situation where an element that should not emit light emits light. As shown in Figure 2, if the desired situation is that element EM1 emits light but element EM2 does not, the conductivity of the charge generation layer causes element EM2 to also emit light, which causes lateral leakage of light and forms crosstalk.

[0044] To prevent light leakage from the sides, structures such as spacer columns can be installed, thereby mitigating or preventing light leakage from the sides, improving image quality, and being particularly advantageous for improving low-gradation image quality.

[0045] Figure 3 is a cross-sectional view of the display panel. Figure 4 is a plan view of the display panel.

[0046] As shown in Figure 3, a separation structure 06 (indicated by the dashed frame F1) is installed. A passivation layer PVX2 is installed on the planarization layer PLN3, and grooves or through holes are provided where the passivation layer PVX2 is installed on the planarization layer PLN3, thereby forming a separation structure 06 to block the common layer in the light-emitting functional layer, thereby mitigating or preventing lateral light leakage and improving image quality.

[0047] Figure 4 shows subpixels SP1, SP2, and SP3. For example, two subpixels SP1, one subpixel SP2, and one subpixel SP3 constitute one repeating unit PX. Subpixel SP1 includes a light-emitting element 201, subpixel SP2 includes a light-emitting element 202, and subpixel SP3 includes a light-emitting element 203. A subpixel is indicated by the light-emitting region of its light-emitting element. As shown in Figure 4, position P2 is the outer edge of the light-emitting region of the subpixel's light-emitting element. Position P3 is the outer edge of the passivation layer PVX2 for forming the isolation structure 06. Position P1 is the location of the isolation structure 06. The outermost arc-shaped portion of the light-emitting element shown in Figure 4 is an opening in the pixel definition layer PDL that exposes the isolation structure 06.

[0048] For example, as shown in Figure 3, the size of the passivation layer PVX2 is about 3 μm larger than the size of the pixel electrode. For example, the size of the passivation layer PVX2 is greater than 20 μm, and the gap between adjacent passivation layers PVX2 is about 5 μm, which leads to a serious shortage of pattern design space. As shown in Figure 3, in order to expose the isolation structure 06, the outer boundary of the pixel definition layer PDL is always smaller than the outer boundary of the passivation layer PVX2.

[0049] However, the display panel shown in Figure 3 has at least one of the following problems: First, the passivation layer PVX2 is placed between the pixel electrode E1 and the planarization layer PLN3 (for example, at the location of the dashed frame F3), and the flatness of the passivation layer PVX2 is lower than that of the planarization layer, resulting in the pixel electrode E1 not being flat, leading to a decrease in light efficiency and being detrimental to improving the display effect. Second, the pixel definition layer PDL comes into contact with the passivation layer PVX2 for forming the separation structure 06 (at the location of the dashed frame F2), and a situation in which the pixel definition layer PDL is separated from the passivation layer PVX2 is likely to occur. Third, the area of ​​the passivation layer PVX2 for forming the separation structure 06 is large, which is detrimental to gas release in the planarization layer below it. Fourth, due to the limitations on the spacing of the pixel electrodes, the separation structure can only be installed on one side. Fifth, the passivation layer PVX2 has a serious impact on the bending performance of the display panel.

[0050] Other structures shown in Figures 2 and 3 can be found in the descriptions of other cross-sectional views; they are not described here.

[0051] Embodiments of this disclosure provide a display panel and a display device including the display panel, wherein the pixel electrode E1 and the separation structure are separated by at least a portion of the planarization layer, which is advantageous for planarization of the pixel electrode E1 and advantageous for improving the display effect. The following description will be made with reference to Figures 5 to 21.

[0052] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 6 is a partially enlarged view of Figure 5. Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 8 is a partially enlarged view of Figure 7. Figure 9 is a plan view of a display panel according to an embodiment of the present disclosure. Figures 10 to 14 are cross-sectional views of several display panels according to an embodiment of the present disclosure. Figure 15A is a plan view of a display panel according to an embodiment of the present disclosure. Figure 15B is a plan view of a display panel according to an embodiment of the present disclosure. Figure 16A is a schematic diagram of the area division of a display panel according to an embodiment of the present disclosure. Figure 16B is a schematic diagram of the area division of another display panel according to an embodiment of the present disclosure. Figure 17 is a schematic diagram of the area division of another display panel according to an embodiment of the present disclosure. Figures 18 to 21 are cross-sectional views of several display panels according to an embodiment of the present disclosure.

[0053] As shown in Figures 5-8, 10-14, and 18-21, embodiments of the present disclosure provide a display panel comprising a base substrate BS, a plurality of pixel circuits 100, an insulating layer ISL, a plurality of pixel electrodes E1, a light-emitting functional layer EML, and a separation structure 600. The plurality of pixel circuits 100 are located on the base substrate BS. The insulating layer ISL is located on the side of the plurality of pixel circuits 100 away from the base substrate BS and includes a plurality of planarization layers, each planarization layer containing an organic material. The pixel electrodes E1 are located on the side of the plurality of planarization layers away from the base substrate BS and are connected to one of the plurality of pixel circuits 100. The light-emitting functional layer EML includes a common layer CL, the orthographic projection of the common layer CL on the base substrate BS overlaps with the orthographic projection of the plurality of pixel electrodes E1 on the base substrate BS, and at least a portion of the common layer CL is located on the side of the plurality of pixel electrodes E1 away from the base substrate BS. As shown in Figures 5-8, 10-14, 18-19, and 21, the separation structure 600 has a protrusion PR that extends from the planarization layer below it, or, as shown in Figure 20, the separation structure 600 itself has a protrusion PR. As shown in Figures 7 and 8, the separation structure 600 is positioned so as to block the common layer CL at the protrusion PR. As shown in Figures 5-8, 10-14, and 18-21, the separation structure 600 is located between adjacent pixel electrodes E1, contains an inorganic material, is located on at least a portion of the planarization layer, and is separated from the separation structure 600 and the multiple pixel electrodes E1 by at least a portion of the planarization layer. For example, the separation of the separation structure 600 and the multiple pixel electrodes E1 by at least a portion of the planarization layer means that at least a portion of one planarization layer is installed between the separation structure 600 and the multiple pixel electrodes E1. A cross-sectional view of this disclosure shows a planarization structure layer PLN composed of multiple planarization layers.

[0054] The display panel according to the embodiment of this disclosure has at least one of the following effects: First, the separation structure 600 has a protruding portion PR that protrudes from the planarization layer below it, or the separation structure 600 itself has a protruding portion PR, and the pixel electrode E1 and the separation structure 600 are separated by at least a portion of the planarization layer, ensuring flatness, which is advantageous for planarization of the pixel electrode E1, improving light efficiency, and advantageous for improving the display effect. Second, the pixel electrode E1 and the separation structure 600 are separated by at least a portion of the planarization layer, the separation structure 600 is located below the pixel electrode E1, and even if there is a limitation that the spacing between the pixel electrodes is small, both-sided blocking (bidirectional blocking) can be performed, improving the blocking effect. Third, the pixel definition layer does not directly contact the structure forming the separation structure 600, avoiding the risk of the pixel definition layer being separated. Fourth, the structure forming the separation structure 600 can be made smaller, which is advantageous for gas release of the planarization layer in the annealing process, and reduces the risk of gas release (outgas) due to the subsequent high-temperature process. Fifth, the impact on the bending performance of the display panel can be reduced. Sixth, lateral crosstalk between adjacent subpixels can be avoided. For example, the structure forming the isolation structure 600 includes the passivation layer PVX2, which will be mentioned later.

[0055] For example, the common layer CL includes, but is not limited to, a charge generation layer.

[0056] For example, as shown in Figures 5-8, 10-14, 18-19, and 21, the separation structure 600 includes a passivation layer PVX2, and the placement of the passivation layer PVX2 is used to form a protruding portion PR. Figure 20 shows a situation in which the separation structure 600 itself includes a protruding portion PR.

[0057] For example, as shown in Figures 5 to 8, Figures 10 to 14, and Figures 18 to 21, the multiple planarization layers include planarization layer PLN1, planarization layer PLN2, and planarization layer PLN3, which are installed in order, with planarization layer PLN1 being closer to the base substrate BS than planarization layer PLN3, and in a direction perpendicular to the base substrate BS, the separation structure 600 is located above at least some of the planarization layers and below at least some of the planarization layers.

[0058] For example, the flattening layer PLN1 may be called the first flattening layer, the flattening layer PLN2 may be called the second flattening layer, and the flattening layer PLN3 may be called the third flattening layer, but is not limited to these.

[0059] In the embodiments of this disclosure, the number of planarization layers is not limited to those shown, and at least two planarization layers may be installed. For example, three or more planarization layers may be installed, depending on the layer structure of the display panel.

[0060] For example, as shown in Figures 5-8, 10-12, 14, 19, and 21, the flattening layer located below the separation structure 600 has a groove GRV or a first through-hole H1 in the protruding portion PR. For example, the passivation layer PVX2 protrudes from the flattening layer located below it in the groove GRV or the first through-hole H1 to form the protruding portion PR.

[0061] For example, in the embodiments of this disclosure, the distance between the protrusion PR and the bottom surface of the groove GRV or the first through-hole H1 is 0.4 μm or more in order to better perform the blocking role.

[0062] For example, in the embodiments of this disclosure, in order to better perform the blocking role, the distance between the protrusion PR and the bottom surface of the groove GRV or the first through hole H1 is 0.4 μm or more and 2 μm or less.

[0063] For example, in the embodiments of this disclosure, the protrusion size of the lateral projection PR is 0.1 μm or larger in order to better perform the blocking role.

[0064] As shown in Figures 5-8, 10-12, 14, 19, and 21, the planar layer located below the separation structure 600 has a groove GRV in the protruding portion PR. As shown in Figures 13 and 18, the planar layer located below the separation structure 600 has a first through-hole H1 in the protruding portion PR. In the embodiments of this disclosure, the groove GRV does not penetrate the planar layer located below the separation structure 600, while the first through-hole H1 penetrates the planar layer located below the separation structure 600. As shown in Figure 8, providing the groove GRV or the first through-hole H1 is advantageous because, when a common layer CL is subsequently formed, a portion of the common layer CL is located within the groove GRV or the first through-hole H1, which is advantageous for the common layer CL to be divided at the protruding portion PR of the separation structure 600. Figure 8 shows the separation portion CL11 formed by the division of the first common layer CL1 at the separation structure 600 and the separation portion CL21 formed by the division of the second common layer CL2 at the separation structure 600.

[0065] Note that the configuration of at least one of the separation section CL11 or separation section CL21 may differ from that shown in Figure 8. For example, in some embodiments, at least one of the separation section CL11 or separation section CL21 may cover the side wall of the groove GRV or the first through hole H1.

[0066] Figures 7 and 8 illustrate an example in which the electron transport layer ETL-2 and the common electrode E2 are continuous in the separation structure 600. Embodiments of this disclosure are not limited thereto. In some other embodiments, the electron transport layer ETL-2 and the common electrode E2 may be separated in the separation structure 600. Whether or not the common electrode E2 is separated in the separation structure 600 may be related to the size of the projection PR and / or the depth of the groove GRV or first through hole H1 below the projection PR. Of course, in some other embodiments, the display panel may be fitted with the electron transport layer ETL-2.

[0067] For example, as shown in Figures 5 to 8, 10 to 12, 14, 19 and 21, the flattening layer located above the separation structure 600 has a second through-hole H2 in the protruding portion PR, and the first through-hole H1 and the second through-hole H2 are in communication.

[0068] For example, as shown in Figures 5-8, 10-12, 14, 19, and 21, the maximum size of the first through-hole H1 is smaller than the maximum size of the second through-hole H2.

[0069] For example, as shown in Figures 9, 15A, and 15B, the passivation layer PVX2 extends around the light-emitting region of the light-emitting element, and the maximum size of the first through-hole H1 in the direction perpendicular to the extension direction of the passivation layer PVX2 is smaller than the maximum size of the second through-hole H2 in the direction perpendicular to the extension direction of the passivation layer PVX2. That is, the maximum width of the first through-hole H1 is smaller than the maximum width of the second through-hole H2.

[0070] For example, as shown in Figures 5-6, 10-12, 14, 19 and 21, the display panel further includes a pixel definition layer PDL, the pixel definition layer PDL has a plurality of first apertures PN1, each of which is arranged to expose one of a plurality of pixel electrodes E1, and the pixel definition layer PDL further has a second aperture PN2, the second aperture PN2 is in communication with a second through-hole H2. The second aperture PN2 is arranged to expose a separation structure 600, thereby advantageous for the common layer CL to be separated in the separation structure 600.

[0071] For example, as shown in Figures 5-6, 10-12, 14, 19, and 21, the orthographic projection of the second opening PN2 on the base substrate BS overlaps with the orthographic projection of the separation structure 600 on the base substrate BS, thereby making it advantageous for the second opening PN2 to expose the separation structure 600.

[0072] As shown in Figures 5-8, 10-12, 14, 19, and 21, the main body of the pixel definition layer PDL does not come into contact with the passivation layer PVX that forms the separation structure 600, thereby avoiding the phenomenon of the pixel definition layer PDL being easily separated. The main body of the pixel definition layer PDL has a structure that contains the material of the pixel definition layer.

[0073] For example, as shown in Figure 10, the separation structure 600 has one protrusion PR in the groove GRV or the first through hole H1. That is, the separation structure 600 forms a one-sided structure, achieving isolation of the common layer CL on one side. In the case of one-sided isolation (unidirectional isolation), the occupied area of ​​the passivation layer PVX2 and the separation structure 600 can be reduced.

[0074] For example, as shown in Figure 10, the thickness of the passivation layer PVX2 may be approximately 0.07 μm, and the width of the passivation layer PVX2 may be designed to be approximately 3 μm.

[0075] For example, in other embodiments of this disclosure, the thickness of the passivation layer PVX2 may be set to approximately 0.07 μm. Of course, the thickness of the passivation layer PVX2 is not limited to the above.

[0076] For example, as shown in Figures 5-6, 11-12, 14, 19, and 21, in order to improve the blocking effect, the separation structure 600 includes two separation parts, namely separation part PT1 and separation part PT2, in the groove GRV or first through hole H1, and the two separation parts each form two protrusions PR, namely protrusions PR1 and protrusions PR2. Protrusion PR1 is formed in separation part PT1, and protrusion PR2 is formed in separation part PT2. This forms a double-sided structure between two adjacent subpixels (two adjacent light-emitting elements), achieving blocking of the common layer CL on both sides, which is even more advantageous for blocking the common layer CL. As shown in Figures 9, 15A, and 15B, the groove GRV or first through hole H1 is elongated. Referring to the partial cross-sectional view and the plan view shown in Figure 9, the two protrusions PR are located within the groove GRV or first through hole H1 and are located on opposite sides of the elongated groove GRV or first through hole H1. One of the two protrusions PR is positioned closer to the light-emitting region of the light-emitting element than the other. The shape of the second opening PN2 in the plan view is similar to the shape of the groove GRV or the first through-hole H1, but the size of the groove GRV or the first through-hole H1 may be slightly smaller than the size of the second opening PN2.

[0077] Whether to form a unilateral or bilateral separation structure can be determined by the distance between two adjacent light-emitting elements.

[0078] For example, as shown in Figures 7 and 8, the display panel further includes a common electrode E2, at least a portion of which is located away from the base substrate BS of the light-emitting functional layer EML, and the multiple pixel electrodes E1, the light-emitting functional layer EML, and the common electrode E2 constitute multiple light-emitting elements 200. Figures 7 and 8 show light-emitting elements EM1 and EM2. Figures 9, 15A, and 15B show multiple light-emitting elements 200.

[0079] Figures 7 and 8 show the light-emitting functional layer EML and the common electrode E2. For other display panels in cross-sectional views where the light-emitting functional layer EML and the common electrode E2 are not shown, refer to those shown in Figure 7.

[0080] For example, as shown in Figures 5-8, 10-12, 14, 19, and 21, the passivation layer PVX2 for forming the separation structure 600 protrudes laterally from the planarization layer below it and laterally from the planarization layer above it. For example, the laterally direction refers to the direction parallel to the main surface of the base substrate.

[0081] For example, as shown in Figures 5-8, 10-12, 14, 19, and 21, in order to facilitate the formation of the separation structure 600, a portion of the lower surface of the passivation layer PVX2 is in contact with the upper surface of the flattening layer located below the passivation layer PVX2, while a portion of the lower surface of the passivation layer PVX2 is not in contact with the upper surface of the flattening layer located below the passivation layer PVX2.

[0082] For example, as shown in Figures 5-8, 10-12, 14, 19, and 21, in order to facilitate the formation of the separation structure 600, a portion of the lower surface of the passivation layer PVX2 is in contact with the upper surface of the flattening layer located above the passivation layer PVX2, while a portion of the lower surface of the passivation layer PVX2 is not in contact with the upper surface of the flattening layer located above the passivation layer PVX2.

[0083] For example, in some embodiments, the material of the light-emitting functional layer EML is coated on at least some of the sides of the protruding portion PR of the passivation layer PVX2. For example, the material of at least one of the common layer CL and the local layer LL is coated on at least some of the sides of the protruding portion PR of the passivation layer PVX2. For example, the common layer CL is coated on at least some of the sides of the protruding portion PR of the passivation layer PVX2. In embodiments of this disclosure, the protruding portion PR has a bottom surface, a top surface, and sides located between the top surface and the bottom surface. The bottom surface of the protruding portion PR is closer to the base substrate than the top surface.

[0084] If the material of the light-emitting functional layer EML is coated on at least some of the sides of the protrusion PR of the passivation layer PVX2, the protrusion PR also plays a role in separating at least one film layer of the common layer CL.

[0085] For clarity in the illustrations, Figures 7 and 8 do not show the material of the light-emitting functional layer EML on the side surface of the protruding portion PR of the passivation layer PVX2.

[0086] For example, as shown in Figures 9, 15A, and 15B, the light-emitting element 200 includes a first light-emitting element 201, a second light-emitting element 202, and a third light-emitting element 203. Subpixel SP1 includes the first light-emitting element 201 and a pixel circuit connected to the first light-emitting element 201 (not shown in Figures 9, 15A, and 15B). Subpixel SP2 includes the second light-emitting element 202 and a pixel circuit connected to the second light-emitting element 202 (not shown in Figures 9, 15A, and 15B). Subpixel SP3 includes the third light-emitting element 203 and a pixel circuit connected to the third light-emitting element 203 (not shown in Figures 9, 15A, and 15B).

[0087] For example, as shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding one light-emitting element 200 includes multiple isolation substructures 660. As shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding a light-emitting element 201 includes two isolation substructures 660. As shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding a light-emitting element 202 includes four isolation substructures 660.

[0088] For example, as shown in Figures 9, 15A, and 15B, the plurality of separation substructures 660 include at least two separation substructures 660 located on opposite sides of the light-emitting region of the light-emitting element 200 (position P2 is the outer edge of the light-emitting region and corresponds to the first aperture PN1). This arrangement is advantageous for forming a notch G0 between adjacent separation substructures 660. Providing the notch G0 is advantageous for the continuity of the common electrode E2 and for the application of a signal to the common electrode E2. That is, it is advantageous for the common electrode E2 corresponding to adjacent light-emitting elements to form an integrated structure, which is advantageous for the application of a signal. In other words, the common electrode E2 is blocked in the separation structure 600 but connected in the notch G0, thereby ensuring the continuity of the common electrode E2 of different light-emitting elements. Of course, a separation structure can be installed around the entire circumference, i.e., the separation structure surrounds the entire circumference of the light-emitting region, in which case the connection of the common electrode E2 corresponding to different subpixels can be realized by other film layers.

[0089] For example, as shown in Figures 7 and 8, the common electrode E2 is not separated in the separation structure 600. Of course, the embodiments of this disclosure are not limited thereto. The common electrode E2 may be separated in the separation structure 600. The common electrode E2 may be continuous in the notches G0 between the separation substructures 660, which will be mentioned later. Of course, if the common electrodes E2 of different subpixels are not a single structure, the connection of the common electrodes E2 corresponding to different subpixels can also be achieved by other film layers.

[0090] For example, as shown in Figures 9, 15A, and 15B, the spacing between at least one of the multiple separation substructures 660 and the two adjacent light-emitting elements 200 is not equal. As shown in Figures 9, 15A, and 15B, for a light-emitting element 201 and its adjacent light-emitting element 203, the spacing D1 is smaller than the spacing D2. As shown in Figures 9, 15A, and 15B, for a light-emitting element 201 and its adjacent light-emitting element 202, the spacing D3 is smaller than the spacing D4. The separation structure 600 (separation substructure 660) between adjacent light-emitting elements is installed close to one of the light-emitting elements. When two protrusions PR are provided within a second opening PN2, the center line between the two protrusions PR can be one end of the spacing calculation.

[0091] As shown in Figure 9, position P1 is the location of one protrusion of the separation structure 600, position P4 is the location of another protrusion of the separation structure 600, and position P2 is the outer edge of the light-emitting region of the subpixel's light-emitting element, corresponding to the edge of the first aperture PN1. The plan view shown in Figure 9 corresponds to a situation where one separation structure 600 has two protrusions PR and both sides are blocked. For example, Figure 9 may be a plan view of the display panel shown in Figures 5, 7, 11-13, 18, 19, or 21.

[0092] The display panel shown in Figure 15A uses a single-sided shield and may be a plan view of the display panel shown in Figure 10.

[0093] The display panel shown in Figure 15B uses shielding on both sides, and both ends of the passivation layer PVX2 or metal structure MT perpendicular to its extension direction may be located within grooves GRV (grooves may be replaced with through holes), and Figure 15B may be a plan view of the display panel shown in Figure 14 or Figure 20.

[0094] As shown in Figures 5, 7, 11-14, and 18-20, both protrusions PR are located within the same second opening PN2.

[0095] In the plan views shown in Figures 9, 15A, and 15B, the first aperture PN1 and the second aperture PN2 are shown, and the pixel definition layer PDL is represented by the apertures in the plan views. In the pixel definition layer PDL, the portion other than the first aperture PN1 and the second aperture PN2 is the main body.

[0096] As shown in Figures 15A and 15B, position P2 is the outer edge of the light-emitting region of the subpixel's light-emitting element and corresponds to the edge of the first aperture PN1, while position P1 is the position of the separation structure 600 (the protruding part of the separation structure 600).

[0097] For example, as shown in Figures 9, 15A, and 15B, the light-emitting region of the first light-emitting element 201 is smaller than the light-emitting region of the second light-emitting element 202, the light-emitting region of the second light-emitting element 202 is smaller than the light-emitting region of the third light-emitting element 203, and the separation structure 600 includes a first separation structure 601 and a second separation structure 602, with the first separation structure 601 located on the outer periphery of the light-emitting region of the first light-emitting element 201 and the second separation structure 602 located on the outer periphery of the light-emitting region of the second light-emitting element 202.

[0098] For example, as shown in Figures 9, 15A, and 15B, the first separation structure 601 includes two first separation substructures 6601 located on opposite sides of the light-emitting region of the first light-emitting element 201, the second separation structure 602 includes four second separation substructures 6602, the four second separation substructures 6602 are arranged surrounding the light-emitting region of the second light-emitting element 202, two of the four second separation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202, and the other two second separation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202. As shown in Figure 9, the four second separation substructures 6602 are arranged sequentially surrounding the light-emitting region of the second light-emitting element 202. As shown in Figure 9, there is a notch G01 between the two first separation substructures 6601. As shown in Figures 9, 15A, and 15B, there is a notch G02 between two adjacent second separation substructures 6602. The size of notch G01 is larger than the size of notch G02.

[0099] For example, as shown in Figures 9, 15A, and 15B, the light-emitting region of the first light-emitting element 201 is surrounded by two first isolation substructures 6601 and two second isolation substructures 6602 located in the notches of the first isolation substructures 6601. As a result, isolation structures 600 / isolation substructures 660 are installed in the regions between the first light-emitting element 201 and the two adjacent second light-emitting elements 202, and between the first light-emitting element 201 and the two adjacent third light-emitting elements 203, which is advantageous for reducing or avoiding crosstalk between adjacent subpixels.

[0100] For example, as shown in Figures 9, 15A, and 15B, the light-emitting region of the third light-emitting element 203 is surrounded by four first isolation substructures 6601 and two second isolation substructures 6602. As a result, isolation structures 600 / isolation substructures 660 are installed in the regions between the third light-emitting element 203 and the two adjacent second light-emitting elements 202, and between the third light-emitting element 203 and the four adjacent first light-emitting elements 201, which is advantageous for reducing or avoiding crosstalk between adjacent subpixels.

[0101] For example, as shown in Figures 9, 15A, and 15B, the first light-emitting element 201 is arranged to emit green light, the second light-emitting element 202 is arranged to emit red light, and the third light-emitting element 203 is arranged to emit blue light. Figure 9 illustrates an example in which the first light-emitting element 201 is arranged to emit green light, the second light-emitting element 202 is arranged to emit red light, and the third light-emitting element 203 is arranged to emit blue light. Note that the light-emitting colors of the light-emitting elements given in the embodiments of this disclosure are not limited to these and can be determined as needed.

[0102] For example, as shown in Figures 9, 15A, and 15B, a repeating unit PX includes two first subpixels SP1, one second subpixel SP2, and one third subpixel SP3. For example, as shown in Figure 9, in one repeating unit PX, the second subpixel SP2 and the third subpixel SP3 are located separately on either side of the central connection line of the two first subpixels SP1. Of course, the pixel arrangement of the display panel is not limited to that shown in Figure 9, and the pixel arrangement can be set as needed.

[0103] As shown in Figures 9, 15A, and 15B, the distance from the light-emitting region of one light-emitting element, which is surrounded by a separation substructure 660, to the light-emitting region of that light-emitting element is greater than the distance from the separation substructure 660 to the light-emitting region of an adjacent light-emitting element. In other words, the separation substructure 660 is closer to the light-emitting region of whichever light-emitting element it surrounds.

[0104] Figures 9, 15A, and 15B illustrate, but are not limited to, a case in which multiple passivation layers PVX2 are installed to form a separation structure 600 and surround the light-emitting region of a light-emitting element. The passivation layers PVX2 installed to surround the light-emitting region of a light-emitting element may be installed as a single-circumference structure, or multiple discrete second openings PN2 may be provided surrounding the light-emitting region of the same light-emitting element. For multiple separation substructures installed in the light-emitting region of the same light-emitting element, the space between adjacent second openings PN2 is a notch G0. That is, in the embodiment of this disclosure, in order to facilitate the continuity of the common electrode E2, multiple second openings PN2 are provided surrounding the light-emitting region of the same light-emitting element, and the space between adjacent second openings PN2 is a notch G0.

[0105] Figures 9, 15A, and 15B show an example where the separation structure 600 / separation substructure 660 is arc-shaped, but it is not limited to this and can be set as needed. For example, the separation structure 600 / separation substructure 660 can be set based on the shape of the outer edge of the light-emitting region of the light-emitting element.

[0106] Figures 9, 15A, and 15B show an example where the light-emitting region of the subpixel / light-emitting element is circular, but are not limited to this. The light-emitting region of the subpixel / light-emitting element may be set to other shapes as needed, for example, a pentagon, hexagon, rectangle, etc.

[0107] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the separation structure 600 does not come into contact with the multiple pixel electrodes E1. This avoids the separation structure 600 affecting the flatness of the pixel electrodes E1 and thus avoids affecting the display effect.

[0108] For example, as shown in Figures 5-8, 10-14, 18-19, and 21, the inorganic material included in the separation structure 600 includes an inorganic nonmetallic material, and the inorganic material is an insulating material. The separation structure 600 includes a passivation layer PVX2, which protrudes from the planarization layer below it, thereby forming a protruding portion PR. The passivation layer PVX2 includes an inorganic nonmetallic material, and the inorganic material is an insulating material. For example, the material of the passivation layer PVX2 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0109] For example, as shown in Figure 20, the separation structure 600 includes a metal structure MT, the inorganic material included in the separation structure 600 includes a metal material, or the metal structure MT includes a metal material, and the separation structure 600 / metal structure MT includes a first sublayer 610, a second sublayer 620, and a third sublayer 630 that are stacked and sequentially installed, the first sublayer 610 being closer to the base substrate BS than the third sublayer 630, and the third sublayer 630 protruding outward from the second sublayer 620 to form a protrusion PR. For example, the materials of the first sublayer 610, the second sublayer 620, and the third sublayer 630 each include metal. For example, the materials of the first sublayer 610 and the third sublayer 630 are the same and different from the material of the second sublayer 620. For example, the materials of the first sublayer 610 and the third sublayer 630 include titanium. For example, the material of the second sublayer 620 includes aluminum. For example, the first sublayer 610, the second sublayer 620, and the third sublayer 630 form a structure in which three Ti / AlTi sublayers are superimposed. For example, as shown in Figure 20, the second sublayer 620 shrinks inward relative to the first sublayer 610 and the third sublayer 630.

[0110] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the display panel further includes a first connection electrode CE1 and a second connection electrode CE2, the pixel circuit 100 includes a transistor T1, the first connection electrode CE1 is located on the planarization layer PLN1 and connected to the transistor T1 via a via hole penetrating the planarization layer PLN1, the second connection electrode CE2 is located on the planarization layer PLN2 and connected to the first connection electrode CE1 via a via hole penetrating the planarization layer PLN2, and the pixel electrode E1 is located on the planarization layer PLN3 and connected to the second connection electrode CE2 via a via hole penetrating the planarization layer PLN3.

[0111] For example, as shown in Figures 5-8, 10-14, and 18-21, the transistor T1 includes a gate GT1, a gate insulating layer GI1, an active layer AT1, a first electrode Ea, and a second electrode Eb, with the first electrode Ea and the second electrode Eb connected to opposite ends of the active layer AT1, respectively. The first connecting electrode CE1 is connected to the second electrode Eb. For example, the active layer AT1 of the transistor T1 is made of low-temperature polycrystalline silicon (LTPS), but is not limited to this.

[0112] For example, as shown in Figures 5-8, 10-14, and 18-21, the pixel circuit 100 further includes a transistor T2, which includes a gate GT2, a gate GT3, a gate insulating layer GI2, a gate insulating layer GI3, an active layer AT2, a first pole Ec, and a second pole Ed, the first pole Ec and the second pole Ed being connected to the opposite ends of the active layer AT2, respectively. For example, the gates GT2 and GT3 of transistor T2 form a dual-gate structure, thereby improving the performance of transistor T2. For example, the active layer AT2 of transistor T2 may be an oxide semiconductor, such as indium gallium zinc oxide (IGZO), but is not limited to this.

[0113] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the insulating layer ISL further includes an inorganic insulating layer PVX1, which is located between the pixel circuit 100 (including transistors T1 and T2) and the planarization layer PLN1, and the first connecting electrode CE1 also penetrates the inorganic insulating layer PVX1.

[0114] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the inorganic insulating layer PVX1 is installed on the side closer to the base substrate BS of the planarization layer.

[0115] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the pixel electrode E1 is connected to one of the multiple pixel circuits 100 via a via hole that penetrates at least a portion of the insulating layer ISL. When a connecting electrode is installed, the pixel electrode E1 is connected to the connecting electrode via a via hole that penetrates at least a portion of the insulating layer ISL, and the connecting electrode is further connected to the pixel circuit 100. When no connecting electrode is installed, the pixel electrode E1 is connected to the pixel circuit 100 via a via hole that penetrates the insulating layer ISL.

[0116] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the base substrate BS includes a first base substrate PI1, a barrier layer BR1, and a second base substrate PI2. Of course, the structure of the base substrate BS is not limited to the above. For example, the base substrate BS may have a single-layer structure.

[0117] For example, the base substrate BS may be a flexible base substrate, but is not limited to this. A flexible base substrate is advantageous for bending, allows for a smaller frame, or enables the formation of a foldable display panel.

[0118] As shown in Figures 5-8, 10-14, and 18-21, the barrier layer BR2 is located on the base substrate BS, a light-shielding layer LS is provided on the barrier layer BR2, a buffer layer BF1 is provided on the light-shielding layer LS, a buffer layer BF2 is provided on the buffer layer BF1, an active layer AT2 is provided on the buffer layer BF2, a gate insulating layer GI1 is provided on the active layer AT2, the gate GT1 is located on the gate insulating layer GI1, a buffer layer BF3 is provided on the gate GT1, a gate GT2 is provided on the buffer layer BF3, a gate insulating layer GI2 is provided on the gate insulating layer GI2, an active layer AT2 is provided on the active layer AT2, a gate insulating layer GI3 is provided on the gate insulating layer GI3, an interlayer insulating layer ILD is provided on the interlayer insulating layer ILD, and the first electrode Ea, second electrode Eb, first electrode Ec, and second electrode Ed are provided on the interlayer insulating layer ILD. The light-shielding layer LS can perform a light-shielding role and improve the performance of transistor T1.

[0119] For example, barrier layer BR2 and barrier layer BR1 may be made of the same material, but are not limited to this.

[0120] As shown in Figures 5-8, 10-14, and 18-21, the display panel further includes a connecting electrode Ee, which may be connected to a light-shielding layer LS. The connecting electrode Ee may also be connected to other signal lines, such as a power line providing a constant voltage, thereby reducing the resistance of the power line. For example, the power line may be a signal line providing a power supply voltage VDD. The connecting electrode Ee is located in the interlayer insulation layer ILD and may be installed on the same layer as the first electrode Ea, second electrode Eb, first electrode Ec, and second electrode Ed.

[0121] As shown in Figures 5-8, 10-14, and 18-21, the display panel further includes connecting electrodes CEa and CEb, where connecting electrode CEa is connected to connecting electrode CEb, connecting electrode CEa is located on planarization layer PLN1, and connecting electrode CEb is located on planarization layer PLN2, and connecting electrode CEb is connected to connecting electrode CEa via a via hole penetrating planarization layer PLN2. Connecting electrode CEa is located on the same layer as connecting electrode CE1, and connecting electrode CEb is located on the same layer as connecting electrode CE2.

[0122] As shown in Figures 5-8, 10-14, and 18-21, the display panel further includes a memory capacitor Cst, which includes a first plate Ca and a second plate Cb. For example, the first plate Ca is located on the same layer as gate GT1, and the second plate Cb is located on the same layer as gate GT2.

[0123] As shown in Figures 5-8, 10-14, and 18-21, the display panel further includes a photospacer PS, which is positioned to support a fine metal mask during the deposition of the local layer LL of the light-emitting functional layer EML.

[0124] For example, the photospacer PS may form an integrated structure with the pixel definition layer PDL, or it may be fabricated using a two-tone mask.

[0125] For example, as shown in Figures 5-8, 10-14, and 18-21, the planarization layer PLN3 includes planarization sublayers PLN3-1 and PLN3-2 to facilitate the planarization of the pixel electrode E1. Planarization sublayer PLN3-1 is closer to the base substrate BS than planarization sublayer PLN3-2. Of course, in other embodiments, the planarization layer PLN3 may be a single-layer structure.

[0126] As shown in Figures 5, 7, 10, 19, and 21, the passivation layer PVX2 is placed on top of the planarization sublayer PLN3-1 (part of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (part of the planarization layer PLN3). In Figure 5, a groove GRV is formed in the planarization sublayer PLN3-1.

[0127] As shown in Figure 11, the passivation layer PVX2 is placed on top of the planarization layer PLN2 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN3 (part of the planarization layer). In Figure 11, a groove GRV is formed in the planarization layer PLN2.

[0128] As shown in Figure 12, the passivation layer PVX2 is placed on top of the planarization layer PLN1 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN2 and the planarization layer PLN3 (part of the planarization layer). In Figure 12, a groove GRV is formed in the planarization layer PLN1.

[0129] Figures 10 to 12 show the separation structure 600 being moved downward to form a display panel with a different structure. The separation structure 600 can be placed above the planarization layer PLN1 and at any film layer position separated from the pixel electrode E1 by at least a portion of the planarization layer.

[0130] As shown in Figures 13 and 18, the passivation layer PVX2 is placed on top of the planarization sublayer PLN3-1 (part of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (part of the planarization layer PLN3). In Figure 13, the first through-hole H1 is formed in the planarization sublayer PLN3-1.

[0131] As shown in Figure 14, the passivation layer PVX2 is placed on the planarization sublayer PLN3-1 (part of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (part of the planarization layer PLN3). In Figure 14, a groove GRV is formed in the planarization sublayer PLN3-1. Of course, the groove GRV shown in Figure 14 may be a through hole, and the through hole can penetrate at least the planarization sublayer PLN3-1. For example, the through hole may penetrate the planarization sublayer PLN3-1 and the planarization layer PLN2, or it may not penetrate the planarization layer PLN2, but may be in the form of a groove in the planarization layer PLN2. In the embodiments of this disclosure, if it penetrates one layer, it can be called a through hole.

[0132] For example, as shown in Figure 14, the passivation layer PVX2 is located between two adjacent subpixels. For example, the passivation layer PVX2 may be located in the center of two adjacent subpixels, and the width of the passivation layer PVX2 may be designed to be approximately 5 μm, forming bidirectional shielding and enhancing the shielding effect.

[0133] As shown in Figure 20, the passivation layer PVX2 is placed on top of the planarization layer PLN2 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN3 (part of the planarization layer). In Figure 14, the first through-hole H1 is formed in the planarization layer PLN2.

[0134] As shown in Figure 16A, the display panel includes a display area R1 and a peripheral area R2, the peripheral area R2 may surround the display area R1. The peripheral area R2 has a folding area R21, which allows a portion of the display panel to be folded back, thereby reducing the size of the display panel frame.

[0135] For example, as shown in Figures 5 and 16A, the display panel has a bending region R21, and via holes V0 may be provided in the bending region R21, thereby allowing the planarization layer to be filled into the via holes V0, thereby enhancing the bending performance of the display panel.

[0136] As shown in Figures 5 to 8 and Figures 10 to 14, the via hole V0 penetrates the passivation layer PVX1, the interlayer insulation layer ILD, the gate insulation layer GI3, the gate insulation layer GI2, the buffer layer BF3, the gate insulation layer GI1, the buffer layer BF2, the buffer layer BF1, and the barrier layer BR2.

[0137] As shown in Figures 5-8 and 10-14, the connecting electrode CEc is located in the bent region R21. The connecting electrode CEc overlaps with the via hole V0. For example, the connecting electrode CEc may be connected to a signal line located within the display region, such as a data line or a power line providing a constant voltage. For example, a power line providing a constant voltage includes a power line providing a constant voltage VDD and a power line providing a constant voltage VSS. Of course, the connecting electrode CEc may be connected to other signal lines. Embodiments of this disclosure do not limit the signal lines to which the connecting electrode CEc is connected.

[0138] As shown in Figure 16B, the display panel includes a display area R1 and a peripheral area R2, the peripheral area R2 may surround the display area R1. The peripheral area R2 has a lead-out area R22. For example, the lead-out area R22 may, but is not limited to, being used to connect to an integrated circuit or a flexible circuit board. If the display panel does not require bending, a bending area is not provided.

[0139] As shown in Figure 17, the display panel includes a display area R1 and a surrounding area R2, and the surrounding area R2 may surround the display area R1.

[0140] For example, as shown in Figure 17, the display panel has a hole region R3, and a plurality of isolation structures 600 are installed therein, at least some of the isolation structures 600 located in a frame region R0 close to the hole region R3. The frame region R0 is used for installing wiring. At least a portion of the display panel located in the hole region R3 may be removed to form a housing cavity, and a sensor may be installed in the housing cavity. For example, the sensor includes, but is not limited to, a camera.

[0141] In the frame region R0 shown in Figures 18 and 19, and in the separation structure 600, the passivation layer PVX2 is located on the planarization layer PLN1. However, the planarization layer here is not limited to the planarization layer PLN1, and other planarization layers may be used.

[0142] As shown in Figures 18 and 19, the separation structure 600 located within the display area R1 and the separation structure 600 located within the frame area R0 may be manufactured using the same patterning process.

[0143] As shown in Figures 18 and 19, the separation structure 600 located within the display area R1 and the separation structure 600 located within the frame area R0 have the same structure.

[0144] Figures 18 to 21 show the display area R1, the frame area R0, and the hole area R3. In the display panel shown in Figures 18 to 21, all the structures in the hole area R3 have been removed.

[0145] Figure 21 shows a separation structure 600 placed between adjacent subpixels within the display area. The display panels shown in Figures 5, 7, and 10-14 do not require a folding area and further form a structure similar to that shown in Figure 21.

[0146] For example, in some embodiments, the passivation layer PXV2 for forming the separation structure 600 is located only in the display area R1. Of course, in a display panel having a frame area R0, the passivation layer PXV2 for forming the separation structure 600 may be located in both the display area R1 and the frame area R0.

[0147] In some embodiments, the display panel may have a folding region R21 and a perforated region R3.

[0148] For example, in embodiments of this disclosure, components located in the same layer may be formed by the same film layer through the same patterning process. In embodiments of this disclosure, patterning or the patterning process may consist only of a photoetching process, or it may consist of a photoetching process and an etching step, or it may include other processes for forming a predetermined pattern, such as printing or inkjet printing. A photoetching process refers to a process that includes processes such as film deposition, exposure, and development, and uses a photoresist, mask, exposure apparatus, etc., to form a pattern. A corresponding patterning process can be selected based on the structure formed in embodiments of this disclosure.

[0149] For example, in the embodiments of this disclosure, if the planarization layer PLN3 includes planarization sublayers PLN3-1 and PLN3-2, the thickness of the planarization sublayer PLN3-1 may be 1 to 2 μm, and the thickness of the planarization sublayer PLN3-2 may also be 1 to 2 μm. For example, in this case, the thickness of the planarization layer PLN3 may be 2 to 4 μm.

[0150] For example, in the embodiments of this disclosure, if the planarization layer PLN3 has a single-layer structure, the thickness of the planarization layer PLN3 may be 1 to 2 μm.

[0151] For example, in the embodiments of this disclosure, the thickness of the planarization layer PLN1 may be 1 to 2 μm.

[0152] For example, in the embodiments of this disclosure, the thickness of the planarization layer PLN2 may be 1 to 2 μm.

[0153] For example, in the embodiments of this disclosure, the thickness of the passivation layer PVX1 may be 0.1 to 0.25 μm.

[0154] For example, in the embodiments of this disclosure, the base substrate BS, buffer layer BF1, buffer layer BF2, buffer layer BF3, gate insulating layer GI1, gate insulating layer GI2, gate insulating layer GI3, interlayer insulating layer ILD, passivation layer PVX1, passivation layer PVX2, planarization layer PLN1, planarization layer PLN2, planarization layer PLN3, and pixel definition layer PDL are all made of insulating material.

[0155] For example, the material of the base substrate BS may include, but is not limited to, polyimide. For example, the material of the base substrate PI1 may include, but is not limited to, polyimide. For example, the material of the base substrate PI2 may include, but is not limited to, polyimide. For example, the base substrate BS may be a flexible base substrate, thereby forming a flexible display panel.

[0156] For example, at least one of the materials among buffer layer BF1, buffer layer BF2, buffer layer BF3, gate insulating layer GI1, gate insulating layer GI2, gate insulating layer GI3, interlayer insulating layer ILD, passivation layer PVX1, and passivation layer PVX2 includes an inorganic insulating material. For example, the inorganic insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0157] For example, the materials for the pixel definition layer (PDL) and the planarization layer include organic insulating materials. For example, planarization layers PLN1, PLN2, and PLN3 include organic insulating materials. For example, the organic insulating material includes one or more combinations of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, etc.

[0158] For example, in the embodiments of this disclosure, the pixel definition layer PDL and the planarization layer may both be called organic layers or organic insulating layers. For example, planarization layer PLN1, planarization layer PLN2, and planarization layer PLN3 may each be called organic layers. The pixel definition layer PDL may be called an organic layer. Planarization sublayer PLN3-1 may be called an organic sublayer or organic insulating sublayer, and planarization sublayer PLN3-2 may be called an organic sublayer or organic insulating sublayer.

[0159] For example, in the embodiments of this disclosure, the insulating layer ISL may be called an insulating material layer.

[0160] For example, in the embodiments of this disclosure, at least one of the gate GT1, gate GT2, gate GT3, first electrode plate Ca, second electrode plate Cb, first electrode Ea, second electrode Eb, first electrode Ec, second electrode Ed, connecting electrode CE1, connecting electrode CE2, connecting electrode Cea, connecting electrode CEb, and connecting electrode CEc is made of metal or an alloy.

[0161] For example, in the embodiments of this disclosure, the active layer AT1 and the active layer AT2 are semiconductor layers and may be made of polycrystalline silicon or a metal oxide semiconductor material.

[0162] For example, in the embodiments of this disclosure, one of the pixel electrode E1 and the common electrode E2 is the anode of the light-emitting element, and the other of the pixel electrode E1 and the common electrode E2 is the cathode of the light-emitting element. The embodiments of this disclosure will be explained using the case where the pixel electrode E1 is the anode and the common electrode E2 is the cathode as an example.

[0163] For example, the pixel electrode E1 is made of a conductive material. For example, the material of the pixel electrode E1 includes metals and conductive metal oxides. For example, the pixel electrode E1 uses a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are stacked. The material and structure of the pixel electrode E1 can be set as needed.

[0164] For example, the common electrode E2 is made of a conductive material. For example, the material of the common electrode E2 includes metal or alloy. For example, the material of the common electrode E2 includes an Mg / Ag alloy. The material and structure of the common electrode E2 can be set as needed.

[0165] The embodiments described herein are explained using the common layer CL as an example in which the common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3, but are not limited thereto. The common layer CL may be a single-layer structure or a laminated structure including multiple film layers. For example, in some embodiments, the common layer CL includes at least a charge generation layer.

[0166] For example, in the embodiments of this disclosure, at least one of the light-emitting functional layers (EMLs) may be fabricated by a vapor deposition process.

[0167] Although the embodiments described herein use a Tandem structure as an example, the invention is not limited to this, and other suitable structures may be used for the light-emitting element.

[0168] For example, the display panel may further include a sealing layer, which is arranged to prevent the intrusion of water and oxygen by sealing multiple light-emitting elements.

[0169] For example, a black pixel definition layer (PDL) may be used. Typically, the structure of a color filter on encapsulation (COE) can be combined with a black pixel definition layer.

[0170] For example, the display panel may further include a touch layer, which may be placed between the sealing layer and the COE structure.

[0171] In the embodiments of this disclosure, the structure shown in the cross-sectional view of the folding region of the display panel is the structure before folding. For example, the folding region on the right side of the drawing can be folded downward to place some of the display panels behind other parts of the display panel, which is advantageous in reducing the size of the display panel frame.

[0172] In the embodiments of this disclosure, the pixel circuit 100 includes transistor T1, transistor T2, and memory capacitor. For example, transistor T1 may be a light emission control transistor, and transistor T2 may be a threshold compensation transistor or a reset control transistor, but is not limited to these. The embodiments of this disclosure do not limit the structure of the pixel circuit 100, and a general pixel circuit may be used. For example, the pixel circuit 100 may be a 7T1C pixel circuit, a 7T2C pixel circuit, an 8T1C pixel circuit, or a 9T1C pixel circuit. Of course, the number of transistors and capacitors included in the pixel circuit 100 are not limited to the above and can be determined as needed. The cross-sectional view does not show the connection relationships between transistors or between transistors and capacitors, and here it is a normal structure.

[0173] In the drawings provided in the embodiments of this disclosure, the plan view shows directions X and Y, and the cross-sectional view shows direction Z. Direction X intersects with direction Y. For example, direction X is perpendicular to direction Y. Both directions X and Y are parallel to the main surface of the base substrate. For example, direction Z is perpendicular to both direction X and direction Y.

[0174] For example, in embodiments of this disclosure, if the separation structure 600 includes an inorganic nonmetallic material (passivation layer PVX2), the pattern of the pixel definition layer PDL and the second through-hole H2 in the planarization layer located above the separation structure 600 may be formed, followed by the formation of the first through-hole H1 or groove GRV in the planarization layer located below the separation structure 600. Of course, the method of manufacturing the display panel is not limited to the above. For example, in some other embodiments, the first through-hole H1 or groove GRV in the planarization layer located below the separation structure 600 may be formed first, followed by the fabrication of the subsequent pattern, and this process continues until a display panel having the described structure is formed. Embodiments of this disclosure are not limited to the method of manufacturing the display panel, and an appropriate manufacturing method may be set as needed.

[0175] Embodiments of the present disclosure further provide a display device, which includes any of the above-described display panels.

[0176] For example, the display device may be a display device such as an organic light-emitting diode display device, or any product or component having a display function, such as a television, digital camera, mobile phone, wristwatch, tablet PC, notebook computer, or navigator, but the embodiments of this disclosure are not limited to these.

[0177] The above describes only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can easily conceive of within the scope of the art disclosed herein should also be included within the scope of protection of the present disclosure. Accordingly, the scope of protection of the present disclosure should be the same as the scope of protection of the claims. [Explanation of Symbols]

[0178] 06 Separation structure 100-pixel circuit 200 light-emitting elements 201 First light-emitting element 202 Second light-emitting element 203 Third light-emitting element 600 Separate structure 601 1st separation structure 602 Second separation structure 610 First Sublayer 620 Second Sublayer 630 Third Sublayer 660 Separation substructures 6601 First Separation Substructure 6602 Second Separation Substructure BF1 Buffer Layer BF2 Buffer Layer BF3 Buffer Layer BR1 Barrier Layer BR2 barrier layer BS base board Ca 1st plate Cb 2nd plate CE1 First connecting electrode CE2 Second connecting electrode CEa connecting electrode CEb connection electrode CEc connection electrode CGL charge generation layer CL common layer CL1 First Common Layer CL2 2nd common layer CL3 Third Common Layer CL11 Separation part CL21 Separation part CPL optical coupling layer E1 Pixel electrode E2 common electrode Ea 1st pole Eb 2nd pole Ec 1st pole Ed's second pole Ee connecting electrode EM1 light-emitting element EM2 light-emitting element EML Light-Emitting Functional Layer ETL electron transport layer ETL-1 electron transport layer ETL-2 electron transport layer G Emitting Layer G1 Luminescent Material G2 Luminescent Material GI1 Gate Insulation Layer GI2 Gate Insulation Layer GI3 Gate Insulation Layer GT1 Gate GT2 Gate GT3 Gate H1 1st through hole H2 2nd through hole HTL Hole Transport Layer HTL-1 Hole Transport Layer HTL-2 Hole Transport Layer ILD (Interlayer Insulation Layer) ISL insulating material layer ISL Insulation Layer LL local layer LS light shielding layer MT metal structure N-CGL charge generation layer P-CGL charge generation layer PDL Pixel Definition Layer PI1 First Base Board PI2 Second Base Board PLN planarization structure layer PLN1 planarization layer PLN2 planarization layer PLN3 planarization layer PLN3-1 Flattening sublayer PLN3-2 Flattening Sublayer PN1 1st opening PN2 2nd opening PR protrusion PR1 protrusion PR2 protrusion PS Photo Spacer PT1 separation part PT2 separation section PVX Passivation Layer PVX1 Inorganic insulating layer, passivation layer PVX2 Passivation Layer PXV2 Passivation Layer R0 frame region R1 display area R1 Luminescent material R2 Luminescent Material R2 surrounding area R3 hole area R21 area R22 Drawer area

Claims

1. A display panel comprising a base substrate, a plurality of pixel circuits, an insulating material layer, a plurality of pixel electrodes, a light-emitting functional layer, and a separation structure, The plurality of pixel circuits are located on the base substrate, The insulating material layer is located on the side of the plurality of pixel circuits away from the base substrate and includes a plurality of organic insulating layers, each of the plurality of organic insulating layers includes an organic material. The pixel electrode is located on the side of the plurality of organic insulating layers away from the base substrate and is connected to one of the plurality of pixel circuits. The light-emitting functional layer includes a common layer, the orthographic projection of the common layer on the base substrate overlaps with the orthographic projection of the plurality of pixel electrodes on the base substrate, and at least a portion of the common layer is located on the side of the plurality of pixel electrodes away from the base substrate. The separation structure has a protrusion that extends from the organic insulating layer below it, or has a protrusion itself, and the separation structure is arranged so as to block the common layer at the protrusion. A display panel wherein the separation structure is located between adjacent pixel electrodes and comprises an inorganic material, the separation structure is located on at least a portion of an organic insulating layer, and the separation structure and the plurality of pixel electrodes are separated by at least a portion of an organic insulating layer.

2. The display panel according to claim 1, wherein the organic insulating layer located below the separation structure has a groove or a first through hole in the protruding portion.

3. The display panel according to claim 2, wherein the organic insulating layer located above the separation structure has a second through-hole in the protruding portion, and the first through-hole and the second through-hole are in communication.

4. The display panel according to claim 3, further comprising a pixel definition layer, the pixel definition layer having a plurality of first openings, each of the plurality of first openings being arranged to expose one of the plurality of pixel electrodes, and the pixel definition layer further having a second opening, the second opening communicating with the second through-hole.

5. The display panel according to claim 4, wherein the orthographic projection of the second opening on the base substrate overlaps with the orthographic projection of the separation structure on the base substrate.

6. The display panel according to any one of claims 2 to 5, wherein the separation structure has one protrusion in the groove or the first through hole.

7. The display panel according to any one of claims 2 to 5, wherein the groove or first through-hole is elongated, the separation structure includes two separation parts in the groove or first through-hole, each of the two separation parts forms two protrusions, and the two protrusions are located within the groove or first through-hole and on opposite sides of the elongated groove or first through-hole.

8. The display panel according to any one of claims 1 to 7, further comprising a common electrode, at least a portion of which is located on the side of the light-emitting functional layer away from the base substrate, and the plurality of pixel electrodes, the light-emitting functional layer, and the common electrode constitute a plurality of light-emitting elements.

9. The display panel according to claim 8, wherein the isolation structure surrounding one light-emitting element includes a plurality of isolation substructures.

10. The display panel according to claim 9, wherein the plurality of separation substructures include at least two separation substructures located on opposite sides of the light-emitting region of the light-emitting element.

11. The display panel according to any one of claims 9 to 10, wherein the spacing between at least one of the plurality of isolated substructures and two adjacent light-emitting elements is not equal.

12. The display panel according to claim 8, wherein the light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, the light-emitting region of the first light-emitting element is smaller than the light-emitting region of the second light-emitting element, the light-emitting region of the second light-emitting element is smaller than the light-emitting region of the third light-emitting element, and the separation structure includes a first separation structure and a second separation structure, the first separation structure is located on the outer periphery of the light-emitting region of the first light-emitting element, and the second separation structure is located on the outer periphery of the light-emitting region of the second light-emitting element.

13. The display panel according to claim 12, wherein the first separation structure includes two first separation substructures located on opposite sides of the light-emitting region of the first light-emitting element, the second separation structure includes four second separation substructures, the four second separation substructures are arranged surrounding the light-emitting region of the second light-emitting element, two of the four second separation substructures are located on opposite sides of the light-emitting region of the second light-emitting element, and the other two second separation substructures of the four second separation substructures are located on opposite sides of the light-emitting region of the second light-emitting element.

14. The display panel according to claim 13, wherein the light-emitting region of the first light-emitting element is surrounded by two first separation substructures and two second separation substructures located in notches of the first separation substructures.

15. The display panel according to claim 13 or 14, wherein the light-emitting region of the third light-emitting element is surrounded by four first separation substructures and two second separation substructures.

16. The display panel according to any one of claims 8 to 15, wherein the common electrode is not divided in the separation structure.

17. The display panel according to any one of claims 12 to 16, wherein the first light-emitting element is arranged to emit green light, the second light-emitting element is arranged to emit red light, and the third light-emitting element is arranged to emit blue light.

18. The display panel according to any one of claims 1 to 17, wherein the separation structure does not come into contact with the plurality of pixel electrodes.

19. The display panel according to any one of claims 1 to 18, wherein the separation structure includes a passivation layer, the passivation layer is arranged to form the protrusion, the inorganic material includes an inorganic nonmetallic material, and the inorganic material is an insulating material.

20. The display panel according to any one of claims 1 to 19, wherein the inorganic material includes a metallic material, and the separation structure includes a first sublayer, a second sublayer, and a third sublayer that are stacked and arranged in order, the first sublayer being closer to the base substrate than the third sublayer, and the third sublayer protruding outward from the second sublayer to form the protruding portion.

21. The display panel according to any one of claims 1 to 20, wherein the plurality of organic insulating layers include a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer arranged in order, the first organic insulating layer being closer to the base substrate than the third organic insulating layer, and the separation structure being located above at least a portion of the first organic insulating layer and below at least a portion of the third organic insulating layer in a direction perpendicular to the base substrate.

22. The display panel according to claim 21, further comprising a first connecting electrode and a second connecting electrode, wherein the pixel circuit includes a transistor, the first connecting electrode is located on the first organic insulating layer and connected to the transistor via a via hole penetrating the first organic insulating layer, the second connecting electrode is located on the second organic insulating layer and connected to the first connecting electrode via a via hole penetrating the second organic insulating layer, and the pixel electrode is located on the third organic insulating layer and connected to the second connecting electrode via a via hole penetrating the third organic insulating layer.

23. The display panel according to claim 22, wherein the insulating material layer further comprises an inorganic insulating layer, the inorganic insulating layer is located between the transistor and the first organic insulating layer, and the first connecting electrode also penetrates the inorganic insulating layer.

24. The display panel according to any one of claims 1 to 23, wherein the display panel has a folding area.

25. The display panel according to any one of claims 1 to 24, wherein the display panel has a perforated region, a plurality of separation structures are installed, and at least some of the separation structures are located in a frame region close to the perforated region.

26. A display device including a display panel according to any one of claims 1 to 25.

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