Topology Outcome Code for Clifford Circuits

Abstract

A method (50) for correcting errors in applying a Clifford circuit to a qubit register (12) of a quantum computer (10) includes receiving circuit data defining the Clifford circuit (52), receiving additional data identifying one or more measurements belonging to each of several faces (48) of a lattice (44) (56), and outputting an outcome code (58) based on the circuit data, the outcome code including a sequence of outcome checks, each outcome check outputting an outcome code based on the circuit data corresponding to an expected error syndrome in applying the Clifford circuit to the qubit register, and outputting a topology outcome code (60) based on the circuit data, additional data, and outcome code, the topology outcome code including a sequence of check operators supporting quantum error correction by a topology decoder, thereby outputting a topology outcome code that enables error correction in applying the Clifford circuit to the qubit register.

Description

Background Art

[0001] Background

[0001] A quantum computer is a physical machine configured to perform logical operations based on quantum mechanical phenomena. Examples of such logical operations include mathematical calculations. Current interest in quantum computer technology is driven by analytical results suggesting that when a properly constructed quantum computer is applied to certain types of problems, its computational efficiency may outperform that of any practical non-quantum computer. Such problems include computer modeling of natural and artificial quantum systems, integer factorization, data search, and function optimization when applied to systems of linear equations and machine learning. Summary of the Invention Means for Solving the Problems

[0002] Summary

[0002] One aspect of the present disclosure relates to a method for correcting errors in applying a Clifford circuit to a qubit register of a quantum computer. The method comprises: (a) receiving circuit data defining the Clifford circuit; (b) receiving additional data identifying one or more measurement values belonging to each of a plurality of faces of a lattice; (c) outputting an outcome code based on the circuit data, wherein the outcome code includes a sequence of outcome checks, each outcome check corresponding to an expected error syndrome for applying the Clifford circuit to the qubit register; and (d) outputting a topological outcome code based on the circuit data, the additional data, and the outcome code, wherein the topological outcome code includes a sequence of check operators that support quantum error correction by a topological decoder, thereby enabling error correction in applying the Clifford circuit to the qubit register.

[0003]

[0003] Another aspect of the present disclosure relates to a computer system operationally coupled to a quantum computer. The computer system includes a processor and a computer memory operationally coupled to the processor and holding instructions that cause the processor to perform error correction in applying a Clifford circuit to a qubit register of a quantum computer. These instructions include (a) an instruction that receives circuit data defining a Clifford circuit; (b) an instruction that receives additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) an instruction that outputs an outcome code based on the circuit data, the outcome code comprising a sequence of outcome checks, each outcome check being an instruction that outputs an outcome code based on the circuit data corresponding to an expected error syndrome in applying a Clifford circuit to a qubit register; and (d) an instruction that outputs a topology outcome code based on the circuit data, the additional data, and the outcome code, the topology outcome code comprising a sequence of check operators that support quantum error correction by a topology decoder, thereby enabling error correction in applying a Clifford circuit to a qubit register.

[0004]

[0004] This "Outline" is provided to introduce some concepts in a simplified form, which will be described in detail in the "Modes for Carrying Out the Invention." This "Outline" is not intended to highlight any important or essential features of the claims, nor is it used to limit the scope of the claims. The claims are not limited to any implementation that resolves any or all of the disadvantages described in any part of this disclosure. [Brief explanation of the drawing]

[0005] Brief explanation of the drawing [Figure 1]

[0005] An exemplary embodiment of a quantum computer is shown. [Figure 2]

[0006] This shows a Bloch sphere. The Bloch sphere is a graphical representation of the quantum state of one qubit in a quantum computer. [Figure 3]

[0007] This shows an example of a signal waveform for performing quantum gate operations or quantum gate measurements in a quantum computer. [Figure 4]

[0008] This is a schematic diagram of a physical qubit lattice, a non-restrictive example. [Figure 5]

[0009] This document presents an exemplary algorithm for generating code checks that can be used with a topology decoder. [Figure 6]

[0010] Figure 5 shows an example of a procedure in the algorithm that converts the checks for abbreviated codes into a concise chronological order. [Figure 7]

[0011] This document describes an exemplary method for correcting one or more errors in applying a Clifford circuit to the qubit register of a quantum computer. [Figure 8]

[0012] Figure 5 shows an example of a classical computer system applicable to the algorithm, Figure 6 shows the procedure, and Figure 7 shows the method. [Modes for carrying out the invention]

[0006] Detailed explanation 1. Overview

[0013] As detailed herein, [Reference 1] proposes an end-to-end process for detecting and correcting errors in Clifford circuits. This process implements either a lookup table decoder or an LDPC decoder, but the lookup table decoder can be difficult to construct, and the LDPC decoder can have very high runtime costs; these are limitations of the process. This specification proposes an extension of the process in [Reference 1] that is compatible with topology decoders that are more efficient to construct and execute (e.g., minimum-weight perfect matching and union-find). More specifically, this extension enables automated decoder construction for topology code implementations, including surface code and Floquet code.

[0007] 2. Quantum Computer Architecture

[0014] To present the context of quantum error correction using topology outcome codes, we first describe several embodiments of exemplary quantum computer architectures. Referring here to the drawings, Figure 1 shows an embodiment of an exemplary quantum computer 10 configured to perform quantum logic operations (see below). While conventional computer memory holds digital data in the form of arrays of bits and performs bitwise logic operations, a quantum computer holds data in the form of arrays of qubits and performs quantum mechanical operations on the qubits to carry out the desired logic. Thus, the quantum computer 10 in Figure 1 includes a set of qubit registers 12 (e.g., a state register 12S and an auxiliary register 12A). Each qubit register contains a sequence of qubits 14. The number of qubits in a qubit register is not particularly limited but may be determined according to the complexity of the quantum logic that the quantum computer performs.

[0008]

[0015] The qubits 14 of the qubit register 12 may take various forms depending on the desired architecture of the quantum computer 10. Each qubit may, as a non-limiting example, be a superconducting Josephson junction, a trapped ion, a trapped atom coupled to a high-finesse resonator, an atom or molecule confined in a fullerene, an ion or neutral dopant atom confined in a host lattice, a quantum dot exhibiting a discrete spatial electronic state or spin electronic state, an electron hole in a semiconductor junction carried together by an electrostatic trap, a coupled quantum wire pair, an atomic nucleus addressable by magnetic resonance, a free electron in helium, a molecular magnet, or a metallic carbon nanosphere. The qubits may be implemented in multiple processing states corresponding to various modes of light propagation through linear optical elements (e.g., mirrors, beam splitters, and phase shifters), as well as in states stored in a Bose-Einstein condensate. More generally, each qubit 14 may include any particle or system of particles that can exist in two or more discrete quantum states that can be experimentally measured and manipulated.

[0009]

[0016] Figure 2 depicts the Bloch sphere 16, which is a graphical description of several quantum mechanical aspects of individual qubits 14. In this description, the north and south poles of the Bloch sphere correspond to the standard basis vectors |0> and |1>, respectively, and to the up-spin and down-spin states of, for example, an electron or other fermion. The set of points on the surface of the Bloch sphere contains all possible pure states |ψ> of the qubit, while the points inside correspond to all possible mixed states. Mixed states of a given qubit may arise from decoherence that can occur due to undesirable coupling with external degrees of freedom.

[0010]

[0017] Referring again to Figure 1, the quantum computer 10 includes a controller 18. The controller may include at least one processor 20 and associated computer memory 22. The processor 20 may be operationally coupled to peripheral components such as network components to enable the quantum computer to be operated remotely. The processor 20 may take the form of a central processing unit (CPU), a graphics processing unit (GPU), etc. Thus, the controller 18 may include classical electronic components. In this specification, the terms “classical” and “non-quantum” apply to any component that can be accurately modeled without considering the quantum state of any individual particles included. Examples of classical electronic components include integrated, microlithographically formed transistors, resistors, and capacitors. The computer memory 22 may be configured to hold program instructions 24 that cause the processor 20 to execute any function or process of the controller 18. The computer memory may also be configured to hold additional data 26. In some examples, data 26 may include a register of classical control bits 28, which operate the quantum computer during runtime (for example, to provide classical control inputs to one or more quantum gate operations). In examples where the qubit register 12 is a low-temperature or cryogenic device, the controller 18 may include a control component that can operate at low temperatures or cryogenic temperatures (for example, a field-programmable gate array (FPGA) operating at 77K). In such examples, the low-temperature control component may be operationally coupled with an interface component that can operate at normal temperatures.

[0011]

[0018] The controller 18 of the quantum computer 10 is configured to receive a plurality of inputs 30 and to provide a plurality of outputs 32. These inputs and outputs may each include digital lines and / or analog lines. At least some of the inputs and outputs may be data lines that supply data to and / or extract data from the quantum computer. Other inputs may include control lines that can adjust or otherwise control the operation of the quantum computer.

[0012]

[0019] The controller 18 is operationally coupled to the qubit register 12 via a quantum interface 34. The quantum interface is configured to exchange data (solid line) bidirectionally with the controller. The quantum interface is further configured to exchange signals (dashed line) corresponding to the data bidirectionally with the qubit register. Such signals may be electrical signals, magnetic signals, and / or optical signals, depending on the physical implementation of the qubit 14. The controller can examine, or otherwise influence, any, some, or all quantum states held in any qubit register, as determined by the overall quantum state of the qubits contained therein, via the signals carried through the quantum interface. For this purpose, the quantum interface includes a qubit programmer 36 and a qubit reader 38. The qubit programmer is configured to output signals to one or more qubits in the qubit register based on the write data received from the controller. The qubit reader is configured to detect signals from one or more qubits in the qubit register and to output read data to the controller based on those signals. In some examples, the readout data received from the qubit readout may be an estimate of the observable for the measured quantum state held in the qubit register. In summary, the controller 18 and interface 34 may be called the "control system".

[0013]

[0020] In some examples, a well-configured signal from a qubit programmer 36 may physically interact with one or more qubits 14 of a qubit register 12 to trigger a measurement of the quantum state held in one or more qubits. A qubit reader 38 may then detect the resulting signal emitted from one or more qubits according to its measurement and supply readout data corresponding to the resulting signal to a controller 18. In other words, the qubit reader may be configured to output estimates of one or more observables reflecting the quantum state of one or more qubits in the qubit register, based on the received signal, and to supply these estimates to the controller 18. As a non-limiting example, the qubit programmer may, based on data from the controller, apply a pulse or pulse train of appropriate voltage to the electrodes of one or more qubits to initiate a measurement. The qubit reader can then immediately detect the photon emission from its one or more qubits and assert the corresponding digital voltage level on the quantum interface line entering the controller. Generally speaking, any measurement of a quantum mechanical state is defined by an operator O corresponding to the observable being measured, and the result of the measurement, R, is guaranteed to be one of the possible eigenvalues ​​of O. In quantum computers, R is statistically related to the state of the qubit register before measurement, but is not uniquely determined by the state of the qubit register.

[0014]

[0021] The quantum interface 34 may be configured to implement one or more quantum logic gates that act on the quantum states held in the qubit register 12 in accordance with appropriate inputs from the controller 18. As used herein, the term "state vector" refers to the quantum state held in the sequence of qubits 14S of the state register 12S of the quantum computer 10. Whereas the functions of various logic gates in classical computer systems are described according to corresponding truth tables, the functions of various quantum gates are described by corresponding operator matrices. The operator matrix acts on (i.e., is multiplied by) a complex vector representing a qubit register state to produce a specified rotation of that vector within Hilbert space.

[0015]

[0022] For example, the Hadamard gate H is defined by the following equation.

Formula

[0016]

[0023] The H gate acts on a single qubit. That is, it maps the ground state |0> to

Formula

Formula

[0017]

[0024] The phase gate S is defined by the following equation.

Formula

[0018]

[0025] The S gate leaves the ground state |0> unchanged, but changes |1> to e iπ / 2It maps to |1>. Therefore, the probability of measuring either |0> or |1> remains unchanged by this gate, but the phase of the quantum state of the qubit is shifted. This is equivalent to rotating |ψ> by 90 degrees along the lines of latitude on the Bloch sphere in Figure 2.

[0019]

[0026] Some quantum gates act on two or more qubits. For example, the SWAP gate acts on two different qubits to swap their values. This gate is defined by the following equation:

number

[0020]

[0027] A "Clifford gate" is a quantum gate belonging to the Clifford group (i.e., the set of quantum gates that perform rearrangements of Pauli operators). In the case of n qubits, the Pauli operators form the following group:

number

number

[0021]

[0028] The above list of quantum gates and their associated operator matrices is not exhaustive, but is provided for the sake of clarity. Other non-restrictive examples of quantum gates include the Pauli X gate, Pauli Y gate, Pauli Z gate,

number

number

[0022]

[0029] Continuing to refer to Figure 1, in order to assert any desired quantum gate operation, a well-configured signal from the qubit programmer 36 of the quantum interface 34 may physically interact with one or more qubits 14 of the qubit register 12. As described above, the desired quantum gate operation involves a well-defined rotation of a complex vector representing the qubit register state. In some examples, the qubit programmer performs the desired rotation O for a predetermined duration T. i A predetermined signal level S over a certain period i A signal level S may be applied. In some examples, multiple signal levels may be applied over multiple durations, ordered or otherwise associated, to assert a quantum gate operation on one or more qubits of a qubit register, as shown in Figure 3. Generally, each signal level S i and each duration T i This is a control parameter that can be adjusted by appropriate programming of the controller 18.

[0023]

[0030] In this specification, the terms “quantum circuit” and “quantum algorithm” mean a predetermined sequence of basic quantum gates and / or measurement operations that can be executed by the quantum computer 10. A quantum circuit may be used, for example, to transform the quantum state of the qubit register 12 for performing classical or non-basic quantum gate operations or for applying density operators. In some examples, a quantum circuit may be used to perform a predetermined operation f(x) that can be incorporated into a complex sequence of operations. To ensure that adjoint operations are performed, a quantum circuit that maps n input qubits |x> to m output qubits or auxiliary qubits |y=f(x)> is used, and a quantum gate that acts on (n+m) qubits is used.

number

number

[0024]

[0031] Although implicit in this specification, it is possible to examine each qubit 14 of any qubit register 12 from the quantum interface 34 so that the standard basis vector |0> or |1> characterizing the quantum state of each qubit 14 is reliably revealed. However, in some implementations, errors may occur in measuring the quantum state of physical qubits. Therefore, any qubit 14 can be implemented as a logical qubit, which involves grouping physical qubits measured according to an error-correcting quantum algorithm or circuit that reveals the quantum state of logical qubits with confidence above a threshold.

[0025] 3. Topology Outcome Code

[0032] Because isolating qubits from their noisy environments is inherently difficult, quantum error correction is almost certainly necessary to reliably execute large-scale quantum algorithms. A quantum error correction circuit includes a set of measurements whose parity for the error-free outcome is predetermined. Thus, these sets of measurements correspond to a check for a code that can be used to identify and correct errors. A wide class of quantum circuits can efficiently find so-called “outcome codes” [Reference 1].

[0026]

[0033] However, a major problem is decoding, which involves inversely mapping code check violations to their corresponding causal errors. The general problem with decoding is that it is NP-hard [Reference 2]. [Reference 1] proposes a sparsification algorithm that identifies low-weight checks in outcome codes that can be used to efficiently construct so-called LDPC decoders. Unfortunately, current LDPC decoders are slow to run on quantum codes, making them difficult or impossible to use at large scales. Furthermore, these decoders generally perform poorly on topological quantum codes.

[0027]

[0034] Decoders based on the minimum-weight perfect matching (MWPM) algorithm [Reference 3] and the union-find (UF) algorithm [Reference 4] show significant improvements in execution time and are usable for common and practical quantum codes, including surface codes [Reference 3] and Floquet codes [References 5][Reference 6]. However, these topology decoders are not simply low-weight because they require corresponding code checks to satisfy additional constraints. In particular, the original structure of the topology decoder is such that an error in each circuit violates exactly two code checks. The sparsification algorithm in [Reference 1] is not guaranteed to respect that structure.

[0028]

[0035] Some of the terminology used in this disclosure can be visualized as shown in Figure 4. Figure 4 is a schematic diagram of a lattice 40 of physical qubits 14. As is consistent with the description in Section 1, each physical qubit contributes 1 degree of freedom to the entire set of quantum states held in the quantum computer (e.g., the qubit register 12 in Figure 1). In some examples, each degree of freedom is a spin-1 / 2 degree of freedom, as represented by the Bloch sphere in Figure 2. In the lattice 40, each physical qubit 14 is mapped to the corresponding vertex 42 of a planar graph 44. The structure and properties of the planar graph are understandable in the context of graph theory, which will be familiar to those skilled in the art. In the illustrated example, the lattice 40 is a square lattice, but this feature is not essential, as lattices of non-square geometries are also conceivable. In the planar graph 44, edges 46 intersect in the set of vertices 42 and also define the set of faces 48. In the topology error correction quantum code, the stabilizer operator A i However, this acts on the physical qubits surrounding each vertex i. Furthermore, the stabilizer operator B i However, this acts on the physical qubits that define each face j. The “stabilizer space” of a topology error-correcting quantum code is a vector space in which operators A and B each shrink to become the identity operator. (As an unrestricted example) In the case of a toric topology error-correcting quantum code, the stabilizer space is 4-dimensional and therefore capable of representing the quantum information of 2 logical qubits. Generally speaking, each circuit error causes a quantum state of lattice 40 to move out of the stabilizer space, resulting in vertices and faces in which operators A and / or B differ from the identity operator. The location of such anomalous operators on lattice 40 defines a “syndrome” in the topology error-correcting quantum code, which can be used for error correction. If interested in further information, a comprehensive literature on topology error-correcting quantum codes is referred to.

[0029]

[0036] Figure 5 shows the code for exemplary Algorithm 1, which generates checks usable with a topology decoder. The high-level concept is to leverage the grid structure by searching for checks of outcome codes along the timeline of the grid faces. Each face has a corresponding abbreviated outcome code. The checks of the abbreviated codes are converted into a concise time-series order defined below.

[0030]

[0037] For input circuits based on topology codes (e.g., toric codes) or Floquet codes, the output of algorithm 1 is a set of checks that can be used to construct a topology decoder. Each check corresponds to a vertex in the graph. Each error that can occur in the circuit is detected by some subset of the checks. Subsets of checks correspond to edges or hyperedges in the graph. If each error is detected by two or fewer checks, the graph may have no hyperedges and be used directly by an MWPM decoder or UF decoder. Otherwise, the hyperedges may be converted to some other form of edge (e.g., as described in [Reference 7]).

[0031]

[0038] Figure 6 shows exemplary Procedure 2, which transforms abbreviated code checks into a concise chronological order achieved by a sequence of row operations. First, the matrix of checks is transformed into abbreviated row echelon form. Algorithm 1 sets a unique starting point for each check to make the columns chronological order. The remaining task is to transform each row so that each row has a unique ending point and the overall duration is minimized. In each iteration, the row with the last ending point is identified. If there are multiple rows with the same ending point, the lowest-ranking such row is selected and used to shorten the ending points of the remaining rows, making them more "concise." Then, if possible, the weight of the selected row is reduced.

[0032]

[0039] Algorithm 1 requires, in addition to the circuit, an input that identifies the measurements belonging to each face of the lattice. The choice of lattice depends on the quantum error correction code from which the circuit is derived. For example, the surface code corresponds to a square lattice, and the honeycomb code corresponds to a hexagonal lattice. In some examples, this input may be supplied by the user. However, in other examples, the faces may be inferred by the program from the circuit. In some circuits, face inference is direct. For example, a CNOT-based syndrome extraction circuit for a surface code specifies some qubits as data and some qubits as auxiliary. The coordinates of each auxiliary qubit correspond to the center of the face, and the entire face is defined by a CNOT gate with a support at the center. In the case of a circuit consisting of 1-qubit and 2-qubit measurements (e.g., the circuit used for the Floquet code), a planar embedding may be computed and used to identify the faces.

[0033]

[0040] Some circuits, even those based on topology codes, may include checks that are non-local within the grid plane or not confined to the grid plane. This can occur, for example, in circuits that prepare and measure the logical operators of the code. Such global checks can interfere with the structure and performance of the topology decoder.

[0034]

[0041] Several variations of Algorithm 1 take this scenario into consideration. One option is to retain only checks whose duration falls below a certain cutoff value. In the case of a typical syndrome extraction circuit where a circuit of constant depth is repeatedly applied, the cutoff value will be proportional to the depth of the repeated sub-circuits. Another option is a modification of line 8, which is to add all eigenchecks found with respect to a given face. In another example, a suitable algorithm may add only checks that are not yet in the span of set T. This is computationally more expensive, but ensures that non-local checks appear at most once in the set of checks.

[0035]

[0042] Figure 7 shows an exemplary method 50 for correcting one or more errors in applying a Clifford circuit to a quantum computer's qubit register. Generally speaking, each Clifford circuit applicable to this method may include one or more Clifford gates and may further include one or more Pauli measurements.

[0036]

[0043] In method 50, 52, the classical computer receives circuit data defining a Clifford circuit. In 54, the classical computer selects a lattice corresponding to the Clifford circuit and the class of the desired quantum error correction code. For example, a square lattice may be selected if a surface code is desired, and a hexagonal lattice may be selected if a honeycomb code is desired. Operationally, the classical computer may reach a decision regarding the lattice based on the circuit data received in 52.

[0037]

[0044] In step 56, the classical computer receives additional data that identifies one or more measurements belonging to each of several faces of the lattice. In step 58, the classical computer outputs an outcome code based on the circuit data. The outcome code includes a sequence of outcome checks, each corresponding to an expected error syndrome with respect to applying the Clifford circuit to the qubit register. Typically, the outcome code output in step 58 is an arbitrary outcome code, which is not necessarily a topology outcome code at this stage of the process and may not be suitable for downstream topology decoding.

[0038]

[0045] In method 50, the classical computer outputs a topology outcome code based on circuit data, additional data, and outcome code. The topology outcome code includes a sequence of check operators that support quantum error correction by the topology decoder. In this way, method 50 enables error correction by applying a Clifford circuit to the qubit register. In some examples, the topology outcome code may include a surface code, and in some examples, the topology outcome code may include a Floquet code. Other types of topology outcome codes are also conceivable. Generally speaking, each error found and corrected by method 50 violates exactly two outcome checks of the topology outcome code according to topology decoding.

[0039]

[0046] More specifically, in outputting a topology outcome code, the classical computer accumulates outcome checks along multiple timelines on multiple faces of the grid in step 62. For each of the multiple faces of the grid, the classical computer computes a shortened outcome code corresponding to that face in step 64. In step 66, the classical computer transforms the multiple outcome checks of the shortened outcome code into a concise time-series order (e.g., sorts them). In some examples, the concise time-series order is an order that reduces the overlap between outcome checks. In some examples, the concise time-series order is an order that reduces the duration of one or more outcome checks among the outcome checks.

[0040]

[0047] Method 50 allows for various variations and extensions. For example, the outcome code corresponding to a circuit may include at least one outcome check that is non-local within a grid plane or not confined to a grid plane. In some examples, the method may retain such outcome checks only if their duration falls below a predetermined threshold in order to address this state. In a more specialized variation of this approach, the Clifford circuit may be a syndrome extraction circuit to which subcircuits of constant depth are repeatedly applied, where the threshold may be proportional to the constant depth. In another example where the outcome code includes outcome checks that are non-local within a grid plane or not confined to any grid plane, only outcome checks that are not in an existing span of the accumulation set are accumulated (e.g., in row 8 of algorithm 1).

[0041]

[0048] Continuing in method 50, in 68 the classical computer builds a topology decoder for the topology outcome code. Generally speaking, the topology decoder may be built according to the circuit data received in 62. In some examples, the topology decoder is further built according to additional data received in 64. In 70 the topology decoder decodes the execution result of the topology outcome code to correct one or more errors in applying the Clifford circuit to the qubit register. In some examples, the topology decoder is a minimum-weight perfect matching decoder or a union-find decoder.

[0042] 4. References, description of classical computers, and conclusions

[0049] For those interested, please refer to the following references, which are included herein by reference for all purposes. [Reference 1] Nicolas Delfosse and Adam Paetznick, “Spacetime codes of Clifford circuits” (2023). [Reference 2] Elwyn Berlekamp, ​​Robert McEliece, and Henk Van Tilborg, “On the inherent intractability of certain coding problems (corresp.)” IEEE Transactions on Information Theory 24:3, 384-386 (1978). [Reference 3] Eric Dennis. Alexei Kitaev, Andrew Landahl, and John Preskill, “Topological quantum memory” Journal of Mathematical Physics 43:9, 4452-4505 (2002). [Reference 4] Nicolas Delfosse and Naomi H. Nickerson, “Almost-linear time decoding algorithm for topological codes,” Quantum 5,595 (2021). [Reference 5] Matthew B. Hastings and Jeongwan Haah, “Dynamically generated logical qubits,” Quantum 5, 564 (2021). [Reference 6] Jeongwan Haah and Matthew B. Hastings, “Boundaries for the Honeycomb Code,” Quantum 6, 693 (Apr 2022). [Reference 7] Nicolas Delfosse, Adam Paetznick, Jeongwan Haah, Matthew Hastings, and Marcus Silva, “Splitting decoder for quantum codes”.

[0043]

[0050] The methods described herein may be associated with a computer system including one or more computing devices. Such methods and processes may be implemented as application programs or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0044]

[0051] Figure 8 is a schematic diagram of a classical computer 94 configured to provide some or all of the classical computer system functionality disclosed herein. The classical computer 94 may take the form of a personal computer, an application server computer, or any other computing device.

[0045]

[0052] Classical computer 94 includes a logic system 96 and a computer memory system 98. Classical computer 94 may optionally include a display system 100, an input system 102, a network system 104, and / or other systems not shown.

[0046]

[0053] A logic system 96 includes one or more physical devices configured to execute instructions. For example, a logic system may be configured to execute instructions that are part of at least one operating system (OS), application, service, and / or other program structure. A logic system may include at least one hardware processor (e.g., a microprocessor, central processor, CPU, and / or graphics processing unit (GPU)) configured to execute software instructions. Additionally or alternatively, a logic system may include at least one hardware device or firmware device configured to execute hardware instructions or firmware instructions. The processors of a logic system may be single-core or multi-core, and the instructions executed therein may be configured for sequential, parallel, and / or distributed processing. Individual components of a logic system may optionally be distributed across two or more separate devices, which may be remotely located and / or configured to perform cooperative processing. Embodiments of a logic system may be virtualized and executed by a group of remotely accessible, network-connected computing devices configured as a cloud computing form.

[0047]

[0054] The computer memory system 98 includes at least one physical device configured to temporarily and / or permanently hold computer system information (e.g., data and instructions executable by the logic system 96). If the computer memory system includes two or more devices, those devices may be located in the same location or separately. The computer memory system 98 may include at least one volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location addressable, file addressable, and / or content addressable computer memory device. The computer memory system 98 may include at least one removable and / or built-in computer memory device. When the logic system executes an instruction, the state of the computer memory system 98 may be transformed (e.g., to hold different data).

[0048]

[0055] The embodiments of the logic system 96 and the computer memory system 98 may be integrated into one or more hardware logic components. Any such hardware logic component may include, for example, at least one integrated circuit for a specific program or application (PASIC / ASIC), a standard product for a specific program or application (PSSP / ASSP), a system on a chip (SOC), or a coupled programmable logic device (CPLD).

[0049]

[0056] The logic system 96 and the computer memory system 98 can cooperate to instantiate one or more logic machines or logic engines. In this specification, the terms “machine” and “engine” refer collectively to a combination of cooperating hardware, firmware, software, instructions, and / or other arbitrary components that provide computer system functionality. In other words, machines and engines are not abstract concepts but always have a tangible form. A machine or engine can be instantiated by a single computing device, or a machine or engine may include two or more sub-components instantiated by two or more different computing devices. In some implementations, a machine or engine includes local components (e.g., software applications executed by a computer system processor) that cooperate with remote components (e.g., cloud computing services provided by a network of one or more server computer systems). The software and / or other instructions that give functionality to a particular machine or engine may optionally be stored as one or more unexecuted modules in one or more computer memory devices.

[0050]

[0057] The machines and engines may be implemented using any preferred combination of machine learning (ML) techniques and artificial intelligence (AI) techniques. Non-limiting examples of techniques that may be incorporated into one or more machine implementations include support vector machines, multilayer neural networks, convolutional neural networks (e.g., spatial convolutional networks for processing images and / or videos, and / or other preferred convolutional neural networks configured to convolve and pool features spanning one or more time and / or spatial dimensions), recurrent neural networks (e.g., long-short-term memory networks), associative memories (e.g., lookup tables, hash tables, Bloom filters, neural Turing machines, and / or neural random-access memories), unsupervised spatial analysis and / or clustering methods (e.g., nearest neighbor algorithms, topology data analysis, and / or k-means algorithms), and / or graphical models (e.g., (hidden) Markov models, Markov random fields, (hidden) conditional random fields, and / or AI knowledge bases).

[0051]

[0058] If a display system 100 is included, it may be used to present a visual representation of the data held in the computer memory system 98. In some examples, the visual representation may take the form of a graphical user interface (GUI). The display system may include one or more display devices utilizing almost any type of technology. In some implementations, the display system may include one or more virtual reality, augmented reality, or mixed reality displays.

[0052]

[0059] If an input system 102 is included, it may include one or more input devices, or may interface with one or more input devices. The input devices may be sensor devices or user input devices. Examples of user input devices include keyboards, mice, or touchscreens.

[0053]

[0060] If a network system 104 is included, it may be configured to connect the classical computer 94 to one or more other computer systems. The network system may include wired and / or wireless communication devices compatible with one or more different communication protocols. The network system may be configured to communicate over a personal area network, a local area network, and / or a wide area network.

[0054]

[0061] In conclusion, one aspect of the present disclosure relates to a method for correcting errors in applying a Clifford circuit to a qubit register of a quantum computer, the method comprising: (a) receiving circuit data defining a Clifford circuit; (b) receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) outputting an outcome code based on the circuit data, the outcome code comprising a sequence of outcome checks, each outcome check outputting an outcome code based on the circuit data corresponding to an expected error syndrome in applying a Clifford circuit to a qubit register; and (d) outputting a topology outcome code based on the circuit data, the additional data, and the outcome code, the topology outcome code comprising a sequence of check operators supporting quantum error correction by a topology decoder, thereby outputting a topology outcome code that enables error correction in applying a Clifford circuit to a qubit register.

[0055]

[0062] In some implementations, the topology outcome code includes a surface code or a Floquet code. In some implementations, an error is one of several errors, and each error violates exactly two outcome checks. In some implementations, the method further includes selecting a Clifford circuit and a lattice according to the class of quantum error correction code. In some implementations, the outcome code includes outcome checks that are non-local within a lattice plane or not confined to any lattice plane, and the method further includes retaining the outcome check only if its duration falls below a predetermined threshold. In some implementations, the Clifford circuit is a syndrome extraction circuit to which subcircuits of constant depth are repeatedly applied, and the threshold is proportional to that constant depth. In some implementations, outputting a topology outcome code includes accumulating outcome checks along multiple timelines of multiple faces of a lattice, computing a shortened outcome code corresponding to each of the multiple faces of the lattice, and converting the multiple outcome checks of the shortened outcome code into a time-series order, where the time-series order is an order that reduces overlap between outcome checks and / or an order that shortens the duration of one or more outcome checks among the outcome checks. In some implementations, the outcome code includes outcome checks that are non-local within the faces of the lattice or not confined to any face of the lattice, and only outcome checks that are not in an existing span of the accumulation set are accumulated. In some implementations, the Clifford circuit includes one or more Clifford gates. In some implementations, the Clifford circuit includes one or more Pauli measurements. In some implementations, the method further includes building a topology decoder for the topology outcome code and decoding the execution result of the topology outcome code with the topology decoder in order to correct errors in applying the Clifford circuit to the qubit register.In some implementations, the topology decoder is either a minimum-weight perfect matching decoder or a union-find decoder. In some implementations, the topology decoder is built based on circuit data.

[0056]

[0063] Another aspect of the present disclosure relates to a computer system operationally coupled to a quantum computer, the computer system including a processor and a computer memory operationally coupled to the processor, which holds instructions causing the processor to perform error correction in applying a Clifford circuit to a qubit register of a quantum computer. These instructions include (a) an instruction to receive circuit data defining a Clifford circuit; (b) an instruction to receive additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) an instruction to output an outcome code based on the circuit data, the outcome code comprising a sequence of outcome checks, each outcome check being an instruction to output an outcome code based on the circuit data corresponding to an expected error syndrome in applying a Clifford circuit to a qubit register; and (d) an instruction to output a topology outcome code based on the circuit data, the additional data, and the outcome code, the topology outcome code comprising a sequence of check operators supporting quantum error correction by a topology decoder, thereby enabling error correction in applying a Clifford circuit to a qubit register.

[0057]

[0064] In some implementations, these instructions further include instructions for selecting a lattice according to the Clifford circuit and the class of quantum error correction code. In some implementations, outputting a topology outcome code includes accumulating outcome checks along multiple timelines of multiple faces of the lattice, computing a shortened outcome code corresponding to each of the multiple faces of the lattice, and converting the multiple outcome checks of the shortened outcome code into a time-series order, where this time-series order is an order that reduces overlap between outcome checks and / or an order that shortens the duration of one or more outcome checks. In some implementations, these instructions further include instructions for building a topology decoder for the topology outcome code, and instructions for decoding the execution result of the topology outcome code by the topology decoder in order to correct errors in applying the Clifford circuit to the qubit registers. In some implementations, the topology decoder is a minimum-weight perfect matching decoder or a union-find decoder. In some implementations, the topology decoder is built based on the circuit data.

[0058]

[0065] Another aspect of the present disclosure relates to a method for correcting errors in applying a Clifford circuit to a qubit register of a quantum computer. The method comprises (a) receiving circuit data defining a Clifford circuit, (b) receiving additional data identifying one or more measurements belonging to each of several faces of a lattice, and (c) outputting an outcome code based on the circuit data, the outcome code comprising a sequence of outcome checks, each outcome check outputting an outcome code based on the circuit data corresponding to an expected error syndrome in applying a Clifford circuit to a qubit register, and (d) Outputting a topology outcome code based on circuit data, additional data, and outcome codes, wherein the topology outcome code includes a sequence of check operators that support quantum error correction by a topology decoder, thereby enabling error correction in applying a Clifford circuit to a qubit register, and outputting a topology outcome code includes accumulating outcome checks along multiple timelines of multiple faces of a lattice, calculating a shortened outcome code corresponding to each of the multiple faces of the lattice, and converting the multiple outcome checks of the shortened outcome code into a time-series order, where the time-series order is an order that reduces overlap between outcome checks and / or an order that shortens the duration of one or more outcome checks among the outcome checks.

[0059]

[0066] This disclosure is presented with reference to the figures in the accompanying drawings as illustrative examples. Components, process steps, and other elements that may be substantially the same in one or more drawings are identified as equivalent and described with minimal repetition. However, it should be noted that each element identified as equivalent may differ to some extent. Furthermore, it should be noted that the drawings are schematic and are not generally drawn to the correct scale. Rather, the drawing scale, aspect ratio, and number of illustrated components may be deliberately varied to make certain features or relationships clearer. The plots shown in the figures are theoretical unless otherwise noted.

[0060]

[0067] Naturally, the configurations and / or approaches described herein are illustrative in nature, and their specific embodiments or examples should not be taken as limiting, as various variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Accordingly, the various actions illustrated and / or described may be performed in the order illustrated and / or described, in a different order, in parallel, or omitted. Similarly, the order of the processes described above may also be changed. With this in mind, the phrase "based at least partly on" is intended to be recognized as not requiring, nor excluding, appropriate additional logic that, when performed in combination with the described logic, provides additional benefits.

[0061]

[0068] The scope of this disclosure includes all novel and non-trivial combinations and subcombinations of the various processes, systems and configurations disclosed herein, as well as other features, functions, actions, and / or characteristics, and any equivalent thereof.

Claims

1. A method (50) for correcting errors in applying a Clifford circuit to a qubit register (12) of a quantum computer (10), Receiving circuit data that defines the Clifford circuit (52), Receiving additional data (56) that identifies one or more measurements belonging to each of the multiple faces (48) of the grid (44), (58) Outputting an outcome code based on the circuit data, wherein the outcome code includes a sequence of outcome checks, each outcome check outputting an outcome code based on the circuit data that corresponds to an error syndrome expected with respect to applying the Clifford circuit to the qubit register. Outputting a topology outcome code based on the circuit data, the additional data, and the outcome code (60), wherein the topology outcome code includes a sequence of check operators that support quantum error correction by the topology decoder, thereby enabling error correction in applying the Clifford circuit to the qubit register. Methods that include...

2. The method according to claim 1, wherein the topology outcome code includes a surface code or a Floquet code.

3. The method according to claim 1, wherein the error is one of several errors, and each error violates exactly two outcome checks.

4. The method according to claim 1, further comprising selecting the lattice according to the class of the Clifford circuit and quantum error correction code.

5. The method according to claim 1, wherein the outcome code includes an outcome check that is non-local within the plane of the grid or is not confined to any plane of the grid, and the method further includes retaining the outcome check only if the duration of the outcome check falls below a predetermined threshold.

6. The method according to claim 5, wherein the Clifford circuit is a syndrome extraction circuit to which a sub-circuit of a constant depth is repeatedly applied, and the predetermined threshold is proportional to the constant depth.

7. Outputting the aforementioned topology outcome code means Accumulating outcome checks along multiple timelines on multiple faces of the grid, For each of the plurality of faces of the grid, Calculate the shortened outcome code corresponding to the aforementioned surface, The transformation involves converting the multiple outcome checks of the shortened outcome code into a time-series order, wherein the time-series order is such that it reduces the overlap between the outcome checks and / or shortens the duration of one or more of the outcome checks. The method according to claim 1, including the method described in claim 1.

8. The method according to claim 1, wherein the outcome code includes outcome checks that are non-local within the plane of the grid or not confined to any plane of the grid, and only outcome checks that are not in an existing span of the accumulation set are accumulated.

9. The method according to claim 1, wherein the Clifford circuit includes one or more Clifford gates.

10. The method according to claim 1, wherein the Clifford circuit includes one or more Pauli measurements.

11. Building a topology decoder for the topology outcome code, In order to correct the error when applying the Clifford circuit to the qubit register, the execution result of the topology outcome code is decoded by the topology decoder, The method according to claim 1, further comprising:

12. The method according to claim 11, wherein the topology decoder is a minimum weight perfect matching decoder or a pie set data structure decoder.

13. The method according to claim 11, wherein the topology decoder is built according to the circuit data.

14. A computer system (94) that is operationally coupled to a quantum computer (10), Processor (96) and, A computer memory (98) which is operationally coupled to the processor and holds instructions that cause the processor to correct errors in applying a Clifford circuit to the qubit register (12) of the quantum computer, wherein the instructions are Instruction (52) to receive circuit data defining the Clifford circuit, Instruction (56) to receive additional data that identifies one or more measurements belonging to each of the multiple faces of the grid, An instruction (58) to output an outcome code based on the circuit data, wherein the outcome code includes a sequence of outcome checks, each outcome check being an instruction to output an outcome code based on the circuit data, which corresponds to an error syndrome expected with respect to applying the Clifford circuit to the qubit register. An instruction (60) to output a topology outcome code based on the circuit data, the additional data, and the outcome code, wherein the topology outcome code includes a sequence of check operators that support quantum error correction by a topology decoder, thereby enabling error correction in applying the Clifford circuit to the qubit register, Computer memory, including A computer system, including a computer system.

15. The computer system according to claim 14, wherein the instruction further includes an instruction to select the lattice according to the Clifford circuit and the class of quantum error correction code.

16. Outputting the aforementioned topology outcome code means Accumulating outcome checks along multiple timelines on multiple faces of the grid, For each of the plurality of faces of the grid, Calculate the shortened outcome code corresponding to the aforementioned surface, The transformation involves converting the multiple outcome checks of the shortened outcome code into a time-series order, wherein the time-series order is such that it reduces the overlap between the outcome checks and / or shortens the duration of one or more of the outcome checks. The computer system according to claim 14, including the computer system described in claim 14.

17. The aforementioned instruction further states: Instructions for building a topology decoder for the topology outcome code, In order to correct the error when applying the Clifford circuit to the qubit register, an instruction is given to decode the execution result of the topology outcome code using the topology decoder, The computer system according to claim 14, including the computer system according to claim 14.

18. The computer system according to claim 17, wherein the topology decoder is a minimum weight perfect matching decoder or a pie set data structure decoder.

19. The computer system according to claim 17, wherein the topology decoder is built according to the circuit data.

20. A method (50) for correcting errors in applying a Clifford circuit to a qubit register (12) of a quantum computer (10), wherein the method is Receiving circuit data that defines the Clifford circuit (52), Receiving additional data (56) that identifies one or more measurements belonging to each of the multiple faces (48) of the grid (44), (58) Outputting an outcome code based on the circuit data, wherein the outcome code includes a sequence of outcome checks, each outcome check outputting an outcome code based on the circuit data that corresponds to an error syndrome expected with respect to applying the Clifford circuit to the qubit register. Outputting a topology outcome code based on the circuit data, the additional data, and the outcome code (60), wherein the topology outcome code includes a sequence of check operators that support quantum error correction by the topology decoder, thereby enabling error correction in applying the Clifford circuit to the qubit register. Includes, Outputting the aforementioned topology outcome code means Accumulating outcome checks along multiple timelines on multiple faces of the grid (62), For each of the plurality of faces of the grid, Calculating a shortened outcome code corresponding to the aforementioned surface (64), The transformation involves converting the multiple outcome checks of the shortened outcome code into a time-series order, wherein the time-series order is such that it reduces the overlap between the outcome checks and / or shortens the duration of one or more of the outcome checks. Methods that include...

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