Selection of Decoders Used in Quantum Computing Devices
Patent Information
- Application Number
- JP2026501091
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2024-07-29
- Publication Date
- 2026-09-01
Smart Images
Figure 2026529477000001_ABST
Abstract
Description
Technical Field
[0001] Cross-Reference to Related Applications
[0001] The present application claims priority to U.S. Provisional Patent Application No. 63 / 578,730, filed on August 25, 2023, which is incorporated herein by reference in its entirety for all purposes. Background Art
[0002]
[0002] A fault-tolerant quantum computing device is a quantum computing device in which error correction is performed using an error correction code. One such error correction code is the surface code, which is implemented in a plurality of different quantum hardware configurations. Summary of the Invention Means for Solving the Problems
[0003]
[0003] According to one aspect of the present disclosure, a computing system including one or more processing devices is provided. The one or more processing devices are configured to receive a plurality of quantum circuit parameters including code parameters of the error correction code and the number of T gates included in the quantum circuit. The one or more processing devices are further configured to receive individual decoder parameters for each of a plurality of candidate decoders. The decoder parameters include a physical noise rate of a plurality of physical qubits on which the quantum circuit is configured to be executed and a stopping time of the candidate decoder. The one or more processing devices are further configured to calculate individual space-time costs for the candidate decoders based at least in part on the quantum circuit parameters and the decoder parameters. The one or more processing devices are further configured to output a selection of a minimum space-time cost decoder among the plurality of candidate decoders for implementation in a quantum computing device.
[0004] This Summary is provided to introduce a simplified form of a series of concepts that are further described in the detailed description below. This Summary is not intended to identify key features or essential features of the subject matter recited in the claims, nor is it intended to be used to limit the scope of the subject matter recited in the claims. Furthermore, the subject matter recited in the claims is not limited to implementations that solve any or all disadvantages noted anywhere in the present disclosure. [Brief Description of Drawings]
[0005] Brief Description of Drawings [Figure 1]
[0005] According to an exemplary embodiment, a schematic diagram is shown of an exemplary computing system that includes one or more processing devices on which decoder selection is performed with respect to a quantum computing device. [Figure 2A]
[0006] According to the example of Figure 1, an example of a physical qubit layout configured for use with a surface code is shown. [Figure 2B]
[0007] According to the example of Figure 1, an example of a physical qubit layout configured for use with a Rook code is shown. [Figure 3]
[0008] According to the example of Figure 1, a schematic diagram is shown of the computing system in a case where one or more processing devices are further configured to calculate a maximum decoding time and decoding execution time distribution of candidate decoders. [Figure 4]
[0009] According to the example of Figure 1, a schematic diagram is shown of the computing system in a case where one or more processing devices are further configured to calculate syndrome extraction circuit depth. [Figure 5]
[0010] According to the example of Figure 1, a schematic diagram is shown of the computing system in a case where one or more processing devices are configured to calculate a minimum odd integer code distance of candidate decoders. [Figure 6]
[0011] According to the example of Figure 1, an exemplary error threshold simulation plot is shown, which shows results of a maximum range error threshold simulation for an exemplary surface code. [Figure 7A]
[0012] Figure 1 shows a first execution time distribution plot illustrating the individual decoding execution time distributions of the first and second decoders against a first value of the syndrome extraction circuit cycle time. [Figure 7B]
[0013] Figure 7A shows the first range plots of the individual ranges of the first and second decoders, as in the example. [Figure 7C]
[0014] A second execution time distribution plot is shown, illustrating the individual decoding execution time distributions of the first and second decoders against a second value of the syndrome extraction circuit cycle time, as in the example of Figure 1. [Figure 7D]
[0015] Figure 7C shows a second range plot of the ranges for the first and second decoders, as an example. [Figure 8A]
[0016] Figure 1 shows a flowchart illustrating a method for selecting a decoder to be implemented in a quantum computing device, to be used in conjunction with the computing system. [Figure 8B]
[0017] The following are additional steps to the method shown in Figure 8A, which may be performed when calculating the spatiotemporal cost from the quantum circuit parameters and decoder parameters. [Figure 8C]
[0018] This shows an additional step in the method of calculating spatiotemporal costs as shown in Figure 8B. [Figure 8D]
[0019] Figure 8D illustrates an example of additional steps that may be performed when calculating the syndrome extraction circuit depth. [Figure 8E]
[0020] Additional steps of the method shown in Figure 8A may be performed in some cases. [Figure 9]
[0021] Figure 1 shows a schematic diagram of an exemplary computing environment in which the computing system can be instantiated. [Modes for carrying out the invention]
[0006] Detailed explanation
[0022] Several different decoder algorithms have been developed for surface codes. For example, in recent years, efficient decoders for surface codes based on minimum-weight matching algorithms have been developed and further optimized. Another decoder algorithm is the Union-Find decoder, which has a low worst-case computational complexity but slightly lower accuracy. Other decoders based on Markov chain Monte Carlo, neural networks, and reinforcement learning have also been proposed. Therefore, developers of quantum computing devices face the challenge of deciding which decoder to implement.
[0007]
[0023] Decoders are typically compared to each other by considering their accuracy (relating to the logical error rate they achieve) or their average or worst-case computational complexity. However, metrics such as asymptotic complexity do not provide all the information relevant to selecting a decoder for use in a given fault-tolerant quantum computer. Rather, decoder selection depends on several contextual factors. First, the type of qubits included in the quantum computer affects the performance of different decoders due to differences in qubit noise rate, gate speed, and measurement speed. In cases where the qubit speed is slow, slower decoders may also be more viable.
[0008]
[0024] Secondly, the encoding used for the logic qubit also influences the decoder selection. More broadly, the implementation details of the logic gate and the compilation algorithm also influence the decoder selection. To simplify the explanation of the decoder selection protocol in the following example, we consider a simple compilation algorithm for a single logic qubit. However, other compilation algorithms may be used in other examples.
[0009]
[0025] Figure 1 schematically shows an exemplary computing system 10, which includes one or more processing units 12 on which decoder selection is performed for a quantum computing device 50. The computing system 10 further includes one or more memory devices 14 that are communicatively coupled to one or more processing units 12. The multiple processing units 12 may include, for example, one or more central processing units (CPUs), one or more graphics processing units (GPUs), and / or one or more other hardware accelerators. The one or more memory devices 14 may include one or more volatile memory devices and / or one or more non-volatile memory devices. In some examples, the functions of the one or more processing units 12 and the one or more memory devices 14 are distributed across multiple physical computing devices, such as computing nodes located within a data center, while in other examples, the one or more processing units 12 and the one or more memory devices 14 are contained within a single physical computing device.
[0010]
[0026] In one or more processing units 12, a decoder is selected from among several candidate decoders 32 for implementation in the quantum computing device 50. In the quantum computing device 50, multiple logical qubits are instantiated, each having multiple individual physical qubits. The physical qubits are encoded to form logical qubits using an error correction code 22. For example, the error correction code 22 may be a surface code or a Floquet code.
[0011]
[0027] In the following explanation, we consider a single logical qubit encoded with a surface code of distance d. The surface code of distance d uses a d×d grid of data qubits. Figure 2A shows an example of a physical qubit layout 100 configured for use with the surface code. In the example in Figure 2A, each of the multiple brackets 102 contained in the physical qubit layout 100 contains four data qubits 104 arranged in a square. Each bracket 102 further contains an ancilla qubit 106 located at the center of the bracket 102. Individual electrical connections 108 extend between adjacent pairs of data qubits 104 and between each ancilla qubit 106 and each of the data qubits 104. Individual controlled NOT (CNOT) gates 110 are located along each of the ancilla qubit-data qubit electrical connections.
[0012]
[0028] Figure 2B shows another exemplary physical qubit layout 120 configured for use with the Flouke code. In physical qubit layout 120, the data qubits 104 form a square-octagonal grid.
[0013]
[0029] Returning to the example in Figure 1, one or more processing units 12 are further configured to receive a plurality of quantum circuit parameters 20. These quantum circuit parameters 20 include the code parameters 23 of the error correction code 22. In some examples, as will be discussed in more detail below, the code parameter 23 is the code distance d of the error correction code 22. In other examples, the code parameter 23 is the code length n of the error correction code 22.
[0014]
[0030] To avoid the accumulation of defects, a syndrome extraction circuit (SEC) 26 is continuously executed during the implementation of the error correction code 22. In the example where the error correction code 22 is a surface code, the syndrome extraction circuit 26 performs local measurements within the square lattice using an ancilla qubit 106 located at the center of each square bracket 102. For superconducting qubits, syndrome extraction can be implemented with one round of preparation, four rounds of CNOT gates, and one round of measurement. For other types of qubits, syndrome extraction can use a sequence of multiple measurements.
[0015]
[0031] One execution of the syndrome extraction circuit 26 is called an SEC cycle, and the time required for one SEC cycle is t SEC Expressed in seconds. In the example in Figure 1, the SEC cycle duration t of SEC26 is shown. SEC This is included within multiple quantum circuit parameters 20. SEC cycle duration t of SEC26 SEC This depends on the gate time and measurement time and can vary considerably. The most relevant time metric for decoder selection is not the decoding time itself, but rather the decoding time compared to the SEC cycle duration t. SEC The question is how it is compared to that. Therefore, in this specification, the execution time of SEC26 is used as the unit to represent the decoding time. For superconducting qubits, the standard assumption is t SEC =1O -6 That is. During the SEC cycle, d 2 -One syndrome bit is extracted (one per surface code bracket). These syndrome values are used by the decoder to identify and correct errors.
[0016]
[0032] Decoder selection is performed on quantum circuit 24. Quantum circuit 24 includes single-qubit Clifford gates H and S, implemented by a variation of the surface code patch with additional qubits. In the following explanation, we assume that the H and S gates are implemented within 2d SEC cycles. The logic Z measurement is performed on all d qubits contained in the surface code patch. 2may be executed within d SEC cycles ending with a physical measurement of qubits. Each of these gates is completed by a T gate implemented by state injection. To implement the T gate, a second logical qubit encoded in a surface code also with distance d is used to prepare the logical T state. The T gate is obtained using a standard state injection circuit.
[0017]
[0033] Single-qubit logical operations can be described or approximated by quantum circuit 24 of the following form:
Formula
[0018]
[0034] One goal of decoder selection is to, for a given number n T of T gates, achieve a sufficiently low logical error rate to reliably implement any sequence having the above form. Accordingly, the plurality of quantum circuit parameters 20 further include the number n T of T gates included in the quantum circuit 24.
[0019]
[0035] The one or more processing devices 12 are further configured to receive individual decoder parameters 30 for each of the plurality of candidate decoders 32. These decoder parameters 30 include a physical noise rate p of a plurality of physical qubits configured to execute the quantum circuit 24. As discussed in more detail below, the decoder parameters for each candidate decoder 32 further include an individual cutoff time M.
[0020]
[0036] The failure rate of a surface code decoder is the probability P that a logical error will appear after correction when d consecutive SEC cycles are executed at a physical noise rate p. L This is estimated by considering (d,p). One heuristic estimation based on standard CNOT-based SEC26 numerical results gives the following failure rate:
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[0021]
[0037] The decoding time elapsed during the execution of candidate decoder 32 is a random variable that depends on the fault configuration that occurs. The probability that candidate decoder 32 will be executed in t seconds is given by the decoding execution time distribution.
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[0022]
[0038] Figure 4 schematically shows the computation system 10 when one or more processing units 12 are further configured to calculate the SEC depth Δ, as will be discussed in more detail below. In the following example, the candidate decoder 32 is a sliding window decoder. The sliding window decoder takes d consecutive rounds of syndrome data, here denoted as r+1, r+2, ... as input and returns a Pauli correction for n data qubits. This Pauli correction is calculated to cancel out the effects of faults that occurred during the first half of the decoding window, covering the first t=(d+1) / 2 rounds. Then, this window is advanced t rounds, and the decoder is applied to the rounds r+t+1, r+t+2, ... In this way, the syndrome data for d consecutive rounds is decoded.
[0023]
[0039] In addition to the syndrome data, the candidate decoder 32 also takes the correction estimated for the previous window as input. Thus, the candidate decoder 32 waits for the decoding result of the previous window. Since this correction is a Pauli correction that is propagated through the quantum circuit 24 and can be applied to the qubit later, in circuits that only involve Clifford operations, this correction can be applied later. However, in non-Clifford gates (T gates in the current example), the application of the conditional S gate takes the logic result of the measurement of the ancilla qubit extracted by the candidate decoder 32 as input. This extraction is performed t for each T gate. max / t SEC This causes delays in the SEC cycle.
[0024]
[0040]
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[0025]
[0041] The minimum odd integer code distance σ is, up to n T For a sequence containing n T-gates, the following definition applies: Number of T-gates n T Given the physical noise rate p, the smallest odd integer code distance σ is the smallest odd integer σ ≥ 3, and the following equation holds:
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[0026]
[0042] Figure 5 schematically shows a calculation system 10 when one or more processing units 12 are configured to calculate the minimum odd integer code distance σ. One or more processing units 12 are configured to calculate a value of the estimated logic error rate term 80 equal to the left-hand side of the above inequality. One or more processing units 12 are further configured to execute a code distance minimization loop 82 in which one or more processing units 12 iteratively search for the minimum odd integer code distance σ.
[0027]
[0043] In the example in Figure 5, the quantum circuit parameter 20 further includes a logic error threshold ε. The logic error threshold ε is set to 1 / 2 in the example of the inequality discussed above. In other examples, the logic error threshold ε is a user-defined parameter. When one or more processors 12 execute the code distance minimization loop 82, one or more processors 12 are configured to compare an estimated logic error term 80 with the logic error threshold ε and calculate the minimum odd integer code distance σ as the code distance for which the value of the estimated logic error term 80 is less than the logic error threshold ε.
[0028]
[0044] The estimated logic error rate term 80 is used as a surrogate index of the logic error rate of the entire quantum circuit 24. However, the estimated logic error rate term 80 does not take into account the implementation details of H gates and S gates due to code deformation, so the logic error rate P L This is an inaccurate approximation of (d,p). The logic error rate P applies to H gates and S gates. L Using the same estimate for (d,p) is an approximation.
[0029]
[0045] Returning to Figure 1, the execution of the candidate decoder 32 may be stopped midway when it reaches its allocated maximum time. Therefore, the decoder parameter 30 further includes the stop time M of the candidate decoder 32. Accordingly, the maximum execution time of the candidate decoder 32 is the logical error rate P L This can be reduced at the expense of an increase in (d,p). For example, the pause time M can be chosen such that the logic error rate doubles when considering decoding timeout failures. This reduction in execution time allows the candidate decoder 32 to run at a rate that keeps pace with the rate of error accumulation in the quantum computer 50.
[0030]
[0046] The technique discussed below enables the identification of the stop time M of the candidate decoder 32 so that the candidate decoder 32 approaches the Pareto front of speed and logic error rate. Using the technique discussed below, the stop time M of the candidate decoder 32 is selected based at least in part on the failure rate and execution time distribution of the candidate decoder 32. One or more processing units 12 calculate the decoding execution time distribution calculated by Monte Carlo simulation 66 as discussed above with respect to Figure 3.
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[0031]
[0047] To reduce the impact of decoding delay, the candidate decoder 32 can be stopped after M seconds. The stop time M is instead the SEC cycle time t. SEC It may be measured in units of . The initial decoding execution time distribution
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[0032]
[0048] In the numerical simulations discussed below, the upper limit
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[0033]
[0049] The performance of candidate decoder 32 can be measured as a function of its pause time M. The decoder's performance can be reliably implemented in the manner discussed above with respect to the definition of the minimum odd integer code distance σ.
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[0034]
[0050] As shown in the example in Figure 3, the range 60 of the candidate decoder 32 can be maximized by varying M. In the range maximization loop 64, one or more processing units 12 are configured to iteratively update the pause time M to search for the maximum value of the range 60. One or more processing units 12 are configured to calculate the pause time M of the candidate decoder 32 as the maximum range pause time M that nearly maximizes the range 60 of the candidate decoder 32. Maximizing the range 60 of the candidate decoder 32 is achieved by having a logic error rate P less than the logic error rate threshold ε on the output distribution of the entire quantum circuit 24. L This increases the depth of the logic gate sequence that can be implemented. As shown in the example in Figure 5, the range 60 of the candidate decoder 32 is calculated for the corresponding value of the minimum odd integer code distance σ. This value of the minimum odd integer code distance σ can be held as a constant input to the range calculation performed within the range maximization loop 64.
[0035]
[0051] In other examples, other criteria may be used when selecting the pause time M. For example, when one or more processing units 12 calculate the pause time M, the spatial and temporal overhead costs of the encoding specified by the error correction code 22 may be taken into consideration.
[0036]
[0052] For example, a qubit with a physical noise level p=10 -3 and the SEC cycle time of 1 microsecond, i.e., t SEC =10 -6 These values are the physical noise rate p and SEC cycle time t of the superconducting qubit. SEC This roughly corresponds to the logical error rate P of the candidate decoder 32 in this example, which is estimated using the heuristic discussed above. L It has (d,p). Candidate decoder 32 has d 6 Secondary maximum execution time and pd in microseconds 3 This logic error rate is achieved with a linear average execution time. The execution time distribution of candidate decoder 32 in this example is:
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[0037]
[0053] The maximum range stop time M of the candidate decoder 32 can be calculated numerically. Figure 6 shows the physical noise rate p = 10 -3 An example of a stop time simulation plot 200 is shown, which illustrates the maximum range stop time simulation results for a surface code at a distance of 25. In the example in Figure 6, the maximum range stop time M is equal to 58 SEC cycles. The stop time simulation plot 200 shows the execution time distribution 202 of stop probabilities at different numbers of SEC cycles. The stop time simulation plot 200 further shows the decoder range 204, with the number of SEC cycles that maximizes the decoder range 204 (58 SEC cycles) indicated by a dashed vertical line.
[0038]
[0054] Figures 7A to 7D show a comparison of the maximum range stop time simulation results for the first decoder 302 and the second decoder 304, where the first decoder 302 is slower but more accurate than the second decoder 304. The logic error rate P of the first decoder 302 in Figures 7A to 7D is estimated using the heuristic discussed above. L (d,p) is present. The maximum execution time of the first decoder 302 in Figures 7A to 7D is d 6 The second-order maximum execution time is equal to microseconds, and its average execution time is 5pd 3 Equivalent to a microsecond. The second decoder 304 is 2p L The logical error rate of (d,p), d 3 Linear maximum execution time in microseconds, and pd 3 It has an average execution time of microseconds.
[0039]
[0055] Figure 7A shows the physical noise rate p = 10 -3 and t SEC =10 -6 Individual decoding execution time distributions of the first decoder 302 and the second decoder 304 for a surface code of distance 25 with an SEC cycle time of seconds.
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[0040]
[0056] Figure 7C shows the physical noise rate p = 10 -3 and t SEC =10 -4 Individual decoding execution time distributions of the first decoder 302 and the second decoder 304 for a surface code of distance 25 with an SEC cycle time of seconds.
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[0041]
[0057] Returning to the example in Figure 1, we discuss below a protocol for selecting among the candidate decoders 32. Identifying the maximum range pause time M relates to maximizing the depth of logic circuits that can be reliably implemented with a given code distance d and a given decoder. However, because there is a trade-off between decoder speed and accuracy, optimizing pause time alone does not provide guidance on which candidate decoder 32 is more resource-efficient. The protocol discussed below identifies the most resource-efficient decoder for a fault-tolerant quantum computer 50 configured to perform a given number of logic operations. Using this protocol, one or more processors 12 are configured to calculate the individual spatiotemporal costs 40 of the candidate decoders 32 based at least in part on quantum circuit parameters 20 and decoder parameters 30.
[0042]
[0058] The decoder resource cost calculation protocol is n T This is used when designing a quantum computer 50 configured to reliably execute a certain number of logic T gates (in this example, it refers to the result of a complete logic circuit with an error probability less than the logic error threshold ε). The spatiotemporal cost 40 of the candidate decoder 32 is given by the physical noise rate p and the SEC cycle time t. SEC The computation is performed given a qubit having the following properties. The spatiotemporal cost 40 of the candidate decoder 32 is defined as follows:
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[0043]
[0059] In the above equation for spatiotemporal cost 40, the SEC depth Δ is used as a surrogate indicator of the temporal duration for which the candidate decoder 32 is executed. In addition, 2d 2 The coefficient is used as a surrogate index of the spatial domain used to execute the candidate decoder 32. Thus, the spatiotemporal cost 40 incorporates both temporal and spatial information regarding decoder efficiency.
[0044]
[0060] The minimum spatiotemporal cost 41 of a candidate decoder 32 can be defined as the minimum of the spatiotemporal costs 40 of all odd distances and all stop times related to that candidate decoder 42. Therefore, the minimum spatiotemporal cost 41 of a candidate decoder 32 is given as follows: mincost(p,n T )=min{cost(p,n T ,d,M)|σodd,M>0} The number of T-gates is n T In cases where the physical noise rate p exceeds the threshold within the above range that can be achieved, the minimum spatiotemporal cost 41 can be infinite. The pair (σ,M) that achieves the minimum spatiotemporal cost 41 is given by σ,M = argmincost(p,n T It is represented as ).
[0045]
[0061] n TTo select the most efficient decoder for a fault-tolerant quantum computer 50 configured to implement 100 logic T-gates, one or more processors 12 are configured to select the minimum spatiotemporal cost decoder 42 from among a plurality of candidate decoders 32. When selecting the minimum spatiotemporal cost decoder 42, one or more processors 12 are configured to compare the minimum spatiotemporal costs 41 of the candidate decoders 32. The corresponding minimum odd integer code distance σ and maximum range stop time M of the minimum spatiotemporal cost decoder 42 are also selected. One or more processors 12 are further configured to output the selection of the minimum spatiotemporal cost decoder 42 from among the plurality of candidate decoders 32 for implementation in the quantum computer 50. In addition, one or more processors 12 may be further configured to output the minimum odd integer code distance σ and the maximum range stop time M.
[0046]
[0062] An example of calculating the spatiotemporal cost will be discussed below with respect to the first decoder 302 and the second decoder 304 in Figures 7A to 7D. In this example, the spatiotemporal cost 40 of the first decoder 302 and the second decoder 304 is n T =10 6 The minimum spatiotemporal cost 40 of the first decoder 302 is numerically approximated as 42,250,000,000, achieved with σ=13 and M=34. The minimum spatiotemporal cost of the second decoder 304 is numerically approximated as 35,828,000,000, achieved with σ=13 and M=15. Thus, the second decoder 304 has a higher spatiotemporal cost 40, even though the first decoder 302 provides twice as small a logic error rate as the second decoder 304.
[0047]
[0063] In some other examples, a different function is used when calculating the spatiotemporal cost 40 of the candidate decoder 32. For example, the relative importance of space and time can be adjusted by introducing weights related to the number of qubits and / or circuit depth into the cost function. These weights are given by Equation 2d 2 Δ(p,n TThis can be applied by raising the spatial coefficient or time coefficient in ,d,M) to an exponent other than 1. Equation 2d 2 Δ(p,n T The coefficient of 2 in d,M) can also be replaced with a different scalar constant if the Floke code is used as an error correction code 22 instead of a surface code.
[0048]
[0064] Figure 8A shows a flowchart of Method 400 for use with a computing system to select a decoder to be implemented in a quantum computing device. Method 400 can be performed in a classical computing device during the development of a quantum computing device.
[0049]
[0065] In step 402, method 400 includes receiving a plurality of quantum circuit parameters. The plurality of quantum circuit parameters relate to a quantum circuit comprising a plurality of logic operations. For example, the quantum circuit may be a sequence of logic gates, each of which is either an HT gate or an HST gate. The quantum circuit parameters include the code parameters of an error correction code on which the logic operations are encoded. For example, the error correction code may be a surface code or a Floquet code. The code parameters of the error correction code may be the code distance or code length of the error correction code. In addition, the quantum circuit parameters include the number of T gates contained within the quantum circuit.
[0050]
[0066] In step 404, method 400 further includes receiving individual decoder parameters for each of a plurality of candidate decoders. The decoder parameters include the physical noise rates of a plurality of physical qubits configured to run a quantum circuit. In addition, the decoder parameters include the pause time of the candidate decoder. The pause time of the candidate decoder can be calculated iteratively as discussed below.
[0051]
[0067] In step 406, method 400 further includes calculating the individual spatiotemporal costs of candidate decoders based at least in part on quantum circuit parameters and decoder parameters. The spatiotemporal costs of candidate decoders encode estimates of both the spatial and temporal efficiency of the decoders. In step 408, method 400 further includes outputting the selection of the minimum spatiotemporal cost decoder from among the multiple candidate decoders for implementation in a quantum computing device. Thus, an efficient decoder is selected.
[0052]
[0068] Figures 8B–8E illustrate additional steps of method 400 performed in some examples. Figure 8B illustrates additional steps that may be performed when calculating the spatiotemporal cost of each from the quantum circuit parameters and the individual decoder parameters of the candidate decoders. In step 410, method 400 further includes calculating the range of the individual candidate decoders based at least in part on the code parameters, physical noise rate, and stop time. The range of the candidate decoders is an estimate of the number of logic gates that can be reliably executed within the performance criteria using the candidate decoders, as discussed below.
[0053]
[0069] In step 412, method 400 further includes determining whether the range is greater than the number of T gates contained in the quantum circuit. In step 414, method 400 further includes determining a value for the spacetime cost, at least in part, based on the determination of whether the range is greater than the number of T gates. For example, if the range is less than the number of T gates, the spacetime cost can be set to infinity or another large positive number, while if the range is greater than the number of T gates, the spacetime cost can be calculated in a different way. In this way, if a candidate decoder has a range that is too short for the quantum computer to reliably implement the quantum circuit, that candidate decoder can be rejected.
[0054]
[0070] Figure 8C shows additional steps of method 400 that may be performed when the value of the spatiotemporal cost is determined in step 414. In step 416, method 400 further includes determining that the range is greater than the number of T gates. In step 418, method 400 further includes calculating the syndrome extraction circuit (SEC) depth for each candidate decoder. The SEC depth is the total number of SEC cycles performed during the execution of the quantum circuit. In step 420, method 400 further includes calculating the spatiotemporal cost based at least in part on the SEC depth. The SEC depth can be used as a surrogate indicator of the amount of time used to execute the quantum circuit with a particular candidate decoder.
[0055]
[0071] Figure 8D shows the steps that may be performed when calculating the SEC depth in an example in which the steps of Figure 8C are performed. In the example of Figure 8D, the quantum circuit parameters further include the SEC cycle duration of the SEC, which indicates the amount of time elapsed when performing syndrome extraction using the SEC. In step 422, method 400 further includes calculating the maximum decoding time of each candidate decoder. In step 424, method 400 further includes calculating the SEC depth based at least in part on the SEC cycle duration and the maximum decoding time. The calculation of the SEC depth can also take the number of T gates, the code depth, and the physical noise factor as inputs.
[0056]
[0072] Figure 8E shows additional steps of method 400 that may be performed in some examples. In step 426, method 400 further includes calculating the stop time of the candidate decoder as the maximum range stop time that approximates the range of the candidate decoder. In some examples, the stop time and range are iteratively recalculated in a range maximization loop. Step 426 includes, in step 428, calculating the stop time based at least in part on the decoding execution time distribution. The decoding execution time distribution is calculated by Monte Carlo simulation and shows the estimated probability that the decoder execution will be completed at each individual time.
[0057]
[0073] In the example in Figure 8E, the quantum circuit parameters further include a logic error rate threshold. In step 430, step 426 further includes calculating the range of the candidate decoder as the maximum number of T gates that can be executed in the quantum circuit and candidate decoder with an estimated logic error rate term value less than the logic error rate threshold. Thus the estimated logic error rate term is approximately proportional to the logic error rate at which the quantum circuit is executed using the candidate decoder.
[0058]
[0074] In the example in Figure 8E, the code parameter is the code distance of the error correction code. In step 432, method 400 further includes calculating the minimum odd integer code distance for which the value of the estimated logical error rate term is below the logical error rate threshold. Candidate code distance values may be iteratively recalculated to search for the minimum odd integer code distance. In step 434, method 400 further includes outputting the minimum odd integer code distance and the stop time that maximizes the range. The minimum odd integer code distance and the maximum range stop time may be output as parameters for the minimum spatiotemporal cost decoder.
[0059]
[0075] Using the systems and methods discussed above, decoders are selected for implementation in a quantum computing device. The selection of decoders is not based solely on accuracy, but also considers both spatial and temporal efficiency. Therefore, selecting decoders using the techniques discussed above allows for more efficient scaling of the quantum computing device under development to a larger number of qubits.
[0060]
[0076] In some embodiments, the methods and processes described herein can be linked to a computing system of one or more computing devices. Specifically, such methods and processes can be implemented as computer application programs or services, application programming interfaces (APIs), libraries, and / or other computer program products.
[0061]
[0077] Figure 9 schematically illustrates a non-limiting embodiment of a computing system 500 capable of performing one or more of the above methods and processes. The computing system 500 is shown in a simplified form. The computing system 500 can embody the computing system 10 described above and shown in Figure 1. The components of the computing system 500 may be contained within one or more personal computers, server computers, tablet computers, home entertainment computers, network computers, game consoles, mobile computers, mobile communication devices (e.g., smartphones), and / or other computing devices, as well as wearable computing devices such as head-mounted augmented reality devices.
[0062]
[0078] The computing system 500 includes a logical processor 502, a volatile memory 504, and a non-volatile storage device 506. The computing system 500 may optionally include a display subsystem 508, an input subsystem 510, a communication subsystem 512, and / or other components not shown in Figure 9.
[0063]
[0079] The logical processor 502 includes one or more physical devices configured to execute instructions. For example, the logical processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data constructs, or other logical constructs. Such instructions may be implemented to perform a task, to implement a data type, to change the state of one or more components, to achieve a technical effect, or to reach a desired result.
[0064]
[0080] A logic processor may include one or more physical processors configured to execute software instructions. In addition, or separately, a logic processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processor of the logic processor 502 may be single-core or multi-core, and the instructions executed therein may be configured with respect to sequential, parallel, and / or distributed processing. Individual components of the logic processor may be optionally distributed between two or more separate devices located separately and / or configured for cooperative processing. Aspects of the logic processor may be virtualized and executed by remotely accessible networked computing devices configured within a cloud computing configuration.
[0065]
[0081] The non-volatile storage device 506 includes one or more physical devices configured to hold instructions executable by a logic processor for implementing the methods and processes described herein. When such methods and processes are implemented, the state of the non-volatile storage device 506 can be changed, for example, to hold various types of data.
[0066]
[0082] The non-volatile storage device 506 may include removable and / or embedded physical devices. The non-volatile storage device 506 may include optical memory, semiconductor memory, and / or magnetic memory, or other mass storage technology. The non-volatile storage device 506 may include non-volatile, dynamic, static, read / write, read-only, sequential access, position-addressable, file-addressable, and / or content-addressable devices. It will be understood that the non-volatile storage device 506 is configured to retain instructions even when power to the non-volatile storage device 506 is cut off.
[0067]
[0083] The volatile memory 504 may include a physical device containing random access memory. The volatile memory 504 is typically used by the logical processor 502 to temporarily store information during the processing of software instructions. It will be understood that the volatile memory 504 typically does not retain instructions when power to the volatile memory 504 is cut off.
[0068]
[0084] Aspects of the logic processor 502, volatile memory 504, and non-volatile storage device 506 can be integrated into one or more hardware logic components. Such hardware logic components may include, for example, rewritable gate arrays (FPGAs), program-specific integrated circuits and application-specific integrated circuits (PASICs / ASICs), program-specific standard products and application-specific standard products (PSSPs / ASSPs), systems on a chip (SOCs), and composite programmable logic devices (CPLDs).
[0069]
[0085] The terms “module,” “program,” and “engine” may be used to describe aspects of a computing system 500 that are implemented in software by a processor to perform a specific function, typically using a portion of volatile memory, and that function includes transformation processing that specifically configures the processor to perform that function. Thus, a module, program, or engine may be instantiated by a logical processor 502 that executes instructions held by a non-volatile storage device 506 using a portion of volatile memory 504. It will be understood that different modules, programs, and / or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same module, program, and / or engine may be instantiated by different applications, services, code block, object, routine, API, function, etc. The terms “module,” “program,” and “engine” may encompass each or a group of executable files, data files, libraries, drivers, scripts, database records, etc.
[0070]
[0086] If included, the display subsystem 508 may be used to present a visual representation of the data held by the non-volatile memory 506. This visual representation may take the form of a graphical user interface (GUI). Since the methods and processes described herein modify the data held by the non-volatile memory and thus change the state of the non-volatile memory, the state of the display subsystem 508 can also be changed to visually represent the changes in the underlying data. The display subsystem 508 may include one or more display devices utilizing virtually any kind of technology. Such display devices may be combined with the logical processor 502, the volatile memory 504, and / or the non-volatile memory 506 within a shared enclosure, or they may be peripheral display devices.
[0071]
[0087] If included, the input subsystem 510 may include, or interface with, one or more user input devices such as a keyboard, mouse, touchscreen, camera, or microphone.
[0072]
[0088] If included, the communication subsystem 512 may be configured to connect the various computing devices described herein to each other and to other devices in a communicative manner. The communication subsystem 512 may include wired and / or wireless communication devices compliant with one or more different communication protocols. In non-limiting examples, the communication subsystem may be configured for communication over wired or wireless local or wide-area networks, broadband cellular networks, etc. In some embodiments, the communication subsystem may enable the computing system 500 to send and receive messages with other devices over a network such as the Internet.
[0073]
[0089] The following paragraphs discuss several aspects of the present disclosure. According to one aspect of the present disclosure, a computing system is provided which includes one or more processors configured to receive a plurality of quantum circuit parameters, including code parameters of an error correction code. The quantum circuit parameters further include the number of T gates included in the quantum circuit. One or more processors are further configured to receive individual decoder parameters for each of a plurality of candidate decoders. The decoder parameters include the physical noise rate of a plurality of physical qubits configured to run the quantum circuit. The decoder parameters further include the stop time of the candidate decoder. One or more processors are further configured to calculate the individual spatiotemporal cost of the candidate decoders, at least in part, based on the quantum circuit parameters and decoder parameters. One or more processors are further configured to output a selection of the minimum spatiotemporal cost decoder from among the plurality of candidate decoders for implementation in a quantum computing device. The above features may have the technical effect of selecting decoders for a quantum computing device in a manner that considers both spatial and temporal efficiency.
[0074]
[0090] According to this embodiment, one or more processing units may be configured to at least partially calculate each of the spatiotemporal costs by calculating the range of each candidate decoder based at least partially on the code distance, physical noise rate, and stop time. Calculating each of the spatiotemporal costs may further include determining whether the range is greater than the number of T gates contained in the quantum circuit. Calculating each of the spatiotemporal costs may further include determining the value of the spatiotemporal cost based at least partially on the determination of whether the range is greater than the number of T gates. The above features may have the technical effect of allowing the quantum computer to check whether the candidate decoder has a sufficiently long range in order to reliably implement the quantum circuit.
[0075]
[0091] According to this embodiment, one or more processors can determine that the range is greater than the number of T gates. One or more processors may be further configured to calculate the spatiotemporal cost of a candidate decoder at least partially by calculating the syndrome extraction circuit (SEC) depth of each candidate decoder. The SEC depth is the total number of SEC cycles performed during the execution of the quantum circuit. One or more processors may be further configured to calculate the spatiotemporal cost at least partially based on the SEC depth. The above features may have the technical effect of incorporating an estimate of the temporal duration into the calculation of the spatiotemporal cost.
[0076]
[0092] In this embodiment, the quantum circuit parameters may further include the SEC cycle duration of the SEC. For each candidate decoder, one or more processors may be further configured to calculate the maximum decoding time of the candidate decoder. One or more processors may be further configured to calculate the SEC depth based at least in part on the SEC cycle duration and the maximum decoding time. The above features may have the technical effect of calculating the maximum number of SEC cycles performed during the execution of the quantum circuit.
[0077]
[0093] According to this embodiment, one or more processing units may be further configured to calculate the stop time of a candidate decoder as a maximum range stop time that substantially maximizes the range of the candidate decoder. The above feature may have the technical effect of increasing the depth of the logic gate sequence that can be implemented with a logic error rate below a threshold.
[0078]
[0094] According to this embodiment, one or more processing units may be configured to calculate the pause time based at least in part on a decoding execution time distribution calculated by Monte Carlo simulation. The above feature may have the technical effect of calculating an estimate of the maximum range pause time.
[0079]
[0095] In this embodiment, the quantum circuit parameters may further include a logic error rate threshold. One or more processing units may be further configured to calculate the range of the candidate decoder as the maximum number of T-gates that can be executed in the quantum circuit and candidate decoder with an estimated logic error rate term value less than the logic error rate threshold. The above features may have the technical effect of calculating the range of the candidate decoder at a given value of an acceptable logic error rate.
[0080]
[0096] According to this embodiment, the code parameter of the error correction code can be the code distance or the code length. The above feature may have the technical effect of incorporating spatial information related to the candidate decoder into the calculation of the spatiotemporal cost.
[0081]
[0097] In this embodiment, the code parameter may be the code distance of the error correction code. One or more processors may be further configured to calculate the minimum odd integer code distance at which the value of the estimated logic error rate term falls below a logic error rate threshold. One or more processors may be further configured to output the minimum odd integer code distance and the stop time that maximizes the range. The above features may have the technical effect of calculating and outputting the minimum code distance that enables reliable implementation of the quantum circuit. The above features may have the additional technical effect of outputting the stop time at which the range of the candidate decoder is maximized.
[0082]
[0098] In this embodiment, the error correction code may be a surface code or a Floquet code. The above features may have the additional technical effect of performing quantum error correction in a manner that enables efficient encoding and decoding.
[0083]
[0099] In this embodiment, the quantum circuit is a sequence of logic gates, each of which is either an HT gate or an HST gate. The above features may have the additional technical effect of performing single-qubit logic operations in the quantum circuit.
[0084]
[0100] Another aspect of this disclosure provides a method comprising receiving a plurality of quantum circuit parameters, including a code parameter for an error correction code. The quantum circuit parameters further include the number of T gates contained within the quantum circuit. The method further comprises receiving individual decoder parameters for each of a plurality of candidate decoders. The decoder parameters include the physical noise rate of a plurality of physical qubits configured for the quantum circuit to run. The decoder parameters further include the stop time of the candidate decoder. The method further comprises calculating the individual spatiotemporal cost of the candidate decoders based at least in part on the quantum circuit parameters and decoder parameters. The method further comprises outputting a selection of the minimum spatiotemporal cost decoder from the plurality of candidate decoders for implementation in a quantum computing device. The above features may have the technical effect of selecting a decoder for a quantum computing device in a manner that considers both spatial and temporal efficiency.
[0085]
[0101] In this embodiment, calculating each of the spatiotemporal costs may include calculating the range of each candidate decoder based at least in part on the code parameters, physical noise rate, and stop time. Calculating each of the spatiotemporal costs may further include determining whether the range is greater than the number of T gates contained in the quantum circuit. Calculating each of the spatiotemporal costs may further include determining the value of the spatiotemporal cost based at least in part on the determination of whether the range is greater than the number of T gates. The above features may have the technical effect of checking whether the candidate decoders have a sufficiently long range so that the quantum computer can reliably implement the quantum circuit.
[0086]
[0102] In this embodiment, the method may further include determining that the range is greater than the number of T gates. The method may further include calculating the spatiotemporal cost of a candidate decoder at least partially by calculating the syndrome extraction circuit (SEC) depth of each candidate decoder. The SEC depth is the total number of SEC cycles performed during the execution of the quantum circuit. The method may further include calculating the spatiotemporal cost at least partially based on the SEC depth. The above features may have the technical effect of incorporating an estimate of the temporal duration into the calculation of the spatiotemporal cost.
[0087]
[0103] According to this embodiment, the quantum circuit parameters may further include the SEC cycle duration of the SEC. The method may further include calculating the maximum decoding time of each candidate decoder. The method may further include calculating the SEC depth based at least in part on the SEC cycle duration and the maximum decoding time. The above features may have the technical effect of calculating the maximum number of SEC cycles performed during the execution of the quantum circuit.
[0088]
[0104] According to this embodiment, the method may further include calculating the stop time of the candidate decoder as the maximum range stop time that nearly maximizes the range of the candidate decoder. The above feature may have the technical effect of increasing the depth of the logic gate sequence that can be implemented with a logic error rate below a threshold.
[0089]
[0105] According to this embodiment, the quantum circuit parameters may further include a logic error rate threshold. The method may further include calculating the range of the candidate decoder as the maximum number of T gates that can be executed in the quantum circuit and candidate decoder with an estimated logic error rate term value less than the logic error rate threshold. The above feature may have the technical effect of calculating the range of the candidate decoder for a given value of an acceptable logic error rate.
[0090]
[0106] In this embodiment, the code parameter may be the code distance of the error correction code. The method may further include calculating the minimum odd integer code distance at which the value of the estimated logic error rate term falls below a logic error rate threshold. The method may further include outputting the minimum odd integer code distance and the stop time that maximizes the range. The above features may have the technical effect of calculating and outputting the minimum code distance that enables reliable implementation of the quantum circuit. The above features may have the additional technical effect of outputting the stop time at which the range of the candidate decoder is maximized.
[0091]
[0107] In this embodiment, the error correction code may be a surface code or a Floquet code. The above features may have the additional technical effect of performing quantum error correction in a manner that enables efficient encoding and decoding.
[0092]
[0108] According to another aspect of this disclosure, a computing system is provided comprising one or more processors configured to receive a plurality of quantum circuit parameters. The plurality of quantum circuit parameters include the code distance of an error correction code and the number of T gates contained within the quantum circuit. One or more processors are further configured to receive individual decoder parameters for each of a plurality of candidate decoders. The decoder parameters include the physical noise rate of a plurality of physical qubits configured to run the quantum circuit. One or more processors are further configured to calculate individual maximum range pause times that approximate the individual range of each candidate decoder. The individual range of each decoder is calculated at least in part on the code distance, the physical noise rate, and the pause time. One or more processors are further configured to calculate the individual spatiotemporal cost of the candidate decoders at least in part on the quantum circuit parameters and decoder parameters. One or more processors are further configured to output a selection of the minimum spatiotemporal cost decoder from among the plurality of candidate decoders for implementation in a quantum computing device. The above features may have the technical effect of selecting decoders for a quantum computing device in a manner that considers both spatial and temporal efficiency.
[0093]
[0109] As is clearly stated in the truth table below, when used herein, "and / or" is defined as inclusive or as ∨.
[0094] [Table 1]
[0095]
[0110] The configurations and / or methods described herein are essentially illustrative, and numerous modifications are possible; therefore, it should be understood that these particular embodiments or examples should not be considered in an restrictive sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions illustrated and / or described may be performed in the order illustrated and / or described, in other orders, simultaneously, or omitted. Similarly, the order of the processes described above can be changed.
[0096]
[0111] The contents of this disclosure include all novel and non-trivial combinations and subcombinations of the various processes, systems, and configurations disclosed herein, as well as other features, functions, actions, and / or characteristics, and any and all equivalents thereof.
Claims
1. A calculation system (10), One or more processing devices (12), The error correction code (22) has code parameters (23), and The number of T gates (n) included in the quantum circuit (24) Ｔ ) Receiving multiple quantum circuit parameters (20) including, The process involves receiving the individual decoder parameters (30) of each of the multiple candidate decoders (32), wherein the decoder parameters are: The physical noise rate (p) of the plurality of physical qubits configured so that the quantum circuit is executed, and Stop time (M) of the candidate decoder Receiving individual decoder parameters (30), including Calculating the individual spatiotemporal costs (40) of the candidate decoders based at least partially on the quantum circuit parameters and the decoder parameters, and For implementation in a quantum computing device (50), the selection of the minimum spatiotemporal cost decoder (42) from among the multiple candidate decoders is output. One or more processing units (12) configured to perform the following: A computing system (10) including the above.
2. The one or more processing devices described above are: Calculating the range of each candidate decoder based at least partially on the code distance, the physical noise rate, and the stop time, To determine whether the range is greater than the number of T gates included in the quantum circuit, and Determining the value of the spatiotemporal cost based at least in part on the determination of whether the range is greater than the number of T gates. The calculation system according to claim 1, configured to calculate at least partially each of the spatiotemporal costs by means of the following:
3. The one or more processing devices determine that the range is greater than the number of T gates, The one or more processing devices described above are: Calculating the syndrome extraction circuit (SEC) depth of each candidate decoder, wherein the SEC depth is the total number of SEC cycles performed during the execution of the quantum circuit, and Calculating the spatiotemporal cost based at least partially on the SEC depth. The system is further configured to calculate, at least partially, the spatiotemporal cost of the candidate decoder. The calculation system according to claim 2.
4. The quantum circuit parameters further include the SEC cycle duration of the SEC, For each of the candidate decoders, the one or more processing units are further configured to calculate the maximum decoding time of the candidate decoder. The one or more processing units are further configured to calculate the SEC depth based at least partially on the SEC cycle duration and the maximum decoding time. The calculation system according to claim 3.
5. The calculation system according to any one of claims 2 to 4, wherein the one or more processing units are further configured to calculate the stop time of the candidate decoder as the maximum range stop time that substantially maximizes the range of the candidate decoder.
6. The calculation system according to claim 5, wherein one or more processing units are configured to calculate the stop time at least in part based on a decoding execution time distribution calculated by Monte Carlo simulation.
7. The quantum circuit parameters further include a logic error rate threshold, The one or more processing units are further configured to calculate the range of the candidate decoder as the maximum number of T-gates that can be executed in the quantum circuit and the candidate decoder with an estimated logic error term value less than the logic error threshold. The calculation system according to claim 5 or 6.
8. The calculation system according to claim 7, wherein the code parameter of the error correction code is the code distance or the code length.
9. The code parameter is the code distance of the error correction code, The one or more processing devices described above are: The minimum odd integer code distance for which the value of the estimated logical error rate term falls below the logical error rate threshold is calculated. The minimum odd integer code distance, and The stop time that maximizes the range Output The calculation system according to claim 8, further configured as follows.
10. The calculation system according to any one of claims 1 to 9, wherein the error correction code is a surface code or a floke code.
11. The computing system according to any one of claims 1 to 10, wherein the quantum circuit is a sequence of logic gates, each of which is an HT gate or an HST gate.
12. Method (400), Error correction code parameters, and The number of T-gates contained in a quantum circuit Receiving multiple quantum circuit parameters including (402), Receiving individual decoder parameters for each of the multiple candidate decoders (404), wherein the decoder parameters are: The physical noise rate of a plurality of physical qubits configured to execute the aforementioned quantum circuit, and Stop time of the candidate decoder Receiving individual decoder parameters, including (404), Calculating the individual spatiotemporal costs of the candidate decoders based at least partially on the quantum circuit parameters and the decoder parameters (406), and For implementation in a quantum computing device, output the selection of the minimum spatiotemporal cost decoder from among the multiple candidate decoders (408) Method (400), including the method (400).
13. Calculating each of the aforementioned spatiotemporal costs is Calculating the range of each candidate decoder based at least partially on the code parameters, the physical noise rate, and the stop time, To determine whether the range is greater than the number of T gates included in the quantum circuit, and Determining the value of the spatiotemporal cost based at least in part on the determination of whether the range is greater than the number of T gates. The method according to claim 12, including the method described in claim 12.
14. The range is determined to be greater than the number of T gates. Calculating the syndrome extraction circuit (SEC) depth of each candidate decoder, wherein the SEC depth is the total number of SEC cycles performed during the execution of the quantum circuit, and Calculating the spatiotemporal cost based at least partially on the SEC depth. This allows for the calculation of the spatiotemporal cost of the candidate decoder, at least partially. The method according to claim 13, further comprising:
15. The quantum circuit parameters further include the SEC cycle duration of the SEC, The aforementioned method, For each of the candidate decoders, calculate the maximum decoding time of the candidate decoder, and The SEC depth is calculated based at least partially on the SEC cycle duration and the maximum decoding time. The method according to claim 14, further comprising:
16. The method according to any one of claims 13 to 15, further comprising calculating the stop time of the candidate decoder as the maximum range stop time that substantially maximizes the range of the candidate decoder.
17. The quantum circuit parameters further include a logic error rate threshold, The method further includes calculating the range of the candidate decoder as the maximum number of T-gates that can be executed in the quantum circuit and the candidate decoder with an estimated logic error term value less than the logic error threshold, The method according to claim 16.
18. The code parameter is the code distance of the error correction code, The aforementioned method, The calculation of the smallest odd integer code distance such that the value of the estimated logical error rate term falls below the logical error rate threshold, and The minimum odd integer code distance, and The stop time that maximizes the range Output The method according to claim 17, further comprising:
19. The method according to any one of claims 12 to 18, wherein the error correction code is a surface code or a floke code.
20. A calculation system (10), One or more processing devices (12), The code distance (d) of the error correction code (22), and The number of T gates (n) included in the quantum circuit (24) Ｔ ) Receiving multiple quantum circuit parameters (20) including, Receiving individual decoder parameters (30) of each of a plurality of candidate decoders (32), wherein the decoder parameters include the physical noise rate (p) of a plurality of physical qubits configured to perform the quantum circuit. Calculating the individual maximum range stop time (M) that approximates the individual range (60) of each of the candidate decoders, wherein the individual range of each decoder is calculated at least in part on the code distance, the physical noise rate, and the stop time. Calculating the individual spatiotemporal costs (40) of the candidate decoders based at least partially on the quantum circuit parameters and the decoder parameters, and For implementation in a quantum computing device (50), the selection of the minimum spatiotemporal cost decoder (42) from among the multiple candidate decoders is output. One or more processing units (12) configured to perform the following: A computing system (10) including the above.