Precise execution of the deterministic cycle of software
Patent Information
- Application Number
- JP2026501415
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-31
- Filing Date
- 2024-07-12
- Publication Date
- 2026-09-01
Smart Images
Figure 2026529485000001_ABST
Abstract
Description
Technical Field
[0001] Various embodiments generally relate to computer processor execution time, and more specifically, to systems and methods for providing deterministic execution time for a number of tasks.
Background Art
[0002] A computer interrupt is a mechanism that enables a computer's central processing unit (CPU) to efficiently process and prioritize various tasks and events. While a computer is operating, it continuously monitors external and internal signals, such as hardware devices or software-generated signals that require attention. When an interrupt occurs, the CPU temporarily suspends its current task, saves its state, and shifts its focus to an interrupt handler, which is a specific routine designed to address the cause of the interrupt. Interrupts can be classified into two types: hardware interrupts generated by external devices such as keyboards or network cards, and software interrupts triggered by specific software instructions. The ability of a CPU to manage these interrupts in real time and respond to them enables modern computers to effectively perform multitasking and provide a responsive interactive user experience.
[0003] In one example, a CPU executes code that causes the CPU to read registers in response to an interrupt. However, the time required for the CPU to suspend execution, save state, and transition to the interrupt handler may require a variable number of CPU clock cycles, even for the same interrupt type. In another example, some software code may include a branch instruction, and the number of CPU clock cycles required to complete execution may vary depending on the outcome of the branch instruction. Such execution time may be referred to as non-deterministic. Non-deterministic execution time can pose challenges to real-time execution.
[0004] In this field, there is a need for efficient techniques to provide deterministic execution time. [Overview of the project]
[0005] In one example, the device includes a processor core configured to execute machine code instructions over multiple clock cycles and to receive hardware signals, and a circuit coupled to the processor core, which includes a counter, the circuit being configured to generate hardware signals and to further modify a value stored in the counter by either incrementing or decrementing the value according to a clock associated with a clock cycle, to receive a read operation from the processor core to the counter, to determine the value stored in the counter in response to receiving the read operation, to determine whether to change the state of a hardware signal based at least in part on the value stored in the counter, and to change the state of the hardware signal to a first state.
[0006] In another example, a method comprising starting a counter, receiving a read operation directed to the counter from the processor core, and stalling the processor core, the hardware signal being transmitted on a bus from a hardware logic unit to the processor core, holding the first state of the hardware signal for a period of time during which the counter performs its counter operation, and un-stalling the processor core by causing the hardware signal to a second state in response to the counter reaching a specified value.
[0007] In another example, the device includes a hardware counter circuit coupled to a first bus, the first bus being a data bus configured to support read and write access to the hardware counter circuit from a processing unit, and hardware logic coupled to the hardware counter circuit and a second bus, the second bus being coupled to the processing unit, and further, the hardware logic being configured to assert and deassert hardware signals on the second bus in response to the value of the hardware counter circuit in a read operation on the first bus. [Brief explanation of the drawing]
[0008] Next, refer to the attached drawing.
[0009] [Figure 1] This section provides illustrative timelines for various implementations to demonstrate deterministic execution.
[0010] [Figure 2] This is a diagram illustrating an exemplary hardware architecture for providing deterministic execution, as shown in the timeline of Figure 1, according to various embodiments.
[0011] [Figure 3] This is a diagram illustrating an exemplary hardware architecture according to various embodiments.
[0012] [Figure 4] Figures 2 and 3 illustrate an exemplary method that can be implemented by a module having hardware logic, such as the DEU module having hardware logic, according to several embodiments. [Modes for carrying out the invention]
[0013] This disclosure will be described with reference to the accompanying drawings. The drawings are not drawn to any particular scale and are provided solely to illustrate the disclosure. Several aspects of this disclosure will be described hereafter with reference to illustrative applications for illustrative purposes. Many specific details, relationships, and methods will be described in order to provide an understanding of this disclosure. Since some actions may occur in a different order and / or concurrently with other actions or events, this disclosure is not limited by the order in which such actions or events are described. Furthermore, not all of the exemplified actions or events are necessary to implement the methodology in accordance with this disclosure.
[0014] Various embodiments provide techniques that use hardware logic and hardware signals to stall the processor cores of a central processing unit (CPU) for a set number of cycles, thereby providing deterministic execution time in some cases.
[0015] In one example, a hardware module may be configured to use a hardware or software trigger event to start a counter. The counter may be used to count a specified number of processor core clock cycles. In an example where the processor core performs a read to the counter, the hardware module may assert or deassert a hardware signal to stall the processor core until the counter expires. Once the counter expires, the hardware module may unstall the processor core by changing the state of a hardware signal. In the following example, the hardware module may be referred to as a deterministic execution unit (DEU).
[0016] In one example, a hardware module provides determinism from the time an interrupt occurs to the time to read some kind of input, such as an analog-to-digital converter (ADC) reading from a corresponding register or a sensor reading from a corresponding register. In another example, a hardware module provides determinism for the execution of a sequence of code that may have multiple paths. For example, part of the code may have if / then / else branches that can take a different number of cycles depending on certain conditions when part of the code is executed. Various embodiments may provide a deterministic quantity of processor core clock cycles, regardless of the number of cycles it takes for the code or peripheral devices to complete.
[0017] In one example, application code writes values such as configuration parameters to peripheral registers (PeriphRegA), and the values written (WRITE_VALUE1 / 2 / 3) depend on another variable (VarA). This can be written in the C programming language as shown below. / / Start Code: if(VarA==0) PeriphRegA=WRITE_VALUE1; else if(VarA > 0) PeriphRegA=WRITE_VALUE2; else if(VarA<0) PeriphRegA=WRITE_VALUE3; / / End Code: Rest of Code…
[0018] For the above code segment, a user may desire that the total number of cycles required to execute the above portion (from Start Code to End Code) is the same regardless of the path taken through the code. Normally, it is impossible for the user to control the total number of cycles. For example, if the VarA==0 test evaluates to true, WRITE_VALUE1 is written, which can take 10 processor core clock cycles (from the start code to the end code). If the VarA>0 test evaluates to true, WRITE_VALUE2 is written, which can take 15 cycles (from the start code to the end code). If the VarA<0 test evaluates to true, WRITE_VALUE3 is written, which can take 20 cycles (from the start code to the end code). However, applications in this case can benefit when the number of execution cycles is 20 for all possible paths the code may take.
[0019] If a DEU unit is available, the user may add the DEU_Start(20) function at the beginning and add the DEU_Read() function at the end. / / Start Code: DEU_Start(20); if(VarA==0) PeriphRegA=WRITE_VALUE1; else if(VarA>0) PeriphRegA=WRITE_VALUE2; else if(VarA<0) PeriphRegA=WRITE_VALUE3; DEU_Read(); / / End Code: Rest Of Code…
[0020] The DEU_Start(20) function may perform a write operation to the DEU unit counter register, which has a value of 20. As soon as the write operation is performed, the DEU counter may begin to decrement with each processor core cycle (e.g., processor core clock cycle). At the end of the code, when the DEU_Read() function is executed, if the DEU counter has not reached the value of 0, the DEU may hold the processor core in a stalled state until the counter reaches 0, and then may be allowed to continue execution by unstalling the processor core.
[0021] For example, if VarA == 0 is determined to be true, 10 cycles have been executed before DEU_Read() occurs. The DEU counter may have a value of (20-10)=10. The processor core is then stalled for 10 cycles. If VarA > 0 is determined to be true, 15 cycles have been executed before DEU_Read() occurs. The DEU counter may have a value of (20-15)=5. The processor core is then stalled for 5 cycles. If VarA < 0 is determined to be true, 20 cycles have been executed before DEU_Read() occurs. The DEU counter may have a value of (20-20)=0. The processor core is then stalled for 0 cycles. Therefore, regardless of the path taken, Rest of Code execution may begin after 20 cycles have elapsed, regardless of the path taken in the code.
[0022] Various embodiments may offer potential advantages over other solutions. For example, some embodiments may allow result values to be read from registers according to a pre-programmed amount of clock cycles. Such embodiments can synchronize the processor core and peripherals to ensure that the result read from the register is the correct value, not a value read prematurely before the peripheral has the opportunity to write the value. Also, during development time, developers can use debugging tools or other tools to determine the appropriate amount of clock cycles for the counter, thereby avoiding the use of values that are too large (which may stall the processor core for longer than necessary) and values that are too small (which may result in inaccurate data reads from the registers). In general, various embodiments can allow parts of the code to be executed according to a pre-programmed amount of clock cycles, which facilitates real-time processing.
[0023] In contrast, some solutions may involve inserting no-operation (NOOP) statements into parts of the code to extend the amount of cycles that those parts of the code use to execute. However, assuming that parts of the code may be indeterminate, adding NOOPs only increases the amount of clock cycles on top of the indeterminate time. In other words, the total number of clock cycles remains indeterminate. However, the DEUs described herein can make the total amount of time deterministic, thereby avoiding clock cycles that are too small or too large.
[0024] Figure 1 shows an illustrative timeline 100 according to various embodiments for providing deterministic execution. The example in Figure 1 illustrates operation in response to interrupts generated by peripheral devices. Examples of peripheral devices include analog-to-digital converters (ADCs) that write to registers, sensors that write to registers, and pulse-width modulation (PWM) generators that write to registers. The scope of implementation is not limited to any specific peripheral device.
[0025] At time T0, the peripheral device generates an interrupt to the processor core. Also at time T0, the DEU (for example, as shown in Figure 2) receives the interrupt and starts a counter. For example, starting a counter may involve populating the counter with a value that specifies the amount of clock cycles to be counted. The value may correspond to the time required by the peripheral device to perform a certain task (for example, the duration of an ADC conversion cycle or the duration of a sensor sensing cycle). The counter may be populated from another counter, such as a counter written during device initialization to store the amount of cycles to be counted. Hardware logic within the DEU may then populate the counter and start counting in response to the receipt of the interrupt.
[0026] Continuing with this example, the peripheral device performs a certain action. In the case of an ADC, during the conversion cycle, the ADC may receive a signal, sample that signal, and generate digital bits from the signal. In the example of a sensor, during the sensing cycle, the sensor may have a transducer that reacts to a phenomenon and generates digital bits based on that phenomenon. A PWM device may generate digital bits from a control input, and these digital bits may, for example, define a duty cycle. In any case, the peripheral device requires time T0 to time T2 before the results are ready to be accessed by the processor core (for example, before the peripheral device writes bits to a register).
[0027] Simultaneously, the processor core responds to the interrupt by performing context saving and executing the interrupt handler. In this example, the processor core response may take an indeterminate number of clock cycles, such that the number of clock cycles between time T0 and time T1 may vary in some cases. Such variations may arise from the specific context being saved or other parameters.
[0028] Furthermore, the DEU also includes a counter, as described above. The counter begins to decrement from a specific value that is input. In this example, at time T1, the counter has not yet reached the specified value (zero in this example). In other words, at time T1, the processor core has saved the context, executed the interrupt handler, and is otherwise ready to read the register that the peripheral device is programmed to write to. However, as described above, the peripheral device has not yet written to the register.
[0029] Various embodiments can cause the processor core to read the DEU counter register. For example, the processor core may execute a machine code instruction that directs a read operation from the processor core to the counter. At time T1, the counter register has not yet reached zero. In response to the read operation, the hardware logic within the DEU determines the value (non-zero value) stored in the counter register and then determines whether to change the state of a hardware signal based at least partially on the value stored in the counter register. In this case, since the DEU counter register has not yet reached zero, the hardware logic of the DEU determines to change the state of a hardware signal to stall the processor core at time T1.
[0030] Continuing this example, the DEU's hardware logic maintains a hardware signal state to stall the processor core until the counter reaches zero at time T3. Since time T3 is based on a pre-programmed number of clock cycles, the time elapsed between time T0 and time T3 is deterministic and known in advance. In fact, in this example, the amount of clock cycles during development time is pre-programmed to be no less than the maximum amount of clock cycles that peripheral devices are generally expected to take to perform their actions and complete their write operations to registers.
[0031] When the counter reaches zero, the DEU module's hardware logic changes the state of a hardware signal, thereby uninstalling the processor core. The processor core then continues processing, including reading from peripheral registers in this example. In this example, the processor core does not read from peripheral registers before (or after) time T3. Therefore, peripheral devices are given sufficient time to write to peripheral registers, and the processor core does not read from peripheral registers before the peripheral device's write operation is complete.
[0032] Figure 2 is a diagram of an exemplary hardware architecture 200 that provides deterministic execution in the timeline of Figure 1, etc., according to various embodiments.
[0033] The hardware architecture 200 includes peripheral devices 201, such as an ADC or other suitable peripheral equipment. The architecture 200 also includes a processor core 210, which may be any suitable processor, such as a general-purpose processor, an application-specific integrated circuit (ASIC), or a graphics processing unit (GPU). The DEU module 220 communicates with the processor core 210 via buses 232-235.
[0034] The processor core 210 is coupled to several peripheral devices 201-205. Some of the peripheral devices may not have real-time constraints, while others may have them. For example, peripheral devices 201, 204, and 205 may have real-time processing requirements and therefore may be coupled to the processor core via the DEU module 220. On the other hand, peripheral devices 202-203 are less affected by time and therefore may not be coupled to the DEU module 220.
[0035] The peripheral device 201 includes registers such as the peripheral register 251, as described above with respect to Figure 1. The processor core 210 can read the peripheral register 251 via bus 231. The processor core can write to the DEU maximum counter value register 221 via bus 232 and read from the decrement counter 222 via bus 233. The minimum and maximum registers 223 can be read from the processor core 210 via bus 234 and written to therein. Bus 235 can carry hardware signals to stall and unstall the processor core 210.
[0036] The DEU module 220 may be implemented using fixed-purpose (i.e., hardcoded) and / or programmable circuit elements and may include hardware logic 240 that controls the operation of the DEU module 220. For example, the hardware logic 240 may cause the decrement counter 222 to receive a value from the DEU maximum counter register 221, among other functions, and may cause hardware signals on the bus 235 to acquire a desired state (e.g., high or low).
[0037] The DEU module 220, peripheral device 201, and processor core 210 may generally follow the timeline described above with respect to Figure 1. For example, peripheral device 201 may generate an interrupt signal on bus 236 at time T0. In response to receiving the peripheral interrupt signal, the processor core begins to respond to the interrupt, such as performing context saving and executing the peripheral handler. Also in response to receiving the peripheral interrupt signal, the DEU module starts counter 222 by inputting the value stored in the maximum counter register 221 into counter 222.
[0038] The decrement counter 222 continues to decrement as defined by the processor core clock (clk) cycles. Simultaneously, peripheral device 201 performs actions to generate and store digital data when the processor core 210 executes machine code instructions to handle interrupts. When the processor core is ready to read data from peripheral register 251 at time T1, there is a machine code instruction that causes the processor core 210 to perform a read operation directed to the decrement counter 222. In response to the read operation, hardware logic 240 determines that the decrement counter 222 is still counting (i.e., has not yet reached the specified value, zero), and then asserts a hardware signal on bus 235 at or immediately after time T1. When the hardware signal is asserted on bus 235, the processor core detects the assertion and stalls in response to the assertion from time T1 to time T3. At any time between time T1 and time T3, the peripheral device 201 terminates its operation by writing a digital value to its peripheral register 251 at time T2.
[0039] When the decrement counter reaches the specified value of zero at time T3, hardware logic 240 changes the state of a hardware signal on bus 235 so that the signal is deasserted and the processor core 210 uninstalls. In this example, when the processor core 210 is uninstalled, the execution of machine code instructions is suspended, and when it is uninstalled, the execution of machine code instructions is resumed. Also in this example, when the signal on bus 235 is deasserted, the processor core 210 resumes the execution of a machine code instruction that causes the processor core to read a value from peripheral register 251 via bus 231.
[0040] Of course, the scope of implementation is not limited to high signals stalling the processor core 210 and low signals unstalling the processor core 210. Rather, any appropriate value may be transmitted as a hardware signal on bus 235, and that value may be programmed in the processor core 210 to trigger any appropriate action. For example, the hardware signal on bus 235 may be active high or active low, as needed.
[0041] In some embodiments, values can be written to the minimum and maximum registers 223 in response to a read operation by the processor core 210 directed to the decrement counter 222. This value indicates whether the decrement counter 222 is ready to allow reads when the processor core 210 is ready to read the peripheral registers 251. Specifically, hardware logic 240 can write values from the decrement counter 222 to the minimum and maximum registers 223 during a read operation on the bus 233. In one example, if the value in the decrement counter 222 is a non-zero value lower than any value stored in the minimum and maximum registers 223, the previous lower value may be replaced by the current value. Continuing this example, if the value in the decrement counter 222 is a non-zero value higher than any value stored in the minimum and maximum registers 223, the previous higher value may be replaced by the current value.
[0042] In this way, the minimum and maximum registers 223 can store the minimum and maximum values encountered during processor core read operations. Such information can be useful to developers during development time to set the maximum counter value appropriately high in order to avoid premature read attempts of peripheral registers 251. Specifically, developers can use the maximum values in the minimum and maximum registers 223 to understand possible high values and how to compare those high values to the known number of cycles associated with the operation of peripheral device 201. If it is assumed that the high value is below the known number of cycles associated with the operation of peripheral device 201, it indicates that it may be beneficial to implement stall using the DEU module 220.
[0043] The development phase may include determining an appropriate maximum counter value for register 221, and then writing the appropriate machine code instruction and data value to a boot loader (not shown). The boot loader may have various configurations, such as loading a value into the maximum counter value register 221 during initialization. Similarly, the development phase can determine appropriate maximum counter values for multiple different peripheral devices (e.g., peripherals 204-205), and write the machine code instruction and data value to the boot loader in a similar manner to that for peripheral device 201.
[0044] Furthermore, the scope of implementation is not limited to the increment counter 222. Rather, some implementations may use an increment counter that starts at a specified value, such as zero, and increments toward a value stored in the maximum counter value register 221. Hardware logic 240 may track the values in register 221 and the increment register (not shown) and may stall the processor core 210 between the time the processor core 210 issues a read on bus 233 and the time the increment counter is still counting. When the increment counter reaches the value stored in the maximum counter value register 221, hardware logic 240 may uninstall the processor core 210 by changing the state of a signal on bus 235.
[0045] Furthermore, some implementations may include a multiplexing function 225 for multiplexing among peripheral devices 201, 204, and 205. However, other implementations may distribute unique copies of the maximum counter value register 221, the decrement counter 222, and the minimum and maximum registers 223 to each different peripheral device having related and different maximum counter values. For example, different peripheral devices may use different amounts of clock cycles between times T0 and T2, and these different amounts of clock cycles are reflected in the different DEU maximum counter values of register 221. However, some peripherals may use the same amount of clock cycles, and these peripherals may be adaptable to the multiplexing function 225. In contrast, peripherals associated with different DEU maximum counter values of register 221 may include their own DEU modules, or at least their own registers 221, counters 222, and registers 223, to account for the different number of cycles to be counted.
[0046] Figure 3 shows an illustrative hardware architecture 300 according to various embodiments. Hardware architecture 300 is similar to hardware architecture 200 in Figure 2, but architecture 300 is simplified to illustrate an embodiment of software triggering.
[0047] In some examples, software code executed by the processor core 210 may include machine code instructions read from non-temporary memory 261, configured to perform a write operation to the maximum counter value register 221 via bus 232. In other words, in this example, the maximum counter value register 221 is populated by a write operation from the processor core 210, rather than by the boot loader, during initialization, as shown in the example in Figure 2.
[0048] Continuing this example, the hardware logic 240 can recognize that a certain value has been written to the maximum counter value register 221, and in response, the hardware logic 240 can input the maximum counter value into the subtraction counter 222. The subtraction counter 222 continues to count from the maximum counter value from register 221 down to a specified value, such as zero.
[0049] Meanwhile, the processor core 210 can continue executing a series of codes that eventually include read operations directed to the decrement counter 222 via the bus 233. Hardware logic 240 detects the read operations and determines whether the value currently stored in the decrement counter 222 has reached a specified value (e.g., zero). If the decrement counter 222 has a non-zero value indicating that the decrement counter 222 is still counting, hardware logic may cause a hardware signal on the bus 235 to acquire a state to stall the processor core 210. Hardware logic then continues to monitor the value in the decrement counter 222, and if the decrement counter 222 has reached the specified value, it may change the state of the hardware signal on the bus 235 to unstall the processor core 210.
[0050] In this example, the value that the processor core 210 writes to the maximum counter register 221 determines the amount of time required for the processor core to start one part of the code from the beginning of the next part of the code. Specifically, the processor core 210 may be delayed by a pre-programmed time under the direction of the hardware logic 240, and thus may provide deterministic execution time. The exemplary operation is given by the pseudocode below. .... DEU_Write_Counter(#DEU_Max_Counter_Value); User Critical Code .... User Critical Code DEU_Read_Counter(); Rest of Code
[0051] In the pseudocode example above, when the instruction (DEU_write_Counter) is executed by the processor core 210, it causes the processor core 210 to write a certain value to register 221. Hardware logic 240 writes that value from register 221 to counter 222, thereby initializing counter 222. The counter continues counting. The processor core 210 executes the code (User Critical Code) and reaches a machine code instruction that directs a read operation (DEU_read_counter) to counter 222. It should be noted that the code (User Critical Code) may contain one or more branch instructions, which can change the expected number of cycles due to the code depending on the conditions and parameters. In other words, there may be an expected minimum number of cycles and an expected maximum number of cycles due to various substitutions of branch operations. The DEU_Write_Counter value may be configured to be at least the same as the expected maximum number of cycles during design time.
[0052] The hardware logic 240 detects a read operation and, assuming that counter 222 has not finished counting, stalls the processor core 210 with a hardware signal on bus 235. When counter 222 finishes counting, the hardware logic 240 changes the state of the hardware signal on bus 235, thereby unstalling the processor core 210. The processor core 210 then continues executing machine code instructions beginning with Rest of Code.
[0053] As shown in the pseudocode above, the amount of processor core clock cycles between the write operation to register 221 and the resumption of execution in Rest of Code is known and determined by the value stored in register 221. In other words, time is deterministic.
[0054] As mentioned above with respect to Figure 2, some implementations may use an increment counter instead of a decrement counter, if necessary. This also applies to the implementation in Figure 3. Similarly, the minimum and maximum registers 223 can be input and used in the same way as described above with respect to Figure 2.
[0055] The hardware architectures in Figures 2 and 3 can be constructed in any suitable manner. For example, the processor core 210, the DEU module 220, and various peripheral devices such as peripheral device 201 can be constructed on a semiconductor die and packaged in a semiconductor package. For example, the various hardware items shown in Figures 2 and 3 may be implemented as a system-on-a-chip (SOC) or on any of various separate semiconductor chips. In one example, the hardware architectures in Figures 2 and 3 can be implemented in embedded systems, such as those used in automotive applications, industrial machinery applications, sensor applications, and / or similar applications. However, the scope of implementation is not limited to any specific end application.
[0056] Furthermore, hardware signals on bus 235 may vary between high and low values and may include electrical signals carried on one or more conductors of bus 235. Hardware logic, such as various logic gates, can cause electrical signals to take high or low values, and further hardware logic in the processor core 210 may receive high or low electrical signals from the conductors and take certain actions in response. Also, in some cases, hardware logic 240 may generate hardware signals on bus 235 without the influence of software operation, and the processor core 210 may receive hardware signals on bus 235 and stall or unstall without the influence of software operation.
[0057] Figure 4 is a diagram illustrating an exemplary method 400, which can be implemented by a module having hardware logic, such as a DEU module 220 having hardware logic 240, according to several embodiments.
[0058] Action 402 includes starting the counter. In an example where deterministic execution is applied to an interrupt scenario, starting the counter may include starting the counter to count in response to receiving an interrupt signal. In the example in Figure 2, the interrupt signal causes hardware logic 240 to input the value stored in the maximum counter value register 221 into counter 222. Counter 222 may then be decremented. However, in an example where counter 222 is incremented rather than decremented, action 402 may include starting the counter to count in response to receiving the interrupt signal. In any case, in this example where deterministic execution is applied to interrupts, the value stored in the maximum counter value register 221 may be set during initialization.
[0059] In an example of applying deterministic execution to application code, action 402 may include the processor core executing a machine code instruction to store a counter value in the maximum counter value register 221, to which the hardware logic 240 may cause the counter to increment or decrement as necessary. Note that in an example of applying deterministic execution to application code, the maximum counter value is set by the processor core executing the application code, not at initialization.
[0060] Action 404 includes receiving a read action from the processing unit. In the examples in Figures 2 and 3, the processor core 210 executes a machine code instruction to cause the processor core 210 to issue a read operation directed to the register implementing counter 222. Note that the read operation of action 404 is directed to a different register (e.g., counter 222) associated with the DEU module 220 and hardware logic 240, not to a register associated with a peripheral device (e.g., peripheral device 201).
[0061] Action 406 involves stalling the processor core using a hardware signal. For example, hardware logic, such as hardware logic 240, may detect the read operation of action 404. In response, the hardware logic can cause a hardware signal, such as a hardware signal on bus 235, to acquire a specific value. The specific value is configured to cause the processor core to suspend the execution of machine code instructions. In this example, the hardware signal on bus 235 is generated by hardware logic and received by hardware logic (not shown) in the processor core 210. In some implementations, actions of the DEU module 220 may omit any functionality associated with software and instead be provided by hardware. Also, the stall and unstall actions of the processor core 210 may be performed by hardware logic, which receives signals on bus 235. The advantage of using hardware logic to stall and unstall the processor core is that it can be performed in a relatively short clock cycle (e.g., one clock cycle) and can be deterministic in itself. In other words, hardware logic can avoid any latency that may be associated with the execution of software or firmware. However, the scope of implementation does not exclude the use of software or firmware.
[0062] Furthermore, in some embodiments, stalling the processor core in action 406 may include stalling the execution of all machine code instructions. However, in other embodiments, the processor core may include multiple cores, and stalling may include stalling one core associated with the read action of action 404 while allowing other cores to operate normally. Also, some processor architectures may allow the execution of multiple threads, and stalling the processor core in action 406 may include pausing the execution of the thread associated with the read operation of action 404 while allowing other threads to execute properly. In other words, the scope of implementation may be adapted to the capabilities and sophistication of the processing unit.
[0063] Action 408 involves holding a first state of the hardware signal for the duration of the time period during which the counter performs counter operations. In this example, the read action of action 404 is received by the hardware logic before the counter reaches a specified number. As described above, the specified number may be stored in the maximum counter value register 221, and the specified number may correspond to the number of processor core clock cycles from the counter that have been started up to the resumption of execution of machine code instructions by the processor core.
[0064] The identified number can be determined during development time. Specifically, a developer can determine an appropriate deterministic time using a debugger or other suitable tool. For example, a deterministic time period may correspond to the expected maximum number of processor core clock cycles that a peripheral device will take to perform a certain action and write data to a register. In another example, a deterministic time period may correspond to the expected maximum number of processor core clock cycles that a portion of the code will execute, taking into account various possible branch swaps.
[0065] Action 410 may include causing a hardware signal to acquire a second state. For example, if the first state stalls the processor core, the second state may be configured to unstall the processor core. Action 410 may be performed in response to a counter reaching a specified value. For example, hardware logic 240 may track the value of a counter and perform action 410 in response to the counter reaching a specified value.
[0066] The scope of implementation is not limited to the sequence of operations shown in Figure 4. Rather, various embodiments may add, omit, rearrange, or modify various actions. In one example, the processor core may perform a read action on peripheral register 251 after action 410. Also, in some implementations, there may be an initialization process that inputs a certain value into register 221 before action 402.
[0067] Various embodiments may include a processor having an interrupt controller and an execution pipeline. The interrupt controller may be configured to handle interrupts, and the execution pipeline may be configured to execute machine code instructions. The interrupt handler may be configured to receive interrupts, such as on bus 236 in Figure 2, and the execution pipeline may be configured to execute machine code instructions to cause the processor core to perform read and write operations associated with buses 232, 233, and 234.
[0068] Various embodiments may also include a hardware module having a first register configured to store a counter value, a second register configured to receive a value from the first register and to increment or decrement a specified value, and hardware logic configured to stall and unstall the processing unit in response to the value stored in the second register and in response to read and / or write operations received on the bus from the processing unit.
[0069] Various embodiments may also include a non-temporary computer-readable medium for storing a computer program containing a set of computer-readable instructions for execution by a computer processor, the computer program causing the processor to perform the processor core actions described in relation to Figures 1 to 3 (e.g., performing read and write operations, handling interrupts) when the set of computer-readable instructions is executed by the processor.
[0070] In this specification, the term “semiconductor die” is used. A semiconductor die may include an integrated circuit having hundreds or thousands of transistors coupled to form a functional circuit, such as a microprocessor or memory device. A semiconductor device may also be referred to in this specification as a semiconductor device or integrated circuit (IC) die.
[0071] In this specification, the term “semiconductor package” is used. A semiconductor package has at least one semiconductor die electrically coupled to terminals, and a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies can be packaged together. For example, a power metal oxide semiconductor (MOS) field-effect transistor (FET) semiconductor device and a second semiconductor device (such as a gate driver die or controller die) can be packaged together to form a single packaged electronic device. Additional components such as capacitors, resistors, and passive components such as inductors or coils may be included in the packaged electronic device. The semiconductor die is mounted together with a package substrate that provides conductive leads. Some of the conductive leads form terminals for the packaged device. In a wire-bonded integrated circuit package, bond wires couple the conductive leads of the package substrate to bond pads on the semiconductor die. The semiconductor die can be mounted on a package substrate, which has a device-side surface facing away from the substrate and a back surface facing the die pads of the package substrate and to which the die pads are attached. A semiconductor package may have a package body, which is formed in a molding process by a thermosetting epoxy resin molding compound, or by the use of epoxy, plastic, or resin that is liquid at room temperature and then hardens. The package body may provide a hermetically sealed package for the packaged device. The package body may be formed in a mold using a sealing process, but some of the leads of the package substrate are not covered during sealing, and these exposed lead portions form terminals for the semiconductor package. Semiconductor packages are sometimes referred to as "integrated circuit packages," "microelectronic device packages," or "semiconductor device packages."
[0072] While various examples of this disclosure have been described, these are merely examples and not limiting. Many modifications to the disclosed examples can be made in accordance with the disclosures herein without departing from the spirit or scope of this disclosure. Modifications can be made to the described embodiments, and other embodiments are also possible, within the scope of the claims of the present invention. Therefore, the breadth and scope of the present invention are not limited by any of the examples described above. Rather, the scope of this disclosure is defined in accordance with the following claims and their equivalents.
Claims
1. It is a device, A processor core configured to execute machine code instructions and receive hardware signals over multiple clock cycles, The processor core is coupled to a circuit including a counter, Includes, The circuit is configured to generate the hardware signal, The aforementioned circuit further, The value stored in the counter is modified by increasing or decreasing it according to the clock associated with the clock cycle. The processor core receives a read operation directed to the counter, In response to receiving the aforementioned read operation, the value stored in the counter is determined, The system determines whether to change the state of the hardware signal based at least partially on the value stored in the counter. The state of the hardware signal is changed to the first state. It is configured in such a way. Device.
2. The apparatus according to claim 1, wherein the processor core further comprises A device configured to stall in response to the state of the hardware signal being changed to the first state.
3. The apparatus according to claim 2, The circuit is further configured to change the state of the hardware signal to a second state in response to the value stored in the counter being changed to a specified value. The processor core is further configured to resume execution of the machine code instruction in response to the second state of the hardware signal. Device.
4. The apparatus according to claim 2, The circuit is further configured to change the state of the hardware signal to a second state in response to the value stored in the counter becoming equal to a specified value. The processor core is further configured to read a first register associated with a peripheral device in response to the second state of the hardware signal. Device.
5. The apparatus according to claim 4, wherein the circuit is further configured to input from a second register to the counter in response to detecting an interrupt from the peripheral device.
6. The apparatus according to claim 5, wherein the second register is configured to store a non-zero value, and the counter is configured to decrement the non-zero value in each clock cycle.
7. The apparatus according to claim 5, wherein the second register is configured to store a non-zero value, and the counter is configured to increment from zero to the non-zero value in each clock cycle.
8. The apparatus according to claim 1, wherein the processor core is further configured to input a non-zero value into a first register for the duration of execution, and the counter is configured to decrement the non-zero value in each clock cycle.
9. The apparatus according to claim 1, wherein the processor core is further configured to input a non-zero value to a first register for the duration of execution, and the counter is configured to increment from zero to the non-zero value in each clock cycle.
10. The apparatus according to claim 1, wherein the circuit is further configured to input a first value stored in the counter to a second register in a manner corresponding to the time it takes for the read operation to be received from the processor core.
11. It is a method, Starting the counter, The processor core receives a read operation directed to the aforementioned counter, Stalling the processor core, which includes causing a hardware signal to acquire a first state in response to the read operation from the processor core, wherein the hardware signal is transmitted on the bus from a hardware logic unit to the processor core, causing the processor core to delay. The counter maintains the first state of the hardware signal for the duration of the time period during which it performs counter operations. The counter, in response to reaching a specified value, causes the hardware signal to acquire a second state, thereby uninstalling the processor core. Methods that include...
12. A method according to claim 11, wherein the start of the counter is performed in response to the detection of an interrupt signal from a peripheral device.
13. The method according to claim 11, wherein the start of the counter is performed in response to the detection of an interrupt signal from a peripheral device, and the method further A method comprising reading a register associated with the peripheral device after the hardware signal has acquired the second state.
14. A method according to claim 11, wherein starting the counter includes receiving a write operation from the processor core for a duration of execution, wherein the write operation is configured to store a non-zero value in the counter, the non-zero value corresponding to the amount of clock cycles of the processor core associated with the identified value.
15. The method according to claim 11, further, The read operation includes storing the value of the counter corresponding to the time the read operation was received, A method comprising replacing a previously stored value of a counter in response to the value of the counter being greater than a previously stored value, or in response to the value of the counter being less than a previously stored value.
16. It is a device, A hardware counter circuit coupled to a first bus, wherein the first bus includes a data bus configured to support read and write access to the hardware counter circuit from a processing unit, Hardware logic coupled to the hardware counter circuit and the second bus, Includes, The apparatus wherein the second bus is coupled to the processing unit, and the hardware logic is configured to assert and deassert hardware signals on the second bus in response to the value of the hardware counter circuit in a read operation on the first bus.
17. The apparatus according to claim 16, wherein the hardware logic further includes an interrupt signal input coupled to a peripheral bus.
18. The apparatus according to claim 16, further comprising a register configured to input a value from the register to the hardware counter circuit in order to start a counting operation.
19. The apparatus according to claim 18, wherein the hardware logic further comprises An interrupt input configured to input the value from the register to the hardware counter circuit in response to receiving an interrupt.
20. The apparatus according to claim 18, The system further includes a third bus that connects the registers to the processing unit, A device wherein the third bus is configured for read and write access to the register during execution time, including write operations from the processing unit of a non-zero value corresponding to the amount of clock cycles of the processing unit associated with the value.