System and method for DRAM-less garbage collection with improved performance

Abstract

A system and associated method comprising: a system memory having a source memory block and a destination memory block, each of the source memory block and the destination memory block being of the memory block size; a first volatile memory and a second volatile memory, each of the first volatile memory and the second volatile memory being of the volatile memory size. The system comprises a processing circuit for receiving a garbage collection request associated with the destination memory block. The processing circuit then determines whether the memory block size is greater than the volatile memory size and suspends data modification operations while allowing passive operation to continue. While data modification operations are suspended, the processing circuit loads a first portion of the data from the source memory block into the first volatile memory and a second portion of the data into the second volatile memory. The processing circuit writes each portion of the data from the volatile memory to the destination memory block to complete garbage collection and release the suspension of data modification operations.

Description

Technical Field

[0001] The present disclosure is directed to systems and methods for performing garbage collection within a storage device.

Summary of the Invention

[0002] In accordance with the present disclosure, systems and methods are provided for garbage collection in a storage system that does not include dynamic random access memory (DRAM). A DRAM-less storage system may comprise a system memory having memory blocks of a memory block size, and a volatile memory of a volatile memory size, wherein the memory block size is larger than the volatile memory size. The systems and methods disclosed herein enable garbage collection of memory blocks that are larger in size than the volatile memory, while processing circuitry of the storage system is capable of handling passive operations such as read operations. The system may receive a garbage collection request indicating a destination address of a destination memory block to be erased. The system erases any invalid or stale destination data stored at the destination address by overwriting destination data in the system memory with valid source data from a source memory block. The systems and methods disclosed herein temporarily store portions of the source data using volatile memory to overwrite invalid or stale destination data indicated by the garbage collection request. This improves the overall bandwidth and efficiency of processing circuitry of a storage device (e.g., a solid-state drive (SSD) device) during garbage collection processing.

[0003] In some embodiments, a system (e.g., a storage device) is provided comprising a system memory, a volatile memory, and a processing circuit, all of which are communicatively coupled. In some embodiments, the processing circuit receives a garbage collection request indicating invalid or old data to be erased or overwritten. In some embodiments, the processing circuit loads at least two portions of valid source data into the volatile memory, and the source data of these at least two portions is used to overwrite invalid destination data stored in the system memory. The garbage collection request received by the processing circuit includes a destination address corresponding to the destination data to be erased by garbage collection. [Brief explanation of the drawing]

[0004] The following description includes a discussion of the drawings, which have examples given as implementations of embodiments of the embodiments of this disclosure. The drawings should be understood as examples, not limitations. Where used herein, references to one or more “embodiments” should be understood as describing specific features, structures, and / or characteristics contained in at least one implementation. Thus, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations, and not all necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0005] [Figure 1] The following are illustrative diagrams of a storage device comprising a processing circuit, system memory, and volatile memory according to some embodiments of the present disclosure.

[0006] [Figure 2] The following are illustrative diagrams illustrating the process of transferring source data from a source memory block to a destination memory block according to some embodiments of this disclosure.

[0007] [Figure 3] An exemplary diagram of the operation queue shown in Figure 1, according to some embodiments of the present disclosure, is provided.

[0008] [Figure 4] The flowcharts below illustrate exemplary steps for performing garbage collection on a DRAM-less storage device according to some embodiments of the present disclosure.

[0009] [Figure 5] The flowcharts illustrate exemplary stages of subprocesses in some embodiments of the present disclosure that suspend data modification operations queued by a processing circuit while allowing read operations and error handling operations to continue. [Modes for carrying out the invention]

[0010] This disclosure provides a system and method for garbage collection in a storage system (e.g., an SSD device) that does not have dynamic random access memory (DRAM). An SSD device may receive a garbage collection request and perform garbage collection on data corresponding to the destination address of a destination memory block in system memory. Garbage collection may erase the destination data stored at the destination address. However, the destination data may also be overwritten by other data (e.g., source data of a source memory block). For example, a processing circuit in a DRAM-less storage system may load valid source data of a source memory block into volatile memory and temporarily store the source data before overwriting invalid destination data that is subject to garbage collection. In a DRAM-less storage system, the memory block size of each memory block (e.g., a source memory block and a destination memory block) is larger than the volatile memory size of the volatile memory (e.g., a first volatile memory and a second volatile memory). In such a system, the processing circuit loads first and second portions of the source data into the first and second volatile memories. This process occurs while the processing circuit is holding back on processing a data modification operation (e.g., a write operation).

[0011] In some embodiments, the processing circuit may first receive a garbage collection request associated with a destination memory block in system memory. The garbage collection request is used to indicate a portion or all of a memory block in system memory that will be overwritten or deleted due to old or invalid data. Next, the processing circuit determines whether the memory block size of the memory block (e.g., source memory block and destination memory block) is greater than the volatile memory size of the volatile memory (e.g., first volatile memory and second volatile memory). If the memory block size is greater than the volatile memory size, the processing circuit pauses any data modification operations (e.g., write operations) previously queued by the processing circuit, while allowing the processing circuit to continue processing passive operations (e.g., read operations and error handling operations). Data modification operations are stalled during the garbage collection process to prevent any data involved in the garbage collection process (e.g., data associated with the source memory block) from being unexpectedly modified. However, passive operations such as read operations should not cause any problems during the garbage collection process. Due to the large memory block size, the source data is divided into at least two parts (e.g., a first part of the data and a second part of the data) and loaded into at least two volatile memories (e.g., a first volatile memory and a second volatile memory). The volatile memories can be used to temporarily store parts of the data due to their fast read-time characteristics. Once the parts of the source data are loaded into the volatile memories, the processing circuit completes the garbage collection process by writing the first part of the data from the first volatile memory and the second part of the data from the second volatile memory to the destination memory block. Finally, once the garbage collection process for the destination memory block is complete, the processing circuit releases the pause for data modification operations and proceeds to process write operations that have been queued by the processing circuit since the start of the most recent garbage collection process.

[0012] In some embodiments, the system memory of the systems disclosed herein may include any of the following memory densities: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC), and any preferred memory density greater than 5 bits per memory cell. In some embodiments, the system memory includes at least two memory blocks.

[0013] For the purpose of brevity and clarity, the features of the disclosure described herein are in the context of an SSD having processing circuits, volatile memory, and system memory. However, the principles of the disclosure may be applied to any other suitable context in which garbage collection of a DRAM-less system is used. The storage device may include processing circuits, volatile memory, and system memory, which are communicatively coupled to one another by a network bus or interface. In some embodiments, the processing circuits receive requests or operations, which may be driven on the network bus or interface from an external source of the storage device, or transmitted from within the storage device (e.g., from system memory).

[0014] In particular, this disclosure provides a system and method for performing garbage collection in a DRAM-less storage system by dividing source data into at least two data parts and temporarily storing the source data in at least two volatile memories. The system and method utilize the fact that data modification operations, such as write operations by processing circuits, are temporarily suspended while passive operations (e.g., read operations and error handling operations) during garbage collection are allowed to continue. This improves the overall throughput of the storage system while processing circuits are handling the garbage collection of invalid or old data.

[0015] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly handling high bandwidth input data (for example, by initiating simultaneous processing of instructions before the completion of previous instructions).

[0016] In some embodiments, the systems and methods of the present disclosure may refer to storage device systems (e.g., SSD storage systems) that include storage devices such as solid-state drive devices that are communicably coupled to processing circuits by a network bus or interface.

[0017] An SSD is a data storage device that uses an integrated circuit assembly as memory for permanently storing data. SSDs have no moving mechanical components, and this characteristic distinguishes them from conventional electromechanical magnetic disks such as hard disk drives (HDDs) or floppy disks, which include rotating disks and moving read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shocks, operate quietly, have shorter access times, and have lower latency.

[0018] Many types of SSDs use NAND-based flash memory, including types of non-volatile storage technologies, to retain data without power. The quality of service (QoS) of an SSD can relate to low latency predictability and high consistency of input / output operations per second (IOPS) while handling read / write input / output (I / O) workloads. This means that delays or I / O command completion times must remain within a specified range without unexpected outliers. Throughput or I / O speed may also need to be tightly controlled without causing abrupt performance degradations.

[0019] The subject matter of this disclosure can be better understood by referring to Figures 1 to 5.

[0020] Figure 1 shows an exemplary diagram of a system 100 of a storage device 102 comprising a processing circuit 104, a system memory 106, and a volatile memory 108, according to some embodiments of the present disclosure. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., an SSD device). In some embodiments, the processing circuit 104 may include a processor or any preferred processing unit. In some embodiments, the system memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device 102 may include a hard disk drive (HDD) device in addition to, or instead of, an SSD.

[0021] In some embodiments, the processing circuit 104 is configured to receive garbage collection requests, which include a memory address for a destination memory block in system memory 106 to be garbage collected. Garbage collection may be requested for invalid or old data that the processing circuit 104 has determined is no longer needed. Garbage collection generally refers to memory management by reacquiring portions of memory previously allocated for now invalid or old data. In some embodiments, garbage collection may erase invalid or old data allocated to the memory address included in the garbage collection request. In some embodiments, garbage collection may overwrite invalid or old data with valid data that is more likely to be used while the processing circuit 104 is executing an instruction or operation. In some embodiments, garbage collection requests are transmitted to the processing circuit 104 over a network bus or interface. In some embodiments, garbage collection requests are transmitted from an external source (e.g., a host device communicably coupled to a storage device 102). The processing circuit 104 may receive garbage collection requests from both internal and external sources of the storage device 102. The processing circuit 104 includes an operation queue 105, which is configured to temporarily store any unprocessed instructions (e.g., read instructions or write instructions) that are to be processed by the processing circuit 104.

[0022] In some embodiments, the operation queue of the processing circuit 104 is configured to include at least two buffers or queues, the first queue being configured to temporarily store prioritized instructions (e.g., read instructions or error handling instructions), and the second queue being configured to temporarily store data modification operation instructions, such as write instructions. The implementation of the prioritized queue (e.g., the first queue) allows the processing circuit 104 to perform operations that do not interfere with the performance of ongoing garbage collection on a portion of the system memory 106. Data modification operations, such as write operations, remain in the data modification operation queue (e.g., the second queue) during garbage collection to prevent unexpected results from occurring in the system memory 106 due to writes to memory addresses used within the garbage collection process.

[0023] In addition, the storage device 102 includes a system memory 106. In some embodiments, the system memory 106 includes one or more non-volatile memories such as Phase Change Memory (PCM), PCM and switch (PCMS), Ferroelectric Random Access Memory (FeRAM), or Ferroelectric Transistor Random Access Memory (FeTRAM), Memlistor, Spin-Transfer Torque Random Access Memory (STT-RAM), Magnetoresistive Random Access Memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the system memory 106 includes a source memory block 110 containing source data at a source address, and a destination memory block 112 containing destination data at a destination address. The destination memory block 112 is the memory block on which garbage collection will be performed, and the source memory block 110 contains source data that the processing circuit 104 uses to overwrite invalid destination data in the destination memory block 112. In some embodiments, the processing circuit 104 is communicatively coupled to system memory 106 to store and access data corresponding to memory blocks (e.g., source memory block 110 and destination memory block 112). In some embodiments, a data bus interface is used to carry garbage collection requests or data associated with garbage collection.A data bus between the system memory 106 and the processing circuit 104 provides a network bus for accessing or writing data to the system memory 106 (e.g., any memory block of the system memory 106).

[0024] The storage device 102 also includes a volatile memory 108. In some embodiments, the volatile memory 108 includes any one or more of volatile memories such as static random access memory (SRAM). In some embodiments, the volatile memory 108 includes at least a first volatile memory 114 and a second volatile memory 116, each of which is configured to temporarily store data (e.g., source data) during execution of operations by the processing circuit 104. In some embodiments, the processing circuit 104 is communicatively coupled to the volatile memory 108 for storing and accessing data corresponding to the volatile memories (e.g., the first volatile memory 114 and the second volatile memory 116). In some embodiments, the data bus interface is used to carry data associated with garbage collection between the system memory 106 and the volatile memory 108. A data bus between the system memory 106 and the volatile memory 108 provides a network bus for accessing or writing data to or from the system memory 106 (e.g., the source memory block 110 and the destination memory block 112).

[0025] In some embodiments, the processor or processing unit of the processing circuit 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as the processing circuit 104, may include any suitable software, hardware, or both for controlling the system memory 106 and the processing circuit 104. In some embodiments, the storage device 102 may further include a multicore processor. The system memory 106 may also include hardware elements for non-temporary storage of instructions, commands, or requests.

[0026] The processing circuit 104 is configured to perform garbage collection on the DRAM-less storage device 102 by dividing data from the source memory block 110 into a plurality of groups or portions. The processing circuit 104 may first receive a garbage collection request associated with the destination memory block 112. When the processing circuit 104 receives the garbage collection request, the processing circuit 104 determines whether a memory block size of the system memory 106 is larger than a volatile memory size of the volatile memory 108. If the memory block size is larger than the volatile memory size, source data of the source memory block 110 must be divided into at least two portions (e.g., a first portion of data and a second portion of data) to be loaded into at least two volatile memories (e.g., a first volatile memory 114 and a second volatile memory 116). The processing circuit 104 is further configured to suspend execution of any data change operations queued by the processing circuit 104 in an operation queue 105, while allowing continued execution of read operations and error handling operations. In some embodiments, the processing circuit 104 loads the first portion of data into the first volatile memory 114 and loads the second portion of data into the second volatile memory 116. The garbage collection in the DRAM-less storage device 102 disclosed herein ensures that the processing circuit 104 can process instructions for operations that do not cause any unexpected changes to data in the system memory 106 during garbage collection, such as read operations and error handling operations. This processing improves the operating bandwidth of the processing circuit 104 during garbage collection in a DRAM-less storage device (e.g., the storage device 102).

[0027] A storage device (e.g., an SSD device) may include one or more packages of memory dies (e.g., system memory 106), where each die includes a storage cell. In some embodiments, the storage cells are organized into pages, and the pages are organized into blocks such as a source memory block 110 and a destination memory block 112. Each storage cell may store one or more bits of information.

[0028] System 100 illustrates one embodiment in which a DRAM-less storage device (e.g., storage device 102) is configured to have the ability to perform garbage collection with improved bandwidth for read operations and error handling operations during garbage collection, in accordance with this disclosure. However, it will be understood that any other suitable device may be implemented in a similar manner.

[0029] For the purpose of clarity and brevity, and not as an limitation, this disclosure is provided in the context of performing garbage collection with improved bandwidth for passive operations (e.g., read operations, error handling operations) during garbage collection, and thereby provides the features and functionalities disclosed herein. The process of performing garbage collection with improved bandwidth for passive operations may consist of any suitable software, hardware, or both for implementing such features and functionalities. As disclosed, the performance of garbage collection may be implemented, for example, in storage device 102 (e.g., as part of processing circuit 104 or as part of any other suitable device). For example, for a solid-state storage device (e.g., storage device 102), garbage collection with improved bandwidth for read operations and error handling operations may be implemented in processing circuit 104.

[0030] Figure 2 shows an exemplary diagram illustrating a process 200 for transferring source data 203 from a source memory block 110 to a destination memory block 112, according to some embodiments of the present disclosure. The source memory block 110 contains source data 203 stored at source address 202. The destination memory block 112 contains destination data 205 stored at destination address 204.

[0031] At time t1209, the processing circuit 104 loads the first portion 206 of the data associated with the source memory block into the first volatile memory 114 and the second portion 208 of the data associated with the source memory block into the second volatile memory 116. The source data 203 at source address 202 is divided into at least two parts due to the larger size of the memory blocks in the system memory 106 (e.g., source memory block 110 and destination memory block 112) compared to the respective volatile memory sizes of the first volatile memory 114 and the second volatile memory 116. In some embodiments, the source data 203 may be divided into more than two parts, for example, three parts of the data associated with the source data 203. In such an example, the processing circuit 104 loads the third portion of the data associated with the source data 203 into a third volatile memory (not shown in Figure 2).

[0032] In some embodiments, while a data modification operation (e.g., a write operation) is pending in the operation queue 105, a first portion 206 of the data is loaded into the first volatile memory 114 and a second portion 208 of the data is loaded into the second volatile memory 116. During this initial phase of garbage collection, passive operations may be processed in parallel with the loading operations of the first portion 206 and the second portion 208 of the data. For example, a read operation may be processed by a processing circuit to read at a memory address in system memory, including the source address 202 and the destination address 204. By using the first volatile memory 114 and the second volatile memory 116 as intermediate memory allocations, it is possible to continue processing passive operations without affecting the data stored in system memory 106. After the processing circuit 104 loads the first portion 206 of the data associated with the source memory block 110 into the first volatile memory 114 and the second portion 208 of the data associated with the source memory block 110 into the second volatile memory 116, the processing circuit 104 writes the first portion 206 and the second portion 208 of the data into the destination memory block 112.

[0033] At time t2210, the processing circuit 104 completes garbage collection by writing the first portion 206 of the data from the first volatile memory 114 associated with the source memory block 110, and the second portion 208 of the data from the second volatile memory 116 associated with the source memory block 110, to the destination address 204. In some embodiments, the processing circuit overwrites the destination data 205 at destination address 204 with the first portion 206 and the second portion 208 of the data associated with the source data 203. In some embodiments, the destination data 205 contains invalid or old data. When the invalid or old destination data 205 is overwritten with the source data 203, the garbage collection process is completed. In some embodiments, passive operations (e.g., read operations and error handling operations) are continued by the processing circuit at time t2210. Once the processing circuit has written the first part 206 and the second part 208 of the data to the destination memory block 112 and completed garbage collection, the processing circuit 104 then releases the suspension of any pending data modification operations held in the operation queue 105.

[0034] In some embodiments, a data bus memory interface is used to transport the first portion 206 and the second portion 208 of the data associated with the source data 203 between the system memory 106 and the volatile memory 108. The data bus memory interface between the system memory 106 and the volatile memory 108 provides a memory network bus for accessing or writing data in the system memory 106 and the volatile memory 108.

[0035] In some embodiments, the system memory 106 includes one or more non-volatile memories such as phase-change memory (PCM), PCM and switch (PCMS), ferroelectric random access memory (FeRAM), or ferroelectric transistor random access memory (FeTRAM), memristor, spin-injection torque random access memory (STT-RAM), magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the volatile memory may include a separate cache or other suitable volatile memory 108 for temporarily storing data before it is written to the system memory 106. In some embodiments, the system memory 106 may also include hardware elements for non-temporary storage of instructions, commands, or requests.

[0036] Figure 3 shows an exemplary diagram of the operation queue 105 of Figure 1 according to some embodiments of the present disclosure. In some embodiments, the operation queue 105 may be located within the processing circuit 104, or elsewhere in the storage device 102 and communicatively coupled to the processing circuit 104. The operation queue is configured to store unprocessed instructions to be processed by the processing circuit 104.

[0037] In some embodiments, the operation queue 105 includes a data change operation queue 302 and a prioritized queue 304. The data change queue 302 is configured to temporarily store data change operations, such as write instructions (e.g., write instructions 308 and 309). The prioritized queue 304 is configured to temporarily store passive operations, such as read instructions (e.g., read instruction 310) and error handling instructions. In some embodiments, the operation queue 105 includes a multiplexer 306, which is configured to select instructions to be sent to the processing circuit 104 for processing. In some embodiments, the multiplexer 306 selects from the top of the data change operation queue 302 and the top of the prioritized queue 304. The multiplexer 306 may use a selection signal (e.g., a single selection bit for selecting between two queues) to select from which queue to send instructions to the processing circuit 104. In some embodiments, the operation queue 105 may include more than two queues / buffers (e.g., a data change operation queue 302 and a prioritized queue 304). In some embodiments, the operation queue 105 may include stacks, queues, and / or any preferred form of buffer including stacks.

[0038] In addition, the operation queue 105 may include a register or latch in which a status bit can be stored. During the initialization of the garbage collection process, the processing circuit 104 may send an interrupt signal to the operation queue 105 to modify the status bit to indicate that garbage collection is currently in progress. During garbage collection, the operation queue 105 may hold any pending data modification operations (e.g., write instructions 308 and 309) for selection by the multiplexer 306, while allowing passive operations (e.g., read instructions 310) to be selected by the multiplexer 306 and sent to the processing circuit 104.

[0039] Figure 4 shows an exemplary step-by-step flowchart of a process 400 for performing garbage collection on a DRAM-less storage device according to some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuit, operation queue, system memory, volatile memory, source memory block, destination memory block, first volatile memory, second volatile memory, source data, destination data, first part of data, and second part of data may be implemented as storage device 102, processing circuit 104, operation queue 105, and system memory 106, volatile memory 108, source memory block 110, destination memory block 112, first volatile memory 114, second volatile memory 116, source data 203, destination data 205, first part of data 206, and second part of data 208, respectively. In some embodiments, the process 400 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0040] In step 402, the processing circuit receives a garbage collection request associated with a destination memory block to delete potentially invalid or outdated destination data. Invalid data may be defined as data that is no longer needed by the processing circuit. In some embodiments, the garbage collection request may include the destination address 204 of the destination memory block to indicate to the processing circuit the data to be garbage collected. In some embodiments, the garbage collection request is received by the processing circuit from a network bus or interface. In some embodiments, the received garbage collection request is one of at least two garbage collection requests in a stream of requests. In some embodiments, system memory may include other memory blocks and / or memory pages. In some embodiments, the storage device receives different types of requests, such as read requests, write requests, and error handling requests. At least one of the received requests may be stored in an operation queue, volatile memory, system memory, or any form of temporary memory. In some embodiments, the processing circuit may include a multicore processor capable of performing garbage collection. When the processing circuit receives a garbage collection request, in step 404, the processing circuit determines whether the memory block size is greater than the volatile memory size.

[0041] In step 404, the processing circuit determines whether the memory block size is greater than the volatile memory size. The memory block size is defined as the memory size of each memory block in the system memory (e.g., the source memory block and the destination memory block). The volatile memory size is defined as the memory size of each volatile memory (e.g., the first volatile memory and the second volatile memory). In some embodiments, if the volatile memory size is greater than the memory block size, the garbage collection process may be able to load the entire memory block into the volatile memory (e.g., the first volatile memory or the second volatile memory). If there is only one load operation to move data from system memory to volatile memory, the likelihood of a data modification operation (e.g., a write operation) causing unexpected changes or results in system memory while the processing circuit is performing garbage collection is reduced. If the processing circuit determines that the memory block size is larger than the volatile memory size, the processing circuit then, in step 406, pauses the data modification operations (e.g., write operations) that have been queued by the processing circuit, while allowing passive operations (e.g., read operations and error handling operations) to continue.

[0042] In step 406, the processing circuit pauses data modification operations queued by the processing circuit while allowing read operations and error handling operations to continue. In some embodiments, data modification operations include write operations or any other operations that modify data stored in memory blocks of system memory (e.g., source memory blocks and destination memory blocks). In some embodiments, the processing circuit allows any preferred passive operations that do not modify data stored in system memory during the garbage collection process. In some embodiments, the processing circuit temporarily stores data modification operations (e.g., write operations) in an operation queue until garbage collection is complete. If the processing circuit receives a passive operation (e.g., a read operation or an error handling operation), the passive operation may bypass the operation queue to be processed by the processing circuit during garbage collection. In some embodiments, the operation queue may include at least two buffers or queues, where the first queue stores data modification operations (e.g., write operations) and the second queue stores passive operations (e.g., read operations and error handling operations). In some embodiments, the processing circuit queues any further data modification operations received during the garbage collection process. The processing circuit may temporarily store the data modification operations in any suitable volatile memory. When the processing circuit pauses the data modification operations it has queued, in step 408, it loads a first portion of the data associated with the source memory block into the first volatile memory.

[0043] In step 408, the processing circuit loads a first portion of the data associated with the source memory block into the first volatile memory. The source data at source address 202 is divided into at least two parts due to the large size of the memory block in system memory. In some embodiments, the first portion of the source data is loaded into the first volatile memory while a data modification operation is held in the operation queue. During this initial phase of garbage collection, passive operations may be processed in parallel with the load operation. For example, a read operation may be processed by the processing circuit to read at a memory address in system memory, including the source address and destination address. By using the first volatile memory as an intermediate memory allocation, it is possible to continue processing passive operations without affecting data stored in system memory. After the processing circuit has loaded the first portion of the data associated with the source memory block into the first volatile memory, in step 410, the processing circuit loads a second portion of the data associated with the source memory block into the second volatile memory.

[0044] In step 410, the processing circuit loads the second portion of the data associated with the source memory block into the second volatile memory. Similar to step 408, step 410 occurs while the data modification operation is paused from being processed by the processing circuit, and the processing of passive operations by the processing circuit may continue. In some embodiments, the processing circuit divides the source data in the source memory block of the system memory into more than two parts of the data. For example, the source data may be divided into three parts of the data associated with the source memory block. In such an example, the processing circuit loads the third portion of the data associated with the source memory block into the third volatile memory. Once the processing circuit has loaded the second portion of the data associated with the source memory block into the second volatile memory, in step 412, the processing circuit completes garbage collection by writing the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory, respectively, to the destination memory block.

[0045] In step 412, the processing circuit completes garbage collection by writing the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory to the destination memory block. In some embodiments, the processing circuit overwrites the destination data at destination address 204 with the first and second portions of the data associated with the source data. Garbage collection is completed when the invalid or old destination data has been overwritten with the source data. In some embodiments, passive operations (e.g., read operations and error handling operations) are continued by the processing circuit during step 412. Once the processing circuit has completed garbage collection by writing the first and second portions of the data to the destination memory block, the processing circuit releases the suspension of data modification operations in step 414.

[0046] In step 414, the processing circuit unsuspends any data modification operations (e.g., write operations) that were suspended in step 406. Once garbage collection is complete, the processing circuit may continue to modify the contents of the system memory by processing any outstanding data modification operations from the operation queue. In some embodiments, if the processing circuit receives another garbage collection request to erase invalid or old data at a different destination address in a different destination memory block, process 400 may be repeated.

[0047] Figure 5 shows a flowchart of exemplary stages of a subprocess 500 according to some embodiments of the present disclosure, which suspends data modification operations queued by the processing circuit (for example, in stage 406 as shown in Figure 4) while allowing read operations and error handling operations to continue. In some embodiments, the referenced storage device, processing circuit, operation queue, system memory, volatile memory, source memory block, destination memory block, first volatile memory, second volatile memory source data, destination data, first part of data, and second part of data may be implemented as storage device 102, processing circuit 104, operation queue 105 and system memory 106, volatile memory 108, source memory block 110, destination memory block 112, first volatile memory 114, second volatile memory 116, source data 203, destination data 205, first part of data 206, and second part of data 208, respectively. In some embodiments, the subprocess 500 may be modified, for example, by rearranging, changing, adding, and / or deleting stages.

[0048] In step 502, the processing circuit sends a control signal to the operation queue to allow read operations to continue while suspending data modification operations within the operation queue. In some embodiments, before initiating garbage collection, the processing circuit may send an interrupt to the operation queue to pause any unprocessed data modification operations and any further data modification operations received during garbage collection. In some embodiments, the interrupt may configure the operation queue to allow only passive operations (e.g., read operations and error handling operations) to continue and be processed by the processing circuit.

[0049] Unless otherwise explicitly stated, the terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments.”

[0050] Unless otherwise explicitly stated, the terms “including,” “comprising,” and “having,” and their variations, mean “including, but not limited to.”

[0051] Unless otherwise explicitly stated, the list of enumerated items does not imply that any or all of the items are mutually exclusive.

[0052] Unless otherwise explicitly stated, the terms “a,” “an,” and “the” mean “one or more.”

[0053] Unless otherwise explicitly stated, multiple devices communicating with each other do not need to communicate with each other continuously. In addition, multiple devices communicating with each other may communicate directly or indirectly through one or more intermediate media.

[0054] A description of an embodiment having multiple components communicating with one another does not imply that all such components are required. On the contrary, various optional components are described to illustrate a wide variety of conceivable embodiments. Furthermore, while processing steps, method steps, algorithms, or the like may be described in a sequential order, such processing, methods, and algorithms may be configured to function in alternative orders. In other words, any order or sequence of steps that may be described does not necessarily imply that these steps must be performed in that order. The processing steps described herein may be performed in any practical order. Furthermore, several steps may be performed simultaneously.

[0055] Where a single device or article is described herein, it will be readily apparent that more than one device / article may be used instead of a single device / article (whether they work together or not). Similarly, where more than one device or article is described herein (whether they work together or not), it will be readily apparent that a single device / article may be used instead of more than one device or article, or that a different number of devices / articles may be used instead of the number of devices or programs shown. The functions and / or features of a device may be embodied by one or more other devices not expressly described as having such functions / features. Therefore, other embodiments do not necessarily have to include the device itself.

[0056] At least certain operations, which may be shown in the figures, represent specific events occurring in a specific order. In alternative embodiments, certain operations may be performed, modified, or omitted in a different order. Furthermore, steps may be added to the logic described above, and it may still be compatible with the described embodiments. Moreover, the operations described herein may be performed sequentially, or certain operations may be processed in parallel. Furthermore, operations may be performed by a single processing unit or by distributed processing units.

[0057] The above description of various embodiments is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact forms disclosed. In light of the above teachings, many modifications and variations are possible.

Claims

1. System memory having a source memory block and a destination memory block, each of the source memory block and the destination memory block being of a memory block size; The first volatile memory and the second volatile memory, each of the first and second volatile memories, is a volatile memory size; and Processing circuit that is communicatively coupled to the system memory, the first volatile memory, and the second volatile memory. A system comprising the processing circuit receiving a garbage collection request associated with the destination memory block and responding to the garbage collection request: Determine whether the memory block size is larger than the volatile memory size. The aforementioned processing circuit temporarily suspends the queued data modification operations while allowing the read operations and error handling operations to continue. While data modification operations are paused and read operations are permitted to continue: A first portion of the data associated with the source memory block is loaded into the first volatile memory. Load a second portion of the data associated with the source memory block into the second volatile memory, and The first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory are written to the destination memory block to complete garbage collection, and To release the temporary suspension of the aforementioned data modification operation, system.

2. The first volatile memory and the second volatile memory are segments of a volatile memory, the volatile memory includes a plurality of segments, each segment of the volatile memory is the size of the volatile memory, and the processing circuit further, A portion of the data associated with the source memory block is loaded into each of the multiple segments of the volatile memory. The system according to claim 1.

3. The system according to claim 1, wherein the data modification operation includes a write operation.

4. The system according to claim 1, further comprising an operation queue coupled to the processing circuit, wherein the processing circuit further transmits a control signal to the operation queue to allow a read operation to pass to the processing circuit while suspending a data modification operation within the operation queue.

5. The system according to claim 1, wherein the processing circuit further overwrites the previously stored data in the destination memory block with a first portion of the data from the first volatile memory and a second portion of the data from the second volatile memory.

6. The system according to claim 1, wherein the system memory has a non-volatile memory, and the non-volatile memory includes one of the following: a phase-change memory (PCM), a PCM and switch (PCMS), a ferroelectric random access memory (FeRAM), or a ferroelectric transistor random access memory (FeTRAM), a memristor, a spin-transfer torque random access memory (STT-RAM), a magnetoresistive random access memory (MRAM), and a flash memory.

7. The system according to claim 1, wherein the first volatile memory and the second volatile memory include static random access memory (SRAM).

8. The memory device processing circuit receives a garbage collection request associated with the destination memory block of the system memory of the memory device, and responds to the garbage collection request: The processing circuit determines whether the memory block size of the system memory is larger than the volatile memory size of the volatile memory of the memory device. The processing circuit pauses the data modification operation queued by the processing circuit, while allowing the read operation and error handling operation to continue. While data modification operations are paused and read operations are permitted to continue: The processing circuit loads a first portion of the data associated with the source memory block of the system memory into the first volatile memory of the volatile memory. The processing circuit loads a second portion of the data associated with the source memory block into the second volatile memory of the volatile memory, and The processing circuit completes garbage collection by writing each of the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory to the destination memory block, and The processing circuit then releases the temporary suspension of the data modification operation. A method for providing this.

9. The first volatile memory and the second volatile memory are segments of a volatile memory, the volatile memory includes a plurality of segments, each segment of the volatile memory is the volatile memory size, and the method further, The step of loading the portion of the data associated with the source memory block into each of the multiple segments of the volatile memory. The method according to claim 8, comprising:

10. The method according to claim 8, wherein the data modification operation includes a write operation.

11. The method according to claim 8, wherein the step of temporarily suspending the data modification operation queued by the processing circuit while allowing the continuation of the read operation and error handling operation includes the step of transmitting a control signal to instruct the operation queue to allow the read operation to continue while the data modification operation is held in the operation queue.

12. The method according to claim 8, wherein the step of writing each of the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory to the destination memory block to complete garbage collection comprises the step of overwriting previously stored data in the destination memory block with the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory.

13. The method according to claim 8, wherein the first volatile memory and the second volatile memory include static random access memory (SRAM).

14. A non-temporary computer-readable medium on which non-temporary computer-readable instructions are encoded, wherein, when executed, the non-temporary computer-readable instructions include the steps of receiving a garbage collection request associated with a destination memory block in system memory, and responding to the garbage collection request: A step of determining whether the memory block size of the system memory is larger than the volatile memory size of the volatile memory, A stage in which queued data modification operations are temporarily suspended, while read operations and error handling operations are allowed to continue. While data modification operations are paused and read operations are permitted to continue: A step of loading a first portion of the data associated with the source memory block of the system memory into the first volatile memory of the volatile memory, The steps include loading a second portion of the data associated with the source memory block into the second volatile memory of the volatile memory, and A step of completing garbage collection by writing each of the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory to the destination memory block, and The step of releasing the temporary suspension of the aforementioned data modification operation. A non-temporary computer-readable medium that performs a method having [a certain characteristic].

15. The first volatile memory and the second volatile memory are segments of a volatile memory, the volatile memory includes a plurality of segments, each segment of the volatile memory is the volatile memory size, and the method further, The step of loading the portion of the data associated with the source memory block into each of the multiple segments of the volatile memory. A non-temporary computer-readable medium according to claim 14, having the following characteristics.

16. The non-temporary computer-readable medium according to claim 14, wherein the data modification operation includes a write operation.

17. The non-temporary computer-readable medium according to claim 14, wherein the step of pausing queued data modification operations while allowing read operations and error handling operations to continue includes the step of transmitting a control signal to instruct the operation queue to allow read operations to continue while the data modification operations remain in the operation queue.

18. The non-temporary computer-readable medium according to claim 14, wherein the step of writing each of the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory to the destination memory block to complete garbage collection includes the step of overwriting previously stored data in the destination memory block with the first portion of the data from the first volatile memory and the second portion of the data from the second volatile memory.

19. The non-temporary computer-readable medium according to claim 14, wherein the system memory has a non-volatile memory, and the non-volatile memory includes one of the following: phase-change memory (PCM), PCM and switch (PCMS), ferroelectric random access memory (FeRAM), or ferroelectric transistor random access memory (FeTRAM), memristor, spin-transfer torque random access memory (STT-RAM), magnetoresistive random access memory (MRAM), and flash memory.

20. The non-temporary computer-readable medium according to claim 14, wherein the first volatile memory and the second volatile memory include static random access memory (SRAM).

Images