Plasma etching in semiconductor processing

Abstract

A semiconductor processing method may include forming plasma emitters of multiple precursors (e.g., etchant precursors, oxygen-containing precursors, and silicon-fluorine-containing precursors such as silicon tetrafluoride). The plasma emitters may then come into contact with a silicon-containing material and a mask material on a substrate within a processing area of ​​a semiconductor processing chamber. The mask material may have one or more openings inside that allow the plasma emitters to access the silicon-containing material. By bringing the silicon-containing material and the mask material into contact with the plasma emitters, it may be possible to (i) etch the silicon-containing material using the plasma emitters to form and / or deepen one or more features within the silicon-containing material, and (ii) etch the mask material and deposit a silicon-oxygen-containing material on the mask material using the plasma emitters simultaneously.

Description

[[TECHNICAL FIELD]]

[0001] Cross-reference to Related Applications This application claims the benefit and priority of U.S. Non-Provisional Application No. 18 / 234,685 entitled "PLASMA ETCHING IN SEMICONDUCTOR PROCESSING" filed on August 16, 2023, the contents of which are hereby incorporated by reference in its entirety for all purposes.

[0002] The present technology relates to methods and components for semiconductor processing. More specifically, the present technology relates to systems and methods for etching silicon-containing materials. [[BACKGROUND ART]]

[0003] Integrated circuits are enabled by processes that produce complex patterned layers of material on the surface of a substrate. Producing patterned material on a substrate requires controlled methods for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or reducing the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than other materials, for example, to facilitate a pattern transfer process. As a result of the diversity of materials, circuits, and processes, etching processes with selectivity for various materials have been developed.

[0004] Etching processes can be called wet or dry, depending on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes have difficulty penetrating some constrained trenches, and the remaining material may be deformed. Dry etching is performed in a localized plasma formed within the substrate processing area, but it can penetrate more constrained trenches and lessen the deformation of fragile remaining structures. However, the electric arc generated when the localized plasma discharges can damage the substrate.

[0005] Therefore, there is a need for improved systems and methods that can be used to fabricate high-quality devices and structures. These and other needs are addressed by this technology. [Overview of the project]

[0006] An exemplary semiconductor processing method may include forming a plasma emitter of several precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor). An exemplary silicon- and fluorine-containing precursor is silicon tetrafluoride. The plasma emitter then contacts a silicon-containing material and a mask material on a substrate within a processing area of ​​a semiconductor processing chamber. More specifically, the silicon-containing material may be placed on the substrate, and the mask material (e.g., a dielectric material) may be placed on the silicon-containing material. The mask material may have one or more openings inside that allow the plasma emitter to access the silicon-containing material. By contacting the silicon-containing material and the mask material with the plasma emitter, it may be possible to (i) etch the silicon-containing material using the plasma emitter to form and / or deepen one or more features within the silicon-containing material, and (ii) etch the mask material and deposit a silicon- and oxygen-containing material on the mask material using the plasma emitter simultaneously.

[0007] In some embodiments, the etchant precursor may include one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor other than silicon tetrafluoride. In some embodiments, the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor may be about 50:1 or less. Furthermore, the volume ratio of the etchant precursor to the oxygen-containing precursor may be about 20:1 or less. In some cases, a carrier gas may be present when forming the plasma emission, and the volume ratio of the carrier gas to the oxygen-containing precursor may be about 10:1 or less.

[0008] In some embodiments, the silicon-containing material may include one or more of crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, and silicon germanium. The semiconductor processing method can selectively remove the silicon-containing material from the mask material. For example, the semiconductor processing method can remove the silicon-containing material from the mask material with a selectivity of about 4 or more.

[0009] In some cases, one or more openings are characterized by a critical dimension of approximately 1000 nm or less, or preferably approximately 50 nm or less (e.g., 5 nm to 25 nm). After etching the silicon-containing material, one or more features may be characterized by a depth of approximately 100 nm or more. One or more features are characterized by an aspect ratio of approximately 5:1 or more.

[0010] In some embodiments, the pressure within the processing area can be maintained at about 5 Torr or less. In some embodiments, the temperature within the processing area can be maintained at about 100°C or less. In some embodiments, plasma emissions can be generated with a plasma output of about 5000 W or less.

[0011] Some embodiments of this technology may encompass a semiconductor processing method. This method may include forming a plasma emitter of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-fluorine-containing precursor) in the presence of a carrier gas. An exemplary silicon-fluorine-containing precursor is silicon tetrafluoride. The volume ratio of the oxygen-containing precursor to the silicon-fluorine-containing precursor may be about 50:1 or less, the volume ratio of the etchant precursor to the oxygen-containing precursor may be about 20:1 or less, and the volume ratio of the carrier gas to the oxygen-containing precursor may be about 10:1 or less. The plasma emitter then comes into contact with a silicon-containing material and a mask material on a substrate within the processing area of ​​a semiconductor processing chamber. More specifically, the silicon-containing material may be placed on the substrate, and the mask material (e.g., a dielectric material) may be placed on the silicon-containing material. The mask material may have one or more openings inside that allow the plasma emitter to access the silicon-containing material. By bringing a silicon-containing material and a mask material into contact with a plasma emitter, it is possible to (i) etch the silicon-containing material using the plasma emitter to form and / or deepen one or more features within the silicon-containing material, and (ii) simultaneously etch the mask material and deposit a silicon- and oxygen-containing material onto the mask material using the plasma emitter.

[0012] The semiconductor processing method can selectively remove silicon-containing material from the mask material. For example, the semiconductor processing method can remove silicon-containing material from the mask material with a selectivity of about 4 or more. In some cases, one or more openings are characterized by a critical dimension of about 1000 nm or less, or preferably about 50 nm or less (e.g., 5 nm to 25 nm). After etching the silicon-containing material, one or more features may be characterized by a depth of about 100 nm or more. One or more features may be characterized by an aspect ratio of about 5:1 or more.

[0013] Some embodiments of this technology may encompass semiconductor processing methods. These methods may include forming plasma emitters of multiple precursors (e.g., an etchant precursor, an oxygen-containing precursor, and silicon tetrafluoride), where the volume ratio of the oxygen-containing precursor to silicon tetrafluoride is approximately 50:1 or less. The plasma emitters then contact a silicon-containing material and a mask material on a substrate within a processing area of ​​a semiconductor processing chamber. More specifically, the silicon-containing material may be placed on the substrate, and the mask material (e.g., a dielectric material) may be placed on the silicon-containing material. The mask material may have one or more openings internally, allowing the plasma emitters to access the silicon-containing material. By contacting the silicon-containing material and the mask material with the plasma emitters, it is possible to simultaneously (i) etch the silicon-containing material using the plasma emitters to form and / or deepen one or more features within the silicon-containing material, and (ii) etch the mask material and deposit a silicon- and oxygen-containing material on the mask material using the plasma emitters.

[0014] In some embodiments, the plasma emitter may be a first plasma emitter of a first plurality of precursors, and the method may further include forming a second plasma emitter from a second plurality of silicon tetrafluoride-free precursors. The second plasma emitter can etch the silicon-containing material to form and / or deepen one or more features within the silicon-containing material.

[0015] The semiconductor processing method can selectively remove silicon-containing material from the mask material. For example, the semiconductor processing method can remove silicon-containing material from the mask material with a selectivity of about 4 or more. In some cases, one or more openings are characterized by a critical dimension of about 1000 nm or less, or preferably about 50 nm or less (e.g., 5 nm to 25 nm). After etching the silicon-containing material, one or more features may be characterized by a depth of about 100 nm or more. One or more features may be characterized by an aspect ratio of about 5:1 or more.

[0016] Such technologies can offer many advantages over conventional systems and techniques. For example, embodiments of this technology can improve the formation and deepening of features in semiconductor structures. The above and other embodiments, along with many of their advantages and features, will be described in more detail in the following description and accompanying drawings.

[0017] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0018] [Figure 1] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of this technology is shown. [Figure 2] The following describes the steps in a semiconductor processing method according to several embodiments of this technology. [Figure 3A] An exemplary schematic cross-sectional structure fabricated according to several embodiments of this technology is shown. [Figure 3B] An exemplary schematic cross-sectional structure fabricated according to several embodiments of this technology is shown. [Figure 3C] An exemplary schematic cross-sectional structure fabricated according to several embodiments of this technology is shown. [Modes for carrying out the invention]

[0019] Some of the figures are included as schematic diagrams. Figures are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include elements that are exaggerated for illustrative purposes.

[0020] In the accompanying drawings, similar components and / or features may have the same reference signs. Further, various components of the same type may be distinguished by adding a character after the reference sign to distinguish between similar components. When only the first reference sign is used herein, the description applies to any similar component having the same first reference sign regardless of the character.

[0021] As the size of semiconductor structures decreases, the dimensions of the aforementioned structural features also decrease and often become more dense. Forming features on a semiconductor structure can be accomplished using various methods including etching, in which a mask material can be used to protect the underlying silicon-containing material, and openings in the mask material allow the underlying silicon-containing material to be etched at desired locations. In the prior art, plasma etching and masks are used to increase the depth of features on a semiconductor structure. However, etchant can damage the mask, leading to features having irregular dimensions. Further, as the critical dimension (or width) at the opening of a feature decreases, reactions at the top of the mask or the feature tend to clog the opening, which can prevent etchant from accessing the interior of the feature. One approach to overcoming this is a thicker mask, and the cost and time for manufacturing such a mask increase with the thickness.

[0022] The present technology overcomes these problems using a precursor containing silicon and fluorine (e.g., silicon tetrafluoride). In a plasma etching method, the precursor containing silicon and fluorine can generate silicon-containing plasma emissions and fluorine-containing plasma emissions. As described in more detail herein, the silicon-containing plasma emissions can facilitate regeneration of mask material that is simultaneously etched during the process. Overall, this simultaneous operation can minimize changes in mask thickness during processing of the present disclosure, facilitating the use of thinner masks.

[0023] Furthermore, the fluorine-containing plasma effluent has a relatively high electronegativity, which allows the fluorine-containing plasma effluent to prevent deposition of undesired material, particularly at openings of features, thereby reducing clogging of the openings.

[0024] In the remaining disclosure, specific semiconductor processing methods utilizing the disclosed technology will be routinely identified and one type of semiconductor processing chamber will be described, but it will be readily understood that the described processes may be performed in any number of semiconductor processing chambers. Therefore, the present technology should not be considered to be limited to use with only these specific deposition processes or chambers. In the present disclosure, before describing a semiconductor processing method according to the present technology, one possible chamber that may be used to perform a process in accordance with embodiments of the present technology will be described.

[0025] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 102 within the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that aspects of the present technology may be practiced in any number of chambers, and a substrate support according to the present technology may be included in an etch chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber space 101 within which a substrate may be processed. The chamber body 105 may have sidewalls 112 and a bottom 118, which are coupled to ground 126. The sidewalls 112 have a liner 115 to protect the sidewalls 112 and may extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limiting and may generally be larger in proportion to the size of the substrate 102 processed therein. Examples of substrate sizes include those of 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, such as display or solar cell substrates, among others.

[0026] The chamber body 105 may surround the chamber space 101, supporting the chamber lid assembly 110. The chamber body 105 may be manufactured from aluminum or other suitable material. A substrate access port 113 may be formed through the side wall 112 of the chamber body 105, facilitating the transfer of substrates 102 into and out of the plasma processing chamber 100. The access port 113 may be connected to the transfer chamber and / or other chambers of the substrate processing system, as described above. A pumping port 145 may be formed through the side wall 112 of the chamber body 105 and connected to the chamber space 101. A pumping device may be connected to the chamber space 101 through the pumping port 145 to exhaust the processing space and control the pressure. The pumping device may include one or more pumps and throttle valves.

[0027] The gas panel 160 may be connected to the chamber body 105 by a gas line 167 to supply the process gas into the chamber space 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include inert gases, non-reactive gases, and reactive gases that can be used for any number of processes.

[0028] Examples of process gases that can be provided by the gas panel 160 include, but are not limited to, methane, silicon tetrafluoride, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as any number of additional materials. In addition, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as H2, NH3, H2O, H2O2, NF3, HF, F2, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, SO2, and COS, among any number of additional precursors.

[0029] Valve 166 controls the flow of processing gas from gas panel 160 sources 161, 162, 163, and 164 and can be managed by controller 165. The flow of gas supplied from gas panel 160 to chamber body 105 may include a combination of gases from one or more sources. Lid assembly 110 may include nozzles 114. Nozzles 114 may be one or more ports for introducing processing gas from gas panel 160 sources 161, 162, 164, and 163 into the chamber space 101. After the processing gas is introduced into the plasma processing chamber 100, the gas may be activated to form a plasma. Antennas 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. Antenna power supply 142 can power antennas 148 via matching circuit 141 and inductively couple energy (e.g., RF energy) to the processing gas to maintain the plasma formed from the processing gas within the chamber space 101 of the plasma processing chamber 100. In place of or in addition to the antenna power supply 142, processing electrodes located below and / or above the substrate 102 can be used to capacitively couple RF power to the processing gas and maintain plasma within the chamber space 101. The operation of the power supply 142 may be controlled by a controller (e.g., controller 165) that also controls the operation of other components within the plasma processing chamber 100.

[0030] A substrate support pedestal 135 is positioned within the chamber space 101 to support a substrate 102 during the process. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 102 during the process. The electrostatic chuck ("ESC") 122 may hold the substrate 102 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include an electrode 121 embedded in a dielectric. The electrode 121 is coupled to the RF power supply 125 and may provide a bias that attracts plasma ions formed by the processing gas in the chamber space 101 to the ESC 122 and the substrate 102 fixed on the pedestal. The RF power supply 125 may be switched on and off repeatedly or pulsed during the process of the substrate 102. The ESC122 may have an insulating section 128 to prevent the sidewalls of the ESC122 from being attracted to the plasma, in order to extend the maintenance life of the ESC122. In addition, the substrate support pedestal 135 may have a cathode dryer 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gas and to extend the maintenance interval of the plasma processing chamber 100.

[0031] Electrode 121 may be connected to a power supply 150. The power supply 150 may provide electrode 121 with a chucking voltage of approximately 5,000 volts to approximately -5,000 volts. The power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing a DC current to electrode 121 for chucking and dechucking the substrate 102. For example, similar to an RF power supply 125, power supply 150 may provide a bias to attract plasma ions formed by the processing gas in the chamber space 101 to the ESC 122 and the substrate 102 mounted on the pedestal. Power supply 150 may be repeatedly switched on and off or pulsed during the processing of the substrate 102. In embodiments, power supply 150 may provide RF power, DC current or voltage, or a combination thereof, for chucking and / or biasing. In additional embodiments, multiple power supplies may be configured to provide RF power and DC current or voltage for chucking and / or biasing. The ESC122 may include a heater located within a pedestal and connected to a power supply to heat the substrate. Meanwhile, the cooling base 129 supporting the ESC122 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC122 and the substrate 102 placed on top of it. The ESC122 may be configured to operate within the temperature range required by the thermal balance of the device being manufactured on the substrate 102. For example, the ESC122 may be configured to maintain the substrate 102 at a temperature of approximately -150°C to approximately 500°C, depending on the process being performed.

[0032] A cooling base 129 may be provided to assist in temperature control of the substrate 102. To mitigate processing drift and time, the temperature of the substrate 102 may be kept substantially constant by the cooling base 129 while the substrate 102 is in the cleaning chamber. In some embodiments, the temperature of the substrate 102 may be maintained at a temperature between approximately -150°C and approximately 500°C throughout the subsequent cleaning process, although any temperature may be utilized. A covering 130 may be positioned on the ESC 122 and along the outer periphery of the substrate support pedestal 135. The covering 130 may be configured to shield the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100 while containing etching gases in desired portions of the exposed upper surface of the substrate 102. As described above, lift pins may be selectively moved through the substrate support pedestal 135 to lift the substrate 102 above the substrate support pedestal 135 to facilitate access to the substrate 102 by a transfer robot or other suitable transfer mechanism.

[0033] The controller 165 may be used to adjust the gas flow from the gas panel 160 to the plasma processing chamber 100 and other process parameters, thereby controlling the process sequence. Software routines, executed by the CPU, can cause the CPU to function as a purpose-specific computer, such as a controller, and control the plasma processing chamber 100 so that processing is performed in accordance with this disclosure. Software routines may also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0034] The chamber described above may be used when performing exemplary methods, including etching and processing methods. Figure 2 shows exemplary steps of Method 200 according to an embodiment of the present technology. Prior to the first step of the Method, the substrate may be treated by one or more means (e.g., front-end processing, deposition, etching, polishing, cleaning, or any other step) before being positioned within the processing area of ​​the chamber in which Method 200 may be performed. Some or all of these steps may be performed in a chamber or system tool, or in various chambers on the same system tool (which may include the chamber in which the steps of Method 200 are performed).

[0035] Method 200 may include several optional steps that may or may not be particularly related to certain embodiments of the Method relating to the Art. For example, many of the steps are described to provide a broader range of structural forms, but may not be important to the Art, or may be carried out by alternative methodologies, which will be described further below. Method 200 describes the steps schematically shown in Figures 3A to 3C, the examples of which will be described in conjunction with the steps of Method 200. Figures 3A to 3B are only partial schematic diagrams, and it should be understood that the substrate may include any number of structural parts having the configuration shown in the figures, as well as alternative structural configurations from which the steps of the Art can still be beneficial.

[0036] Method 200 may or may not include optional steps for developing the semiconductor structure 300 into a specific manufacturing process. Method 200 may be performed on any number of semiconductor structures 300, and it should be understood that Figure 3A shows one exemplary structure on which a contact cleaning or etching process may be performed. As shown in Figure 3A, the treated semiconductor structure 300 may include a substrate 305 on which a silicon-containing material 310 is placed, with a patterned mask material 315 placed on itself. The substrate 305 may be or include a dielectric material such as an oxide or nitride of any number of materials. For example, the silicon-containing material 310 may be or include crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, silicon germanium, or any combination thereof.

[0037] Although the mask material 315 is illustrated as a single material layer, the mask material 315 may comprise one or more material layers. The mask material 315 may be a hard mask, a photoresist mask, or a combination thereof. For example, the mask material 315 may comprise a hard mask having a photoresist mask placed on it. Alternatively, the mask material 315 may comprise only a hard mask. A hard mask may consist of one or more layers of material (e.g., up to 10 layers). The individual layers of the hard mask may comprise materials such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, or any combination thereof. The mask material 315 may comprise a patterned photoresist layer, such as a lithographically patterned mask, or a patterned photoresist layer manufactured from other materials. The photoresist layer may be a positive photoresist, a negative photoresist, a UV lithography photoresist, an I-line photoresist, an electron beam resist (e.g., a chemically amplified resist (CAR)), or another suitable photoresist. The mask may be characterized by a thickness of approximately 2000 nm or less (e.g., 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm).

[0038] The mask material 315 can be patterned to form an opening 320 that penetrates the mask material 315, exposing a portion 325 of the underlying silicon-containing material 310. The opening 320 may be characterized by a critical dimension 330 (or width of the opening 320) of approximately 1000 nm or less (e.g., 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm). The structures of interest are not intended to be limiting, and it should be understood that a variety of other semiconductor structures are all similarly encompassed. While the method 200 of this disclosure may be applicable to small and large openings, advantageously, the method of this disclosure relates to openings having small critical dimensions 330 of about 50 nm or less (e.g., 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm). Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which silicon-containing material is removed.

[0039] Method 200 may include, in step 205, forming plasma emissions 335, 340, 345, and 350 of a plurality of precursors, including a silicon-fluorine-containing precursor, an etchant precursor, and an oxygen-containing precursor. For example, the silicon-fluorine-containing precursor may include silicon tetrafluoride (SiF4). For example, the etchant precursor may include one or more materials containing a chlorine-containing precursor, a bromine-containing precursor, or a fluorine-containing precursor. For example, the chlorine-containing precursor may include one or more materials containing diatomic chlorine (Cl2) or hydrogen chloride (HCl). For example, the bromine-containing precursor may include hydrogen bromide (HBr). For example, a fluorine-containing precursor may include one or more materials containing nitrogen trifluoride (NF3), hydrogen fluoride (HF), diatomic fluorine (F2), carbon tetrafluoride (CF4), trifluoromethane (CHF3), hexafluoroethane (C2F6), hexafluoropropylene (C3F6), bromine trifluoride (BrF3), chlorine trifluoride (ClF3), sulfur hexafluoride (SF6), additional fluorine-substituted hydrocarbons, or fluorine-containing materials. For example, an oxygen-containing precursor may include one or more materials containing oxygen (O2), carbon dioxide (CO2), carbon monoxide (CO), nitrous oxide (N2O), nitrogen dioxide (NO2), ozone (O3), or water (H2O).

[0040] The precursor may also contain any number of carrier gases, which may include useful precursors such as nitrogen, helium, argon, or other noble gases or inert gases. The carrier gas may be used to dilute the precursor, which may further reduce the etching rate and / or allow sufficient diffusion into the opening 320.

[0041] The plasma emitters 335, 340, 345, and 350 formed from the precursor may be formed locally within a processing area or within a remote plasma system. That is, the plasma emitters 335, 340, 345, and 350 may be generated within the processing area of ​​a semiconductor processing chamber housing the semiconductor structure 300. Alternatively, the plasma emitters 335, 340, 345, and 350 may be generated remotely and supplied to the processing area of ​​a semiconductor processing chamber housing the semiconductor structure 300. For example, the plasma treatment may be generated by a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP), with or without one or more carrier gases such as argon (Ar), helium (He), NH3, nitrogen (N2), H2, or mixtures thereof. The plasma emitters 335, 340, 345, and 350 may be low-level plasmas to limit the amount of impact, sputtering, and surface modification. In the embodiments, the plasma output is approximately 5,000 W or less, and may be approximately 4,500 W or less, approximately 4,000 W or less, approximately 3,500 W or less, approximately 3,000 W or less, approximately 2,500 W or less, approximately 2,000 W or less, approximately 1,500 W or less, approximately 1,000 W or less, approximately 750 W or less, approximately 500 W or less, or less, but the plasma output may also be within the range between any two of these stated values, or within any smaller range that falls within any of the stated ranges. By utilizing low levels of plasma output, the plasma emitters 335, 340, 345, 350 can be well controlled to be supplied through the openings 320 in the mask material 315, while limiting sputtering of the mask material 315 and other exposed surfaces.

[0042] Method 200 may include, in step 210, contacting the silicon-containing material 310 and the mask material 315 with plasma emitters 335, 340, 345, and 350 within the processing area of ​​a semiconductor processing chamber. As shown in Figure 3B, in step 215, contacting the silicon-containing material 310 with the plasma emitters 335, 340, 345, and 350 induces etching of the silicon-containing material 310, which may form and / or deepen features 355 within the silicon-containing material 310. Furthermore, in step 215, contacting the mask material 315 with the plasma emitters 335, 340, 345, and 350 may simultaneously induce etching of the mask material 315 and deposition of a silicon- and oxygen-containing material on the mask material 315.

[0043] Although not limited by theory, it is believed that plasma emitters 335 from silicon-fluorine-containing precursors (e.g., silicon tetrafluoride) and oxygen-containing plasma emitters 345 from oxygen-containing precursors can cause the deposition of silicon-oxygen-containing material on the mask material 315. Simultaneously, plasma emitters 350 from etchant precursors and / or silicon-fluorine-containing precursors can etch the mask material 315 and the silicon-containing material 350. Fluorine-containing plasma emitters 340 from etchant precursors and / or silicon-fluorine-containing precursors (e.g., silicon tetrafluoride) may preferentially contact the silicon-containing material due to their higher electronegativity compared to the other plasma emitters 335, 345, and 350 (in particular, oxygen-containing plasma emitters 345 from oxygen-containing precursors and silicon-containing plasma emitters 335 from silicon-fluorine-containing precursors). By preferentially contacting the silicon-containing material 310, the fluorine-containing plasma emitters 340 may reduce the formation of silicon- and oxygen-containing material on the silicon-containing material 310, particularly near the interface between the mask material 315 and the silicon-containing material 310, thereby reducing the width (or critical dimension) of the feature 355. The reduction in feature width reduces the access of the plasma emitters 350 from the etchant precursor to the feature 355, which will reduce the etching of the silicon-containing material 310 that deepens the feature 355. Thus, while the mask material 315 is simultaneously etched and replenished (through deposition), the silicon-containing material 310 may be etched, resulting in the selective removal of the silicon-containing material 310 relative to the mask material 315. Advantageously, the method 200 of this disclosure can minimize the change in the thickness of the mask material 315 while still forming deep features 355, which may allow for a thinner mask material 315 at the start of the method.

[0044] The illustrated method 200 and semiconductor structure 300 show the formation of feature 355 using plasma emitters 335, 340 from a silicon-fluorine-containing precursor; however, in alternative embodiments, feature 355 may already be formed (or initiated), and the plasma emitters 335, 340 from the silicon-fluorine-containing precursor may be used solely to deepen feature 355. For example, the method may include forming a first plasma emitter from a first precursor containing a first etchant precursor; contacting a mask material and a silicon-containing material with the first plasma emitter to cause etching of a silicon-containing material to form and deepen features (for example, by about 5 nm to 100 nm); then forming a second plasma emitter from a second precursor containing a silicon-fluorine precursor, an oxygen-containing precursor, and a second etchant precursor (which may be the same as or different from the first etchant precursor); and contacting the silicon-containing material and the mask material with the second plasma emitter to etch the silicon-containing material to deepen features, so that etching of the mask material and deposition on the mask material occur simultaneously as described herein.

[0045] The silicon-containing material 310 defines the side walls 360 and bottom 365 of the feature 355, and each of the openings 320 defines an opening 370 at the top of each feature 355 where the mask material 315 interfaces with the silicon-containing material 310. After the method 200 shown in Figure 3C is completed, the feature 355 may be characterized by a critical dimension 375 at the top opening 370 of the feature 355, a depth 380 from the opening 370 to the bottom 365 of the feature 355, an aspect ratio (depth 380 relative to critical dimension 375), or any combination thereof. After Method 200 is completed, feature 355 can be characterized by a critical dimension 375 of about 1000 nm or less, for example, 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm, preferably about 50 nm or less, for example, 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm. After Method 200 is completed, feature 355 can be characterized by a depth 380 of approximately 100 nm or more, for example, 100 nm to 50,000 nm, 100 nm to 1,000 nm, 500 nm to 5,000 nm, 1,000 nm to 10,000 nm, or 5,000 nm to 50,000 nm. After Method 200 is completed, Feature 355 can be characterized by an aspect ratio of approximately 5:1 or greater, for example, approximately 10:1 or greater, approximately 15:1 or greater, approximately 20:1 or greater, approximately 25:1 or greater, approximately 30:1 or greater, approximately 35:1 or greater, approximately 40:1 or greater, approximately 45:1 or greater, approximately 50:1 or greater, approximately 60:1 or greater, approximately 70:1 or greater, approximately 80:1 or greater, approximately 90:1 or greater, approximately 100:1 or greater, or 5:1 to 200:1, 5:1 to 50:1, 25:1 to 100:1, 50:1 to 200:1, or greater.

[0046] The mask material 315 before contact with the plasma emitter can be characterized by a thickness of approximately 2000 nm or less, for example, 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm. After steps 210 and 215, the mask material 315 can be characterized by a thickness of approximately 2000 nm or less, for example, 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm. Comparing the thickness of the mask material 315 before and after steps 210 and 215, the mask material 315 can be characterized by a thickness change of approximately 200 nm or less, for example, 0 nm to 10 nm, 0 nm to 20 nm, 1 nm to 50 nm, 25 nm to 100 nm, or 50 nm to 200 nm. The thickness of the mask material 315 after steps 210 and 215 may depend on various factors, including but not limited to the precursor gas ratio, applied RF power, and chamber pressure.

[0047] Method 200 may be characterized by the preferential (or selective) removal of the silicon-containing material 310 from the mask material 315. Selectivity is determined by the initial thickness (MT) of the mask material 315. S ) and the final thickness (MT) of the mask material 315 F It is defined as the depth of feature 355 divided by the difference between 355 and 380, and is shown by the following formula.

[0048] For example, in Figure 3A before etching, the mask material 315 may have a thickness of 100 nm, and in Figure 3C after etching, the mask material 315 may have a thickness of 60 nm, and the feature 355 may have a depth of 300 nm. Method 200 can be performed. In the above example, the selective removal of the silicon-containing material 310 from the mask material 315 is 300 nm / (100 nm - 60 nm) = 7.5. Method 200 can be characterized by its selectivity for removing silicon-containing material 310 from mask material 315, for example, about 6 or more, about 8 or more, about 10 or more, about 12 or more, about 14 or more, about 16 or more, about 18 or more, about 20 or more, about 22 or more, or more, or 4 to 30, 4 to 15, 10 to 20, or 15 to 30. The selectivity may depend on various factors, including but not limited to precursor gas ratio, RF power, chamber pressure, etc.

[0049] During step 205, the volume ratio of the oxygen-containing precursor to the silicon-fluorine-containing precursor may be approximately 50:1 or less, for example, 10:1 to 50:1, 10:1 to 30:1, 15:1 to 40:1, or 20:1 to 50:1. Although not limited by theory, it is thought that an increase in the flow of SiF4 relative to the flow of O2 (i.e., a decrease in the volume ratio of the oxygen-containing precursor to the silicon-fluorine-containing precursor) can lead to increased mask deposition, which in turn can result in increased clogging. However, there may be an inflection point in the O2:SiF4 volume ratio where there is not enough O2 to support the increased deposition, and the deposition rate of the mask material decreases.

[0050] During process 205, the volume ratio of the etchant precursor to the oxygen-containing precursor may be less than approximately 20:1, for example, 1:1 to 20:1, 1:1 to 15:1, or 5:1 to 20:1. Although not limited by theory, oxygen-containing precursors such as O2 act as both a precursor for mask material deposition (in conjunction with SiF4) and a precursor for passivation for the sidewalls 360 of feature 355. Reduced oxygen-containing precursors (i.e., higher volume ratios of etchant precursor to oxygen-containing precursor) are thought to result in reduced clogging, but may also result in increased feature width and warping. The appropriate volume ratio of the etchant precursor to the oxygen-containing precursor can depend heavily on the composition of the silicon-containing material 310. Therefore, clogging can be more effectively controlled or mitigated by the amount of silicon- and fluorine-containing precursor used (i.e., the volume ratio of oxygen-containing precursor to silicon- and fluorine-containing precursor, as opposed to the volume ratio of etchant precursor to oxygen-containing precursor).

[0051] During process 205, the volume ratio of the carrier gas (e.g., nitrogen, helium, argon) to the oxygen-containing precursor may be approximately 10:1 or less, e.g., 1:1–10:1, 1:1–5:1, 3:1–7:1, or 5:1–10:1. While not limited by theory, most inert carrier gases are thought to enhance plasma stability by minimizing their impact on overall processing performance, diluting the highly electronegative plasma, and reducing reflected power observed within the RF system. However, diatomic inert gases (e.g., N2) can significantly impact plasma chemistry by increasing the fluorine signal (observed by emission spectroscopy), resulting in reduced selectivity and increased mask damage.

[0052] During any step 205, 210, and / or 215 of Method 200, a bias power may be applied to the substrate 305. The bias power may provide a directed flow of plasma emitters toward the substrate 305. Thus, the etchant can be guided into the opening 320, thereby facilitating the plasma emitters to travel through the etched material and reach the substrate 305. In embodiments, the plasma power may be about 500W or more, about 750W or more, about 1,000W or more, about 1,500W or more, about 2,000W or more, about 2,500W or more, about 2,750W or more, about 3,000W or more, about 3,250W or more, about 3,500W or more, about 4,000W or more, about 4,500W or more, about 5,000W or more, or more, but the bias power may also be within the range between any two of these stated values, or within any smaller range that falls within either of the stated ranges. By applying bias power, a narrow ion incidence angle distribution can be obtained, which can provide better etching profile control (e.g., no bending and / or twisting) and perpendicularity. A narrow ion incidence angle distribution can reduce sidewall attack, increase etching rate, and potentially bring the etching tip closer to a right angle.

[0053] In embodiments, bias power may be applied via an RF power supply, such as RF power supply 125, and / or a power supply, such as power supply 150, used to direct a DC current or voltage to the ESC. As previously mentioned with respect to Figure 1, the RF power supply and / or power supply used to direct the DC current or voltage may be switched on and off repeatedly or pulsed during processing. Pulsing allows for better control of ion energy and ion flux, enabling diffusion of plasma emitters at a lower angle. Furthermore, pulsed supply may neutralize the charge of plasma emitters at the etching tip, improving etching uniformity. In embodiments where bias power is applied by both the RF power supply and the power supply used to direct the DC current or voltage to the ESC, the power supplies may be synchronous or unsynchronous. The DC current or voltage may be pulsed on a microsecond scale and may be characterized by a duty cycle between 0% and 100%. In some embodiments, additional electrodes may be present in the ESC for the pulsed DC current or voltage, while in other embodiments, the same electrodes may be used for both chucking and pulsed supply. In some embodiments, RF and pulsed DC may be supplied only to the cooling base 129, while a separate DC chuck power supply 150 may be connected to the chuck electrodes (mesh) in the ceramic ESC.

[0054] Each step of Method 200 can be performed at a constant temperature in some embodiments, while in some embodiments the temperature can be adjusted between different steps. For example, during Method 300, the temperature of the substrate, pedestal, or chamber may be maintained at a temperature of about 100°C or less, about 80°C or less, about 60°C or less, about 40°C or less, about 20°C or less, or about 0°C or less, and in some embodiments the temperature may be maintained at a temperature of about -20°C or less, about -40°C or less, about -50°C or less, about -60°C or less, about -70°C or less, about -80°C or less, about -90°C or less, about -100°C or less, about -110°C or less, about -120°C or less, or below, although the temperature may also be within a range between any two of these stated values, or within any smaller range that falls within either of the stated ranges.

[0055] The pressure inside the processing chamber can be controlled during method 300. For example, while forming a plasma emitter and bringing the material into contact with the plasma emitter, the pressure inside the semiconductor processing chamber can be maintained at or below approximately 5 Torr. Furthermore, in the embodiments, the pressure inside the semiconductor processing chamber may be maintained at a pressure of approximately 4 Torr or less, approximately 3 Torr, approximately 2 Torr or less, approximately 1 Torr or less, approximately 500 mTorr or less, approximately 250 mTorr or less, approximately 200 mTorr or less, approximately 150 mTorr or less, approximately 100 mTorr or less, approximately 80 mTorr or less, approximately 60 mTorr or less, approximately 50 mTorr or less, approximately 45 mTorr or less, approximately 40 mTorr or less, approximately 35 mTorr or less, approximately 30 mTorr or less, approximately 25 mTorr or less, approximately 20 mTorr or less, approximately 15 mTorr or less, approximately 10 mTorr or less, or below, although the pressure may also be within a range between any two of these stated values, or within any smaller range that falls within either of the stated ranges. The pressure inside the processing chamber may affect the ability of flow into the opening. For example, as the pressure increases, it may become more difficult for the plasma emitters to pass through the opening 320 and reach the silicon-containing material 310. Therefore, in some embodiments, the pressure may be maintained at about 1 Torr or less to allow the flow of emitters into the opening 320 and to etch the feature 355 within the silicon-containing material 310 on the substrate 305.

[0056] In the preceding description, numerous details were included for explanatory purposes to facilitate understanding of the various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details. While several embodiments have been disclosed, those skilled in the art will understand that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the descriptions in the preceding specification should not be considered to limit the scope of this technology. In addition, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that listed.

[0057] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. Any narrow range between the listed values ​​or unlisted intervening values ​​within the listed range and other listed or intervening values ​​within the listed range is included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each of these narrower ranges, whether containing one, neither, or both of the limit values, is also included in the Art, provided that there are limit values ​​specifically excluded within the listed range. If one or both of the limits are included in the listed range, the range excluding one or both of the included limits is also included.

[0058] In this specification and the appended claims, the singular forms “a,” “an,” and “the” include multiple references unless otherwise specified in the context. Thus, for example, “a precursor” refers to multiple such precursors, and “the layer” refers to one or more layers and equivalents well known to those skilled in the art, and the same applies to other forms.

[0059] Furthermore, the words “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or processes, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, i) Forming a plasma emission of multiple precursors, comprising an etchant precursor, an oxygen-containing precursor, and a precursor containing silicon and fluorine, wherein the precursor containing silicon and fluorine contains silicon tetrafluoride. ii) Contacting a silicon-containing material and a mask material with a plasma emitter within a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed on a substrate support within the processing area, the silicon-containing material is placed on the substrate, the mask material is placed on the silicon-containing material, the mask material has one or more openings inside that allow the plasma emitter to access the silicon-containing material, and the mask material includes a dielectric material, iii) Etching the silicon-containing material using the plasma emission material to form and / or deepen one or more features in the silicon-containing material, and iv) Simultaneously etching the mask material and depositing a material containing silicon and oxygen onto the mask material using the plasma emission material. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the etchant precursor comprises one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor other than silicon tetrafluoride.

3. The semiconductor processing method according to claim 1, wherein the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor is about 50:1 or less.

4. The semiconductor processing method according to claim 1, wherein the volume ratio of the etchant precursor to the oxygen-containing precursor is about 20:1 or less.

5. The semiconductor processing method according to claim 1, wherein a carrier gas is present when forming plasma ejecta.

6. The semiconductor processing method according to claim 5, wherein the volume ratio of the carrier gas to the oxygen-containing precursor is about 10:1 or less.

7. The semiconductor processing method according to claim 1, wherein the silicon-containing material comprises one or more of crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, and silicon germanium.

8. The semiconductor processing method according to claim 1, wherein the method selectively removes the silicon-containing material from the mask material.

9. The semiconductor processing method according to claim 1, wherein the method removes the silicon-containing material from the mask material with a selectivity of about 4 or more.

10. The semiconductor processing method according to claim 1, wherein one or more openings are characterized by a critical dimension of approximately 1000 nm or less.

11. The semiconductor processing method according to claim 1, wherein, after etching the silicon-containing material, one or more features are characterized by a depth of approximately 100 nm or more.

12. The semiconductor processing method according to claim 1, wherein, after etching the silicon-containing material, one or more features are characterized by an aspect ratio of about 5:1 or greater.

13. The semiconductor processing method according to claim 1, wherein the pressure within the processing area is maintained at approximately 5 Torr or less.

14. The semiconductor processing method according to claim 1, wherein the temperature within the processing area is maintained at approximately 100°C or less.

15. The semiconductor processing method according to claim 1, wherein the plasma emission is generated with a plasma output of approximately 5000 W or less.

16. A semiconductor processing method, i) Forming a plasma emission of multiple precursors in the presence of a carrier gas, wherein the multiple precursors include an etchant precursor, an oxygen-containing precursor, and a silicon-fluorine-containing precursor, the silicon-fluorine-containing precursor includes silicon tetrafluoride, the volume ratio of the oxygen-containing precursor to the silicon-fluorine-containing precursor is approximately 50:1 or less, the volume ratio of the etchant precursor to the oxygen-containing precursor is approximately 20:1 or less, and the volume ratio of the carrier gas to the oxygen-containing precursor is approximately 10:1 or less, ii) Contacting a silicon-containing material and a mask material with a plasma emitter within a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed on a substrate support within the processing area, the silicon-containing material is placed on the substrate, and the mask material is placed on the silicon-containing material, the mask material has one or more openings inside that allow the plasma emitter to access the silicon-containing material, and the mask material includes a dielectric material, iii) Etching the silicon-containing material using the plasma emitter to form and / or deepen one or more features within the silicon-containing material, wherein the silicon-containing material defines the side walls and bottom of the one or more features along the substrate, and each of the one or more openings defines an opening at the top of each of the one or more features, and iv) The process includes simultaneously etching the mask material and depositing a material containing silicon and oxygen onto the mask material using the plasma emitter, The above method is a semiconductor processing method for selectively removing the silicon-containing material from the mask material.

17. The semiconductor processing method according to claim 16, wherein the method removes the silicon-containing material from the mask material with a selectivity of about 4 or more.

18. A semiconductor processing method, i) Forming a plasma emission of an etchant precursor, an oxygen-containing precursor, and a plurality of precursors including silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to the silicon tetrafluoride is approximately 50:1 or less. ii) Contacting a silicon-containing material and a mask material with a plasma emitter within a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed on a substrate support within the processing area, the silicon-containing material is placed on the substrate, and the mask material is placed on the silicon-containing material, the mask material having one or more openings inside that allow the plasma emitter to access the silicon-containing material, and the mask material includes a dielectric material, iii) Etching the silicon-containing material using the plasma emitter to deepen one or more features within the silicon-containing material, wherein the silicon-containing material defines the side walls and bottoms of the one or more features along the substrate, and each of the one or more openings defines an opening at the top of each of the one or more features, and iv) The process includes simultaneously etching the mask material and depositing a material containing silicon and oxygen onto the mask material using the plasma emitter, The above method selectively removes the silicon-containing material from the mask material. Semiconductor processing method.

19. The plasma emitter is a first plasma emitter of a first plurality of precursors, and the method is Forming a second plasma emission from a second plurality of precursors that do not contain silicon tetrafluoride, and Etching the silicon-containing material using the second plasma emission material to form and / or deepen one or more features in the silicon-containing material, The semiconductor processing method according to claim 18, further comprising:

20. The semiconductor processing method according to claim 18, wherein the method removes the silicon-containing material from the mask material with a selectivity of about 4 or more.

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