Crossbar semiconductor device for processing

Abstract

A processing crossbar semiconductor device is disclosed for processing an input vector with a weight tensor and deriving an output vector as a processed version of the weight tensor, wherein the weight tensor has multiple weights, and the crossbar processing device is configured to process each input electrical value in an array of input electrical values ​​representing the input vector, and the processing crossbar semiconductor device A set of weighted elements (101) arranged according to element rows and element columns, where each weighted element corresponds to a weight of a weight tensor, the set of weighted elements is divided into multiple blocks (102), the multiple blocks (102) are arranged according to super columns (108) and super rows (106) such that each super row contains multiple immediately following element rows, and each super column contains multiple immediately following element rows, and A plurality of block output buses, each connected to a plurality of blocks within each superrow, without being connected to a block and without being associated with other superrows, and each of the plurality of block output buses, each containing a plurality of block output lines, wherein each block, when activated, is configured to weight the input electrical values ​​of an array of input electrical values ​​by the corresponding weights of a weight tensor, thereby providing electrically weighted values ​​to the block output buses associated with the superrows of which the block is part, The system comprises a plurality of analog storage elements, each electrically connected to a block output line, thereby providing their respective electrically stored weighted values ​​from the electrically weighted values ​​obtained from the corresponding element sequences of multiple activated blocks in a super row associated with the block output line, thereby deriving an array of stored weighted output values ​​that form an output vector.

Description

[Technical Field]

[0001] This embodiment relates, for example, to a processing crossbar semiconductor device for vector-matrix multiplication (VMM) using analog-in-memory computing. These examples further relate to performing deep neural network processing. [Background technology]

[0002] Analog-in-memory computing using a crossbar architecture is known as VMM computation. The multiplication portion of these VMM operations can be computed by applying an input activation voltage from the input matrix to a synaptic circuit that yields a proportional current or charge, either analogously using a digital-to-analog converter (DAC) or digitally, for example, a selection bit, where the proportionality constant is obtained from the weight matrix. The accumulation portion of the VMM computation essentially arises from the integration of the charge or current into a common node, i.e., a column in the crossbar. The integrated charge or current from the column is further converted to the digital domain by employing an analog-to-digital converter (ADC). [Overview of the project] [Problems that the invention aims to solve]

[0003] Existing solutions known to the authors [1], [2], [3] employ a fixed number of synapses per crossbar column. This limits the constructibility of weight vectors associated with neurons, resulting in underutilization of crossbars due to unused synapses. The limitation of constructibility can also complicate mapping scenarios. These drawbacks can become significant as the columns lengthen, which can range from 128 used in [4] to 2304 in [5]. [Means for solving the problem]

[0004] This embodiment provides solutions to these problems, for example, by employing a configurable and scalable crossbar architecture and by using other relevant building block circuits, such as digitally configurable current source-based synaptic cells, analog-to-digital converters (ADCs), and shift-adder circuits incorporating offset and gain support.

[0005] Before delving into the details of this embodiment, we will provide some information on how vector-matrix multiplication (VMM), as found in conventional in-memory computing architectures, can be computed (e.g., in neural networks). Figure 1 shows a fully connected layer of a neural network with n-dimensional inputs N and m-dimensional output neurons M. This is converted into a VMM given by the following matrix representation. TIFF2026529717000002.tif1960(1)

[0006] Note that the neurons in Figure 1 may have associated nonlinear activation functions, which are applied to the inner product result calculated using the above formula. Figure 2 depicts a typical crossbar array using conventional techniques for in-memory computing, showing R rows and C columns, where each element represents a synaptic weight W (subscripts are not shown in Figure 2, (Use W instead of TIFF2026529717000003.tif1325, etc.) The input activation lines and storage lines typically connect all rows and columns of the crossbar, respectively. To compute the M outputs of the fully connected layer, inputs from the input matrix are applied to these activation lines, either analogously as voltages or digitally as selection bits. The weights from the weight matrix are mapped to the crossbar weight elements in the form of resistance or capacitance. As a result, the storage lines generate a current or charge equal to the neuron pre-activation value. The activation function following the storage result is not shown in Figure 2. The bit lines and word lines shown in Figure 2 are used to constitute the weights in the crossbar. Depending on whether the input matrix N and output matrix M in equation (2) are longer or shorter than the R rows and C columns of the crossbar, respectively, the crossbar can partially or completely map the fully connected layer in Figure 1. Since the input lines and storage lines physically connect entire rows or columns, regardless of size, the crossbar has unused weights in its rows and columns. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example of a fully connected layer that this embodiment can address. [Figure 2] This figure shows an example of a crossbar using conventional technology. [Figure 3] This figure shows an example of what is disclosed herein. [Figure 4] This diagram shows the operation of the example in Figure 2. [Figure 5] This figure shows the characteristics of the arbitrary selection of possible components in the example shown in Figure 3. [Figure 6] This figure shows the characteristics of the arbitrary selection of possible components in the example shown in Figure 3. [Figure 7] This figure shows the characteristics of the arbitrary selection of possible components in the example shown in Figure 3. [Figure 8] This figure shows the characteristics of the arbitrary selection of possible components in the example shown in Figure 3. [Modes for carrying out the invention]

[0008] According to one embodiment, a processing crossbar semiconductor device is provided for processing at least one input vector by at least one weight tensor in order to derive at least one output vector as a result of processing at least one input vector, wherein the at least one weight tensor has a plurality of weights, and the crossbar processing device is a plurality of input lines including a plurality of single input lines, each single input line configured to process each input electrical value of an array of input electrical values ​​representing at least one input vector, and the processing crossbar semiconductor device comprises the following, namely, A set of weighted elements arranged according to element sequences and element rows, wherein each weighted element corresponds to the weights of at least one weight tensor, and the set of weighted elements is divided into multiple blocks, the multiple blocks being arranged according to super sequences and super rows such that each super row contains multiple immediately following element rows, and each super sequence contains multiple immediately following element sequences. Multiple block output buses, each block output bus connected to multiple blocks of each superrow, without being connected to a block associated with at least one other superrow, each block output bus containing multiple block output lines, each block of the multiple blocks, when activated, is configured to weight the input electrical values ​​of an array of input electrical values ​​by corresponding weights of at least one weight tensor, providing electrically weighted values ​​to the block output buses associated with the superrows of which the blocks are part, The present invention comprises a plurality of analog storage elements, each electrically connected to at least one block output line, thereby providing each electrically stored weighted value from electrically weighted values ​​obtained from corresponding element rows of multiple activated blocks in at least one super row associated with at least one block output line, to derive an array of stored weighted output values ​​that form at least one output vector.

[0009] A processing crossbar semiconductor device may be configured such that each block in a super row simultaneously activates multiple weighting elements, thereby providing each block output line with an electrically weighted value simultaneously via the weighting elements, and as a result, each analog storage element that receives an electrically weighted value from the same block output line simultaneously has a storage value.

[0010] A processing crossbar semiconductor device may be configured such that each weighting element supplies an analog current obtained by weighting the input electrical value, thereby allowing each storage element to supply at least one of the stored weighted currents as an electrically stored weighted value.

[0011] A processing crossbar semiconductor device may be configured such that each weighting element provides an analogously obtained charge and / or voltage by weighting an input electrical value, thereby allowing each storage element to provide a stored weighted charge and / or stored weighted voltage as an electrically stored weighted value.

[0012] A processing crossbar semiconductor device may be configured such that at least one electrical input value encodes a binary value, so that a first electrical level of at least one electrical input value corresponds to a first logical level of the binary value, a second electrical level of at least one electrical input value corresponds to a second logical level of the binary value, and each of the associated weighting elements is configured to process the electrical input value according to a weight selected from three or more weight values.

[0013] The processing crossbar semiconductor device may be configured such that at least one of the weighting elements is configured to select either a first current generator providing a first current or a second current generator providing a second current, and the weighting element is configured to independently and selectively route each of the first and second currents to a conductor selected from a first conductor and a second conductor of each block output line, so that each block output line carries one of a plurality of selectable levels of weighted output value.

[0014] A processing crossbar semiconductor device may be configured such that at least one of the associated weighting elements selects either at least one positive polarity that generates a positive weight and one negative polarity that generates a negative weight, by, for a positive electrically weighted value, giving the positive conductor or electrode of the analog storage element a greater electrical level than the negative conductor or electrode of the analog storage element, and for a positive electrically weighted value, giving the negative conductor or electrode a greater electrical level than the positive conductor or electrode.

[0015] A processing crossbar semiconductor device may be such that multiple analog storage elements are grouped into an analog storage element bus, each analog storage element bus is connected and associated with at least one block output bus, and each analog storage element in each analog storage element bus is connected to at least one block output line of the associated at least one block output line, thereby accumulating weighted electrical values ​​from the same element row of at least one super row block associated with the associated at least one block output bus.

[0016] A processing crossbar semiconductor device may have at least one analog storage element bus connected in association with at least one first block output bus connected in association with a first super row, and at least one second block output bus connected in association with a second super row, such that each analog storage element on the analog storage element bus provides an electrically stored weighted value stored from electrically weighted values ​​from both the first block of the first super row and the second block of the second super row.

[0017] According to one embodiment, the processing crossbar semiconductor device further comprises at least one analog-to-digital converter (ADC) for converting at least two electrically stored weighted values ​​from at least two analog storage elements, respectively.

[0018] The processing crossbar semiconductor device can convert at least one electrically stored weighted value into a single bit, depending on the electrical level of the electrically stored weighted value.

[0019] A processing crossbar semiconductor device may be configured to convert at least one electrically stored weighted value into multiple bits, depending on the electrical level of the electrically stored weighted value, i.e., the weight level.

[0020] A processing crossbar semiconductor device may be configured to convert multiple storage-weighted values ​​from different storage elements into a superstring of bits by converting at least one first electrically storage-weighted value into at least one least significant bit or least significant string, and at least one second electrically storage-weighted value into at least one most significant bit or most significant string.

[0021] The processing crossbar semiconductor device may further include at least one digital storage element for storing different storage-weighted values ​​at the point when they are converted digitally from different analog storage elements or different analog storage element buses.

[0022] The processing crossbar semiconductor device includes a first block of a first super row associated with a first block output bus, which includes a selectable multiple connection with a second block of a second super row, the second super row being connected to and associated with the second block output bus, but not to and not to the first block output bus, the first block output bus being associated with a first analog storage element bus including a plurality of first analog storage elements, the second block output bus being connected to a second analog storage element bus including a plurality of second analog storage elements, there being no first analog storage elements connected to the second analog storage elements, and the selectable multiple connection connects the first block to the output bus in such a way that, when selected, weighted electrical values ​​from the first block are provided to the second block output bus and the second analog storage element bus.

[0023] The processing crossbar semiconductor device may be such that multiple blocks of at least one super row are electrically connected in pairs via multiple selectable multiple connections, in such a way that weighted values ​​obtained in the first block of the first super row are selectively provided to a second block output bus that is not electrically connected to the first block output bus to which the first super row is connected.

[0024] The processing crossbar semiconductor device may be configured to evaluate whether the input vector has more elements than the element rows of the first block of the first super row, and if the input vector has more elements than the number of element rows in each first block of the first super row, distribute the electrical input value between the element rows of the first block of the first super row and the element rows of the second block of at least one second super row, and selectively provide an electrically weighted value from each of the first blocks of the first super row to at least one of the further blocks of the second super row, so that the second blocks provide both the weighted value from the first block and the weighted value from the further blocks to the same block output bus to which they are associated.

[0025] A processing crossbar semiconductor device may include a plurality of blocks comprising a first submultiplexity block and a second submultiplexity block separated from the first submultiplexity block, and a plurality of block output buses comprising a first submultiplexity block output bus uniquely connected to the blocks of the first submultiplexity block and a second submultiplexity block output bus uniquely connected to the blocks of the second submultiplexity block, wherein the second submultiplexity block is selectively activatable and deactivatable.

[0026] The processing crossbar semiconductor device may be such that the plurality of analog storage elements include at least a first submultiplex analog storage element that stores electrically weighted values ​​from a first submultiplex block, and a second submultiplex analog storage element that stores electrically weighted values ​​from a second submultiplex block, and the processing crossbar semiconductor device may further include a plurality of further storage elements, each of which may be configured to store a weighted electrical value that stores both a first weighted electrical value from a first analog storage element in the first submultiplex block and a second weighted electrical value from a second analog storage element in the second submultiplex block.

[0027] A processing crossbar semiconductor device could be one in which the additional storage element is a digital storage element.

[0028] The processing crossbar semiconductor device may be configured to evaluate whether the acquired output vector has more elements than the number of elements in the element rows of the first submultiplexity block, and if the output vector has more elements than the number of elements in the element rows of the first submultiplexity block, activate the super-row blocks of the second submultiplexity block, thereby ensuring that the number of rows in the activated super-row blocks matches at least the number of elements in the output vector.

[0029] A processing crossbar semiconductor device may be one in which a second sub-multiplexity block can be selectively activated and deactivated.

[0030] A processing crossbar semiconductor device may be such that each analog storage element is a resistor that receives weighted electrical values ​​from weighted elements in the same element row in multiple blocks of at least one super row, and as a result each electrically stored weighted value is the sum of the weighted electrical values.

[0031] A processing crossbar semiconductor device may be one in which the weighted electrical value is the current, and the electrically stored weighted value is the current which is the sum of the currents from the block output lines.

[0032] A processing crossbar semiconductor device may be such that each analog storage element is a capacitor that receives weighted electrical values ​​from weighted elements in the same element row in multiple blocks of at least one super row, and as a result, each electrical storage weighted value is the sum of weighted electrical values, which are either charge or voltage.

[0033] Processing crossbar semiconductor devices can be configured to activate different blocks independently of each other.

[0034] A processing crossbar semiconductor device may be configured to simultaneously activate multiple blocks of the same superrow in such a way that it provides electrically weighted values ​​by having weighting elements connected to the same block output line provide electrically weighted values ​​to the same block output line.

[0035] In one embodiment, the processing crossbar semiconductor device may be configured to receive an array of electrical values ​​as at least a first input vector and a second input vector independent of the first input vector, wherein the first input vector is input to a first superrow of the block, and the second input vector is simultaneously provided to a second superrow of the block.

[0036] A processing crossbar semiconductor device may be configured such that the weighting elements of each block provide their respective electrical weighted values ​​in parallel to the output lines of each block, thereby pre-accumulating electrical weighted values ​​on the same output lines.

[0037] The crossbar processing device may be configured to implement a neural network that follows multiple layers, including an input layer, an output layer, and optionally at least one hidden layer, where each transition from one layer to the next is performed by processing an analog input vector, where each weight of at least one weight tensor represents a synapse, each analog input value is a neuron, and each output value is a neuron in the next layer.

[0038] A processing crossbar semiconductor device may be one in which the analog input vector is a kernel or part of a kernel that is convolved and applied to at least one weight tensor.

[0039] A processing crossbar semiconductor device may be configured to perform an inference phase in which, after a first phase in which the weights of at least one weight tensor are obtained by minimizing a cost function that provides an error metric on a known dataset, the weights of the weight tensor are established and predictions are provided in response to input values.

[0040] According to one embodiment, a method is provided for deriving at least one input vector from at least one weight tensor and deriving at least one output vector as a result of processing at least one input vector (for example, using one of the above or below devices), wherein at least one weight tensor has a plurality of weights, the method comprises the step of processing each input electrical value in an array of input electrical values ​​representing at least one input vector, the method uses weighting elements arranged according to element rows and element columns, each weighting element corresponds to a weight of at least one weight tensor, the set of weighting elements is divided into a plurality of blocks, the plurality of blocks are arranged according to super columns and super rows such that each super row contains a plurality of immediately following element rows, and each super column contains a plurality of immediately following element rows, the method further uses a plurality of block outputs, each block output bus is connected in association with a plurality of blocks in its respective super row and not connected to blocks connected in association with at least one other super row, each block output bus contains a plurality of block output lines, the method, The steps include: activating the weighting of input electrical values ​​in an array of input electrical values ​​by corresponding weights of at least one weight tensor in order to provide electrically weighted values ​​to a block output bus associated with a super row of which a block is part; The steps include providing each electrically weighted storage value from an electrically weighted value obtained from a corresponding array of elements in a plurality of activated blocks in at least one super row associated with at least one block output line, via a plurality of analog storage elements, each of which is electrically connected to at least one block output line; The process includes the step of deriving an array of accumulated weighted output values ​​that form at least one output vector.

[0041] According to one embodiment, a non-temporary storage unit is provided that, when executed by a processor, stores instructions that cause the processor to perform the above method.

[0042] According to one embodiment, the crossbar processing device further comprises a controller for activating at least one of at least one block, at least one super row, at least one super column, at least one element row, at least one bypass connection, at least one partial multiplexing, and / or associating weights to their respective weight elements, input electrical values ​​to element rows, and / or output electrical values ​​to element columns of at least one block. [Examples]

[0043] This embodiment solves or at least mitigates the above-mentioned problems by a field-configurable crossbar array architecture, see Figure 3, which has the architectural and circuit features described below.

[0044] Before further describing this embodiment, it should be noted that the scope of this embodiment is not limited to the specific parameter dimensions used to illustrate this embodiment in Figure 3, such as the number of element rows and the number of element columns, but includes all other possible dimensions.

[0045] Figure 3 shows an example of a processing crossbar semiconductor device 100 according to this embodiment. The processing crossbar semiconductor device can perform multiplication in the analog domain between matrices and vectors. Nevertheless, it should be noted that the concept of matrices can be generalized to tensors, that is, they have several general dimensions (e.g., 3 dimensions). For example, a tensor is a matrix in equation (1) It could be TIFF2026529717000004.tif2542, but there could be multiple channels representing another matrix of the third dimension, for example the first channel is It could be TIFF2026529717000005.tif2546, and the second channel is It could be TIFF2026529717000006.tif2546, and the p-th channel is It may be TIFF2026529717000007.tif2546. Therefore, a processing crossbar semiconductor device can process at least one input vector, which may be analog or digital, but generally in the form of an array of electrical values ​​with multiple weights of a weight tensor, thereby generating an output vector (in either digital or analog form). For example, given 16 input electrical values ​​(example in Figure 3), it is possible to form an array of input electrical values, which also represents the input vector.

[0046] The input vector may be analog or digital (if digital, it may be converted to an analog value that encodes the digital value). Therefore, the electrical value representing the input vector may, in principle, be either a digital value that can only be sequence-encoded into two logical states (e.g., a first logical state represented by a first electrical level and a second logical state represented by a second electrical value different from the first electrical value) or a string of logical states, or an analog value (e.g., ideally defined by intervals of continuous analog values). The input value may be provided in either digital or analog form, in the form of voltage, charge, current, etc. The processed value (e.g., weighted value, accumulated weighted value, etc.) may be an analog value (e.g., at least one of voltage, charge, current, etc.) when converted from the digital domain. The output element (e.g., an element of the output vector) may be either an analog value (e.g., at least one of voltage, charge, current, etc.) or a digital value (e.g., the value after the processed value has been converted from an analog value to a digital value). Here, weighting is performed in the analog domain, but storage is performed in the analog domain (e.g., by summing several weighted electrical values ​​from multiple weights within each storage element), or, in some examples, includes a first analog step (e.g., summing several weighted electrical values ​​from multiple weights is performed in several different analog storage elements), followed by a second step in which the analog storage weighted values ​​are converted to digital versions of the storage weighted values, and then the digital versions of the storage weighted values ​​provided by the different analog storage elements are added together by their digital versions. Thus, in some examples, the input and output values ​​are digital, but their processing is performed in the analog domain, thereby saving power and increasing processing speed.

[0047] Therefore, the input vector is processed (e.g., multiplied, weighted, scaled) by a weight tensor with weights defined by different dimensions (in the case of a matrix, the dimension becomes 2 and the weight tensor is a weight matrix; in the case of a 3-dimensional tensor, the dimension becomes 3 and the weight tensor is a 3-dimensional tensor). In Figure 3, each of the small rectangles 101 represents a weighting element corresponding to the weight applied to the input electrical value while the input vector is a kernel such as K0_0(301), K0_1(302), K1_0(303), K1_1(304), or part thereof. Thus, at the point depicted in Figure 3, the input vector is multiplied by the weights at positions 301, 302, 303, and 304.

[0048] As seen in Figure 3, matrix elements (tensor elements) are organized in a matrix-style arrangement with a matrix arrangement along multiple element columns (identified as vertical in the figure) and multiple element rows (illustrated horizontally in the figure). Each element row is associated with a specific input electrical value (e.g., all weighting elements in a particular element row are applied to the same electrical input value) (e.g., the input may be a digital value, and this digital value may be converted to an analog value by, for example, weighting element 101 or upstream of weighting element 101) (e.g., it is input and / or processed by it), while each element column (e.g., multiple blocks of the same supercolumn) may be associated with a single specific output value (e.g., an analog value) (e.g., it may provide, it may output). However, to increase configurability, it will be understood that it is possible to selectively use multiple element columns (e.g., corresponding element columns in multiple blocks, where the multiple blocks are in the same supercolumn rather than different supercolumns, see below) for the same output value, or to selectively use different element columns for different inputs. Furthermore, it is possible to selectively use multiple element sequences for the same electrical input value (for example, corresponding element rows within different blocks, where different blocks are in the same super-sequence but belong to different super-rows, see below), or to selectively use them for different electrical input values. Figure 6 shows an example of weighting elements for weighting electrical input vectors controlled by digital inputs d_in, d_in0, d_in1, and d_in2 (in this case, the supply voltage V dd (Controls the supply of). As shown in Figure 6, each weighting element (also called CS_AWE, see below) has a relative block output line (OL-A0, OL-A1, OL-A2, ..., OL-A 31The block has a conventionally positive terminal vout_p and a conventionally negative terminal vout_n that constitute a connection port to (see below). In particular, vout_p may be conventionally connected to the positive terminal of the block output line, and vout_n may be conventionally connected to the negative terminal of the block output line. As shown in Figure 6, by selecting at least one of the deviations (e.g., branches), one single generator (e.g., current generator) from the first and second generators, and a polarity selection (e.g., by selectively exchanging the highest electrical values ​​between vout_p and vout_n), it becomes possible to select one of several (especially more than two) weights of the weighting element, thereby favorably handling the weighting of binary values ​​according to the subbinary resolution. Note that all weighting elements 101 in a row of elements in the block provide electrically weighted values ​​to the same block output line simultaneously and in parallel, and as a result, the block output line may function as a pre-accumulation output line that pre-accumulates multiple weighted values ​​of the same row of elements in the same block.

[0049] Figure 3 shows OL-A here. 0-3 , OL-A 4-7 , OL-A 8-11 ,...,OL-A 28-31 This shows multiple block output buses. Each block output bus (which may be understood as multiple output lines, or a group of parallel lines) may contain multiple single output lines that are not electrically connected to each other (for example, connected in parallel to each other for each block output bus), and are here referred to as block output lines (each block output line may have only one single voltage value at a given time, whereas a block output bus may represent an array of multiple voltage values ​​at a given time). Block Output Bus OL-A 0-3 This is shown to include four output lines OL-A0, OL-A1, OL-A2, OL-A3 (different numbers are also possible). Block output lines OL-A0, OL-A1, OL-A2, ..., OL-A 31Each of may be a dual channel (e.g., having only one first positive conductor connected to vout_p and one negative conductor connected to vout_n), but different implementations are possible (e.g., each single output line may have only a single conductor, and a common analog ground may be used instead of the second conductor. However, it is understood that it is advantageous to use two different conductors instead of a common analog ground, mainly because the use of a common ground may cause process-dependent errors such as those resulting from PVT variations, and may also add asymmetric electrical parasitics capacitance / resistance. Furthermore, when there is no even common analog ground, it is possible to define polarity and provide a sign to a weight, thereby enabling a negative weight to be defined). Examples of a conductor (conventionally selected as a positive conductor) and a conductor (conventionally selected as a negative conductor) are not shown, but FIG. 6 shows a positive terminal vout_p and a negative terminal vout_n of a weighting element, which are respectively connected to the conductor conventionally selected as a positive conductor and the conductor conventionally selected as a negative conductor. It is shown that each output bus is connected and associated to one particular group of weighting elements (or more specifically, a block of weighting elements in the same super row, see below), but is not connected and associated to other groups of weighting elements (or more specifically, a block of weighting elements in different super rows, see below). Similarly, block output buses OL-A0, OL-A1, OL-A2, ..., OL-A 31 each of which means that each receives an analog weighted value only from some parts of an element array (i.e., each block output line receives a weighted value from a corresponding weighting element displaced to an element array of a block in the same super row), and does not mean receiving the weighted value from all weighting elements of any global element array. Generally speaking, each of the block output lines OL-A0, OL-A1, OL-A2, OL-A3 belongs to the same block output bus OL-A 0-3 is electrically isolated from any of the other block output lines OL-A0, OL-A1, OL-A2, OL-A3.

[0050] Each block output bus OL-A 0-3 , OL-A 4-7 , OL-A 8-11 ,...,OL-A 28-31 Generally, it is electrically isolated from other block output buses, or at least some of them (e.g., most of them), or similarly, from the general block output bus OL-A 0-3 Each of the block output lines OL-A0, OL-A1, OL-A2, and OL-A3 is electrically isolated from the block output line buses of other block output buses, or at least from some of the block output line buses of other block output buses (e.g., most of the block output line buses of other block output buses). For example, block output bus OL-A 0-3 Generally, OL-A 4-7 Furthermore, OL-A 8-11 , OL-A 12-15 , OL-A 20-23 , OL-A 24-27 , OL-A 28-31 It is electrically isolated (i.e., from most of the other block output buses). Block output bus OL-A 16-19 Even though it is not directly connected to the block output bus OL-A 0-3 However, that weighted electrical value is the same as that of an analog storage element (AL 0-3 ) provides to and similarly to OL-A 16-19 There is also the option of providing that weighted electrical value (in the same example, OL-A 4-7 and OL-A 20-23 Although they are not directly connected to each other, the same analog storage element AL 4-7 It may be connected to OL-A 8-11 and OL-A 24-27 The same weighted values ​​are used in the analog storage element AL 8-11It is possible to provide this to, etc. However, apart from this, each block output bus may be electrically isolated from most of the other block output buses, in particular from the nearest block output bus. Thus, different block output buses may be associated (e.g., connected) with the same analog storage bus, but not directly electrically connected to each other, but only through the same analog storage bus. It should be noted that by moving along one column direction, it is preferable that a regular spacing between groups of connected block output buses is defined (e.g., such that the distance between two nearest connected block output buses is constant). In the case of N block output buses (e.g., N=8 in Figure 4), and having a connection of block output buses, the first block output bus (OL-A 0-3 ) is the (N / 2+1)th (e.g., the 5th) block output bus (OL-A 16-19 It may also be connected to the second block output bus (OL-A 4-7 ) is the (N / 2+2)th (e.g., the 6th) block output bus (OL-A 20-23 ) is connected to the (N / 2)th (e.g., the 4th) block output bus (OL-A 12-15 ) is the Nth output line (OL-A 28-31 ) is connected. This arrangement can provide an optimal trade-off between configurability (maximized) and the number of multiplexers (minimized), and also allows for the minimization of parasitic capacitance. In practice, the spacing is defined such that different block output buses connected to the same analog storage element bus have a certain number of other block output buses (e.g., OL-A 0-3 and OL-A 16-19 Between them, there are three other block output buses, OL-A 4-7 and OL-A 0-23 There are three other block output buses between them (and so on). In practice, block output buses can be displaced according to a periodic interval in which a certain number of other block output buses exist between two block output buses connected to the same analog storage element bus.

[0051] As can be seen from the diagram, in some examples, the block output bus OL-A 0-3 , OL-A 4-7 , OL-A 8-11 ,...,OL-A 28-31 This allows for the extension of element rows within the device while simultaneously traversing the semiconductor processing device.

[0052] As shown in Figure 3, each block output bus OL-A0, OL-A1, OL-A2, ... OL-A 31 This is a single storage element bus AL0, AL1, AL2, ...AL 31 These may be connected to a single storage line. These multiple storage element buses AL0, A1, A2, ...A 31 (For example, shown in Figure 7.) is the storage element bus AL 0-3 , AL 4-7 , AL 8-11 ,..., AL 28-31 They may be collected together. For example, storage element bus AL 0-3 This can include (collect) an array of analog storage elements AL0, AL1, AL2, AL3, and a storage element bus AL 4-7 This can include an array of analog accumulators such as AL4, AL5, AL6, AL7, etc. Each single accumulator (e.g., AL0, AL1, AL2, AL3) may be electrically connected downstream to at least one respective block output line (e.g., OL-A0, OL-A1, OL-A2, OL-A3). In practice, at least one block output bus is connected to one single accumulator bus, and all block output lines of each block output bus connected to a given accumulator bus are connected to each analog accumulator of the given accumulator bus. Each block output bus is connected to a single accumulator bus, but each accumulator bus may be connected to multiple block output buses. For example, accumulator AL0 is connected to output lines OL-A0 and OL-A3. 16Both may be electrically connected. As can be mentioned, each output line is supplied with analog electrical values ​​coming from a group of weighting elements of the processing crossbar semiconductor device, so the storage line (e.g., AL0) is affected by the integral information of the weighted electrical values ​​(e.g., in storage form) obtained from those weighting elements.

[0053] Each analog storage element AL0, AL1, ...AL 31 It will be understood that, for example, the analog storage element may have a resistor through which a current flows that is the sum of the currents output from the weighting elements to which it is electrically connected (for example, the current of the analog storage element AL0 may be the sum of the currents received from a single output line OL-A0, and in some examples, under appropriate selection, a single output line OL-A 16-19 It may also be the sum of the currents received from the same source, which then becomes a single output line OL-A0 and OL-A0. 16-19 (Received from the weighted elements of the corresponding column of the associated block). Additionally or alternatively, instead of current, the weighted electrical value may be provided as voltage and / or charge generated by different weighted elements. Each analog storage element AL0...AL 31 This could be a capacitor, and its charge could be the sum of the effects of the outputs of different weighted elements to which it is electrically connected (in this case, it may be preferable to avoid, for example, the current generator in Figure 6).

[0054] As shown in Figure 3, the weighted elements 101 may be grouped into blocks, also called cases, and are collectively represented as 104 (specific blocks 104-00, 104-01, 104-10, and 10411 are shown in Figure 3). For example, in Figure 3, there are blocks 104, each having 16 rows and 4 columns (for simplicity, not all 16 rows are shown). Thus, each block (CAE) can be a matrix of 16x4 (of course, different numbers of columns can be chosen for different matrices). As can be seen from these examples, blocks are also arranged according to superrows 106 (narrow along the element rows, horizontal in Figure 3) and supercolumns 108 (vertical and narrow along the element columns in Figure 3). In particular, the superrows are shown from top to bottom as 106-0, 106-1, 106-2, 106-3, 106-4, 106-5, 106-6, and 106-7. Supercolumns 108 are shown from left to right, such as 108-0, 108-1, 108-2, 108-3, etc. For example, the top-left block 104-00 is part of the top-end supercolumn 106-0 (together with block 104-10 and all blocks behind it) and the leftmost supercolumn 108-0 (together with block 104-01 and the block to its right). Thus, each supercolumn 104 contains multiple element rows immediately following it (for example, the top-end supercolumn 106-0 contains the top 16 element rows of the device, and the second-to-last supercolumn 106-1 contains the 17th through 32nd element rows of the device), and each supercolumn contains multiple element rows immediately following it (for example, the leftmost supercolumn 104-0 contains the leftmost 16 element rows of the device, and the second-to-last supercolumn 104-1 contains the 17th through 32nd element rows of the device). For each block 104 of the determined super row 106, each element column is electrically connected to one block output line (for example, the leftmost element column of each block 104-00, 104-01, etc., in the same super row 106-0 is connected to block output line OL-A0; the second leftmost element column of each block 104-00, 104-01, etc., in the same super row 106-0 is connected to block output line OL-A1, etc.).Connecting a given array of elements in a block to its respective block output line may mean that all weighting elements in the given array are connected to their respective block output line, thereby providing weighted electrical values ​​to their respective block output lines. Furthermore, multiple corresponding arrays of elements in different superarrays but in the same superarray row are connected to the same block output line. Corresponding arrays of elements in different blocks in the same superarray row are electrically connected to the same block output line, thereby providing weighted outputs stored by the corresponding storage element AL0. It should be noted that, for each superarray row, all corresponding arrays in all blocks are electrically connected to the same storage element. Blocks 104 in different superarray rows 106 are connected to different block output buses (and therefore different block output lines), and it will be understood that these are generally electrically independent from other block output buses (or at least most of them). OL-A connected to the same analog storage elements AL0, AL1, AL2, AL3. 0-3 and OL-A 16-19 (or the same storage element bus AL 0-3 , AL 4-7 OL-A connected to etc. 20-23 OL-A 4-7 Apart from correspondences such as those with ), different super row 106 blocks 104 route their weighted electrical values ​​to different analog storage elements. (In some examples, block output bus OL-A 16-19 The block of superlines connected to the connection line OL-A 0-3 It is argued that these can be accumulated along with their weighted values). Generally, each superline 106 is associated with a single block output bus (for example, upper superline 106-0 is associated with the first block output bus OL-A). 0-3 Associated and connected to, the uppermost second super row 106-1 is the block output bus OL-A 4-7 Associated with and connected to (and so on).

[0055] Furthermore, the weighted values ​​provided by block 104 of a superrow (e.g., 106-0) are, in principle, independent of the weighted values ​​provided by another superrow (e.g., 106-1), which means that, unlike the prior art in Figure 2, for example, all weighted elements in a column provide an output to the same storage line. In particular, different superrows (e.g., 106-0 and 106-1) may be used simultaneously to process different electrical input values. Since all processing elements 101 in the same element row are provided with the same electrical input value (and thus shared by all blocks 104 in the same superrow), it is possible to provide two different input vectors (independent of each other) to different superrows (e.g., 106-0 and 106-1) and simultaneously obtain different weighted storage values ​​that should be output as independent output values. For example, in Figure 3, kernels K_0_0 (301 in block 104-00) and K_1 (302 in block 104-1) in the upper super row 106-0 have the same electrical input values ​​as each other, but kernels K_1_0 (303 in block 104-10) and K_1_1 (304 in block 104-11) have different electrical input values ​​(applied to different element rows in the second upper super row 106-1) that do not share anything with K_0_0 (301) and K_1 (302). Nevertheless, advantageously, all kernels K_0_0 (301), K0_1 (302), K_1_0 (303), and K_1_1 (304) can be processed simultaneously. This is not possible in Figure 4 (representing the prior art), and due to the fact that it does not make sense to use the same vertical storage line for different kernels, kernels K_0_0(401) and K_0_1(402) cannot be processed simultaneously with K_1_0(403) and K_1_1(404) in the same column as 401 and 402. In this embodiment, as shown in Figure 3, it is advantageous that multiple input vectors can be operated simultaneously due to the fact that different superrows 106 of block 104 route different weighted values ​​to different storage element buses.

[0056] It should be noted that in some examples, all blocks 104 may be activated simultaneously. More generally, multiple blocks 104 may be activated simultaneously. However, in some examples, even if different blocks 104 may be activated simultaneously, they may be activated in a selectable independent manner, for example, it may be decided that some blocks 104 will not be activated at all, thereby favorably reducing power consumption. Nevertheless, simultaneous activation increases the increased speed. In some embodiments, the blocks 104 are activated independently of each other, thereby activating only the blocks that are actually used to perform weighting without activating the inactive blocks. In some embodiments, it is possible to selectively activate the weighting elements within each block 104 to minimize power consumption. In other embodiments, different weighting elements in the same block 104 are activated simultaneously, even if they are not used for weighting.

[0057] Note that some superlines of block 104 (e.g., 106-0, 106-4) share the same analog storage element bus (e.g., AL 0-3 The possibility of connecting to the AL allows the input vector to be processed with more elements than the number of element rows in the block (for example, in Figure 3, each block has 16 rows, and each kernel K_0_0, K_0_1, K_1_0, K_1_1 has 16 electrical input values). If the input vector has more than 16 electrical input values ​​(e.g., 17-32), the same analog element bus AL 0-3 The block output bus OL-A is electrically connected to it. 16-19 The second upper super row 106-1 associated with the upper super row 106-0 can also be further activated alongside the upper super row 106-0, and thus the 17th through 32nd input values ​​are supplied to that super row. Essentially, it is possible to distribute the excess input vector elements to further blocks of further super rows. Thus, the kernel is partially supplied to the first super row (the upper super row in Figure 3), and the other remaining 16 electrical input values ​​are supplied to the output line OL-A 16-19The superline connected to the AL is provided (and the output weighted value is the same as the storage line AL 0-3 (Provided to)

[0058] Furthermore, it is understood that the configurability of the processing crossbar semiconductor device 100 can be further enhanced. In particular, connections between different block output buses connected to the same analog storage bus (for example, the same analog storage bus AL 0-3 OL-A connected to 0-3 and OL-A 16-19 Instead of relying on (or in addition to) ) connecting the superline blocks to the block output bus associated with a different superline (for example, block output bus OL-A associated with the uppermost superline 106-0) 0-3 Instead, block output bus OL-A is associated with the uppermost super row 106-1, such as blocks 104-00, 104-01, etc. 4-7 It is understood that further possibilities exist for connecting to the following: For example, blocks in the same super column (e.g.) can, in some examples, exchange weighted values ​​with each other, thereby bypassing some block output buses (for example, block 104-00 in left super column 108-0 can send a weighted value to block 104-10 in the same left super column 108-0, while at the same time, block 104-01 in the second leftmost column 108-1 can also send a weighted value to block 104-11 in the same second leftmost column 108-0).

[0059] An example is shown by comparing FIG. 3 and FIG. 5. In some cases, it is preferable to have a single kernel formed by 301 and 303 (in this specific case, 301 and 303 are not different kernels, but two parts of the same kernel), and more generally, the input vector is longer (in terms of the number of rows) than the number of rows of each block 104. In this case, it may be preferable to provide all electrically weighted values to the same analog storage element, and not to different individual analog storages. However, in FIG. 3, the blocks (104-00, 104-01) of the first super row (the leading super row 106-0 in this case) are connected to the first block output bus OL-A 0-3 and connected to the second block output bus OL-A 4-7 not connected; the blocks (104-10, 104-11) of the second super row 106-1 are connected to the second block output bus OL-A 4-7 and connected to the first block output bus OL-A 0-3 not connected. Thereby, in principle, the electrically weighted values processed by the blocks 104-00 and 104-01 of the first super row 106-0 flow to the analog accumulation bus OL-A 0-3 , and the electrically weighted values processed by the blocks 104-10 and 104-11 of the second super row 106-1 flow to the analog accumulation bus OL-A 4-7 , therefore, there is no possibility of accumulating all these values on a single analog accumulation bus. However, it is understood that by bypassing one block output bus (e.g., OL-A 0-3 ), all weighted values (coming from blocks of both the first and second super columns) can be provided to one single analog output bus (e.g., OL-A 4-7 ), and thus accumulated by one single analog accumulation bus (e.g., OL-A 4-7 ). In this latter case, the first block output bus OL-A 0-3 and the first analog accumulation bus OL-A 0-3 can also be used for other processing (e.g., the first block output bus OL-A 0-3using several blocks of the same super column that do not bypass ). In practice, all electrical weighting values are sent to the block output bus OL-A 4-7 by providing them to the block output bus OL-A 0-3 it is understood that selective bypassing is possible. In an embodiment, any (e.g., all) blocks of the same super column may be selectively connectable to each other (at least with the same partial plurality, in embodiments having partial pluralities A and B). In particular, the first block 104-00 of the first super row 106-0 can provide a weighted electrical value to the first block (e.g., the corresponding block 104-10) of the second super row (106-1), which in some examples can provide the same electrical value (along with its own electrical weighting value) to the first block of the third super row 106-2, and so on, or route both the electrical weighting value from the first block 104-00 and the electrical weighting value processed by itself to its associated output line OL-A 4-7 . For example, the first block 104-00 of the first super row 106-0, instead of providing the weighted value processed by itself to the first block output bus OL-A (associated with the first super row 106-0) 0-3 can, based on selection, provide the value to the corresponding first block 104-10 of the second super row 106-1, which can pass (based on selection) both the weighted value generated by the first block 104-00 of the first super row 106-0 and also the weighted value generated by its own first block 104-00 of the first super row 106-0 to the second output line OL-A associated with the second super row 106-1 4-7 . Accordingly, the pre-accumulated weighting value (considering the weighting value obtained from the first block of the first super row and the accumulated value obtained from the first block of the second super row) can be sent to the block output bus OL-A 4-7It can be stored in the first super row 106-0. On the other hand, in such a selection, different blocks (for example, other blocks of the first super row 106-0 that are not blocks 104-00 and 104-01) process the electrical input values ​​and different electrical weighted values ​​are output to the first output line OL-A 0-3 It is possible to provide this. Therefore, better configurability can be achieved, and different values ​​can be configured differently. Therefore, 1) If the input vector has more elements than the number of element rows in a block (in other words, if the array of input electrical values ​​has more input electrical values ​​than the number of element rows in each block of a superrow), it is possible to distribute the input electrical values ​​to two or more superrows, on the other hand, 2) Connect the blocks (within the same super row) directly from those super rows, thereby bypassing at least one block output bus, and thereby providing all weighted elements to the block output bus of one super row. 3) If not all supersequences are used (for example, within the same submultiplexity block), it is possible to use at least one block to route weighted values ​​to a block output bus that is bypassed by other blocks.

[0060] Considering Figure 5, it shows a typical first block of a typical first superline (shown here as 106-0) (shown here as 104-00, but could be any other in Figure 3), and this block is associated with the first block output bus ("analog bus", OL-A) of the first superline 106-0. 0-3 ) is connected. Block (CAE) 104-00 is shown as a 16x4 block. For example, the first (left) column has weights w0_0, w1_0, ..., w15_0 (each weight for processing the respective electrical input value) and is typically connected to the associated first block output bus (OL-A 0-3The first corresponding single electrical output line (e.g., OL-A0) of the block provides an electrically weighted value. The second column (from left) has weights w0_1, w1_1, ..., w15_1 (each weight for processing the respective electrical input value) and is typically associated with the first block output bus (OL-A0). 0-3 The second corresponding single electrical output line (e.g., OL-A1) of the first block output bus (OL-A) is provided with an electrically weighted value. The last (right) column has weights w0_3, w1_3, ..., w15_3, and the weighted value is provided to the associated first block output bus (OL-A 0-3 ) is provided to a second corresponding single electrical output line (e.g., OL-A3). (The behavior of the first block 104-00 is repeated by other blocks in the same super row 106-0, and furthermore, the element rows of each block are also corresponding, thereby accumulating different electrical weighted values ​​and providing different elements of the output vector). However, as shown in Figure 5, the connection between each element row of a block and its respective block output line is traversed by a selectable multiplexer 519 (or more generally, more selectable multiplexers), which, for example, can shift the weighted values ​​to the directly adjacent block 104-10 in the same super row 108-0 (shown as "Next CAE"), depending on the selection. In particular, Figure 5 shows the following:

[0061] 1) The connection between each element array and its respective block output line is controlled by two switches (e.g., Sw0a and Sw0b, collectively shown as 518), each of which can be selectively activated (closed) or deactivated (open).

[0062] 2) In particular, one first switch (e.g., Sw0b for columns w0_0, w1_0, ..., w15_0, Sw1b for columns w0_1, w1_1, ..., w15_1, etc.) is a block output bus (e.g., OL-A 0-3 It controls the connection to each block output line (e.g., OL-A0) of the ) (for example, independently).

[0063] 3) On the other hand, a second switch (e.g., Sw0a for columns w0_0, w1_0, ..., w15_0, Sw1a for columns w0_1, w1_1, ..., w15_1, etc.) controls (e.g., independently) the connection to the nearest closed block of the same supercolumn but immediately following superrow.

[0064] 4) Note that for each block sequence (e.g., w0_0, w1_0, ..., w15_0), the first switch (e.g., Sw0b) and the second switch (e.g., Sw0a) may be activated or deactivated simultaneously.

[0065] a. If activated simultaneously, the weighted value is the block output bus associated with the block (e.g., OL-A 0-3 It is provided to both the respective block output line of (e.g., OL-A0) and the nearest closed block in the same supersequence.

[0066] b. If deactivated simultaneously, the block output bus associated with the block in the same supersequence and the most recent closed block (e.g., OL-A 0-3 Weighted values ​​are not provided for each block output line (e.g., OL-A0) of ).

[0067] 5) Each second switch (e.g., Sw0a) may be controlled independently of other second switches in the same block (e.g., Sw1a, Sw2a, etc.) (e.g., by a binary command written to a cell such as an SRMA cell), although in some examples all second switches in a single block are controlled by a single command.

[0068] 6) Each first switch (e.g., Sw0b) may be controlled independently of other first switches in the same block (e.g., Sw1b, Sw2b, etc.) (e.g., by binary commands written to a cell such as an SRMA cell), and in some examples, the binary commands may be controlled by at least one external activation (e.g., a column-by-column activation controlled by the binary command S-Col Select, and a row-by-row activation controlled by the binary command S-Row Select) which is executed via an AND port, for example.

[0069] 7) Generally speaking, a multiplexer is used (e.g., controlled by an AND gate) to selectively select from the following:

[0070] a. Electrically weighted values ​​are applied to the OL-A block output bus. 0-3 To provide (shown as 86 in Figure 3), b. Bypass it (as shown in 85 in Figure 3), thereby providing an electrically weighted value to the adjacent blocks 104-10), or c. Electrically weighted values ​​for the block output bus OL-A 0-3 (Both providing to and providing electrically weighted values ​​to adjacent blocks 104-10)

[0071] As shown in Figure 3, multiple blocks may be divided into different submultiplexities (e.g., different sections). For example, the blocks of the first submultiplexity may be shown as being limited to section A, and the blocks of the second submultiplexity may be limited to section B. Other sections may exist that also contain other submultiplexities. Each submultiplexity has its own supersequence and may share superrows with other submultiplexities (or, in some cases, the superrows of the first submultiplexity may be different from those of the second submultiplexity). All features of the second submultiplexity (section B) may be the same as all features of the first submultiplexity (section A), and therefore will not be repeated here. However, it should be noted that the second submultiplexity (section B) may consist of blocks that are not even activated in some examples (e.g., when the number of elements in the output vector is less than the total number of element sequences in the first submultiplexity). Nevertheless, in the embodiment, different submultiplexities are activated. For example, a first superrow of a part of the second subplurality (section B) may be applied to the same input values ​​as the block of the first superrow of the first subplurality (section A) to which the input values ​​are applied. Nevertheless, those blocks have different output lines (OL-A 0-3 OL-B not connected 0-3 The output is routed to a different storage line (for example, section B in the first superline of the second submultiplicity), and the weighted values ​​are routed to the storage element bus AL. 28-31 Output to the storage element bus AL 28-31 The analog storage bus AL receives weighted values ​​from a block of the first superrow within the first sub-plurality (Section A). 0-3 This is different. In other words, it is a bus AL of two storage elements (two different sub-sub 0-3 and AL 28-31 The values ​​accumulated by this method can potentially be stored digitally in a digital accumulator (S&A, see below).

[0072] Regarding other aspects, Section B may be identical to Section A, or may have at least the same or similar features (not necessarily in combination) as those described in Section A. Naturally, the second submultiplexity may be deactivated (for example, by simultaneously deactivating all blocks of the second submultiplexity) to avoid power consumption when it is not needed. One example of using the second submultiplexity (Section B) is when the output value has a dimension with more elements than the element array of the first submultiplexity. In the example in Figure 3, the second submultiplexity must be activated if the output has more than 16 elements. For example, if the output has an output value of 17-20, only one superarray of the second submultiplexity (Section B) is activated, and the remaining superarrays of the second submultiplexity are not activated, thereby saving power.

[0073] Therefore, for the reasons stated above, the reconfigurable processing device may be at least one of the following options (e.g., a combination of them).

[0074] 1) Selection of the blocks to be activated (therefore, with respect to the prior art in Figures 2 and 4, power consumption can be reduced if some blocks are not used), 2) Selection of different input vectors to be processed simultaneously, by routing their weighted values ​​on different block output buses and different analog storage buses (which is not possible with the prior art shown in Figures 2 and 4, as it is not possible to associate different analog storage elements in the same column). 3) If the length of the input vector is greater than the number of columns in the first general block of the first general super row and first general super column into which the input vector is entered, a. Choose to bypass from the first block to the second block for the same first supercolumn and second superrow, so that the second block provides both weighted values ​​from itself and weighted values ​​from the first block to the second block output bus associated with the second superrow, for example, the first block ceases to provide weighted values ​​from itself to the first block output bus associated with the first superrow, or b. Activating at least one second block from a second superline that is electrically connected to the same analog storage bus that receives weighted values ​​from a first superline of which the first block is part, or c. Both 4) If the length of the output vector is greater than the number of blocks of the same superrow in the first submultiplexity (Section A), select the activation of the blocks in the second submultiplexity, transfer the weighted values ​​to different analog accumulator buses, and then digitally sum the two accumulator values.

[0075] Nevertheless, in some examples, it is also possible to select the magnitude of the weight according to a digital address (e.g., 3 bits), for example, by choosing from multiple different levels of weight (e.g., 7 levels addressed by 3 bits).

[0076] Generally speaking, each electrical input value is provided to its respective element row (a line in the prior art), but each element row is not limited to a single output value (a link in the prior art in Figures 2 and 4). Each different output value arrives from the corresponding element row of a block within the same superrow (or, after bypassing, from the corresponding element row of a block from a different superrow). Therefore, in principle, a single superrow is not confined to a single output value.

[0077] Figure 6 shows an example 501 of how each weighting element 101 (AWE) may be implemented (different implementations are possible). Each weighting element can provide at least one of current, charge, or voltage obtained in the analog domain by weighting an input electrical value (which may be a digital value), to each block output line OL-A0 to be stored by each storage element AL0. Element 101 can provide at least one of weighted current or weighted charge. A weighting element 101 may be parallel to all weighting elements in the same element row of the same block, thereby providing the same electrical weighted values ​​to the same block output line OL-A0 in parallel and simultaneously, to be pre-stored along with other electrical weighted values ​​from corresponding element rows of other blocks in the same superrow. At least one electrical input value can encode a binary value (e.g., d_in in 501 and 502, or d_in0, d_in1, d_in2 in 503 and 504), so that a first electrical level of at least one electrical input value corresponds to a first logical level of the binary value (e.g., 1), and a second electrical level of at least one electrical input value corresponds to a second logical level of the binary value (e.g., 0). This can be obtained, for example, by activating or deactivating a switch controlled by the binary value (e.g., d_in or d_in0, d_in1, d_in2), thereby applying or releasing at least one electrical value (e.g., a power supply voltage V). ddBy applying a voltage and / or by applying a specific current or charge, and / or by releasing the voltage, for example by floating an electrical value, or by applying a different voltage or different electrical value). In the embodiment of 501, the weighting element 101 can be selected to be either a first current generator 110I that provides a first current I, or a second current generator 110I2 that provides a second current I2 (for example, I2 = 2 * I, and more generally I2 ≠ I1). The weighting element 101 independently distributes each of the first current I1 and the second current I2 through their respective conductors (the first is conventionally the positive conductor AL-P of the block output line). <0> In contrast, the second is conventionally the negative conductor AL-N of the block output line. <0> The signals can be selectively routed to each terminal connected to the (see Figure 7) (the first being conventionally the positive terminal vout_p, while the second being conventionally the negative terminal vout_n). This effect can be achieved, for example, by coordinating or deactivating the following, or independently.

[0078] 1) The first switch d_wp is located downstream of the first current generator and upstream of the first terminal (and the positive conductor of the block output line). <1> 2) Upstream second switch d_wn located downstream of the first current generator at the second terminal (and the negative conductor of the block output line) <1> 3) A third switch d_wp located downstream of the second current generator and upstream of the first terminal (and the positive conductor of the block output line) <0> 4) A fourth switch d_wn located downstream of the second current generator and upstream of the second terminal (and the negative conductor of the block output line) <0> .

[0079] A table providing various outputs is shown in the following parts of this specification. For example, it is clear that the sign of the weights can be changed by changing the polarity. For example, If the current flows primarily through the first terminal vout_p (and the positive conductor of the block output lines) rather than the second terminal vout_n (and the negative conductor of the block output lines), the polarity becomes positive, thereby indicating a positive weight, and If the current flows primarily through the second terminal vout_n (and the negative conductor of the block output lines) rather than the first terminal vout_p (and the positive conductor of the block output lines), the polarity becomes negative, and thus it exhibits a negative weight.

[0080] Next, we will describe the optional digital storage 600 in Figure 7 (some element embodiments in Figure 8). This is the analog storage element bus AL 0-3 ,..., AL 28-31 This is because the array of electrically analog stored values ​​accumulated by can be converted back into digital values. However, it should be noted that, especially when each binary input (e.g., d_in) is processed with weights having a resolution of more than 2 (i.e., the binary input may be processed according to weights selected from more than 2 weight values), each digital output value from each processed input value may, advantageously, have a resolution of more than 1 bit (i.e., each digital output value may, for example, have a resolution of more than 1 bit). For this reason, an analog-to-digital conversion may be used to provide an encoded digital output value of more than 1 bit for each analog stored value accumulated by each analog stored element AL0. In particular, each analog stored element AL0, ..., AL 31 It can have one potential stored weighted value which is one of the set of stored weighted values, and the stored weighted value has a cardinality of twice the number of input elements in the input vector multiplied by the number of weight levels that can be assigned to each electrical input value and the number of weighting elements. For example, the output of the ADC in Figure 7 is an analog stored element (e.g., AL 0-3 Each of these can be 9 bits. When different analog storage elements carry different weighted storage values ​​of different bits of the input encoded value, a superstring of bits can be generated, for example, using the shift register in the S&A (sample and adds) element 702.

[0081] Neural Network Here, we discuss some examples of applications for the processing crossbar semiconductor device 100, specifically its application to neural networks. The crossbar processing semiconductor device 100 can implement a neural network with multiple layers, as shown in Figure 1. The layers may include an input layer, an output layer, and, for example, at least one hidden layer (usually a sequence of multiple hidden layers). For example, a given layer may range from N1 to Nn, and for the subsequent layers M1-Mm, each of N1, N2, N3, ..., Nn, M1, M2, M3, ..., Mm is a neuron. Each transition from a layer (N1, N2, N3, ..., Nn) to the subsequent layer (M1, M2, M3, ..., Mm) can be performed using the techniques described herein. For example, 1) The input vectors are N1, N2, N3, ..., Nn (for example, they can be represented by an array of digital values ​​that form the input digital string). 2) The input vector can be converted into an array of input electrical values ​​that represent the input vector. (Each bit of the input digital string may be the binary value d_in in Figure 6, for example V dd (Generates possible input electrical values) 3) In each weighted element 101, each electrical value is determined by, for example, applying current generators 110I and 110I2, and / or switch d_wp <1> d_wp <0> d_wn <1> d_wn <0> The process is weighted by appropriately activating or deactivating the terminals, thereby providing current values ​​to terminals vout_p and vout_n. 4) The weighted electrical values ​​are then routed to the block output lines and the analog storage element bus. 5) The electrically stored weighted values ​​are then digitized and, if necessary, put together to form a superstring. 6) In some cases, an activation function within the digital domain may be applied. 7) The digital activation output may be the output vector M1...Mm that constitutes the subsequent layer.

[0082] Each weight in at least one weight tensor represents a synapse. Each analog input value is a neuron. Each output value is a neuron in the immediately following layer.

[0083] The input vector may be, for example, a kernel.

[0084] This can be performed after a first phase in which the weights of at least one weight tensor are defined by minimizing a cost function that gives an error metric for a known dataset (and evaluating that error metric against known values ​​of the dataset). Subsequently, an inference phase may be performed in which the weights are established and predictions are provided in response to input values. This may be done layer by layer.

[0085] controller A controller (not shown) can be used to perform processing and / or selection.

[0086] In particular, the controller can control the operation of the weighting elements to activate or deactivate the weighting elements and / or blocks.

[0087] The controller may be, for example, the same controller that defines the neural network, or it may be a slave controller that receives requests from the neural network controller to define the neural structure of the neural network (e.g., the number of layers, the number of neurons in each layer, which synapses, which weights, etc.). In either case, we hypothesize that the controller performs the operation of adapting the structure of the processing crossbar semiconductor device 100 to the neural network being used, and that the structure of the neural network is either requested by an external entity or predefined.

[0088] The controller can receive information about the number of elements in the input vector, the number of elements in the output vector, and the values ​​of the weights to be applied. The controller can evaluate at least one of the following:

[0089] 1) Whether the number of elements in the input vector is greater than or less than the number of element rows in one block of the superrow. a. If it is confirmed that the number of elements in the input vector is less than or equal to the number of element rows in the block, the controller assigns each input value to the respective row of the block. b. If the number of elements in the input vector is greater than the number of element rows in the block, the input values ​​will be distributed between the following:

[0090] i. Different superrows (and the weighted values ​​of different superrows can be bypassed to the same block output line to reach the same analog storage element) and / or ii. Different superlines connected to the same analog storage element bus (e.g., cumulative element bus AL 4-7 Superlines 106-0 and 106-4 route to the same cumulative element within. 2) Whether the number of elements in the output vector is greater than or less than the total number of elements in the sequence within the first submultiplicity. a. If it is confirmed that the number of elements in the output vector is greater than the total number of element sequences in the first submultiplexity, some elements of the output vector are assigned to blocks in the first submultiplexity block, and some other elements of the output vector are assigned to additional blocks in the second submultiplexity block (e.g., within the same element row).

[0091] b. Otherwise, only one single block of partial pluralism may be activated. 3) Whether the number of elements in the output vector is greater than or less than the total number of element sequences in one block of a superarray. a. If it is confirmed that the number of elements in an output vector is less than or equal to the number of element sequences in a single block, each output value is assigned to one single block or one single super-sequence. b. If it is determined that the number of elements in the output vector is greater than the number of element rows in one block of a single super row, each input value is assigned to either multiple blocks in the same super row (and, in some cases, weighted values ​​are bypassed to a single block output line, resulting in those weighted values ​​being routed to the same analog accumulator elements) or to blocks with different submultiplicities but the same element rows (i.e., the same electrical input values). 4) After assigning input and output values ​​to a block, and before performing processing, super rows, super columns, etc., the controller can evaluate whether it is possible to insert further input vectors. This is evaluated by:

[0092] a. Check if there are enough empty element sequences and rows to process the elements of the input vector using the same weights as the first input vector (if sufficient, it is possible to proceed with a different input vector in the same weight tensor and apply it further; otherwise, it is not performed). b. Check if there are enough empty element rows to process the elements of the input vector with the same weights as the first input vector, and enough empty element sequences and blocks to insert additional weight tensors. (If sufficient are found, it is possible to proceed with and further apply different input vectors using different weight tensors that are processed simultaneously; otherwise, this is not done.) i. Next, values ​​are assigned to blocks, element rows, element columns, supercolumns, and superrows for the first input vector, but this is done for the first input vector excluding blocks, element rows, element columns, supercolumns, and superrows that have already been assigned to the first input vector.

[0093] It should also be noted that the controller can, for example, associate the weights of the tensor weights with the weight element 101 at positions that fit the activated weight element and weight block.

[0094] Structural characteristics The layout of device 100 can substantially follow Figure 3. In particular, the weighting elements 101 may be arranged such that, for example, one is adjacent to the other, according to their two-dimensional array. Each block into which the two-dimensional array is divided may include, for example, a reduced two-dimensional array containing only weighting elements spatially enclosed within a closed boundary. In the embodiment, all blocks of at least one superrow and / or at least one supercolumn have the same number of element rows and element columns. The two-dimensional array can be obtained, for example, by appropriately doping a silicon substrate to form weighting elements and connections. The two-dimensional array may spread out mostly in a planar manner. The superrows may be geometrically parallel to each other, and the supercolumns may be geometrically parallel to each other. The superrows may be geometrically perpendicular to the supercolumns. The block element output bus may be geometrically parallel to the superrows. The block element storage bus may be geometrically parallel to the supercolumns. The block element output bus may be geometrically perpendicular to the supercolumns. The bypass obtained via the multiplexing 519 is obtained in such a way that each block is connected to the nearest block of the nearest superrow, thereby minimizing the length of the multiplexing 519. The blocks of the first submultiplexity may all reside within a single closed boundary excluding all of the blocks of the second submultiplexity, and / or the blocks of the second submultiplexity may all reside within another single closed boundary excluding all of the blocks of the first submultiplexity. The blocks and weighting elements may be grouped at positions spaced apart from the ADC700. It is understood that these solutions enable a reduction in parasitic capacitance.

[0095] Discussion The complete crossbar array (CA) in Figure 3 can be divided into two sections (sub-multiplicities): Section A (first sub-multiplicity) and Section B (second sub-multiplicity), each section being further divided into blocks (smaller crossbar array elements or cases). Each block (CAE) can contain 4 columns and 16 rows (other numbers are possible) of analog synapses, such as weighted elements or analog weight emulators (AWEs). The columns and rows of a block (CAE) are called supercolumns and superrows, respectively. All blocks (CAEs) in a superrow of a section share a dual-channel analog bus, for example, with a width of 8 (i.e., 8 conductors), and each pair of CAE columns extends horizontally across all supercolumns in the section. These analog buses in Figure 3 are called CAE output lines (block output buses), and there may be as many such analog buses as superrows per section, which are called OL-A and OL-B with respect to Section A (first sub-multiplicity) and Section B (second sub-multiplicity), respectively. Some of these OL-A and OL-B analog buses (block output buses) are connected to another set of dual-channel analog buses in each section (sub-multiplexity), which are called storage lines (storage element buses) in Figure 3, and are called AL-A and AL-B with respect to section A (first sub-multiplexity) and section B (second sub-multiplexity), respectively. In Figure 3, there are 32 storage elements, i.e., 16 per section, and for example, each storage element has a width of 2 (i.e., 2 conductors). There are the same number of AL-A and AL-B as there are ADCs in each section, and they extend to all super rows in each section. The CA in Figure 3 can have the same number of shift-add digital blocks as the ADCs, for example, 32.

[0096] Each block (CAE) can be equipped with a special multiplexer, which can be configured statically, for example, before performing inference, and / or dynamically, while performing inference. As shown by the long and short arrows in Figure 3, these multiplexers allow a CAE (block) to pass its output to the next block (CAE) in the same super-sequence and / or their output lines (e.g., AL-A 0-3 It becomes possible to transfer to the analog block output bus (for example, OL-A). 0-3 , OL-A 4-7 The output from ,...) is different analog storage lines (e.g., AL- 0-3 , AL-A 4-7 The signal is further transferred to the ADC and finally digitized. Thus, using a suitable configuration of the multiplexer, multiple CAEs (blocks) can be configured to support convolutional and fully connected kernels (or more common input vectors) of various dimensions (and to achieve output vectors of even more variable dimensions) without sacrificing the use of analog crossbars. Here, the convolutional or fully connected kernel dimension is defined as the number of weights associated with the neuron computation. For a 2D convolutional layer filter with width 3, height 3, and 3 channels, the kernel dimension is 3 × 3 × 3 = 27, but for the fully connected case shown in Figure 1, the same value is n.

[0097] Kernel Mapping on Crossbars: Exercises on Configuration and Use To illustrate the advantages of this embodiment, we again consider an example using four kernels K0_0, K0_1, K1_0, and K1_1, each with a length of 16. K0_0 and K0_1 form a pair that obtains the same input, while K1_0 and K1_1 form another pair that obtains the same input but is different from the previous pair. Such assumptions are valid model configurations; for example, a CNN layer with two filters obtains the same set of inputs, but the inputs are clearly different for the two different layers.

[0098] Reference numerals 301-304 in Figure 3 and 401-404 in Figure 4 (prior art) illustrate the mapping of the above 4K*_* (where "*" is a general notation meaning "any number") kernels onto the configurable crossbar presented in these examples and the conventional in-memory computing crossbar in Figure 2, respectively. In Figure 4 (prior art), if reference numerals 403 and 404 are mapped to the same element column as 401 and 402, they are connected to the same storage line, and therefore their storage results cannot be computed simultaneously. However, although 303 and 304 are mapped to the same column under 301 and 302, the storage outputs from 301 and 302 or 303 and 304 can be transferred to different storage lines via output lines, and therefore can be computed simultaneously. For example, the storage outputs from 301 and 302 are transferred to output line OL-A 0-3 Through storage line A -3 It can be transferred to, while the accumulated output from 303 and 304 can be simultaneously transferred to output line OL-A. 4-7 via the accumulation line AL 4-7 It can be forwarded to [destination]. The routing configuration for OL and AL is controlled by the CAE multiplexer, and its configuration is set during compile time and runtime.

[0099] Multiplexer Figure 5 shows the multiplexer circuit employed by each CAE(block), where the switch array can be controlled by a combination of S-Col Select, S-Row Select, and signals from the SRAM cells. The accumulated output from each column of the CAE(block) is transferred to the corresponding column of the next CAE(block) when the first row of the SRAM cells contains bit "1", while the output is transferred to the output line when both S-Col Select and S-Row Select are high and the second row of the SRAM cells contains bit "1". The switch array in Figure 5 comprises eight analog switches. Depending on the implementation of AWE (weighting elements) within each CAE(block), the on / off resistance and parasitic capacitance of these switches are important design specifications that must be met.

[0100] The accumulated output from a CAE (block) is transferred to the next CAE (next block) if the kernel length is greater than the height (number of rows) of the CAE (block), which is 16 in Figure 5. This is a neural network-dependent parameter, calculated at compile time, and therefore treated as a static signal. Conversely, the S-Row Select and S-Col Select signals, which control output line access, may be generated by instructions during runtime and are therefore dynamically configured. Driving compile-time signals with SRAM cells simplifies the complexity of the CA (device) interface because they can be configured using existing memory interfaces, and reduces energy consumption because they are located locally within the CAE (block).

[0101] Multiply-accumulate operations, i.e., MAC, using an analog weight emulator or AWE. The multiply-accumulate operation, or MAC, is the fundamental operation of all vector matrix multiplication or VMM, involving a multiplication operation on two operands and an accumulation operation that adds the outputs of the subsequent two multiplication operations. There are several different implementations of MAC operation employed by in-memory computing (IMC) engines, many of which employ SRAM-based IMCs that typically store electric charge, or eNVM-based IMCs that store current[1][3][4][5][6][7][8]. This embodiment can use current-mode storage employing a current source and 6-T CMOS SRAM cells.

[0102] Figure 6 shows an implementation of the current source-based analog weight emulator (CS-AWE, weighted element) used in this embodiment for MAC calculation, which multiplies a 1-bit input and signed weights at 3-bit or 7 levels. This is referred to herein as 1bx3b MAC operation. Example 501 shows a detailed implementation of the CS-AWE (weighted element), while Example 502 shows a compact representation of the CS-AWE (weighted element). The magnitude portion of the synaptic weight is encoded into two binary weighted current sources in Examples 501 and 502, while the sign portion of the weight is effectively calculated by subtracting vout_n from vout_p (thus reversing the polarity). Switches controlled by d_wn<1:0> and d_wp<1:0> control the current flow to either vout_n or vout_p depending on the sign of the weight. Table 1 shows the mapping between the seven possible weight levels or weight values ​​and the switch control signals d_wn<1:0> and d_wp<1:0>. The input bit d_in is essentially used as a selection bit to control the switch that enables the CS-AWE (weighting element).

[0103] Example 503 uses three inputs d_in with synaptic weights W0, W1, and W2. 0-2 An example circuit of a connected neuron is shown. Example 504 shows an equivalent circuit of the neuron implementation in 503, along with the electrical parameters that make the output voltage equal to the inputs and weights. In the example shown in 504, all three inputs of 503 are high, so all weights or CS-AWE (weighting elements) are enabled. The weighted currents of the positive weights W0 and W2 are directed to the vout_p terminal, and the weighted current of the negative weight W1 is directed to the vout_n terminal, controlled by d_wn<1:0> and d_wp<1:0> according to Table 1. The equivalent MAC output of three sum-of-accumulate operations between the three inputs and weights is calculated in 504 and generalized in 505, in which case input = 1, SUM(weights) = -2, and the constant term is the unit current of the current source and the storage resistor R acc Determined by the product of

[0104] [Table 1] Configurable activation and weighting accuracy using a shift-adding circuit This embodiment may include circuits and devices that can be employed to construct the bit precession of neuron activation and weights (see Figure 7). Neuron activation can consist of 1 to 8 unsigned bits in 1-bit steps, and weights can consist of 3 to 9 signed bits in 2-bit steps. The general idea is to separately calculate the accumulation of 1-bit inputs and 3-bit signed weights by using the 1-bit × 3-bit unit MAC described above, and then combine all such accumulations for multiple input bits in the range of 1 to 8 bits and multiple weight bits in the range of 3 to 9 bits, either sequentially over multiple cycles or in parallel in a single cycle. All accumulations corresponding to the same set of inputs and weights with higher precision than the unit MAC precision are performed by shifting and adding the digital accumulation results from each ADC.

[0105] In Figure 7, the 32 pairs of AL-P (positive conductor) and AL-N (negative conductor) signals, indicated by 601, are vertically traversing storage lines that carry the VMM's 1bx3b MAC storage output, which is digitized by 32 ADCs and fed into 32 shift-add blocks. For each bit of the VMM's higher-precision input, the digitized storage result from the ADC is shifted left by 1 and added sequentially to the previous output from the most significant bit (MSB) to the least significant bit (LSB) of the input. For example, an 8-bit VMM input requires 8 storage cycles to calculate the combined 8bx3b MAC storage, with the digitized storage result being left-shifted to the MSB of the input. In Figure 7, the left shift (resulting in a doubling) is indicated by 603. Each ADC and shift-add block, i.e., S&A, is provided with a shift-add sequence, indicated by 602, which facilitates the MAC storage of the corresponding 3-bit weight. For VMMs with higher weight precision, the multiple shift-add column outputs shown in 604 are shifted 2 units to the left (shown in 605) and added to the shift-add column to its left. For example, a 5-bit weight requires two shift-add columns, and a 9-bit weight requires four shift-add columns. The final output is available in the leftmost column of the column combination.

[0106] Figure 8 shows a detailed implementation of the shift-adder circuit. The shift-adder circuit supports sequential addition of digitized stored outputs corresponding to different bits of a multibit input from the same AL and digitized stored outputs corresponding to different bits of multibit weights from different ALs. The shift-adder circuit also supports multiplication of the stored result with a configurable 8-bit gain 801 and the addition of a configurable offset 802, and using combinations thereof, it can support batch normalization functions used in deep neural networks.

[0107] Several aspects This embodiment may include the field-configurable analog crossbar architecture for in-memory computing described above, which provides the ability to map and compute VMM kernels of various dimensions without sacrificing resource utilization and performance.

[0108] This embodiment is not limited to the specific parameter values ​​used to illustrate the above solution, such as dimensions like crossbars, CAE(blocks), superrows, supercolumns, ADCs, and shift additions, but can be extended to other feasible dimensions.

[0109] Some of these embodiments may include multiplexer circuit implementations that can be configured statically at compile time and dynamically at runtime using memory and switches.

[0110] This embodiment is not limited to SRAM (Static Random Access Memory) and CMOS (Complementary Metal-Oxide-Semiconductor) switches, but also extends to non-volatile memories such as RRAM (Resistive Random Access Memory), FeFET (Ferroelectric Field-Effect Transistor), and MRAM (Magnetoresistive Random Access Memory).

[0111] Some of these embodiments provide analog weight emulators or AWE circuits that facilitate multi-bit signed multiplication and accumulation, i.e., MAC calculations.

[0112] This embodiment is not limited to SRAM memory and CMOS switches, but also extends to non-volatile memories such as RRAM, FeFET, and MRAM.

[0113] This embodiment is not limited to 3-bit signed weights and 1-bit inputs, but extends to other bit precisions as well.

[0114] Some of these embodiments provide shift-add circuits that support an integrated batch normalization function.

[0115] This embodiment is not limited to the specific precision used above, but extends to other precisions as well.

[0116] Further features of the drawing: Figure 1 Example of a fully bonded layer Figure 2. Example of an in-memory computing array. Figure 3. Configurable Crossbar Array Architecture Figure 4 shows a conventional in-memory crossbar array architecture illustrating kernel mapping. Figure 5 CAE (block) multiplexer Figure 6: AWE implementation showing three MAC operations. Figure 7 Shift-addition sequence for shift-multibit input and weight configuration Figure 8 Reconfigurable shift-add block for multibit input and multibit weights

[0117] References TIFF2026529717000009.tif170166

Claims

1. A processing crossbar semiconductor device for processing at least one input vector with at least one weight tensor to derive at least one output vector as a result of processing the at least one input vector, wherein the at least one weight tensor has a plurality of weights, and the crossbar processing device is configured to process each input electrical value of an array of input electrical values ​​representing the at least one input vector, and the processing crossbar semiconductor device comprises the following: A set of weighted elements (101) arranged according to element rows and element columns, wherein each weighted element (101) corresponds to a weight of at least one weight tensor, and the set of weighted elements (101) is divided into a plurality of blocks (102), the plurality of blocks (102) being arranged according to super columns (108) and super rows (106) such that each super column includes a plurality of subsequent element rows, and each super column includes a plurality of subsequent element rows. A plurality of block output buses (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , ..., OL-A ２８－３１ ), wherein each block output bus (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , ..., OL-A ２８－３１ ) is associated with and connected to a plurality of blocks (104-00) within said respective super row (102-0) without being connected to blocks (104-10, 104-11) that are associated with and connected to at least one other super row (102-1), each block output bus (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , ..., OL-A ２８－３１ ) comprises a plurality of block output lines (OL-A ０ ..., OL-A ３１ ), each block (104) of said plurality of blocks, when activated, is configured to weight input electrical values of said array of input electrical values by a corresponding weight of said at least one weight tensor, and provides an electrically weighted value to said block output bus associated with said super row (106-0) of which said block (104-00) is a part, the plurality of block output buses; Multiple analog storage elements (AL0 ０ , . . ,AL ３１ ) and each analog storage element (AL0 ０ ) has at least one block output line (OL-A ０ ) is electrically connected to the at least one block output line (OL-A ０ Multiple analog storage elements (AL0) provide their respective electrically stored weighted values ​​from the electrically stored values ​​obtained from the corresponding element arrays of multiple activation blocks (104-00, 104-01) in at least one super row (106-0) related to ), thereby deriving an array of stored weighted output values ​​that form the at least one output vector. ０ A processing crossbar semiconductor device comprising ) and .

2. Each block (14-00) of the super row (106-0) is configured to simultaneously activate a plurality of weighting elements (101) to thereby simultaneously provide the electrically weighted values ​​to each of the block output lines via the weighting elements (101), and as a result, each analog storage element that receives the electrically weighted values ​​from the same block output line simultaneously has the stored values, the processing crossbar semiconductor device according to claim 1.

3. Each weighting element (101) is configured to provide an analog current obtained by weighting the input electrical value, and as a result, each storage element provides at least one of the stored weighted currents as the electrically stored weighted value, according to any one of claims 1 to 2, for the processing crossbar semiconductor device.

4. Each weighting element (101) is configured to provide an analogously obtained charge and / or voltage by weighting the input electrical value, and as a result, each storage element provides a stored weighted charge and / or a stored weighted voltage as the electrically stored weighted value, the processing crossbar semiconductor device according to any one of claims 1 to 3.

5. At least one electrical input value is a binary value (d_in, d_in ０ , d_in １ , d_in ２ A processing crossbar semiconductor device according to any one of claims 1 to 4, wherein the device encodes such that, as a result, a first electrical level of the at least one electrical input value corresponds to a first logical level of the binary value, a second electrical level of the at least one electrical input value corresponds to a second logical level of the binary value, and each of the associated weighting elements (101) is configured to process the electrical input value according to a weight selected from three or more weight values.

6. At least one of the weighting elements (101) is configured to select either a first current generator (110I) that provides a first current (I) or a second current generator (110I2) that provides a second current (I2), and the weighting element (101) is configured to independently and selectively route each of the first current and the second current to a conductor selected from a first conductor and a second conductor of each block output line, so that each block output line carries one selected from a plurality of selectable levels of the weighted output value, the processing crossbar semiconductor device according to claim 5.

7. A processing crossbar semiconductor device according to any one of claims 1 to 6, wherein at least one of the associated weighting elements (101) is configured to select either at least one positive polarity that generates a positive weight and one negative polarity that generates a negative weight, by providing the positive conductor or electrode of the analog storage element with an electrical level greater than that of the negative conductor or electrode of the analog storage element in the case of a positive electrically weighted value, and by providing the negative conductor or electrode with an electrical level greater than that of the positive conductor or electrode in the case of a positive electrically weighted value.

8. The plurality of analog storage elements (AL ０ , AL １ , AL ２ , AL ３ ) is an analog storage element bus (AL ０－３ , . . ,AL ２８－３１ ) are collected in the analog storage element bus (AL ０－３ Each of the ) has at least one block output bus (OL-A ０－３ ) is connected to and associated with each analog storage element bus (AL ０－３ Each analog storage element (AL ０ ) is the associated at least one block output line (OL-A ０－３ ) at least one block output line (OL-A ０ ) is connected to the associated at least one block output bus (OL-A ０－３ A processing crossbar semiconductor device according to any one of claims 1 to 7, which stores weighted electrical values ​​from the same array of elements in the block (104-00, 104-01) of at least one superrow (106-0) associated with ).

9. At least one analog storage element bus (AL ０ ) is connected to at least a first block output bus (AL) associated with the first super line (106-0). ０－３ ) and the second block output bus (OL-A) connected in association with the second super line (106-4) １６－１９ ) and are associated with and connected to, and as a result, the analog storage element bus (AL ０－３ Each analog storage element (AL ０ A processing crossbar semiconductor device according to any one of claims 1 to 8, wherein the device provides an electrically stored weighted value accumulated from both the electrically weighted values ​​from the first block (104-00, 104-01) of the first superrow (106-0) and the second block of the second superrow (106-4).

10. A processing crossbar semiconductor device according to any one of claims 1 to 9, further comprising at least one analog-to-digital converter (ADC) for converting at least two electrically stored weighted values ​​from at least two analog storage elements, respectively.

11. The processing crossbar semiconductor device according to claim 10, configured to convert at least one electrically stored weighted value into a single bit according to the electrical level of the electrically stored weighted value.

12. A processing crossbar semiconductor device according to claim 10, configured to convert at least one electrically stored weighted value into a plurality of bits according to the electrical level of the electrically stored weighted value, i.e., the weight level.

13. A processing crossbar semiconductor device according to any one of claims 10 to 12, configured to convert a plurality of storage-weighted values ​​from different storage elements into a superstring of bits by converting at least one first electrically storage-weighted value into at least one least significant bit or least significant string and at least one second electrically storage-weighted value into at least one most significant bit or most significant string.

14. A processing crossbar semiconductor device according to any one of claims 10 to 14, further comprising at least one digital storage element for storing different storage-weighted values ​​at the time they are converted to digital from different analog storage elements or different analog storage element buses.

15. First block output bus (OL-A ０－３ The first block (104-00) of the first superline (106-0) associated with the second superline (106-1) includes a selectable multiple connection with the second block (104-10) of the second superline (106-1), and the second superline (106-1) is connected to the second block output bus (OL-A ４－７ It is connected in association with the first block output bus (OL-A ０－３ It is configured not to be associated with or connected to the first block output bus (OL-A ０－３ ) consists of multiple first analog storage elements (AL ０ , AL １ , AL ２ , AL ３ ) including the first analog storage element bus (AL ０－３ ) and the second block output bus (OL-A ４－７ ) consists of multiple second analog storage elements (AL ４ , AL ５ , AL ６ , AL ７ ) including a second analog storage element bus (AL ４－７ ) is connected to and associated with the first analog storage element (AL ０ , AL １ , AL ２ , AL ３ ) is the second analog storage element (AL ４ , AL ５ , AL ６ , AL ７ ) is not connected to any of the above, and when the selectable multiple connection is selected, the weighted electrical values ​​from the first block (104-00) are connected to the second block output bus (OL-A ４－７ ) and the second analog storage element bus (AL ０－３ The first block (104-00) is provided to the block output bus (OL-A) in such a manner as to the first block (104-00) ４－７ A processing crossbar semiconductor device according to any one of claims 1 to 14, which is electrically connected to ).

16. Multiple blocks (104-00, 104-01) of at least one super row (108-0) are connected to a second block output bus (OL-A) that is not electrically connected to the first block output bus to which the first super row is connected, with weighted values ​​obtained in the first block block output bus (104-00) of the first super row (106-0). ４－７ A processing crossbar semiconductor device according to any one of claims 1 to 15, electrically connected in pairs via a plurality of selectable multiple connections in a manner that allows for the selection of the device.

17. The system evaluates whether the input vector has more elements than the element rows of the first block (104-00, 104-01) of the first super row (106-0), and if the input vector has more elements than the number of element rows in each of the first blocks (104-00, 104-01) of the first super row (106-0), then the system evaluates whether the input vector has more elements than the number of element rows in each of the first blocks (104-00, 104-01) of the first super row (106-0) and at least one second super row (106 -1) distributes electrical input values ​​to the element rows of the second block (104-10, 104-11) of the first super row (108-0) and provides selectably electrically weighted values ​​from each of the first blocks (104-00, 104-01) of the first super row (108-0) to at least one of the further blocks (104-10) of the second super row (106-1), thereby allowing the second blocks (104-10, 104-11) to be associated with the same block output bus (OL-A ４－７ A processing crossbar semiconductor device according to any one of claims 15 to 16, configured to provide both the weighted values ​​from the first block (104-00, 104-01) and the weighted values ​​from the further block (104-10, 104-11).

18. The plurality of blocks (104) include a first submultiplexity block (A) and a second submultiplexity block (B) separated from the first submultiplexity block, and the plurality of block output buses are first submultiplexity block output buses (OL-A) uniquely connected to blocks (104-00, 104-01) of the first submultiplexity block (A). ０－３ ) and a second partial plural block output bus (OL-B) uniquely connected to the block of the second partial plural block (B). ０－３ , . . , OL-B ２８－３１ A processing crossbar semiconductor device according to any one of claims 1 to 17, comprising, wherein the second partial plural block (B) is selectively activatable and deactivatable.

19. The plurality of analog storage elements include at least one first partial multiple analog storage element (AL) for storing electrically weighted values ​​from the first partial multiple block (A). ０－３ ) and a second partial-multiplex analog storage element (AL) for storing electrically weighted values ​​from the second partial-multiplex block. ２８－３１ The processing crossbar semiconductor device according to claim 18, further comprising a plurality of further storage elements, each of which is configured to store a weighted electrical value obtained by storing both a first weighted electrical value from a first analog storage element in the first partial pluralization block and a second weighted electrical value obtained from a second analog storage element in the second partial pluralization block.

20. The processing crossbar semiconductor device according to claim 19, wherein the further storage element is a digital storage element.

21. A processing crossbar semiconductor device according to any one of claims 18 to 20, wherein the device evaluates whether the output vector to be obtained has more elements than the number of elements in the element array of the first submultiplex block (A), and if the output vector has more elements than the number of elements in the element array of the first submultiplex, the number of columns of the super-column block of the second submultiplex block (B) is activated so that the number of columns of the activated super-column block matches at least the number of elements in the output vector.

22. The processing crossbar semiconductor device according to any one of claims 18 to 21, wherein the second partial pluralization block is selectively activatable and deactivatable.

23. Each analog storage element is a resistor that receives the weighted electrical values ​​from the weighted elements (101) of the same element row in a plurality of blocks of at least one super row, and as a result, each of the electrical storage weighted values ​​is the sum of the weighted electrical values, the processing crossbar semiconductor device according to any one of claims 1 to 22.

24. The processing crossbar semiconductor device according to claim 23, wherein the weighted electrical value is current, and the electrically stored weighted value is current which is the sum of the currents from the block output lines.

25. Each analog storage element is a capacitor that receives the weighted electrical values ​​from the weighted elements (101) of the same element row in a plurality of blocks of at least one super row, and as a result, each of the electrical storage weighted values ​​is the sum of the weighted electrical values ​​which are charge or voltage, according to any one of claims 1 to 24.

26. A processing crossbar semiconductor device according to any one of claims 1 to 25, configured to activate different blocks independently of each other.

27. A processing crossbar semiconductor device according to any one of claims 1 to 26, configured to simultaneously activate multiple blocks of the same super row in such a manner that weighting elements (101) connected to the same block output line provide the electrically weighted values ​​to the same block output line.

28. A processing crossbar semiconductor device according to any one of claims 1 to 27, wherein the array of electrical values ​​is configured to receive as at least a first input vector and a second input vector independent of the first input vector, the first input vector being input to a first super row of the block and the second input vector being provided to a second super row of the block.

29. The processing crossbar semiconductor device according to any one of claims 1 to 28, wherein the weighting element of each block is configured to provide its respective electrical weighted value in parallel to its respective block output line, thereby pre-accumulating the electrical weighted value on the same output line.

30. A crossbar processing device according to any one of claims 1 to 29, configured to implement a neural network according to a plurality of layers, each including an input layer, an output layer, and optionally at least one hidden layer, wherein each transition from one layer to the immediately following layer is performed by processing the analog input vector, each weight of the at least one weight tensor represents a synapse, each analog input value is a neuron, and each output value is a neuron in the immediately following layer.

31. The crossbar processing device according to claim 30, wherein the analog input vector is a kernel or a part of a kernel that is convoluted and applied to the at least one weight tensor.

32. A crossbar processing device according to any one of claims 30 to 31, configured to perform an inference phase in which the weights of the weight tensor are established and predictions are provided in response to input values, after a first phase in which the weights of the at least one weight tensor are obtained by minimizing a cost function that provides an error metric on a known dataset.

33. A method for deriving at least one output vector as a result of processing at least one input vector, wherein the at least one weight tensor has a plurality of weights, and the method comprises the step of processing each input electrical value of an array of input electrical values ​​representing the at least one input vector, the method using weighting elements (101) arranged according to element rows and element columns, each weighting element (101) corresponding to a weight of the at least one weight tensor, the set of weighting elements (101) is divided into a plurality of blocks (102), the plurality of blocks (102) are arranged according to super columns (108) and super rows (106) such that each super row includes a plurality of subsequent element rows, and each super column includes a plurality of subsequent element columns, the method using a plurality of block output buses (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , . . , OL-A ２８－３１ ) is further used, and each block output bus (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , . . , OL-A ２８－３１ ) is connected to a plurality of blocks (104-00) within each super row (102-0) without being connected to blocks (104-10, 104-11) that are associated with and connected to at least one other super row (102-1), and each block output bus (OL-A ０－３ , OL-A ４－７ , OL-A ８－１１ , . . , OL-A ２８－３１ ) consists of multiple block output lines (OL-A ０ . . . , OL-A ３１ ) and the method is The steps include: activating the weighting of the input electrical values ​​of the array of input electrical values ​​by the corresponding weights of the at least one weight tensor in order to provide electrically weighted values ​​to the block output bus associated with the super row (106-0) of which the block (104-00) is part; each analog storage element (AL0 ０ ) electrically connected to at least one block output line (OL-A ０ ) via a plurality of analog storage elements (AL0 ０ , ..., AL ３１ ), providing respective electrical accumulated weight values from said electrically weighted values obtained from said corresponding element columns of a plurality of activation blocks (104-00, 104-01) in said at least one super row (106-0) associated with said at least one block output line (OL-A ０ ); A method comprising the step of deriving an array of accumulated weighted output values ​​that form the at least one output vector.

34. A non-temporary storage unit that, when executed by a processor, stores instructions causing the processor to perform the method according to claim 33.

35. A crossbar processing device according to any one of claims 1 to 32, further comprising a controller for activating at least one of at least one block, at least one super row, at least one super column, at least one element row, at least one bypass connection, at least one partial multiplexing, and / or associating weights to each weight element, input electrical values ​​to element rows, and / or output electrical values ​​to element columns of at least one block.

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