Vias to avoid local interconnection shorts

Abstract

The semiconductor device includes a first source / drain region connected to a back-end obline (BEOL) through a first contact and a first via, and a second source / drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.

Description

Technical Field

[0001] The present invention relates generally to transistors, and more specifically to via formation in transistor structures and methods of fabricating the same. Background Art

[0002] Backside contacts provide a way to establish electrical connection to the backside of a transistor or a substrate, enabling efficient signal transmission, improved device performance, and enhanced manufacturing processes. In a typical transistor structure, the backside or substrate region is distinct from the active region where the channel and source / drain regions of the transistor are located. The electrical connection established by the backside contact provides a path for electrical signals, currents, and voltages to flow, enabling communication between different components of an integrated circuit. Summary of the Invention

[0003] According to an embodiment, a semiconductor device includes a first source / drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source / drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact, and the first source / drain region is formed over the second source / drain region.

[0004] In some embodiments, which may be combined with the previous embodiment, the lateral contact is located above the first and second source / drain regions.

[0005] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a first transistor stacked over a second transistor, and the first and second source / drain regions are located over the first and second transistors, respectively.

[0006] In some embodiments that can be combined with one or more previous embodiments, the second contact further includes a horizontally extending portion over the second source / drain region and a vertically extending portion connecting the horizontally extending portion to the lateral contact.

[0007] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a first isolation layer covering the first via. A portion of the first isolation layer is connected to the lateral contact.

[0008] In some embodiments, which may be combined with one or more previous embodiments, the first isolation layer separates the first via from direct contact with the lateral contact.

[0009] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes gate vias that connect a gate region to a BEOL.

[0010] In some embodiments, which may be combined with one or more previous embodiments, the position of the second via is offset from the centerline of the second source / drain region so as to be away from the gate region.

[0011] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a second isolation layer covering the gate via. The gate via covered by the second isolation layer passes through the lateral contact and the first and second contacts.

[0012] In some embodiments, which may be combined with one or more previous embodiments, the second isolation layer separates the gate via from direct contact with the lateral contact.

[0013] According to another embodiment, a method for forming a semiconductor device includes the steps of forming first and second source / drain regions, forming first and second contacts to the first and second source / drain regions, forming lateral contacts on the second contacts, forming first contact vias to the first source / drain region, and forming a first isolation layer covering the first contact vias, wherein the first source / drain region is formed on the second source / drain region.

[0014] In some embodiments that can be combined with the previous embodiments, the lateral contacts are located above the first and second source / drain regions, and the first isolation layer separates the first contact vias from direct contact with the lateral contacts.

[0015] In some embodiments, which may be combined with one or more previous embodiments, a first level metal layer, a second contact via to a second source / drain region, and a second separation layer covering the second contact via are formed.

[0016] In some embodiments, which may be combined with one or more previous embodiments, the first level metal layer is connected to the lateral contacts through the second contact vias.

[0017] In some embodiments, which may be combined with one or more previous embodiments, a gate contact via, a third separation layer covering the gate contact via, first and second contact metallizations, and a gate contact via metallization are formed. A portion of the third separation layer is connected to a lateral contact.

[0018] In some embodiments, which may be combined with one or more previous embodiments, the second contact is taller than the first contact.

[0019] In some embodiments, which may be combined with one or more previous embodiments, a first transistor is formed stacked on a second transistor. The first and second source / drain regions are located on the first and second transistors, respectively.

[0020] In some embodiments, which may be combined with one or more previous embodiments, the position of the second via is offset from the centerline of the second source / drain region so as to be away from the gate region.

[0021] In some embodiments, which may be combined with one or more previous embodiments, a horizontally extending portion is formed above the second source / drain region, and a vertically extending portion is formed connecting the horizontally extending portion to the lateral contact.

[0022] In yet another embodiment, the semiconductor device includes source / drain vias connecting the source / drain region to the back-end of line (BEOL), and gate vias connecting the gate region to the BEOL. The gate vias and source / drain vias are isolated from direct contact with lateral contacts through first and second dielectric isolation layers formed on the source / drain vias and gate vias, respectively.

[0023] These and other features will become apparent from the following detailed description of the exemplary embodiment, which will be read in conjunction with the attached drawings. [Brief explanation of the drawing]

[0024] The drawings are for example embodiments. They do not illustrate all embodiments. Additionally or alternatively, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or provide a more effective illustration. Some embodiments may be implemented using additional components or steps, and / or without using all of the illustrated components or steps. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0025] [Figure 1-1] 1A to 1C illustrate semiconductor devices according to some embodiments.

[0026] [Figure 1-2] 1D illustrates a top view of a semiconductor device according to some embodiments.

[0027] [Figure 2] 2A to 2C illustrate side views of a semiconductor device after front end of line (FEOL) processing according to some embodiments.

[0028] [Figure 3] 3A to 3C illustrate side views of a semiconductor device after formation of a horizontally extending portion of a second contact according to some embodiments.

[0029] [Figure 4] 4A to 4C illustrate side views of a semiconductor device after patterning of a source / drain contact according to some embodiments.

[0030] [Figure 5] 5A to 5C illustrate side views of a semiconductor device after formation of a deep contact and an inner spacer according to some embodiments.

[0031] [Figure 6]Figures 6A to 6C show side views of semiconductor devices after the formation of lateral contacts according to several embodiments.

[0032] [Figure 7] Figures 7A to 7C show side views of semiconductor devices after patterning of the first via and gate via according to several embodiments.

[0033] [Figure 8] Figures 8A to 8C show side views of semiconductor devices after spacer formation according to several embodiments.

[0034] [Figure 9] Figures 9A to 9C show side views of semiconductor devices after metallization of the first via and gate via, according to several embodiments.

[0035] [Figure 10] Figures 10A to 10C show side views of semiconductor devices after wafer bonding according to several embodiments.

[0036] [Figure 11] Figures 11A to 11C show side views of semiconductor devices after the formation of back-side interconnects according to several embodiments.

[0037] [Figure 12-1] Figure 12A shows a block diagram of a method for forming a semiconductor device according to several embodiments. [Figure 12-2] Figure 12B shows a block diagram of a method for forming a semiconductor device according to several embodiments. [Modes for carrying out the invention]

[0038] [overview] The following detailed explanation includes numerous specific details as examples to provide a thorough understanding of the relevant teachings. However, it is clear that these teachings can be carried out without such details. In other instances, well-known methods, procedures, components, and / or circuit configurations are described at a relatively high level without detail to avoid unnecessarily obscuring aspects of these teachings.

[0039] In one embodiment, spatially related terms such as “front,” “back,” “top,” “bottom,” “down,” “below,” “up,” “top,” “side,” “left,” and “right” are used with reference to the orientation of the figure being described. Components of embodiments of this disclosure may be positioned in several different orientations, and the orientation terms are used for illustrative purposes only, not for limitation. Therefore, spatially relative terms should be understood as intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figure. For example, if the device in the figure is inverted, an element described as being “below” or “below” another element or feature will then be oriented “above” that other element or feature. Therefore, for example, the term “down” may encompass both downward and upward orientations. The device may be oriented in other ways (rotated 90 degrees or seen or referenced in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0040] As used herein, the terms “lateral” and “horizontal” refer to an orientation parallel to the first surface of the chip.

[0041] As used herein, the term “perpendicular” refers to an orientation in which a chip, chip carrier, or semiconductor body is positioned perpendicular to the first surface.

[0042] As used herein, the terms “joined” and / or “electrically coupled” do not mean that elements must be directly coupled together—intermediate elements may be provided between “joined” or “electrically coupled” elements. In contrast, when one element is referred to as “directly connected” or “directly coupled” to another, there is no intermediary element. The term “electrically connected” refers to a low-resistance electrical connection between electrically connected elements.

[0043] In this specification, terms such as "first," "second," etc., may be used to describe various elements, but these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be called the second element, and similarly, the second element may be called the first element. As used herein, the term "and / or" includes any combination of one or more items from the associated listed items.

[0044] Exemplary embodiments are described herein with reference to schematic cross-sectional views of idealized or simplified embodiments (and intermediate structures). Therefore, deformations of the shapes shown in the figures may be expected, for example, as a result of manufacturing methods and / or tolerances. Thus, the areas shown in the figures are essentially schematic, and their shapes do not necessarily represent, nor limit, the actual shapes of the areas of the device.

[0045] It should be understood that other embodiments may be used and structural or reasonable modifications may be made without departing from the scope defined in the claims. The description of embodiments is not limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0046] In this specification, certain terms are used to describe what may be considered idealized behavior, such as "lossless," "superconductor," or "superconducting," which are intended to cover functionality that is within acceptable margins in a given application, although it may not be strictly ideal. For example, a certain level of loss or tolerance may be acceptable, so that the resulting materials and structures can still be described using these "idealized" terms.

[0047] According to one embodiment, the semiconductor device includes a first source / drain region connected to a back-end obline (BEOL) through a first contact and a first via, and a second source / drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact. The first source / drain region is formed on the second source / drain region. Therefore, the first source / drain region is connected to the BEOL through the first via.

[0048] In some embodiments that can be combined with the previous embodiments, the lateral contact is located above the first and second source / drain regions. Therefore, the lateral contact may be closer to the BEOL than the first and second source / drain regions.

[0049] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a first transistor stacked on a second transistor. The first and second source / drain regions are located on the first and second transistors, respectively. Thus, the semiconductor device may be used to connect stacked transistors to a common BEOL.

[0050] In some embodiments, which may be combined with one or more previous embodiments, the second contact further includes a horizontally extending portion over the second source / drain area and a vertically extending portion connecting the recessed contact to the lateral contact. The vertically extending portion is less thick than the horizontally extending portion. Therefore, the second contact requires less space, which may reduce the risk of short circuits.

[0051] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a first isolation layer covering the first via. A portion of the first isolation layer is connected to the lateral contact. Thus, the first via is isolated from other elements.

[0052] In some embodiments, which may be combined with one or more previous embodiments, the first isolation layer separates the first via from direct contact with the lateral contact. Thus, the risk of a short circuit between the lateral contact and the first via is reduced.

[0053] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes gate vias that connect the gate region to the BEOL. Thus, the gate region is connected to the BEOL.

[0054] In some embodiments, which may be combined with one or more previous embodiments, the position of the second via is offset from the centerline of the second source / drain region away from the gate region. Thus, the risk of metal short circuits is reduced.

[0055] In some embodiments, which may be combined with one or more previous embodiments, the semiconductor device includes a second isolation layer covering the gate via. The gate via covered by the second isolation layer passes through the lateral contact and the first and second contacts. Therefore, there is no direct contact between the first contact, the second contact and the via contact.

[0056] In some embodiments, which may be combined with one or more previous embodiments, the second isolation layer separates the gate via from direct contact with the lateral contact. Thus, the risk of lateral contact between the gate via and the lateral contact is reduced.

[0057] According to another embodiment, a method for forming a semiconductor device includes the steps of forming first and second source / drain regions, forming first and second contacts to the first and second source / drain regions, respectively, forming lateral contacts on the second contacts, forming first contact vias to the first source / drain region, and forming a first isolation layer covering the first contact vias, wherein the first source / drain region is formed on the second source / drain region. Thus, the risk of metal short circuits is reduced.

[0058] In some embodiments that can be combined with the previous embodiments, the lateral contact is located above the first and second source / drain regions, and the first isolation layer separates the first contact via from direct contact with the lateral contact. Thus, the risk of a short circuit between the first contact via and the lateral contact is reduced.

[0059] In some embodiments, which may be combined with one or more previous embodiments, a first level metal layer, a second contact via to a second source / drain region, and a second separation layer covering the second contact via are formed. Thus, the risk of metal short circuits is reduced.

[0060] In some embodiments, which may be combined with one or more previous embodiments, the first level metal layer is connected to the lateral contacts through the second contact vias. Thus, the lateral contacts are connected to the BEOL through the first level metal layer.

[0061] In some embodiments, which may be combined with one or more previous embodiments, a gate contact via, a third isolation layer covering the gate contact via, first and second contact metallizations, and a gate contact via metallization are formed. A portion of the third isolation layer is connected to a lateral contact. Thus, the risk of gate contact vias and lateral contacts is reduced.

[0062] In some embodiments, which may be combined with one or more previous embodiments, the second contact is taller than the first contact. This ensures that the second source / drain region located at the bottom of the semiconductor device is connected to the base-of-loop (BEOL).

[0063] In some embodiments, which may be combined with one or more previous embodiments, a first transistor is formed stacked on a second transistor. The first and second source / drain regions are located on the first and second transistors, respectively. Thus, the semiconductor device can be used in multilayer semiconductor applications.

[0064] In some embodiments, which may be combined with one or more previous embodiments, the position of the second via is offset from the centerline of the second source / drain region away from the gate region. Thus, the risk of metal short circuits is reduced.

[0065] In some embodiments, which may be combined with one or more previous embodiments, a horizontally extending portion is formed above the second source / drain region, and a vertically extending portion is formed connecting the horizontally extending portion to the lateral contact. The vertically extending portion is less thick than the horizontally extending portion. Therefore, the second contact requires less space, which may reduce the risk of short circuits.

[0066] In yet another embodiment, the semiconductor device includes source / drain vias connecting the source / drain region to the back-end of line (BEOL), and gate vias connecting the gate region to the BEOL. The gate vias and source / drain vias are isolated from direct contact with lateral contacts through first and second dielectric isolation layers formed on the source / drain vias and gate vias, respectively. Thus, both the source / drain region and the gate region are connected to the BEOL.

[0067] The concepts described herein relate to multilayer field-effect transistors (FETs), fundamental electronic devices that have revolutionized the field of electronics and the way in which various elements of transistors are electrically connected. Multilayer FETs are a type of transistor architecture that improves functionality and advantages in integrated circuit (IC) design. Multilayer FETs involve stacking multiple FETs vertically, enabling improved performance and increased integration density.

[0068] Pin access refers to accessing or the method of accessing individual FETs within a multilayer FET, for example, for testing or debugging purposes. The series arrangement of multilayer FETs can make interaction with individual FETs difficult. Unlike standard configurations, in typical multilayer FETs, the shadowing effect of the top source / drain can severely restrict the first-level metal layer (M1 track) relative to the bottom source / drain.

[0069] In recent years, the use of local interconnects in multilayer FET configurations has attracted attention. However, there are challenges to using local interconnects. These challenges include increased complexity in the design and fabrication process, potential signal matching problems due to the proximity of interconnects, and the possibility of short circuits between local interconnects and nearby contact structures, particularly gate contacts over the active region.

[0070] To address the aforementioned problems, a multilayer FET utilizing local interconnects (hereinafter referred to as "lateral contacts") and a semiconductor device having gate and source / drain contact vias that avoid short circuits between the source / drain contacts and the lateral contacts are disclosed. For this purpose, the contact vias and source / drain vias are isolated from each other by an isolation layer. Such electrically isolated vias ensure that short circuits between contacts are reliably avoided.

[0071] Accordingly, the teachings herein provide a method and system for forming semiconductor devices using lateral contacts. The technique described herein can be implemented in several ways. Exemplary implementations are provided below with reference to the following figures. [Exemplary semiconductor device with lateral contact structure]

[0072] Here, we refer to Figures 1A to 1C, which show simplified cross-sectional views of the semiconductor device 100 according to an exemplary embodiment. Figure 1D shows a top view of the semiconductor device 100. For example, Figures 1A and 1B show an X cross-section of the semiconductor device, Figures 1B and 1C show a Y1 cross-section of the semiconductor device, and Figures 1C show a Y2 cross-section of the semiconductor device.

[0073] In various embodiments, the semiconductor device 100 is a stacked FET that utilizes the vertical dimension of the semiconductor device 100 to increase the number of active devices within a given area. In this way, instead of relying solely on lateral scaling to reduce the size of semiconductor devices on a semiconductor substrate, stacking FETs vertically makes it possible to incorporate multiple layers of semiconductor devices. This arrangement enables increased circuit complexity and enhanced functionality.

[0074] In some embodiments, the stacked FET structure of the semiconductor device 100 can increase integration density by utilizing the vertical dimension of the semiconductor device 100. In such embodiments, instead of relying solely on limited lateral scaling, stacking FETs on top of the semiconductor device 100 increases the number of transistors within a given chip area. This increase in transistor count allows for the integration of more complex circuits, larger memory arrays, and other functional blocks, thereby improving the capabilities of the semiconductor device 100.

[0075] The disclosed semiconductor device 100 may include a first source / drain region 110a and a second source / drain region 110b, a first contact 112a, a second contact 112b, a lateral contact 114, a backside contact (BSCA) 116, a gate region 118, an interlayer dielectric (ILD) 120, a bottom dielectric isolation (BDI) 122a, a middle dielectric isolation (MDI) 122b, a placeholder 124, a first via 126a, a second via 126b, a gate via 126c, a backside obline (BEOL) 128, one or more gate cut regions 130, a backside interconnect 132, and a first level metal layer (M1 track) 134.

[0076] In some embodiments, the first source / drain region 110a is located on the first transistor, and the second source / drain region 110b is located on the second transistor. In such embodiments, the first transistor is stacked on top of the second transistor.

[0077] Generally, the first source / drain region 110a and the second source / drain region 110b are two main components that play relevant roles in the operation of a semiconductor device. In various embodiments, the first source / drain region 110a and the second source / drain region 110b are regions within a semiconductor material, e.g., a semiconductor device 100, through which current flows in and out of the semiconductor device 100. The source region is the region through which the majority of charge carriers (e.g., electrons or holes) enter the channels of the semiconductor device, and is responsible for providing the current that flows through the semiconductor device. The source region is typically doped to have excess charge carriers, thereby creating a region with a high carrier concentration. Such carrier abundance makes it possible to efficiently inject electrons or holes into the channels when a voltage is applied.

[0078] On the other hand, the drain region is the region where most charge carriers exit the channel. The drain region receives current from the channel and carries charge away from the transistor. Similar to the source, the drain region is doped to have a high carrier concentration. The doping profile within the drain region ensures that carriers can easily flow out of the channel and into the drain region. In some embodiments, the first source / drain region 110a is located above the first transistor, and the second source / drain region 110b is located above the second transistor. The first transistor may be stacked on top of the second transistor to form a semiconductor device 100.

[0079] The first contact 112a, located above the first source / drain region 110a, establishes a connection between the first source / drain region 110a and the BEOL 128. The first contact 112a ensures efficient electrical routing and connectivity within the semiconductor device 100. The fabrication of the first contact 112a includes lithography and etching processes to define the contact area. The first contact 112a can be fabricated using conductive materials such as silicide liners such as Ni, Ti, and NiPt, adhesive metal layers such as TiN, and conductive metal fillers such as tungsten (W), Co, or Ru.

[0080] The second contact 112b, located above the second source / drain region 110b, establishes a connection between the second source / drain region 110b and the lateral contact 114. The second contact 112b ensures efficient electrical routing and connectivity within the semiconductor device 100. Fabrication of the second contact 112b involves lithography and etching processes to define the contact area. The second contact 112b can be fabricated using conductive materials such as silicide liners such as Ni, Ti, and NiPt, adhesive metal layers such as TiN, and conductive metal fillers such as tungsten (W), Co, or Ru.

[0081] The lateral contact 114 can create a conduction path or link within the semiconductor device 100, connecting the second source / drain region 110b to a first-level metal layer, i.e., the M1 track, which is shadowed by the first source / drain region 110a. Such a connection can improve routing flexibility. Without the lateral contact 114, the second source / drain region 110b can only access the first-level metal layer (M1 track) 134, which is directly above the second contact 112b. In some embodiments, the lateral contact 114 is located above the first source / drain region 110a and the second source / drain region 110b. In some embodiments, as shown in Figure 1A, the position of the lateral contact 114 may be offset from the centerline 140 of the second source / drain region 110b, away from the gate region 118.

[0082] BSCA116 is the back-side region of the semiconductor device 100 where electrical connections are made. By establishing electrical contact, BSCA116 ensures the proper functioning of the semiconductor device 100 and facilitates the transmission of electrical signals.

[0083] The BSCA116 can act as a thermal interface between the semiconductor device 100 and a heat sink or other cooling mechanism. By establishing direct contact with the substrate, the BSCA116 can remove heat from the semiconductor device 100 and contribute to improved heat dissipation. In some embodiments, the BSCA116 can help reduce parasitic effects such as substrate coupling or substrate noise from the semiconductor device 100. In further embodiments, the BSCA116 can enable increased integration density in the semiconductor device 100. In one embodiment, the BSCA116 connects (i.e., wires) the second source / drain region 110b to the back surface interconnect.

[0084] In various embodiments, the gate region 118 acts as a control element that manages the flow of current through the semiconductor device 100. The gate region 118 may be made of a conductive material. The gate region 118 can control the flow of current between the source and drain regions. In some embodiments, the conductivity of the channel region is adjusted by applying a voltage to the gate, thereby allowing the semiconductor device 100 to allow or block the flow of current, and as a result, the semiconductor device 100 can act as an electronic switch or amplifier. The gate voltage can be used to determine whether the semiconductor device 100 is in an "on" or "off" state. If the gate voltage is below a certain threshold, the semiconductor device 100 is in an "off" state, and the flow of current between the source and drain is effectively blocked. On the other hand, if the gate voltage is above the threshold, the semiconductor device 100 enters an "on" state, allowing current to flow through the channel region. In addition to acting as a switch, by adjusting the gate voltage, the gate region 118 can control the current flowing through the channel region, and as a result, the output signal can be amplified.

[0085] In some embodiments, the gate region 118 can enable the implementation of Boolean logic operations such as AND, OR, and NOT by controlling the flow of current based on the input voltage. Multiple semiconductor devices can be interconnected to form complex logic circuits, enabling the execution of various computational tasks in digital systems. In some embodiments, the gate region 118, together with other semiconductor device components, can facilitate the miniaturization and integration of electronic circuits. The ability to control the conductivity of the channel region through the gate voltage enables compact and highly efficient circuit design.

[0086] The ILD120 may be a layer of insulating material for electrically isolating different layers of conductive and active components and providing mechanical support between these layers. The ILD120 can enable efficient signal transmission, reduce crosstalk, and ensure proper functioning of the semiconductor device 100. In some embodiments, the ILD120 can electrically isolate adjacent conductive layers or active components within the semiconductor device 100. By providing insulation between different layers, the ILD120 can prevent electrical shorts, reduce leakage current (e.g., minimize it), and ensure that signals are directed only along the desired path. In some embodiments, the ILD120 can help reduce parasitic capacitance between adjacent metal interconnects or active devices and provide mechanical support to the structure of the semiconductor device.

[0087] The BDI 122a can electrically isolate individual components within the semiconductor device 100 and provide electrical isolation between each FET in the multilayer FET. In other words, the BDI 122a can ensure that the operation of one component does not interfere with the operation of other components. By using a dielectric layer, which is an insulating layer that does not conduct electricity, the BDI 122a effectively prevents electrical crosstalk between different components, allowing each to operate independently. Furthermore, by electrically isolating each transistor from other transistors, the BDI 122a reduces the potential for crosstalk, which is the undesirable transmission of signals between circuit elements, thereby improving the overall performance of the semiconductor device 100.

[0088] The BDI 122a helps prevent a failure in one transistor from affecting others by isolating each transistor. This can improve the overall reliability of the device. Furthermore, the BDI 122a allows each transistor in the stack to be accessed and controlled independently, thus increasing flexibility in device design. This can be beneficial in a variety of applications where it may be necessary to activate or deactivate specific transistors based on certain conditions. In some embodiments, the BDI 122a can help reduce parasitic capacitance associated with transistors, which can result in shorter switching times and improved performance.

[0089] Similar to BDI 122a, MDI 122b can electrically isolate individual components within the semiconductor device 100 and provide electrical isolation between each FET in the multilayer FET. That is, MDI 122b can ensure that the operation of one component does not interfere with the operation of other components. By using a dielectric layer, which is an insulating layer that does not conduct electricity, MDI 122b effectively prevents electrical crosstalk between transistors, allowing each to operate independently. Furthermore, by electrically isolating each transistor from other transistors, MDI 122b reduces the potential for crosstalk, which is the undesirable transmission of signals between circuit elements, thereby improving the overall performance of the semiconductor device 100.

[0090] The MDI 122b helps prevent a failure in one transistor from affecting others by isolating each transistor. This can improve the overall reliability of the device. Furthermore, the MDI 122b allows each transistor in the stack to be accessed and controlled independently, thus increasing flexibility in device design. This can be beneficial in a variety of applications where it may be necessary to activate or deactivate specific transistors based on certain conditions. In some embodiments, the MDI 122b can help reduce parasitic capacitance associated with transistors, which can result in shorter switching times and improved performance.

[0091] In some embodiments, the placeholder 124 can be epitaxially grown. The use of the placeholder 124 provides greater flexibility in the fabrication process and can enable the creation of complex geometries or the integration of different types of materials.

[0092] The first via 126a establishes an electrical connection between the first source / drain region 110a and the BEOL 128 through the first contact 112a. The fabrication of the first via 126a may involve a series of processes including at least one of lithography, etching, and deposition. The first via 126a may be formed using conductive materials such as an adhesive metal layer such as TiN and conductive metal fillers such as tungsten (W), Co, Cu, or Ru. The presence of the first via 126a enables improved electrical connectivity (e.g., optimal), contributing to improved device performance and reduced power loss.

[0093] In some embodiments, the semiconductor device 100 may include a first isolation layer 138a. The first isolation layer 138a may cover a first via 126a. In such embodiments, a portion of the first isolation layer 138a is connected to a lateral contact 114. In other words, the first isolation layer 138a can isolate the first via 126a from direct contact with the lateral contact 114. Thus, the first isolation layer 138a can ensure that the lateral contact 114 and the first via 126a do not interfere with each other's operation. Furthermore, the first isolation layer 138a may be a non-conductive, i.e., insulating layer that can be made from a material such as silicon dioxide (SiO2) or silicon nitride (Si3N4). In various embodiments, the first isolation layer 138a is a dielectric material.

[0094] In various embodiments, the first via 126a is connected to the BEOL 128 via the M1 track 134. In one embodiment, the M1 track may be used to connect various elements of the semiconductor device 100 to the BEOL 128.

[0095] The second via 126b connects the lateral contact 114 to the BEOL 128. The second via 126b can establish an electrical path between the lateral contact 114 and the BEOL 128. The fabrication of the second via 126b involves lithography, etching, and deposition processes similar to those used for the first via. The second via 126b may be formed using materials such as an adhesive metal layer, such as TiN, and a conductive metal filler, such as tungsten (W), Cu, Co, or Ru.

[0096] Similarly, the gate via 126c can connect the gate region 118 to the BEOL 128. Like the first via 126a and the second via 126b, the gate via 126c may be formed using conductive materials such as an adhesive metal layer such as TiN and conductive metal fillers such as Cu, tungsten (W), Co, or Ru. In one embodiment, a second isolation layer 138b can cover the gate via 126c. In such an embodiment, a portion of the second isolation layer 138b is connected to the lateral contact 114. The second isolation layer 138b can isolate the gate via 126c from direct contact with the lateral contact 114. Thus, the second isolation layer 138b can ensure that the lateral contact 114 and the gate via 126c do not interfere with each other's operation. Furthermore, the second isolation layer 138b may be a non-conductive, i.e., insulating layer that can be made from a material such as silicon dioxide (SiO2) or silicon nitride (Si3N4). In various embodiments, the second isolation layer 138b is a dielectric. The first isolation layer 138a and the second isolation layer 138b may be made of the same material.

[0097] In some embodiments, the first isolation layer 138a and the second isolation layer 138b provide electrical isolation between different components on the semiconductor device 100, preventing undesirable current flow between different parts of the semiconductor device 100 and helping to reduce crosstalk or interference. Thus, the first isolation layer 138a and the second isolation layer 138b can promote the proper functioning of each individual component by maintaining the integrity and stability of their individual operation.

[0098] The functionality of the semiconductor device can depend on the combination of the first via 126a, the second via 126b, the gate via 126c, the first contact 112a, the second contact 112b, and the lateral contact 114. Collectively, these elements enable efficient electrical connection between the first source / drain region 110a and the second source / drain region 110b and the BEOL 128. The semiconductor device 100 can achieve the effects of improved power distribution, reduced signal loss, and improved signal transmission efficiency. [Exemplary process for semiconductor devices with lateral contact structures]

[0099] Along with the above description of the exemplary semiconductor device 200, it would be useful to discuss an exemplary process for manufacturing it. To this end, Figures 2-11 show various steps in the manufacturing of the semiconductor device 200 according to an exemplary embodiment. As mentioned above, Figures A, B, and C show the manufacturing process of the semiconductor device 100 from different perspectives. Note that the semiconductor device 100 shown in Figures 1A-1C may be the same as the semiconductor device 200 shown in Figures 2-11. For the sake of clarity, the manufacturing process described therein is explained in the context of forming a multilayer transistor. The multilayer transistor is manufactured to include a bottom transistor and a top transistor. The bottom transistor is manufactured to include a bottom source / drain region, and the top transistor is manufactured to include a top source / drain region.

[0100] Here, refer to Figures 2A-2C showing the semiconductor device 200 after front-end-of-line (FEOL) processing. Once FEOL processing is performed, the semiconductor 200 may include an etching stop layer 210 between the first substrate 212a and the second substrate 212b, a bottom dielectric isolation (BDI) 214, a placeholder 216, a bottom source / drain region 218a, a top source / drain region 218b, an intermediate dielectric isolation (MDI) 220, a nanosheet gate 222, a gate spacer 224, an inner spacer 226, an interlayer dielectric (ILD) 228, a gate region 230, a gate cap 232, and a gate cut region 234.

[0101] In the examples shown in Figures 2A to 2C, the semiconductor device 200 is shown as being on silicon as the first substrate 212a and the second substrate 212b. However, it will be clear that other types of substrates can also be used, including but not limited to single-crystal Si, silicon-germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulators (SOI). III-V compound semiconductors include materials having at least one group III element and at least one group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), indium aluminum arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), aluminum gallium antimonide (GaAlSb), gallium arsenide (GaAs), gallium antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and one or more combinations of alloys containing at least one of the above materials. The alloy combinations can include binary (two elements, such as gallium(III) arsenide (GaAs)), ternary (three elements, such as InGaAs), and quaternary (four elements, such as aluminum-gallium-indium phosphide (AlInGaP)) alloys.

[0102] In various embodiments, the first substrate 210a and the second substrate 210b may include any suitable material or combination of materials, such as doped or undoped silicon, glass, or dielectric. For example, the substrate may include, for example, a silicon-on-insulator (SOI) structure with a buried insulating layer, or a bulk material substrate having appropriately doped regions, usually referred to as wells. In another embodiment, the substrate may be silicon with silicon oxide, nitride, or any other insulating film on top.

[0103] In various embodiments, an etching stop layer 210 is formed on the first substrate 212a. The etching stop layer 210 is a thin layer of material incorporated into the structure of the semiconductor device 200, which may provide a selective barrier to the etching process and prevent further removal of underlying material during fabrication. The etching stop layer 210 allows for precise control over the etching depth and helps define the desired device dimensions. The etching stop layer 210 can further provide stopping points for the etching process, ensuring that a particular layer or region is not etched beyond a specific point, resulting in precise patterning and control of important features. The etching stop layer 210 can create clear separation between different layers or components within the device structure, preventing undesirable etching of underlying layers or materials, and enabling the creation of complex multilayer structures with clearly defined interfaces and boundaries. In some embodiments, the etching stop layer 210 acts as a protective barrier for highly sensitive or delicate materials, protecting such materials from aggressive etching solutions and preventing damage or degradation in subsequent fabrication steps.

[0104] In some embodiments, the first substrate 212a is prepared by washing and removing any impurities or oxide layers before forming the etching stop layer 210. The etching stop layer 210 is deposited on the first substrate 212a using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, a photoresist can be applied, exposed to a patterned mask, developed, and used as a protective layer to define the etching stop region. The etching stop layer 210 can then be selectively etched and stopped at a predetermined depth while protecting the underlying layers. After the etching process, the remaining photoresist can be removed through a stripping technique. In some embodiments, SiGe is used to form the etching stop layer 210, but in some embodiments, silicon nitride (SiN) or silicon oxynitride (SiON) can be used as the etching stop layer 210. In some embodiments, a second substrate 212b is epitaxially grown on the etching stop layer 210.

[0105] In some embodiments, the nanosheet (e.g., nanosheet gate) 222 may be formed of alternating layers of Si and SiGe (not shown), where the sidewalls of the SiGe layer are recessed and covered with an inner spacer 226. The SiGe layer can then be removed and replaced with a gate region material.

[0106] The gate spacer 224 may be a thin insulating layer or material placed on the sidewalls of the gate region 230 and gate cap 232. The gate spacer 224 can help control the effective channel length of the semiconductor device 200. In various embodiments, the gate region 230 and gate cap 232, together with the gate spacer 224, can define a current-flow region between the bottom source / drain region 218a and the top source / drain region 218b.

[0107] In some embodiments, the gate spacer 224 can function as an insulating layer between the gate region 230 and the bottom source / drain region 218a and the top source / drain region 218b. That is, the gate spacer 224 helps prevent current leakage or short circuits between the gate region 230 and the bottom source / drain region 218a and the top source / drain region 218b. Such isolation can help maintain the electrical integrity of the semiconductor device and prevent unintended current flows that could adversely affect the performance and reliability of the semiconductor device 200.

[0108] In a further embodiment, the gate spacer 224 may be used to adjust the overlap capacitance between the gate region 230 and the bottom source / drain region 218a and the top source / drain region 218b. The overlap capacitance can affect the electrical properties of the semiconductor device, such as threshold voltage and switching operation. Therefore, by adjusting the thickness and material properties of the gate spacer 224, the overlap capacitance can be optimized, which may allow for better control and adjustment of the operation of the semiconductor device.

[0109] In some embodiments, the gate spacer 224 helps mitigate short-channel effects by physically separating the gate region 230 from the bottom source / drain region 218a and the top source / drain region 218b. To this end, the gate spacer 224 can create a barrier that limits the electric field from spreading into the channel region, thereby reducing the effects of drain-induced barrier drop and subthreshold leakage. This mitigation can improve the performance of the semiconductor device, reduce power consumption, and improve overall device reliability. In some embodiments, the bottom source / drain region 218a and the top source / drain region 218b are separated from the gate cap 232 by the gate spacer 224.

[0110] In one embodiment, the gate spacer 224 can act as a barrier during the doping process to prevent lateral diffusion of dopant atoms from the bottom source / drain region 218a and the top source / drain region 218b into the channel region. Such diffusion can alter the channel characteristics and impair the performance of the semiconductor device. By confining dopant diffusion, the gate spacer 224 can contribute to maintaining the desired characteristics and electrical behavior of the semiconductor device.

[0111] In some embodiments, the gate spacer 224 may be formed on the sidewall of the gate region 230. The gate spacer 224 may be formed by a deposition technique. Alternatively, the gate spacer 224 may be formed by etching or selectively epitaxially growing the gate spacer 224 on the sidewall of the gate region 230. In some embodiments, the gate spacer 224 may contain SiGe.

[0112] In one embodiment, the inner gate spacer 226, like the gate spacer 224, can function as an insulating layer between the gate region 230 and the bottom source / drain region 218a and the top source / drain region 218b. In various embodiments, the inner gate spacer 226 may be the same as the gate spacer 224 and is formed on the portion of the gate region 230 confined between the nanosheet gates 222.

[0113] ILD 228 can be deposited on a substrate using various techniques such as CVD, spin-on deposition, plasma-enhanced CVD (PECVD), or ALD. In some embodiments, planarization techniques are employed after deposition to ensure a flat and smooth surface. In some embodiments, chemical mechanical polishing (CMP) can be used to remove excess material and achieve a uniform surface topography. In some embodiments, silicon dioxide (SiO2) or low-k dielectrics, such as organic silicates, fluorinated silicates, or porous materials, can be used as ILD 228. Alternatively, polymeric materials such as polyimide or polybenzoxazole (PBO) can be used as ILD 228.

[0114] The gate cap 232 may be formed on multiple gate regions. In some embodiments, the gate cap 232 may be made of the same material as the gate spacer 224 and the inner gate spacer 226.

[0115] In some embodiments, the gate region 230 may include a gate dielectric and a thin layer (not shown) of gate metal. The gate metal may be separated from the gate channel by a gate dielectric such as SiO2, HfO2, or HfLaOX.

[0116] The gate cut regions 234 form areas across the semiconductor device 200 where the gate regions 230 are removed, creating discontinuous gates and dividing the stack into individual FET units. In some embodiments, the gate cut regions 234 can physically disconnect these continuous gate regions 230, allowing for independent control of each FET in the stack. The gate cut regions 234 help reduce crosstalk between individual FETs in the stack, improving the overall performance of the semiconductor device 200. Furthermore, by isolating each FET in the stack, the gate cut regions 234 prevent a failure in one transistor from affecting others, thereby improving the overall reliability of the semiconductor device 200. In some embodiments, the gate cut regions 234 provide flexibility in semiconductor device design by allowing individual FETs in the stack to be independently accessed and controlled, which can be advantageous in custom circuit design. In some embodiments, the use of gate cut regions 234 allows for the application of different gate voltages to different FETs in the stack, enabling fine-tuning of the semiconductor device characteristics after fabrication.

[0117] In various embodiments, the first dielectric isolation layer is formed by depositing the first isolation dielectric layer using methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0118] Figures 3A-3C show side views of semiconductor devices after contacts have been formed on the bottom source / drain region according to several embodiments. In one embodiment, contact 310 may be formed on the bottom source / drain region. Contact 310 may be recessed after chemical mechanical polishing (CMP) is performed.

[0119] Figures 4A to 4C show side views of semiconductor devices after patterning of the contact area with respect to the top source / drain region, according to several embodiments. In one embodiment, a portion of the ILD above the top source / drain region is removed to form a cavity. Subsequently, the contact area with respect to the top source / drain region 410 is formed above the top source / drain region by metallization of the cavity with a suitable metal.

[0120] Figures 5A to 5C show side views of semiconductor devices after the formation of a deep contact area for the bottom source / drain region, according to several embodiments. In one embodiment, a first additional layer of ILD can be formed on the top surface of the semiconductor device 200 to cover the entire surface of the semiconductor device 200.

[0121] By removing a portion of the first additional layer of the ILD, a cavity can be formed that extends from the top surface of the semiconductor device 200 to the top surface of the contact above the bottom source / drain region.

[0122] In some embodiments, the second contact may include a horizontally extending portion 520 and a vertically extending portion 530. The horizontally extending portion 520 may be located above the second source / drain region, and the vertically extending portion 530 may connect the horizontally extending portion 520 to the lateral contact. In additional embodiments, the vertically extending portion 530 may be substantially higher (e.g., deeper) than the horizontally extending portion 520. The vertically extending portion 530 may then be formed by filling the cavity with a suitable material, thereby connecting the contact above the bottom source / drain region, e.g., the horizontally extending portion 520, to the top of the first additional layer of the ILD.

[0123] Figures 6A to 6C show side views of semiconductor devices after the formation of lateral contacts according to several embodiments. In some embodiments, a second additional layer of ILD is formed on the semiconductor device 200. A portion of the second additional layer of ILD may be removed from the top surface of the semiconductor device 200 so as to reach the top surface of the deep contact area. In some embodiments, the removed portion of the second additional layer of ILD forms an area substantially larger than the top surface of the deep contact area. Subsequently, the lateral contact 610 is formed within the removed portion of the second additional layer of ILD. Thus, the lateral contact 610 can connect the bottom source / drain region to the top surface of the semiconductor device 200 via the deep contact area and the contact area above the bottom source / drain region.

[0124] Figures 7A to 7C show side views of semiconductor devices after patterning of gate vias and source / drain vias according to several embodiments. In one embodiment, a third additional layer of ILD is formed on the top surface of the semiconductor device 200. Next, a first portion of the ILD layer is removed from the top surface of the semiconductor device 200 to reach the top of the gate region. As a result, a first cavity 710 is formed on the gate region. Similarly, a second portion of the ILD layer is removed from the top surface of the semiconductor device 200 to reach the top of the contact area for the top source / drain region. As a result, a second cavity 720 is formed on the contact area for the top source / drain region.

[0125] Figures 8A to 8C show side views of semiconductor devices after spacer formation according to several embodiments. In one embodiment, a layer of spacer is formed on the side walls of the first cavity 810 and the second cavity 820. The spacer may be a separation material for separating the cavities from local interconnections in contact with the cavities.

[0126] Figures 9A to 9C show side views of semiconductor devices after metallization of gate and source / drain region vias according to several embodiments. In one embodiment, the first and second cavities are filled with a suitable material to form the first via 910 and the second via 920.

[0127] Figures 10A to 10C show side views of semiconductor devices after wafer bonding according to several embodiments. In some embodiments, back-end obline (BEOL) and wafer bonding are performed.

[0128] In various embodiments, carrier wafer bonding, also known as wafer-to-wafer bonding or chip-to-wafer bonding, is performed to join two semiconductor devices by creating a permanent bond between them. In some embodiments, two semiconductor devices can be brought into contact and bonded at the atomic or molecular level to create an interface. In some embodiments, two semiconductor devices are brought into contact under controlled conditions, such as controlled pressure and temperature, to enable atomic or molecular bonding at the interface. Such bonding can be performed at room temperature or high temperature. Alternatively, in some embodiments, an electric field and high temperature are used to create the bond. One semiconductor device may be made of a semiconductor material, and the other semiconductor device may be a glass or silicon dioxide (SiO2) wafer. An electric field can cause ions in the glass or SiO2 to move and chemically bond with the semiconductor material in the other semiconductor device. In additional embodiments, a thin metal layer or metal alloy may be used as an intermediate bonding layer between semiconductor devices. A metal layer 1410 can be deposited or transferred onto the surface of one or both semiconductor devices, and then the semiconductor devices can be brought into contact and exposed to temperature and pressure to create a metal bond 1420.

[0129] Figures 11A-11B show side views of semiconductor devices after the backside interconnects have been patterned, according to several embodiments. In some embodiments, the wafer is inverted and the first substrate is removed. The removal process of the first substrate can proceed until the etching stop layer is reached. For simplicity, the semiconductor device 200 is not shown in the inverted state. In some embodiments, the etching stop layer is removed, and then the remaining substrate, i.e., the second substrate, is removed. The backside ILD (BILD) 1110 is formed below the BDI and surrounds the placeholder and STI. In some embodiments, after the formation of the BILD 1110, a further CMP process is performed.

[0130] BILD 1110 may be an insulating material or layer used to separate the active region of a semiconductor device from the BSCA 1120 and provide electrical insulation between them, and to prevent undesirable electrical contact between the active region and the back contacts, thereby ensuring proper function and integrity of the semiconductor device 200. In various embodiments, BILD 1110 can function as a protective layer, protecting the active region of the semiconductor device 200 from external contaminants, moisture, and mechanical stress. BILD 1110 further helps prevent physical damage such as scratches or particle contamination that could adversely affect the performance of the semiconductor device. Furthermore, BILD 1110 can function as a barrier against the intrusion of moisture that could cause corrosion and degradation of the components of the semiconductor device. In some embodiments, the placeholder may be removed, resulting in the formation of a recess that exposes the bottom of the first source / drain region. The BSCA 1120 is formed within the recess by filling with a metal contact material. A back-side interconnect 1130 is formed to cover the BSCA 1120 and BILD 1110. The back-side interconnect 1130 can be used to connect the semiconductor device 200 to other devices.

[0131] Figures 12A-12B show block diagrams of method 1200A for forming a semiconductor device according to several embodiments. Referring to Figure 12A, method 1200A begins with the formation of first and second source / drain regions, as shown in block 1210. The first source / drain region may be part of the first transistor stacked on top of the second transistor, and the second source / drain region may be part of the second transistor.

[0132] In one embodiment, method 1200A proceeds to form first and second contacts to first and second source / drain regions, as shown in block 1220. The second contact may include a horizontally extending portion over the second source / drain region and a vertically extending portion connecting the horizontally extending portion to the lateral contact.

[0133] In some embodiments, method 1200A continues so that a lateral contact is formed, as shown in block 1230.

[0134] In some embodiments, method 1200A continues so that a first contact via is formed to the first source / drain region, as shown in block 1240.

[0135] In some embodiments, method 1200A continues once a first separation layer is formed covering the first contact via, as shown in block 1250. The first separation layer can separate the first via from direct contact with the lateral contact.

[0136] Referring now to Figure 12B, a method 1200B for forming a semiconductor device is shown. Method 1200B begins with the formation of a first-level metal layer, as shown in block 1260.

[0137] Method 1200B can proceed so that a second contact via is formed to the second source / drain region, as shown in block 1270.

[0138] Method 1200B can proceed so that a second separation layer is formed, as shown in block 1280. The second separation layer can separate the second via from direct contact with the lateral contact.

[0139] In one embodiment, the above method and structure may be used in the fabrication of an integrated circuit chip. The resulting integrated circuit chip may be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip may be mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other high-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chip may then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from low-cost applications such as toys to advanced computer products with displays, keyboards or other input devices, and central processing units. [Conclusion]

[0140] While various embodiments of this teaching have been presented for illustrative purposes, they are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles, practical applications, or technological improvements over existing technologies, or to enable other those skilled in the art to understand the embodiments disclosed herein.

[0141] While the above describes what is considered to be the best-case and / or other examples, it is clear that various modifications are possible, that the subject matter disclosed herein can be implemented in various forms and examples, and that the teachings can be applied to many uses, some of which are described herein. The following claims are intended to claim any application, modification, and variation that falls within the true scope of these teachings.

[0142] The components, steps, features, subjects, advantages, and benefits discussed herein are illustrative only. None of them, nor any of the descriptions relating to them, are intended to limit the scope of protection. While various benefits have been discussed herein, it should be understood that not all embodiments necessarily include all of them. Unless otherwise specified, all measurements, values, ratings, locations, sizes, dimensions, and other specifications described herein, including the claims below, are approximate and not precise. They are intended to be within a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they relate.

[0143] Many other embodiments are also contemplated. These include embodiments having fewer, additional, and / or different components, steps, features, subjects, advantages, and benefits. These also include embodiments in which the components and / or steps are arranged and / or ordered separately.

[0144] As described above in conjunction with exemplary embodiments, it is clear that the term “exemplary” simply means an example, and not the best or optimal. Except as stated immediately above, nothing described or illustrated, whether or not it is included in the claims, is intended, nor should it be construed as providing the public with components, steps, features, subjects, advantages, benefits, or equivalents.

[0145] The terms and expressions used herein shall have the ordinary meanings given to such terms and expressions in relation to their respective fields of study and research, unless otherwise stated herein. Correlative terms such as "first" and "second" may be used solely to distinguish one entity or action from another, without necessarily requiring or suggesting any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus containing a list of elements may not contain only those elements, but may also contain other elements that are not expressly enumerated or are specific to such process, method, article, or apparatus. The element preceded by "a" or "an" does not, unless further constraints apply, exclude the presence of additional identical elements in a process, method, article, or apparatus containing that element.

[0146] An abstract of this disclosure is provided to enable readers to quickly confirm the nature of the technical disclosure. The abstract is submitted with the understanding that it is not to be used to interpret or limit the claims or their meaning. In addition, in the embodiments for carrying out the invention described above, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than those explicitly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention has fewer features than all the features of a single disclosed embodiment combined. Therefore, the following claims are incorporated herein into the detailed description, and each claim stands alone as separately claimed subject matter.

[0147] In preferred embodiments of the present invention described herein, a semiconductor device is provided comprising a source / drain via connecting a source / drain region to a back-end obline (BEOL); and a gate via connecting a gate region to the BEOL, wherein the gate via and the source / drain via are isolated from direct contact with lateral contacts through first and second dielectric isolation layers formed on the source / drain via and the gate via, respectively.

Claims

1. A first source / drain region connected to the backend of line (BEOL) through a first contact and a first via; and The second source / drain region connected to the BEOL through the second contact, the lateral contact, and the second via. The first via passes through the lateral contact, and the first source / drain region is formed on the second source / drain region. Semiconductor devices.

2. The semiconductor device according to claim 1, wherein the lateral contact is located above the first and second source / drain regions.

3. Further comprising a first transistor stacked on top of a second transistor, The first and second source / drain regions are located above the first and second transistors, respectively. The semiconductor device according to claim 1.

4. The aforementioned second contact further, The horizontally extending portion above the second source / drain region; and Vertical extension portion connecting the horizontal extension portion to the lateral contact A semiconductor device according to claim 1, including the above.

5. The semiconductor device according to claim 1, further comprising a first isolation layer covering the first via, wherein a portion of the first isolation layer is connected to the lateral contact.

6. The semiconductor device according to claim 5, wherein the first isolation layer separates the first via from direct contact with the lateral contact.

7. The semiconductor device according to claim 1, further comprising a gate via connecting the gate region to the BEOL.

8. The semiconductor device according to claim 7, wherein the position of the second via is offset from the center line of the second source / drain region so as to be away from the gate region.

9. The system further includes a second separation layer covering the gate via, The gate via covered by the second separation layer passes through the lateral contact and the first and second contacts. The semiconductor device according to claim 7.

10. The semiconductor device according to claim 9, wherein the second isolation layer separates the gate via from direct contact with the lateral contact.

11. A method for forming a semiconductor device, wherein the method is Steps to form the first and second source / drain regions; Steps to form first and second contacts to the first and second source / drain regions, respectively; Steps to form a lateral contact on the second contact; The step of forming a first contact via to the first source / drain region; and A step of forming a first separation layer covering the first contact via, wherein the first source / drain region is formed on the second source / drain region, Methods that include...

12. The method according to claim 11, wherein the lateral contact is located above the first and second source / drain regions, and the first separation layer separates the first contact via from direct contact with the lateral contact.

13. Step of forming the first level metal layer; The step of forming a second contact via to the second source / drain region; and Step of forming a second separation layer covering the second contact via. The method according to claim 11, further comprising:

14. The method according to claim 13, wherein the first level metal layer is connected to the lateral contact through the second contact via.

15. The step of forming gate contact vias; A step of forming a third separation layer covering the gate contact via; The steps of forming the first and second contact metallizations; and In the step of forming gate contact via metallization, a portion of the third separation layer is connected to the lateral contact, The method according to claim 11, further comprising:

16. The method according to claim 11, wherein the second contact is taller than the first contact.

17. The process further includes the step of forming a first transistor stacked on a second transistor, The first and second source / drain regions are located above the first and second transistors, respectively. The method according to claim 11.

18. The method according to claim 17, wherein the position of the second contact via is offset from the center line of the second source / drain region so as to be away from the gate region.

19. The step of forming the second contact is: The step of forming a horizontally extending portion on the second source / drain region; and Step 1: Forming a vertically extending portion that connects the horizontally extending portion to the lateral contact. The method according to claim 13, including the method described in claim 13.

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