Integrated device with embedded interconnection structure

Abstract

The device includes a substrate which includes a first conductor that connects contacts on a first side of the substrate to contacts on a second side of the substrate. The first conductor includes a metal wire disposed in metal layers separated from each other by a dielectric layer, and conductive vias interconnecting the metal wire. The substrate also includes a second conductor which connects contacts on a first side of the substrate to contacts on a first side of the substrate, defining a conductive path between a first die and a second die. The second conductor includes a metal wire disposed in metal layers separated from each other by a dielectric layer, and conductive vias interconnecting the metal wire of the second conductor. At least one metal layer of the second conductor lacks the metal wire of the first conductor.

Description

Technical Field

[0001] Cross-Reference to Related Applications This application claims the benefit of priority from U.S. Non-Provisional Patent Application No. 18 / 455,368, co-owned, filed on August 24, 2023, the entire content of which is hereby expressly incorporated herein by reference.

[0002] Various features relate to integrated devices. Background Art

[0003] Electrical connections exist at each level of a system hierarchy. The system hierarchy includes from interconnection of active devices at the lowest system level to system-level interconnection at the highest level. For example, an interconnection layer can connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnection layers are used to provide electrical connections between devices. Furthermore, more recently, the number of interconnection levels for circuits has increased substantially in modern electronic devices, due to the large number of devices that are now interconnected. Increasing the number of interconnection levels to support the increase in the number of devices involves more complex processes.

[0004] State-of-the-art mobile application devices require small form factors, low costs, tight power budgets, and high electrical performance. Mobile package design has evolved to meet these diverse goals, enabling mobile applications that support multimedia expansion. However, when multiple dies are configured within a small form factor, these mobile applications are susceptible to power and signal routing issues. Designing and manufacturing devices for use in mobile applications is challenging due to conflicts between various design goals. For example, smaller form factor devices are generally more expensive to design and manufacture, and smaller size can exacerbate other issues such as thermal management. Another example is that performance can be improved by providing more signal paths between dies. However, providing more signal paths generally increases cost and size. [Overview of the project]

[0005] Various features are related to integrated devices.

[0006] One example provides a device including a substrate which includes a first conductor that electrically connects a first contact on a first side of the substrate to a second contact on a second side of the substrate. The first conductor includes a first set of metal wires arranged in a first set of metal layers separated from each other by a first set of dielectric layers. The first conductor also includes a first set of conductive vias that penetrate the first set of dielectric layers and interconnect the first set of metal wires. The substrate also includes a second conductor which electrically connects a third contact on a first side of the substrate to a fourth contact on a first side of the substrate, defining a conductive path between a first die and a second die. The second conductor includes a second set of metal wires arranged in a second set of metal layers separated from each other by a second set of dielectric layers. The second conductor also includes a second set of conductive vias that interconnect the second set of metal wires. At least one of the second set of metal layers lacks the metal wires of the first set of metal wires.

[0007] Another example provides a device comprising a first die having a first circuit, a second die having a second circuit, and a substrate. The substrate is configured to electrically connect the first circuit to the second circuit and to electrically connect the first circuit, the second circuit, or both to one or more out-of-package devices. The substrate includes a first conductor that electrically connects a first contact on a first side of the substrate to a second contact on a second side of the substrate. The first conductor includes a first set of metallic wires arranged in a first set of metal layers separated from each other by a first set of dielectric layers. The first conductor also includes a first set of conductive vias that interconnect the first set of metallic wires through the first set of dielectric layers. The substrate also includes a second conductor that electrically connects a third contact on a first side of the substrate to a fourth contact on a first side of the substrate, defining a conductive path between the first die and the second die. The second conductor includes a second set of metallic wires arranged in a second set of metal layers separated from each other by a second set of dielectric layers. The second conductor also includes a second set of conductive vias that interconnect a second set of metal wires. At least one of the second set of metal layers lacks a metal wire from the first set of metal wires.

[0008] Another example provides a method for manufacturing a device, comprising obtaining a first set of layers. The first set of layers includes a first set of metal layers separated from each other by a first set of dielectric layers, the first set of metal layers defining a first set of metal wires. The first set of layers also includes a first set of conductive vias that penetrate the first set of dielectric layers to interconnect the first set of metal wires. The method also comprises forming an embedded interconnect structure on the first set of layers. The embedded interconnect structure includes a second set of metal layers defining a second set of metal wires, at least one of the metal layers in the second set of metal layers lacking metal wires from the first set of metal wires. The embedded interconnect structure also includes a second set of dielectric layers, at least a bottom dielectric layer between the first set of metal layers and the second set of metal layers, and an upper dielectric layer on top of the upper metal layers of the second set of metal layers. The method further comprises forming a first pad and a first conductive via, the first conductive via extending through the embedded interconnect structure to the first set of metal layers. The method also includes forming a first contact on a first pad and forming a second contact including a via portion that penetrates the upper dielectric layer of the embedded interconnect structure and extends to the upper metal layer of a second set of metal layers.

[0009] By reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, various features, essences, and advantages can be revealed. In the drawings, the same reference numerals throughout indicate corresponding elements. [Brief explanation of the drawing]

[0010] [Figure 1] This shows a cross-sectional profile of a device including an embedded interconnect structure. [Figure 2] This shows a disassembled cross-sectional profile of the device layers, including the embedded interconnect structure. [Figure 3A] An exemplary sequence for manufacturing a device including an embedded interconnect structure is also shown. [Figure 3B]An exemplary sequence for manufacturing a device including an embedded interconnect structure is also shown. [Figure 3C] An exemplary sequence for manufacturing a device including an embedded interconnect structure is also shown. [Figure 4] This flowchart shows an exemplary method for manufacturing a device that includes an embedded interconnect structure. [Figure 5] This specification describes various electronic devices that can integrate dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages. [Modes for carrying out the invention]

[0011] The following description includes specific details to provide a complete understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of this disclosure. As another example, various devices and structures disclosed herein are shown schematicly. Such schematics are not to scale and are generally intentionally simplified. For example, an integrated device may have tens or hundreds of contacts and corresponding interconnections. However, in this specification, only a very small number of such contacts and interconnections are shown to highlight the important features of this disclosure without overcomplicating the drawings.

[0012] Specific aspects of this disclosure are described below with reference to the drawings. In this description, common features are indicated by common reference numbers. Where used herein, various terms are used solely for the purpose of describing specific implementations and are not intended to limit the implementations. For example, the singular forms "a," "an," and "the" are intended to include the plural form unless the context otherwise explicitly indicates. Furthermore, some features described herein are singular in some implementations and plural in others. For ease of reference in this specification, such features are generally introduced as "one or more" features, and therefore refer to the singular or any optional plural form (such as indicated by "(singular or plural)") unless an aspect relating to the plural of a feature is described.

[0013] In some drawings, multiple instances of a particular type of feature are shown. In some situations, fewer than all of such features may be identified using reference numbers. For example, a single reference number may be shown and associated with a representative example of the feature, so as not to obscure other aspects of the drawing. Where physical and / or logical distinctions between similar features are important, the same reference number may be used for each such feature, and different examples may be distinguished by adding a letter to the reference number. When a feature is referred herein as a group or type (for example, when no particular feature is referred), the reference number is used without a distinguishing letter. However, when a particular feature of one of several features of the same type is referred herein, the reference number is used with a distinguishing letter. For example, referring to Figure 1, several dies are shown and associated with reference numbers 102A and 102B. When referring to a particular one of these dies, such as die 102A, the distinguishing letter "A" is used. However, when referring to any one of these dies or the group as a whole, the reference number 102 is used without a distinguishing letter.

[0014] As used herein, the terms “comprise,” “comprises,” and “comprising” may be used interchangeably with “include,” “includes,” or “including.” As used herein, “exemplary” refers to an example, an implementation, and / or an aspect, and should not be construed as limiting or indicating a preferred or desirable implementation. As used herein, order-determining terms used to modify elements such as structure, components, and behavior (e.g., “first,” “second,” “third,” etc.) do not in themselves indicate any priority or order of that element over another element, but rather merely distinguish that element from another element that has the same name (apart from the use of order-determining terms). As used herein, the term “set” refers to one or more of a particular element, and the term “plurality” refers to multiple (e.g., two or more) particular elements.

[0015] Improvements in manufacturing technology and the demand for lower-cost, higher-performance electronic devices are increasing the complexity of integrated circuits (ICs). Often, more complex ICs have more complex interconnection schemes to enable interaction between ICs in a device. In state-of-the-art mobile application devices, the number of interconnection levels for circuits has substantially increased due to the sheer number of interconnected devices that are now present.

[0016] These interconnections include back-end-of-line (BEOL) interconnect layers, which may refer to conductive interconnect layers for electrically coupling to the front-end-of-line (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at the corresponding BEOL interconnect levels, where lower BEOL interconnect levels generally use thinner metal layers compared to higher BEOL interconnect levels. The BEOL interconnect layers may be electrically coupled to middle-of-line (MOL) interconnect layers that interconnect to the FEOL active devices of the IC.

[0017] State-of-the-art mobile application devices require small form factors, low costs, tight power budgets, and high electrical performance. Mobile package design has evolved to meet these diverse goals for enabling mobile applications that support multimedia expansion. One approach to reducing package size is to integrate multiple dies within a single package. An example of a multi-die package is a two-dimensional (2D) package architecture, where two or more dies are coupled side-by-side to the package substrate. In this configuration, dies can interact with each other (e.g., via inter-die connections) and with external devices (e.g., via external connections). The challenge of such configurations is that inter-die connections and external connections have different design standards. For example, external connections are generally larger (e.g., in terms of line width, line spacing, etc.) than inter-die connections. Various workarounds have been used to address this size difference. For example, additional devices (e.g., interposer devices or bridge dies) can be added to the package to route inter-die connections using smaller wires. As another example, additional layers or separate laminated substrates can be added to the package substrate to provide redistributed routing for connecting to inter-die connections and external connections to the package.

[0018] Another approach to reducing package size is the 2.5D architecture, in which two or more devices are arranged side-by-side on a package substrate, with one or more additional devices stacked on top of at least one of the side-by-side devices. For example, a stacked die arrangement can be coupled to the package substrate side-by-side with another die, a passive device, another die stack, and so on. Stacked die configurations and chiplet architectures are becoming more common as significant improvements in power performance area (PPA) yield have been demonstrated in stacked die and chiplet architecture product lines.

[0019] Various aspects of this disclosure provide devices including embedded interconnect structures that address many of the challenges of multi-die packages. For example, an embedded interconnect structure is configured to provide a signal path between two or more dies coupled to a package substrate using a set of layers different from the layers used to provide external connections to the package. The technical advantages achieved by using this configuration are that a large number of inter-die signal paths can be provided in a small area of ​​the substrate, and performance can be improved by increasing the number of inter-die interconnects without correspondingly increasing the package size.

[0020] As used herein, the term “layer” includes films and, unless otherwise stated, shall not be construed as indicating vertical or horizontal thickness. As used herein, the term “chiplet” may refer to an integrated circuit block, a functional circuit block, or any other similar circuit block specifically designed to work with one or more other chiplets to form a larger and more complex chiplet architecture.

[0021] Exemplary device including embedded interconnection structure FIG. 1 shows an example of a device 100 including a plurality of dies 102 coupled to a substrate 106. In FIG. 1, the dies 102 include a die 102A and a die 102B. Each die 102 may include circuitry 104, such as a plurality of transistors and / or other circuit elements, configured and interconnected to form a power distribution network (PDN), logic cells, memory cells, and the like. Components of the circuitry 104 may be formed in and / or on a semiconductor substrate of the die 102. Different implementations may use different types of transistors, such as field effect transistors (FETs), planar FETs, fin FETs, gate-all-around FETs, or a mixture of transistor types. In some implementations, to form each of the dies 102, a front-end-of-line (FEOL) process may be used to fabricate the integrated circuitry 104 in and / or on the semiconductor substrate.

[0022] The circuitry 104 of each die 102 is electrically connected to a set of contacts of the die 102. The contacts of the die 102A in FIG. 1 include a contact 162A configured to be electrically connected to the contact 162B of the die 102B, and a contact 164A configured to be coupled to an out-of-package device via the substrate 106 by a contact of the substrate 106 (e.g., a ball grid array (BGA) 160 of FIG. 1). Similarly, the contacts of the die 102B include a contact 162B configured to be electrically connected to the contact 162A of the die 102A, and a contact 164B configured to be coupled to an out-of-package device by a contact of the BGA 160 via the substrate 106. In certain aspects, as further described below, die-to-die connections, such as the signal path between contacts 162A and 162B, are routed through an embedded interconnect structure within a die-to-die interconnect region 130 of the substrate 106.

[0023] The substrate 106 includes a stacked set of layers including a metal layer and a dielectric layer. Adjacent metal layers are separated from each other by one or more dielectric layers and are patterned to define metal lines. The metal lines are interconnected by conductive vias to define conductive paths through the substrate 106. In the specific example shown in FIG. 1, by way of illustration and not limitation, the substrate 106 comprises a metal layer 110 (e.g., an M1 layer), a metal layer 112 (e.g., an M2 layer), a metal layer 114 (e.g., an M3 layer), a metal layer 116 (e.g., an M4 layer), a metal layer 118 (e.g., an M5 layer), a metal layer 120 (e.g., an M6 layer), and a core 124, and includes a set of main metal layers. In FIG. 1, adjacent main metal layers such as the metal layer 114 and the metal layer 112 are separated by a dielectric layer such as dielectric layer 128, and are electrically connected via one or more conductive vias such as conductive via 142.

[0024] FIG. 1 also shows a solder resist layer 108 on a first side of the substrate 106 (e.g., the upper side in the orientation shown in FIG. 1), the solder resist layer 108 defines openings through which contacts 150 (e.g., contacts 150A and 150B) and 152 (e.g., contacts 152A and 152B) pass. Similarly, a solder resist layer 122 on a second side of the substrate 106 (e.g., the bottom side in the orientation shown in FIG. 1) defines an opening to the metal layer 120, through which the solder balls of the BGA 160 are bonded to the substrate 106.

[0025] The first set of conductors includes various metal wires between the main metal layers 110, 112, 114, 116, 118, and 120, and conductive vias (e.g., conductive via 142) between them, forming a conductive path between the BGA 160 and the contacts 164 of the die 102. A second set of conductors, different from the first set of conductors, forms a conductive path between the contacts 162. The second set of conductors includes various metal wires and conductive vias in the inter-die interconnection region 130. For example, in Figure 1, the second set of conductors includes metal wires defined within metal layer 146, metal wires defined within metal layer 148, and conductive vias 168 between them. The metal layers 146 and 148 of the second set of conductors are called "sub-layer metal layers" because they are positioned between adjacent pairs of the main metal layers 110, 112, 114, 116, 118, and 120 of the substrate 106. For example, in Figure 1, the sublayer metal layers 146 and 148 are positioned between the metal layer 110 (e.g., the M1 layer) and the metal layer 112 (e.g., the M2 layer). In some implementation configurations, the inter-die interconnection region 130 may also include metal wires within the metal layer 110 (e.g., the M1 layer).

[0026] In Figure 1, the dielectric layer 170 is disposed between the sublayer metal layers 146 and 148. Furthermore, the dielectric layer is disposed between the sublayer metal layers 146 and 148 and adjacent metal layers of the main metal layers 110, 112, 114, 116, 118, and 120 of the substrate 106. For example, the dielectric layer 144 is disposed between the upper metal layer (e.g., metal layer 146) and metal layer 110 of the sublayer metal layers. As another example, the dielectric layer 172 is disposed between the lower metal layer (e.g., metal layer 148) and metal layer 114 of the sublayer metal layers.

[0027] The sublayer metal layers 146 and 148 are separate from and do not overlap with the metal layers 110, 112, 114, 116, 118, and 120 (e.g., they are separated from them). For example, the metal wires of metal layers 110, 112, 114, 116, 118, and 120 are not in the same layer as any of the metal wires of the sublayer metal layers 146 and 148 (e.g., they are not on the same plane). Therefore, in a mounting configuration in which the inter-die interconnection region 130 includes the sublayer metal layers 146 and 148 and does not contain metal wires within the M1 layer (e.g., metal layer 110), the inter-die region 130 lacks metal wires from the main metal layers 110, 112, 114, 116, 118, and 120. In other words, in such an implementation configuration, none of the metal wires of the main metal layers 110, 112, 114, 116, 118, and 120 cross the inter-die interconnection region 130.

[0028] In Figure 1, the post structure 126 includes a contact pad (on the metal layer 110) and conductive vias extending from the metal layer 110 to the metal layer 112, through layers that form the embedded interconnect structure of the die interconnect region 130. As illustrated with reference to Figure 3B, the post structure 126 can be formed as part of (for example, simultaneously with) the metal layer 110.

[0029] The main metal layers 110, 112, 114, 116, 118, and 120 are sized and positioned to provide external connections (such as power, ground, and conductive paths for external input / output (I / O)). For example, the metal wires of the main metal layers 110, 112, 114, 116, 118, and 120 have, among other things, first characteristic dimensions (e.g., wire width, wire spacing, and wire thickness) selected to provide target current carrying capability and enable the use of standard manufacturing techniques. The sub-layer metal layers 146, 148 are sized and positioned to provide inter-die connections. For example, the metal wires of the sub-layer metal layers 146, 148 have, among other things, second characteristic dimensions (e.g., wire width, wire spacing, and wire thickness) selected to provide a large number of signal paths within a small area. In certain embodiments, the second characteristic dimensions are smaller than their counterparts in the first characteristic dimensions. For example, the metal wires of the sublayer metal layers 146 and 148 have a smaller wire width, smaller wire thickness, and smaller wire spacing than the metal wires of the main metal layers 110, 112, 114, 116, 118, and 120. For example, in Figure 1, the main metal layers 110, 112, 114, 116, 118, and 120 have a characteristic layer thickness T4, while the sublayer metal layers 146 and 148 have a characteristic layer thickness T2 that is smaller than T4. Furthermore, the dielectric layer 128 between adjacent metal layers of the main metal layers 110, 112, 114, 116, 118, and 120 has a characteristic thickness that is larger than the characteristic thickness of the dielectric layers 144, 170, and 172. For example, in Figure 1, the dielectric layer 128 has a thickness T3, while the dielectric layer 144 has a thickness T1 that is smaller than T3.

[0030] One technical advantage of the sub-layer metal layers 146, 148, which have characteristic smaller dimensions than the main metal layers 110, 112, 114, 116, 118, and 120, is that smaller metal wires allow for the routing of a greater number of signal paths between dies 102 with little to no increase in the dimensions of the substrate 106. Increasing the number of signal paths between dies 102 is generally beneficial for improving the performance of device 100. Alternatively, compared to conventional devices that route inter-die connections through the main metal layers 110, 112, 114, 116, 118, and 120, device 100 can route the same (or more) number of inter-die connections through the sub-layer metal layers 146, 148, thereby reducing the overall size of device 100 compared to conventional devices.

[0031] Figure 1 shows an inter-die interconnection region 130 located between the M1 and M2 layers (e.g., metal layers 110 and 112), but in another example, the inter-die interconnection region 130 is located between different adjacent pairs of main metal layers 110, 112, 114, 116, 118, and 120. Furthermore, Figure 1 shows a single inter-die interconnection region 130, but in another example, the device 100 includes two or more inter-die interconnection regions 130. For illustrative purposes, a third die (or another device) can be coupled to the substrate 106 and interconnected with one or both of the dies 102 via another inter-die interconnection region located between the M1 and M2 layers, or via different adjacent pairs of main metal layers 110, 112, 114, 116, 118, and 120.

[0032] Region 130 is referred to herein as the die interconnection region 130, but in other examples, the sublayer metal layers 148, 148, metal wires and associated conductive vias 168 are used to interconnect other types of devices, such as connecting a die to a passive device or connecting two passive devices. Furthermore, in Figure 1, the die interconnection region 130 is shown to include two sublayer metal layers 146, 148, but in other examples, the die interconnection region 130 includes three or more or one or fewer metal layers. Similarly, in Figure 1, the substrate 106 is shown to include six main metal layers 110, 112, 114, 116, 118, and 120, but in other examples, the substrate 106 includes seven or more or five or fewer main metal layers.

[0033] In some implementation configurations, device 100 can be integrated with one or more other devices to form an integrated packaged device. For example, substrate 106 can correspond to the upper or lower substrate of a package-on-package device. For example, when substrate 106 corresponds to the lower substrate of a package-on-package device, another substrate can be placed on top of die 102 and electrically connected to metal layer 110 via interposer conductors.

[0034] In some implementations, die 102 can correspond to chiplets interconnected via an inter-die interconnection region 130. Alternatively, one of the dies 102 can be the bottom chiplet of a stacked chiplet configuration. In such a stacked chiplet configuration, another die (i.e., another chiplet) is stacked on top of one of the dies and electrically connected to that die. Using chiplets arranged and interconnected as a 3D stack can offer several advantages compared to providing the same functional circuitry within a single monolithic chip. For example, each chiplet is smaller than a monolithic die containing all of the same functional circuitry blocks. Yield loss in IC manufacturing tends to increase with increasing die size, so using smaller dies can reduce yield loss in the IC manufacturing process (i.e., increase yield). Another advantage is that chiplets can be manufactured in different locations and / or by different manufacturers, and possibly using different manufacturing technologies (e.g., different manufacturing technology nodes). For example, one die 102 of a chiplet-based integrated device may contain a component having a first minimum size (e.g., an interconnect, a transistor, etc.), and another die of the chiplet-based integrated device may contain a component having a second minimum size (e.g., an interconnect, a transistor, etc.), where the second minimum size is larger than the first minimum size. In contrast, all the circuits of a monolithic die are manufactured using the same manufacturing techniques and equipment. As a result, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex component of the monolithic die. In contrast, when using chiplets, different chiplets can be manufactured using different manufacturing techniques (e.g., different manufacturing technique nodes), and only one or more chiplets containing the most complex component are subject to the most stringent manufacturing constraints.In this configuration, chiplets manufactured using less expensive and / or higher yield manufacturing techniques can be integrated with chiplets manufactured using more expensive and / or lower yield manufacturing techniques to form an integrated device, resulting in overall savings. Furthermore, in some cases, as technology improves, the design of one or both chiplets can be modified so that the new chiplet design integrates with the older chiplet design, which improves manufacturing flexibility and reduces design costs.

[0035] In various implementations, device 100 may include components such as power management integrated circuits (PMICs), application processors (including one or more processor cores), modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory (including multiple memory cells), power management processors, and / or combinations thereof. In such implementations, die 102 can operate as any of these components (or combinations thereof), including active circuits.

[0036] Figure 2 shows an exploded cross-sectional profile of layer 200 of a device including an embedded interconnect structure, such as device 100 in Figure 1. Layer 200 shown in Figure 2 follows the same general configuration as the layer of device 100 described with reference to Figure 1.

[0037] In Figure 2, layer 200 includes a contact layer 202 which includes a contact 220 associated with an inter-die interconnection region (e.g., inter-die interconnection region 130 in Figure 1) and a contact 222 associated with a main metal layer. For example, contact 220 may correspond to contact 152 in Figure 1, which is configured to electrically connect contact 162 of die 102 to sub-layer metal layer 146 of inter-die interconnection region 130. In this example, contact 222 may correspond to contact 150 in Figure 1, which is configured to electrically connect contact 164 of die 102 to the M1 layer (e.g., metal layer 110).

[0038] In certain examples, layer 200 also includes an M1 layer 204 corresponding to the metal layer 110 of the substrate 106 in Figure 1. As shown in Figure 2, the M1 layer 204 includes a contact pad 216 for the contacts 222 and optionally includes metal wires 214 in the die interconnection region, metal wires associated with the main metal layer, or both.

[0039] Layer 200 also includes a set of layers 206 that define a set of sublayer conductors in the die interconnection region (e.g., die interconnection region 130 in Figure 1). In Figure 2, the set of layers 206 includes a dielectric layer 226, a metal layer 228, a dielectric layer 230, a metal layer 232, and a dielectric layer 234. In a particular example, dielectric layer 226 corresponds to dielectric layer 144 in Figure 1, metal layer 228 corresponds to sublayer metal layer 146 in Figure 1, dielectric layer 230 corresponds to dielectric layer 170 in Figure 1, metal layer 232 corresponds to sublayer metal layer 148 in Figure 1, and dielectric layer 234 corresponds to dielectric layer 172 in Figure 1. The metal layers 228 and 232 of the set of layers 206 define metal wires, which can be interconnected by conductive vias (e.g., conductive via 168 in Figure 1) to define conductive paths between two or more of the contacts 220. Although two metal layers 228 and 232 are shown in Figure 2, the set of layers 206 may include three or more or one or fewer metal layers.

[0040] Layer 200 also includes another set of layers 208 that define a set of conductors in the main metal layers. For example, the set of layers 208 may correspond to, or include, the main metal layers 112, 114, 116, and 118 (e.g., layers M2-M5) and the dielectric layers between them (e.g., dielectric layer 128) of the substrate 106 in Figure 1. In Figure 2, the set of layers 208 is shown to include an optional core 236, which may be omitted in some implementation configurations.

[0041] Layer 200 also includes a set of dielectric layers 210, which includes dielectric layers 238, 240, and 242. In a particular configuration, the set of dielectric layers 210 corresponds to or includes dielectric layers between two metal layers at the bottom of the substrate (e.g., the main metal layers 118 and 120 of substrate 106 in Figure 1). In a particular configuration, each of the dielectric layers 238, 240, and 242 is formed or applied to the laminate simultaneously with a corresponding one of the dielectric layers 226, 230, and 234. For example, dielectric layers 226, 230, and 234 and dielectric layers 238, 240, and 242 can be applied in pairs using a symmetrical lamination process. In this example, dielectric layers 234 and 238 are applied to the set of layers 208 to form a first working laminate. Subsequently, metal layer 232 is formed on the first working laminate, and dielectric layers 230 and 240 are applied to form a second working laminate. Subsequently, one or more additional pairs of metal and dielectric layers can be formed on the second working laminate (depending on the specific number of layers desired to form the inter-die interconnection region). For example, a metal layer 228 can be formed on the second working laminate, and dielectric layers 226 and 242 can be applied to form a third working laminate. The technical advantage of using a symmetric lamination process to form dielectric layers 226, 230, 234 and dielectric layers 238, 240, 242 is that symmetric lamination can reduce unbalanced stresses within the substrate (e.g., substrate 106 in Figure 1), thereby reducing substrate warpage.

[0042] Additional main metal layers can be formed on the third working laminate. For example, in the example shown in Figure 2, layers M1 204 and M6 212 can be formed on the third working laminate. Thus, in this example, the set of dielectric layers 210 can be considered to replace one of the dielectric layers that separates the pair of main metal layers.

[0043] The layer 200 shown in Figure 2 represents a stacking configuration that may occur when a symmetric stacking process is used. However, in other configurations, the device 100 in Figure 1 can be formed without using a symmetric stacking process, in which case the set of dielectric layers 210 can be replaced by a single dielectric layer having appropriate characteristic dimensions associated with the main metal layer (for example, having approximately the layer thickness T3 in Figure 1, which is greater than the thickness of each of the dielectric layers 226, 230, 234, 238, 240, and 242).

[0044] Exemplary sequence for manufacturing a device including an embedded interconnect structure In some implementations, manufacturing a device containing an embedded interconnect structure involves several processes. Figures 3A, 3B, and 3C show exemplary sequences for providing or manufacturing a device containing an embedded interconnect structure, as described with reference to Figure 1 or Figure 2. In some implementations, the sequences of Figures 3A–3C may be used to provide (for example, during its manufacture) device 100 in Figure 1, or another device containing layer 200 in Figure 2.

[0045] It should be noted that the sequences in Figures 3A to 3C may be combinations of one or more steps to simplify and / or clarify the sequence for providing or manufacturing an integrated device. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. In the following description, various exemplary steps of the sequence numbered (using circled numbers) in Figures 3A to 3C will be referenced.

[0046] Step 1 in Figure 3A shows the state after the formation of the main metal layer set 300 of the substrate. A simplified main metal layer set 300 is shown in Figures 3A to 3C (relative to Figures 1 and 2) and includes metal layers 302 and 306 within or on the dielectric layer 304. Metal layers 302 and 306 are patterned to form conductive wires such as metal wire 308 in metal layer 302 and metal wire 312 in metal layer 306. Conductive vias interconnect various of the metal wires. For example, a conductive via 310 penetrating the dielectric layer 304 electrically connects metal wire 308 and metal wire 312. The main metal layer set 300 can be formed using a lamination process. For example, metal layers 302 and 306 can be formed simultaneously on the dielectric layer 304 using a symmetric lamination process. Alternatively, the main metal layer set 300 can be constructed on a carrier substrate (not shown) or a core of the substrate (e.g., core 236 in Figure 2). For example, the main metal layer 300 may correspond to or include the set of layers 208 in Figure 2, in which case the main metal layer 300 can be formed on the core 236 using a symmetrical lamination process.

[0047] Metal layers 302 and 306 can be patterned to define metal wires (e.g., metal wires 308, 312) using one or more subtractive processes (e.g., etching, engraving, or ablation of the material of the metal layers), one or more additive processes (e.g., printing or deposition), or a combination of additive and subtractive processes. In the additive or subtractive processes, a patterned mask layer, such as a patterned dry film, can be used to guide the patterning of metal layers 302, 306 to define the metal wires. The dielectric layer 304 can correspond to a polymer layer or prepreg layer that is cured to form the dielectric layer 304. Conductive vias can be formed using a drilling operation to form openings, which are then filled or coated with a conductive material (e.g., using a plating or deposition process) to form conductive vias. In some configurations, plating or deposition induced by a mask layer can be used to form the metal layers while simultaneously filling the openings and forming conductive vias.

[0048] The specific set of main metal layers 300 shown in Figure 3A is merely an example. In other configurations, step 1 ends with obtaining a package substrate of any type or configuration that includes conductors (e.g., two or more metal layers and conductive vias between them) that form a conductive path between the two sides of the set of main metal layers 300. For example, in some configurations, the set of main metal layers 300 includes, or corresponds to, the set of layers 208 in Figure 2, or another substrate that includes contacts on each side and conductors that define a conductive path between them.

[0049] Stage 2 shows the state after forming a first portion of the set of sublayer metal layers on the set of main metal layers 300. The first portion of the set of sublayer metal layers includes a dielectric layer 314 on the metal layer 302, a metal layer 316 on the dielectric layer 314, and a dielectric layer 318 on the metal layer 316. In Stage 2, the metal layer 316 is patterned (for example, using one or more subtractive processes, one or more additive processes, or a combination of additive and subtractive processes) to define a metal wire such as a metal wire 320. In addition, in Stage 2, the dielectric layer 318 is patterned (for example, using one or more subtractive processes, one or more additive processes, or a combination of additive and subtractive processes) to form an opening such as an opening 322 that penetrates the dielectric layer 318 to the metal layer 316.

[0050] Metal layer 316 is thinner than each of metal layers 302 and 306 of the main metal layer set 300. Additionally or alternatively, the metal wires of the sublayer metal layer set (e.g., metal wire 320) are more densely packed than the metal wires of the main metal layer set 300 (e.g., metal wires 308, 312) (e.g., having a smaller wire width, a smaller pitch, or both). Furthermore, in some cases, dielectric layers 318, 314 are thinner than dielectric layer 304.

[0051] In the example shown in Figure 3A, the dielectric layers 314 and 318 are shown to be applied to only one side of the set of main metal layers 300. For example, the metal layer 306 remains exposed on the side surface 330 of the set of main metal layers 300. Optionally, in some implementations, a symmetrical stacking process is used to apply the dielectric layers 314 and 318 of the set of secondary metal layers. In such implementations, the additional dielectric layer is coupled to the set of main metal layers 300 on the surface 330, as described with reference to the set of dielectric layers 210 in Figure 2.

[0052] Stage 3 shows the state after the formation of the second portion of the set of sublayer metal layers. The second portion of the set of sublayer metal layers includes conductive vias (e.g., conductive via 336) and metal layer 332. The conductive vias are formed within openings (e.g., opening 322) in the dielectric layer 318 and are electrically connected to one or more metal wires in metal layer 316. For example, the conductive vias can be formed using one or more plating or deposition operations.

[0053] In some implementations, the metal layer 332 is formed and patterned simultaneously with the formation of conductive vias. For example, a patterned film can be applied to the dielectric layer 318 to define openings for metal wires (e.g., metal wire 338) and conductive vias (e.g., conductive via 336) in the metal layer 332. In this example, the metal layer 332 and conductive vias can be formed using a plating or deposition process induced by the patterned film. The metal wires of the metal layer 332 are interconnected with appropriate metal wires of the metal layer 316 via conductive vias to form a signal path.

[0054] In the examples shown in Figures 3A to 3C, metal layer 332 is the uppermost layer of the set of sublayer metal layers. Therefore, the embedded interconnect structure formed by the set of sublayer metal layers contains two metal layers. However, in other examples, the embedded interconnect structure contains three or more or one or fewer metal layers. The specific number of metal layers used in the embedded interconnect structure depends on factors such as the number of signal paths provided within the embedded interconnect structure, the wire width and spacing of the metal wires within the embedded interconnect structure (which may depend on available process technology, cost constraints, mechanical or thermal constraints, etc.), and other factors. When the embedded interconnect structure contains three or more metal layers, additional metal layers can be formed by repeating the operations described with reference to steps 2 and 3 above. When the embedded interconnect structure contains a single metal layer, the operations described with reference to step 3 may be omitted, and the manufacturing operation can proceed from step 2 to step 4.

[0055] Stage 4 shows the state after the upper dielectric layer 340 of the embedded interconnect structure has been formed on top of the upper metal layer (e.g., metal layer 332 in Figure 3A) of the embedded interconnect structure. In the example shown in Figure 3A, the dielectric layer 340 is shown to be applied to only one side of the embedded interconnect structure. For example, the metal layer 306 remains exposed on the side surface 330 of the set of main metal layers 300. Optionally, in some implementations, a symmetrical stacking process is used to apply the dielectric layer 340. In such implementations, one or more additional dielectric layers are coupled to the set of main metal layers 300 on the side surface 330, as described with reference to the set of dielectric layers 210 in Figure 2.

[0056] Stage 5 shows the state after the openings 350 and 352 have been formed to provide access to the upper metal layer (e.g., metal layer 332) and the set of main metal layers 300 (e.g., metal layer 302) of the embedded interconnect structure, respectively. For example, the openings can be formed using one or more processes such as etching, drilling, or ablation.

[0057] Step 6 in Figure 3B shows the state after conductive vias (e.g., conductive via 354) and metal wires and / or contact pads of the metal layer 358 have been formed. In certain mounting configurations, the formation of the conductive vias and metal layer 358 is induced by a patterned layer 356. The patterned layer 356 includes a dry film layer or another mask layer (e.g., a photoresist layer) formed on the dielectric layer 340. The patterned layer 356 is patterned to include openings aligned with openings that expose the top layer (e.g., metal layer 302) of the set of main metal layers 300, and openings corresponding to the metal wires and / or contact pads of the metal layer 358. The metal layer 358 and the conductive vias (e.g., conductive via 354) electrically connected to the main metal layer 300 can be formed using plating and / or deposition operations induced by the patterned layer 356.

[0058] The patterned layer 356 covers the opening (such as the opening 350) that exposes the upper metal layer (e.g., metal layer 332) of the embedded interconnect structure. Thus, the formation of conductive vias electrically connected to the main metal layer 300 is carried out separately from the formation of conductive vias electrically connected to the embedded interconnect structure.

[0059] Stage 7 shows the state after the patterned layer 356 has been removed. Removal of the patterned layer 356 exposes an opening 350 to provide access to a portion of the metal layer 332. Removal of the patterned layer 356 can be performed using one or more delamination, delamination, or ashing operations, or other operations appropriate for separating the patterned layer 356 from adjacent structures such as the metal layer 358 and / or the dielectric layer 340.

[0060] Step 8 shows the formation of the patterned layer 362 and its state after patterning. The patterned layer 362 may contain or correspond to a dry film or a curable resin. The patterned layer 362 is patterned to define an opening 364 that exposes the upper metal layer of the embedded interconnect structure (e.g., metal layer 332) and an opening 366 that exposes the contact pad 360 of the main metal layer 300 (e.g., the contact pad of metal layer 358).

[0061] Step 9 shows the state after the formation of the bump pads 370 and 372 induced by the patterned layer 362. The bump pad 370 is electrically connected to the corresponding contact pad 360 of the main metal layer 300 (e.g., the contact pad of metal layer 358). The bump pad 372 is electrically connected to the upper metal layer of the embedded interconnect structure (e.g., metal layer 332). Thus, the bump pad 370 has a different shape and size from the bump pad 372. For example, the bump pad 370 includes or corresponds to a simple copper post extending upward from the lower contact pad 360 of metal layer 358 (in the orientation shown in Figure 3B). In contrast, each of the bump pads 372 includes a post portion 374 and a via portion 376. The via portion 376 extends through an opening (e.g., opening 350) in the dielectric layer 340 and electrically connects to the upper metal layer (e.g., metal layer 332) of the embedded interconnect structure, and the post portion 374 extends upward from the corresponding via portion 376 (in the orientation shown in Figure 3B). Thus, the entire post structure from the upper metal layer (e.g., metal layer 302) of the main metal layer 300 to the top of one of the bump pads 370 includes two metal layers (i.e., a two-layer post structure), a first layer including the conductive via 354 and the contact pad 360 of metal layer 358, and a second layer corresponding to the bump pad 370 (e.g., a copper post deposited on the contact pad 360 of metal layer 358). The post structure from the upper metal layer (e.g., metal layer 332) of the embedded interconnect structure to the top of one of the bump pads 372 is a single layer (i.e., a one-layer post structure).

[0062] One challenge in forming bump pads 370, 372 having different shapes and sizes is aligning the tops of the bump pads 370, 372 to enable reliable die mounting. In certain mounting configurations, this challenge is addressed by forming bump pads 370 and 372 simultaneously using a single metal deposition operation and designing the bump pads 370, 372 to have substantially equal three-dimensional volumes. In such a mounting configuration, the plating operation deposits copper (or some other metal or alloy) at approximately the same rate at each deposition location. Thus, the height of the bump pads 370, 372 can be controlled by careful selection of other dimensions of the bump pads 370, 372 to ensure that the bump pads 370, 372 have the same volume at the end of the plating operation.

[0063] Step 10 in Figure 3C shows the state after the patterned layer 362 has been removed. Removal of the patterned layer 362 exposes the sides of the bump pad 370, the top of the bump pad 372 (e.g., the post portion 374), the sides of the contact pad 360, the top surface of the dielectric layer 340, or a combination thereof. Removal of the patterned layer 362 can be performed using one or more delamination, delamination, or ashing operations, or other operations appropriate for separating the patterned layer 362 from adjacent structures such as the metal layer 358, bump pads 370, 372, and / or dielectric layer 340.

[0064] Step 11 shows the state after the formation of the solder resist layer 368 covering the metal layer 358, bump pads 370, 372, and dielectric layer 340. The solder resist layer 368 can be formed using one or more lamination processes or one or more liquid or gel coating processes (e.g., spraying, rolling, dipping, or other coating operations).

[0065] Step 12 shows the state after the solder resist layer 368 has been thinned to expose a portion of the bump pads 370, 372. For example, the solder resist layer 368 can be thinned using one or more etching operations. In some mounting configurations, the solder resist layer 368 is cured after thinning. In other mounting configurations, the solder resist layer 368 is cured or partially cured before thinning (for example, in Step 11).

[0066] Step 13 shows the state after the die 380 (including dies 380A and 380B) has been mounted on bump pads 370 and 372 to form device 390. In a particular mounting configuration, die 380 includes solder bumps 382, ​​which are coupled to bump pads 370, 372 and heated to reflow the solder bumps in order to electrically connect die 380 to bump pads 370, 372. Electrically connecting die 380 to bump pads 370 provides a conductive path between die 380 and the out-of-package contacts. For example, electrically connecting die 380A to bump pad 370A provides a conductive path 388A from die 380A to out-of-package contact 374A, and electrically connecting die 380B to bump pad 370B provides a conductive path 388B from die 380B to out-of-package contact 374B. A conductive path is provided between the dies 380 by electrically connecting the die 380 to the bump pad 372. For example, a conductive path 386 is provided between the dies 380 via an embedded interconnect structure by electrically connecting die 380A to bump pad 372A and die 380B to bump pad 372B.

[0067] Exemplary flowchart of a method for manufacturing a device including an embedded interconnect structure. In some implementations, manufacturing a device containing an embedded interconnect structure involves several processes. Figure 4 shows an exemplary flowchart of Method 400 for providing or manufacturing a device containing an embedded interconnect structure. In some implementations, Method 400 in Figure 400 may be used to provide or manufacture device 100 in Figure 1 or device 390 in Figure 3C. It should be noted that Method 400 in Figure 4 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified.

[0068] Method 400 includes obtaining a first set of layers in block 402. The first set of layers includes a first set of metallic layers separated from each other by a first set of dielectric layers. The first set of metallic layers defines a first set of metallic wires. The first set of layers also includes a first set of conductive vias that penetrate the first set of dielectric layers to interconnect the first set of metallic wires. For example, the first set of layers may include or correspond to the set of layers 208 in Figure 2 or the set of main metallic layers 300 in Figure 3A. The first set of layers can be obtained, for example, by laminating layers on a core (e.g., core 236 in Figure 2) or on a carrier substrate, patterning the metallic layers of the first set of layers to define metallic wires, and forming conductive vias for interconnecting various metallic wires to define conductive paths that penetrate the first set of layers. In some examples, additional operations can be performed. For example, one or more passive devices can be embedded in the core layer of a first set of layers and electrically connected to selected metal wires of a first set of metal wires.

[0069] Method 400 includes forming an embedded interconnect structure on a first set of layers in block 404. The embedded interconnect structure includes a second set of metal layers defining a second set of metal wires, wherein at least one of the metal layers in the second set of metal layers lacks the metal wires of the first set of metal wires. The embedded interconnect structure also includes a second set of dielectric layers, which includes at least a bottom dielectric layer between the first set of metal layers and the second set of metal layers, and an upper dielectric layer on the upper metal layer of the second set of metal layers. For example, the embedded interconnect structure may include or correspond to the features of the die-to-die interconnect region 130 in Figure 1. Exemplarily, the embedded interconnect structure may include dielectric layer 144, dielectric layer 170, dielectric layer 172, metal layer 146, metal layer 148, and conductive via 168. In another example, the embedded interconnect structure may include or correspond to the features of the set of layers 206 in Figure 2. For example, the embedded interconnect structure may include dielectric layer 226, metal layer 228, dielectric layer 230, metal layer 232, and dielectric layer 234. In some implementations, the embedded interconnect structure is located within the die interconnect region, and the metal wires of the first set of metal wires do not traverse the die interconnect region. For example, the metal wires of metal layer 112 do not traverse the die interconnect region 130 in Figure 1. In some implementations, the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires. For example, the metal wires of metal layer 112 are not coplanar with any of the metal wires of metal layers 146 and 148 in Figure 1. Examples of operations that can be used to form the embedded interconnect structure are illustrated with reference to steps 2-4 in Figure 3A.

[0070] Method 400 includes forming a first pad and a first conductive via in block 406, the first conductive via extending through an embedded interconnect structure to a first set of metal layers. For example, the first pad and the first conductive via may include or correspond to the post structure 126 in Figure 1. Examples of operations that can be used to form the first pad and the first conductive via are illustrated with reference to steps 5-6 in Figures 3A-3C.

[0071] Method 400 includes forming a first contact on a first pad in block 408 and forming a second contact including a via portion that penetrates the upper dielectric layer of the embedded interconnect structure and extends to the upper metal layer of a second set of metal layers. For example, the first contact may include or correspond to contact 150 in Figure 1, contact 222 in Figure 2, or bump pad 370 in Figure 3B. The second contact may include or correspond to contact 152 in Figure 1, contact 220 in Figure 2, or bump pad 372 in Figure 3B. Examples of operations that can be used to form the first and second contacts are illustrated with reference to steps 8-9 in Figure 3B.

[0072] In some implementations, the method also includes electrically connecting the first die to the second die via a second contact and embedded interconnect structure. For example, the first and second dies may include or correspond to die 102 in Figure 1 or die 380 in Figure 3C. An example of an operation that can be used to electrically connect the first die and the second die is illustrated with reference to step 13 in Figure 3C.

[0073] Exemplary electronic devices Figure 5 shows various electronic devices that include, or can be integrated with, device 100 in Figure 1 or device 390 in Figure 3C. For example, a mobile phone device 502, a laptop computer device 504, a stationary terminal device 506, a wearable device 508, or a vehicle 510 (e.g., an automobile or an aerial device) may include device 500. Device 500 may include, for example, device 100 in Figure 1, device 390 in Figure 3C, or other devices described herein. Devices 502, 504, 506, and 508 shown in Figure 5, as well as the vehicle 510, are merely examples. Device 500 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0074] One or more of the components, processes, features, and / or functions shown in Figures 1 to 5 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1 to 5 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1 to 5 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, heat dissipation devices, and / or interposers.

[0075] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various components and / or elements in the figures may be optional.

[0076] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two electrically coupled objects may or may not transmit an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or fourth or higher) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The terms “encapsulate,” “encapsulating,” and / or any derived terms mean that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa.As described in this disclosure, a first component located "over" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) a first surface of the second component, and the third component may be located above (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being located above another, the term "on" as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of a component or embedded within a component). Therefore, for example, a first component above a second component may mean (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located "in" a second component may be partially located within the second component, or it may be completely located within the second component. A value of about X to XX may mean a value between X and XX, including X and XX. The value(s) between X and XX may be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10 percent of "value X". For example, a value of "about 1" or "approximately 1" would mean a value in the range of 0.9 to 1.1. The term "multiple" components may include all possible components, or only some of all possible components. For example, if a device contains 10 components, the term "multiple components" may refer to all 10 components, or only some of the 10 components.

[0077] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0078] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0079] Further embodiments are described below to facilitate understanding of this disclosure.

[0080] According to Embodiment 1, the device includes a substrate including a first conductor that electrically connects a first contact on a first side of the substrate to a second contact on a second side of the substrate. The first conductor includes a first set of metal wires arranged in a first set of metal layers separated from each other by a first set of dielectric layers. The first conductor also includes a first set of conductive vias that interconnect the first set of metal wires via the first set of dielectric layers. The substrate also includes a second conductor that electrically connects a third contact on a first side of the substrate to a fourth contact on a first side of the substrate, defining a conductive path between a first die and a second die. The second conductor includes a second set of metal wires arranged in a second set of metal layers separated from each other by a second set of dielectric layers. The second conductor also includes a second set of conductive vias that interconnect the second set of metal wires. At least one of the second set of metal layers lacks the metal wires of the first set of metal wires.

[0081] Example 2 includes the device of Example 1, wherein the first set of metal layers and the second set of metal layers are separate and do not overlap.

[0082] Example 3 includes the device of Example 1 or Example 2, wherein two or more dielectric layers of a second set of dielectric layers are disposed between the first side of the substrate and the first set of metal layers.

[0083] Example 4 includes any of the devices from Examples 1 to 3, wherein the cross-section of each post structure of the first contact is different from the cross-section of each post structure of the third contact and each post structure of the fourth contact.

[0084] Example 5 comprises any device from Examples 1 to 4, further comprising a two-layer post structure including one of the first contacts, and a one-layer post structure including a via structure and one of the third contacts.

[0085] Example 6 includes any device from Examples 1 to 5, and further includes a first die coupled to a third contact and a first subset of the first contacts, and a second die coupled to a fourth contact and a second subset of the first contacts.

[0086] Example 7 includes any of the devices from Examples 1 to 6, wherein a second set of conductors is arranged within the die interconnection region, and none of the first set of metal wires traverses the die interconnection region.

[0087] Example 8 includes any of the devices from Examples 1 to 7, wherein the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires.

[0088] Example 9 includes any device from Examples 1 to 8, wherein a first set of metal wires has a first characteristic dimension, a second set of metal wires has a second characteristic dimension, and the first characteristic dimension is greater than the second characteristic dimension.

[0089] Example 10 includes any device from Examples 1 to 9, wherein a first set of metal wires has a first characteristic line width, and a second set of metal wires has a second characteristic line width, with the first characteristic line width being greater than the second characteristic line width.

[0090] Example 11 comprises any device from Examples 1 to 10, wherein a first set of metal layers has a first characteristic thickness, and a second set of metal layers has a second characteristic thickness, with the first characteristic thickness being greater than the second characteristic thickness.

[0091] Example 12 includes any device from Examples 1 to 11, wherein a first set of dielectric layers has a first characteristic thickness, and a second set of dielectric layers has a second characteristic thickness, with the first characteristic thickness being greater than the second characteristic thickness.

[0092] Example 13 includes any device from Examples 1 to 12 and further includes a plurality of solder balls electrically connected to a second contact to form a ball grid array.

[0093] According to Example 14, the device includes a first die having a first circuit, a second die having a second circuit, and a substrate. The substrate is configured to electrically connect the first circuit to the second circuit and to electrically connect the first circuit, the second circuit, or both to one or more out-of-package devices. The substrate includes a first conductor that electrically connects a first contact on a first side of the substrate to a second contact on a second side of the substrate. The first conductor includes a first set of metallic wires arranged in a first set of metallic layers separated from each other by a first set of dielectric layers, and a first set of conductive vias that interconnect the first set of metallic wires via the first set of dielectric layers. The substrate also includes a second conductor that electrically connects a third contact on a first side of the substrate to a fourth contact on a first side of the substrate, defining a conductive path between the first die and the second die. The second conductor includes a second set of metallic wires arranged in a second set of metallic layers separated from each other by a second set of dielectric layers, and a second set of conductive vias interconnecting the second set of metallic wires. At least one of the metallic layers in the second set of metallic layers lacks a metallic wire from the first set of metallic wires.

[0094] Example 15 includes the device of Example 14, wherein the first set of metal layers and the second set of metal layers are separate and do not overlap.

[0095] Example 16 includes the device of Example 14 or Example 15, wherein two or more dielectric layers of a second set of dielectric layers are arranged between the first side of the substrate and the first set of metal layers.

[0096] Example 17 includes any device from Examples 14 to 16, wherein the cross-section of each post structure of the first contact is different from the cross-section of each post structure of the third contact and each of the fourth contacts.

[0097] Example 18 includes any device from Examples 14 to 17, and further includes a two-layer post structure including one of the first contacts, and a one-layer post structure including a via structure and one of the third contacts.

[0098] Example 19 includes any of the devices from Examples 14 to 18, wherein a second set of conductors is arranged within the die interconnection region, and none of the metal wires from the first set of metal wires traverse the die interconnection region.

[0099] Example 20 includes any device from Examples 14 to 19, wherein the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires.

[0100] Example 21 includes any device from Examples 14 to 20, wherein a first set of metal wires has a first characteristic dimension, a second set of metal wires has a second characteristic dimension, and the first characteristic dimension is greater than the second characteristic dimension.

[0101] Example 22 includes any device from Examples 14 to 21, wherein a first set of metal wires has a first characteristic line width, and a second set of metal wires has a second characteristic line width, with the first characteristic line width being greater than the second characteristic line width.

[0102] Example 23 comprises any device from Examples 14 to 22, wherein a first set of metal layers has a first characteristic thickness, and a second set of metal layers has a second characteristic thickness, with the first characteristic thickness being greater than the second characteristic thickness.

[0103] Example 24 includes any device from Examples 14 to 23, wherein a first set of dielectric layers has a first characteristic thickness, and a second set of dielectric layers has a second characteristic thickness, with the first characteristic thickness being greater than the second characteristic thickness.

[0104] Example 25 includes any device from Examples 14 to 24 and further includes a plurality of solder balls electrically connected to a second contact to form a ball grid array configured to be coupled to one or more out-of-package devices.

[0105] Example 26 includes any device from Examples 14 to 25, wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

[0106] Example 27 includes the device of Example 26, wherein the first circuit of the first chiplet includes one or more first functional circuit blocks, the second circuit of the second chiplet includes one or more second functional circuit blocks, and the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0107] Example 28 includes any device from Examples 14 to 27, wherein a first circuit on a first die defines one or more processor cores, and a second circuit on a second die defines one or more memory cells.

[0108] According to Example 29, a method for manufacturing a device includes obtaining a first set of layers. The first set of layers includes a first set of metal layers separated from each other by a first set of dielectric layers, the first set of metal layers defining a first set of metal wires. The first set of layers also includes a first set of conductive vias that penetrate the first set of dielectric layers to interconnect the first set of metal wires. The method also includes forming an embedded interconnect structure on the first set of layers. The embedded interconnect structure includes a second set of metal layers defining a second set of metal wires, at least one of the metal layers in the second set of metal layers lacking metal wires from the first set of metal wires. The embedded interconnect structure includes a second set of dielectric layers, at least a bottom dielectric layer between the first set of metal layers and the second set of metal layers, and an upper dielectric layer on the upper metal layer of the second set of metal layers. The method includes forming a first pad and a first conductive via. The first conductive via extends through the embedded interconnect structure to the first set of metal layers. The method includes forming a first contact on a first pad and forming a second contact including a via portion that penetrates the upper dielectric layer of the embedded interconnect structure and extends to the upper metal layer of a second set of metal layers.

[0109] Example 29 includes the method of Example 28, further comprising electrically connecting the first die to the second die via a second contact and embedded interconnection structure.

[0110] Example 30 includes the method of Example 28 or Example 29, wherein the embedded interconnection structure is located within the inter-die interconnection region, and the first set of metal wires does not cross the inter-die interconnection region.

[0111] Example 31 includes any method from Examples 28 to 30, wherein the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires.

[0112] Example 32 comprises any method of Examples 28 to 31, wherein a first set of metal wires has a first characteristic dimension, and a second set of metal wires has a second characteristic dimension, and the first characteristic dimension is greater than the second characteristic dimension.

[0113] Example 33 comprises any method of Examples 28 to 32, wherein a first set of metal wires has a first characteristic line width, and a second set of metal wires has a second characteristic line width, and the first characteristic line width is greater than the second characteristic line width.

[0114] Example 34 comprises any method of Examples 28 to 33, wherein the first set of metal layers has a first characteristic thickness, and the second set of metal layers has a second characteristic thickness, with the first characteristic thickness being greater than the second characteristic thickness.

[0115] Example 35 comprises any method of Examples 28 to 34, wherein a first set of dielectric layers has a first characteristic thickness, and a second set of dielectric layers has a second characteristic thickness, and the first characteristic thickness is greater than the second characteristic thickness.

[0116] Example 36 comprises any method of Examples 28 to 35, further comprising forming a ball grid array on the side of a first set of layers opposite to the first contact, wherein the ball grid array is electrically connected to the first contact via a first set of metal wires.

[0117] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the claims. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. It is a device, It is a substrate, A first conductor electrically connects a first contact on the first side of the substrate to a second contact on the second side of the substrate, wherein the first conductor is A first set of metal wires arranged in a first set of metal layers separated from each other by a first set of dielectric layers, A first set of conductive vias interconnects the first set of metal wires via the first set of dielectric layers, A first conductor including, A second conductor electrically connects the third contact on the first side of the substrate to the fourth contact on the first side of the substrate, thereby defining a conductive path between the first die and the second die, wherein the second conductor is A second set of metal wires arranged in a second set of metal layers separated from each other by a second set of dielectric layers, A second set of conductive vias interconnecting the second set of metal wires, A second conductor including, Equipped with, At least one of the second set of metal layers lacks a metal wire from the first set of metal wires. substrate, A device equipped with the following features.

2. The device according to claim 1, wherein the first set of metal layers and the second set of metal layers are separate and do not overlap.

3. The device according to claim 1, wherein two or more dielectric layers of the second set of dielectric layers are disposed between the first side of the substrate and the first set of metal layers.

4. The device according to claim 1, wherein the cross-section of each post structure of the first contact is different from the cross-section of the post structure of each of the third contacts and each of the fourth contacts.

5. The device according to claim 1, further comprising a two-layer post structure including one of the first contacts, and a one-layer post structure including a via structure and one of the third contacts.

6. The first die coupled to the third contact and the first subset of the first contact, The second die coupled to the fourth contact and the second subset of the first contact, The device according to claim 1, further comprising:

7. The device according to claim 1, wherein a second set of conductors is arranged within the inter-die interconnection region, and none of the metal wires of the first set of metal wires cross the inter-die interconnection region.

8. The device according to claim 1, wherein the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires.

9. The device according to claim 1, wherein a first set of metal wires has a first characteristic dimension, a second set of metal wires has a second characteristic dimension, and the first characteristic dimension is larger than the second characteristic dimension.

10. The device according to claim 1, wherein a first set of metal wires has a first characteristic line width, a second set of metal wires has a second characteristic line width, and the first characteristic line width is greater than the second characteristic line width.

11. The device according to claim 1, wherein a first set of the metal layers has a first characteristic thickness, a second set of the metal layers has a second characteristic thickness, and the first characteristic thickness is greater than the second characteristic thickness.

12. The device according to claim 1, wherein a first set of dielectric layers has a first characteristic thickness, a second set of dielectric layers has a second characteristic thickness, and the first characteristic thickness is greater than the second characteristic thickness.

13. The device according to claim 1, further comprising a plurality of solder balls electrically connected to the second contact in order to form a ball grid array.

14. It is a device, A first die having a first circuit, A second die having a second circuit, A substrate configured to electrically connect the first circuit to the second circuit, and to electrically connect the first circuit, the second circuit, or both thereof to one or more external devices, Equipped with, The aforementioned substrate, A first conductor electrically connects a first contact on the first side of the substrate to a second contact on the second side of the substrate, wherein the first conductor is A first set of metal wires arranged in a first set of metal layers separated from each other by a first set of dielectric layers, A first set of conductive vias interconnects the first set of metal wires via the first set of dielectric layers, A first conductor including, A second conductor electrically connects the third contact on the first side of the substrate to the fourth contact on the first side of the substrate, thereby defining a conductive path between the first die and the second die, wherein the second conductor is A second set of metal wires arranged in a second set of metal layers separated from each other by a second set of dielectric layers, A second set of conductive vias interconnecting the second set of metal wires, A second conductor including, Equipped with, At least one of the second set of metal layers lacks a metal wire from the first set of metal wires. device.

15. The device according to claim 14, wherein the first set of metal layers and the second set of metal layers are separate and do not overlap.

16. The device according to claim 14, wherein two or more dielectric layers of the second set of dielectric layers are disposed between the first side of the substrate and the first set of metal layers.

17. The device according to claim 14, wherein the cross-section of each post structure of the first contact is different from the cross-section of the post structure of each of the third contacts and each of the fourth contacts.

18. The device according to claim 14, further comprising a two-layer post structure including one of the first contacts, and a one-layer post structure including a via structure and one of the third contacts.

19. The device according to claim 14, wherein the second set of conductors is arranged within the inter-die interconnection region, and none of the metal wires of the first set of metal wires cross the inter-die interconnection region.

20. The device according to claim 14, wherein the metal wires of the first set of metal wires are not coplanar with any of the metal wires of the second set of metal wires.

21. The device according to claim 14, wherein a first set of metal wires has a first characteristic dimension, a second set of metal wires has a second characteristic dimension, and the first characteristic dimension is larger than the second characteristic dimension.

22. The device according to claim 14, wherein a first set of metal wires has a first characteristic line width, a second set of metal wires has a second characteristic line width, and the first characteristic line width is greater than the second characteristic line width.

23. The device according to claim 14, wherein the first set of metal layers has a first characteristic thickness, the second set of metal layers has a second characteristic thickness, and the first characteristic thickness is greater than the second characteristic thickness.

24. The device according to claim 14, wherein the first set of dielectric layers has a first characteristic thickness, the second set of dielectric layers has a second characteristic thickness, and the first characteristic thickness is greater than the second characteristic thickness.

25. The device according to claim 14, further comprising a plurality of solder balls electrically connected to the second contact to form a ball grid array configured to be coupled to one or more of the above-mentioned out-of-package devices.

26. The device according to claim 14, wherein the first die is a first chiplet, and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

27. The device according to claim 26, wherein the first circuit of the first chiplet includes one or more first functional circuit blocks, the second circuit of the second chiplet includes one or more second functional circuit blocks, and the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

28. A manufacturing method, To obtain a first set of layers, wherein the first set of layers is A first set of metal layers separated from each other by a first set of dielectric layers, wherein the first set of metal layers defines a first set of metal wires, A first set of conductive vias that penetrate the first set of dielectric layers to interconnect the first set of metal wires, Including obtaining, Forming an embedded interconnection structure on the first set of the layers, wherein the embedded interconnection structure is A second set of metal layers defining a second set of metal wires, wherein at least one of the metal layers in the second set of metal layers lacks a metal wire from the first set of metal wires, A second set of dielectric layers comprising at least a bottom dielectric layer between the first set of metal layers and the second set of metal layers, and an upper dielectric layer on the upper metal layer of the second set of metal layers, This includes forming an embedded interconnection structure, Forming a first pad and a first conductive via, wherein the first conductive via extends through the embedded interconnection structure to a first set of metal layers. A first contact is formed on the first pad, and a second contact is formed including a via portion that penetrates the upper dielectric layer of the embedded interconnect structure and extends to the upper metal layer of the second set of metal layers, Methods that include...

29. The method according to claim 28, further comprising electrically connecting the first die to the second die via the second contact and the embedded interconnection structure.

30. The method according to claim 28, wherein the embedded interconnection structure is disposed within the inter-die interconnection region, and the first set of metal wires does not cross the inter-die interconnection region.

Images