Essentially region-selective deposition of silicon-containing insulators on metal substrates

Abstract

Essentially selective methods for depositing a silicon-containing insulating layer on a metal layer include atomic layer deposition or chemical vapor deposition utilizing a chemical precursor and oxidizing agent containing silicon and sulfur. An optional buffer layer may exist between the metal layer and the selectively deposited film.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Application No. 63 / 536,743, filed on 6 September 2023, all of which are incorporated herein by reference. [Background technology]

[0002] To create functional semiconductor devices, it is typically necessary to deposit insulating oxide layers onto metal structures such as interconnects, gate electrodes, and contact pads. However, directly and selectively depositing oxide layers onto metal surfaces in the presence of other oxide or nitride layers can be a challenging process due to differences in reactivity and surface energy between the deposition material and the target substrate, as well as the similarity of the deposition material to the non-target surface. In particular, the deposition of oxide layers as insulating cap layers in embedded trenches has been proposed as a key target area for diode-on-metal (DoM) research due to the difficulties in conventional photolithography and etching processes for creating well-formed, flat insulating layers at the bottom of trenches.

[0003] Current methods for depositing insulators on metals utilize photolithography to form patterns of insulators deposited across the entire substrate. However, as minimum processing dimensions decrease, alignment errors in photolithography masks have become a greater cause of equipment failure. Furthermore, photolithography is a complex process involving many individual steps and associated costs. Area-Selective Deposition (ASD) eliminates the need for photolithography by depositing the desired material only in targeted areas of the substrate, and is becoming an increasingly important field in semiconductor manufacturing. While many ASD schemes have been published in recent years, few deal with selective deposition of oxide-based insulators on metal surfaces using other and / or the same insulator as the non-growth surface. This is due to the inherent difficulty in developing the chemistry for selective deposition of oxide-based insulators on metal surfaces with significantly different chemical and physical properties compared to insulator surfaces with similar chemical and physical properties to the grown layer. Furthermore, within the scope of reported selective diode-on-metal schemes, many deposited metal oxide insulators, such as Al2O3, ZnO, Fe2O3, Ta2O5, or Mn3O4, have high dielectric constants and are therefore unsuitable as insulators for most semiconductor applications.

[0004] The selective deposition of low dielectric constant insulators on metals without simultaneous deposition of the insulator on the existing insulating region of the substrate presents several unique challenges, including the chemical similarity between the grown insulating film and the non-grown surface or surface, and the incompatibility of the harsh deposition process used for insulator deposition on the blocking layer typically used in ASD schemes. Previous reports on dielectric-on-metal deposition address these challenges by depositing insulating layers with different chemical properties from the existing insulating layer of the film, typically containing silica, SiOC low-k insulators, silicon nitride, or other silicon-based films. In these reports, oxides such as alumina, zinc oxide, iron oxide, tantalum oxide, or manganese oxide are selectively deposited on metals compared to insulating surfaces. However, these oxides have high dielectric constants, limiting their practical applications.

[0005] US Patent No. 11,830,732; US Patent No. 11,643,720; US Patent No. 11,450,529; Oh et al. (Advanced Functional Materials (2024); Li et al., (Molecules, 26, 3056 (2021)); Cho et al., (Applied Surface Science, 622 (2023)); Chen et al. (Chem. Mater., 17, 536-544 (2005)); Lui et al., (Adv. Mater. Interfaces, 10 (2023)); and Singh et al., (Chem. Mater., 30, 663-670 Several ASD processes for the selective deposition of insulators on metal substrates have been reported in the literature, such as (2018). These disclosures are limited to high-k oxides such as alumina, hafnia, zirconia, and oxides of tantalum, iron, nickel, and manganese. Furthermore, few of these reports address intrinsic selectivity and utilize complex blocking / unblocking schemes for the direct growth of insulators on target metal surfaces. While high-k oxides are suitable for some applications, low-k oxides containing silicon are highly desirable in many applications and equipment structures. [Overview of the project] [Problems that the invention aims to solve]

[0006] What is desired is a method for selectively depositing a low dielectric constant film, such as SiO2, onto a metallic region of a patterned semiconductor substrate without incidental deposition on the existing insulating region of the substrate, and more preferably a method for such deposition without requiring additional process steps of adding and removing blocking layers on the non-growth surface. [Means for solving the problem]

[0007] Aspects of this disclosure are methods for selectively depositing a silicon-containing insulating layer on a patterned substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated nonmetallic region, and the temperature of the reaction region is between approximately 25°C and approximately 500°C; and (b) A step of forming a silicon-containing insulating layer covering only one metallic region of a patterned substrate by atomic layer deposition or chemical vapor deposition, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. This includes methods.

[0008] A further aspect of the present disclosure is a second method for selectively depositing a silicon-containing insulating layer on a patterned substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposit tank, wherein the patterned substrate has a first layer and a second layer, the first layer includes at least one metallic region and at least one isolated non-metallic region, the second layer includes a buffering material, and the temperature of the reaction region is between about 25°C and about 500°C; and (b) A step of forming a silicon insulating layer on the second layer of the patterned substrate by atomic layer deposition or chemical vapor deposition, covering only at least one metal region of the first layer, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. This includes methods.

[0009] Advantageous improvements to the present invention, whether made alone or in combination, are specified in the dependent claims.

[0010] In summary, the following embodiments are proposed as particularly preferred embodiments within the scope of the present invention: Embodiment 1: A method for selectively depositing a silicon-containing insulating layer on a patterned substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated nonmetallic region, and the temperature of the reaction region is between approximately 25°C and approximately 500°C; and (b) A step of forming a silicon-containing insulating layer covering only one metallic region of a patterned substrate by atomic layer deposition or chemical vapor deposition, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. Methods that include...

[0011] Embodiment 2: The method according to Embodiment 1, wherein the silicon-containing insulating layer is formed on at least one metallic region of the patterned substrate with a thickness of at least about 2 nm, but not on at least one non-metallic region of the patterned substrate, or is formed on at least one non-metallic region of the patterned substrate with a thickness of less than about 1 nm.

[0012] Embodiment 3: The method according to Embodiment 1 or 2, wherein the silicon and sulfur compound comprises silicon and sulfur atoms linked by at least one direct silicon-sulfur bond, or by a linear, branched, or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms.

[0013] Embodiment 4: A compound containing silicon and sulfur is a compound of formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8: [ka] having, wherein n is an integer from 1 to about 4, m is an integer from 1 to about 6, R1, R2, R3, R4, R5, R6, and R7 are each independently hydrogen, or a linear, branched or cyclic, optionally substituted alkoxy group, alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or SiR 13 R 14 R 15 , OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 having the general formula, wherein R 13 , R 14 , and R 15 are each independently hydrogen or an alkyl or alkoxy group having 1 to about 12 carbon atoms, which is a linear, branched or cyclic, optionally substituted silyl group; and R 16 is a linear or branched alkyl group having 1 to about 12 carbon atoms; R8 is hydrogen, or a linear, branched or cyclic, optionally substituted alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or a linear, branched or cyclic, optionally substituted SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 silyl group having the general formula; R9, R 10 and R 11Each is independently a linear, branched, or cyclic alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms; R 12 OH, Cl, NR 17 R 18 , aryl or CN, where R 17 and R 18 Each is independently a hydrogen atom, or an alkyl, aryl, alkyne, alkene, ether, ester, or ketone having one to about 12 optionally substituted carbon atoms in a linear, branched, or cyclic chain; and X = Si(R3,R4)-(S-Si(R5,R6)) p or (CH2) q The method according to any one of Embodiments 1 to 3, wherein p is an integer between 0 and approximately 3, and q is an integer between approximately 1 and approximately 4.

[0014] Embodiment 5: Compounds of formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8 are 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, 2,2-diethoxy-1-thia-2-silacyclopentane, bis(trimethylsilyl)sulfide, (mercaptomethyl)methyldiethoxysilane, trimethylsilanthol, 2,2-methyl-1-thia-2-silacyclopentane Tan, 2,2-dimethoxy-4-methyl-1-thia-2-silacyclopentane, 2,2-diethoxy-4-methyl-1-thia-2-silacyclopentane, silanthiol, triisopropylsilanthiol, trimethoxysilanthiol, triethoxysilanthiol, disilatian, trimethyl(methylthio)silane, trimethyl(ethylthio)silane, 2,2-dimethyl-1,3-dithia-2-silacyclopentane, 2,2,4, 4-Tetramethylcyclodisilatian, 2,2,8,8-Tetramethyl-3,7-Dithia-2,8-Disilanonan, Hexamethylcyclotrisilathian, [(trimethylsilyl)thio]benzene, (3-mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2-(trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3-mercaptopropyl The method according to Embodiment 4, wherein the material is triethoxysilane, 4-(dimethoxymethylsilyl)-1-butanethiol, 3-(trimethoxysilyl)-1-propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl]tetrasulfide, 1,1'-thiobis(methylene)bis[1,1,1-trimethylsilane], or 1-(diethoxymethylsilyl)methanethiol.

[0015] Embodiment 6: The method according to Embodiment 5, wherein the silicon and sulfur-containing compound is 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, (mercaptomethyl)methyldiethoxysilane, or 2,2-diethoxy-1-thia-2-silacyclopentane.

[0016] Embodiment 7: The method according to any one of Embodiments 1 to 6, wherein the patterned substrate is simultaneously brought into contact with a compound containing silicon and sulfur and an oxidizing agent.

[0017] Embodiment 8: The method according to any one of Embodiments 1 to 6, wherein the patterned substrate is sequentially contacted with a compound containing silicon and sulfur and an oxidizing agent.

[0018] Embodiment 9: The method according to any one of Embodiments 1 to 8, further comprising the step of performing an annealing treatment, a cleaning treatment, an etching treatment, or a plasma treatment on the patterned substrate before step (b).

[0019] Embodiment 10: The method according to any one of Embodiments 1 to 9, further comprising the step of contacting the patterned substrate with a chemical blocking agent before step (b) to selectively passivate at least one region of the substrate.

[0020] Embodiment 11: The method according to any one of Embodiments 1 to 10, wherein the oxidizing agent is a plasma generated from a gas mixture containing at least one of O2, H2O, H2O2, O3, CO2, N2O, and NO2, and optionally a carrier gas containing N2, Ar, or He.

[0021] Embodiment 12: The method according to any one of Embodiments 1 to 11, wherein the silicon-containing insulating layer has a thickness of approximately 2 nm or more and approximately 20 nm or less.

[0022] Embodiment 13: The method according to Embodiment 12, wherein the silicon-containing insulating layer has a thickness of approximately 3 nm to approximately 10 nm.

[0023] Embodiment 14: The method according to any one of Embodiments 1 to 13, wherein the temperature of the reaction vessel is approximately 75°C or higher and approximately 300°C or lower.

[0024] Embodiment 15: The method according to any one of Embodiments 1 to 14, wherein the patterned substrate comprises silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, silicon nitride, silicon carbon nitride, silicon carbide borosilicate, carbon, or alumina.

[0025] Embodiment 16: The method according to any one of Embodiments 1 to 15, wherein a silicon-containing insulating layer is selectively grown on at least one region of a patterned substrate comprising copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold.

[0026] Embodiment 17: The method according to any one of Embodiments 1 to 16, wherein the deposited film has a dielectric constant of less than about 10.

[0027] Embodiment 18: The method according to Embodiment 17, wherein the deposited film has a dielectric constant of less than about 5.

[0028] Embodiment 19: The method according to any one of Embodiments 1 to 18, wherein atomic layer deposition is used to form a silicon-containing insulating layer.

[0029] Embodiment 20: Atomic layer deposition method: (b1) A step of bringing a patterned substrate into contact with pulses of a compound containing silicon and sulfur; (b2) A step of optionally purging the storage tank; (b3) A step of bringing the patterned substrate into contact with an oxidizing agent; (b4) A step of optionally purging the storage tank; and (b5) A process that repeats steps (b1) through (b4) until the desired layer thickness is reached. The method according to Embodiment 19, including the method described in Embodiment 19.

[0030] Embodiment 21: The method according to Embodiment 20, further comprising the step of performing an annealing, cleaning, etching, or plasma treatment on the patterned substrate prior to step (b1), and / or contacting the patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate.

[0031] Embodiment 22: The method according to Embodiment 20 or 21, further comprising the steps of annealing, cleaning, etching, or plasma treatment of the patterned substrate after step (b5), and / or contacting the patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate.

[0032] Embodiment 23: The method according to any one of Embodiments 20 to 22, wherein the pulse of the silicon and sulfur compound has a duration of about 0.05 seconds or more and about 30 seconds or less.

[0033] Embodiment 24: The method according to Embodiment 23, wherein the pulse of the silicon and sulfur compound has a duration of about 3 seconds or more and about 10 seconds or less.

[0034] Embodiment 25: The method according to any one of Embodiments 20 to 22, wherein the patterned substrate is in contact with an oxidizing agent for a period of approximately 0.5 seconds to approximately 60 seconds.

[0035] Embodiment 26: The method according to Embodiment 25, wherein the patterned substrate is in contact with an oxidizing agent for a period of approximately 5 seconds to approximately 20 seconds.

[0036] Embodiment 27: The method according to any one of Embodiments 1 to 18, wherein chemical vapor deposition or pulsed chemical vapor deposition is used to form a silicon-containing insulating layer.

[0037] Embodiment 28: Chemical vapor deposition or pulsed chemical vapor deposition: (b1) A step of contacting the patterned substrate with a silicon and sulfur compound and simultaneously with an oxidizing agent until the desired layer thickness is reached; and (b2) Repeat step (b1) until the second desired layer thickness is reached. The method according to Embodiment 27, including the method described in Embodiment 27.

[0038] Embodiment 29: A method for selectively depositing a silicon-containing insulating layer on a substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposit tank, wherein the patterned substrate has a first layer and a second layer, the first layer includes at least one metallic region and at least one isolated non-metallic region, the second layer includes a buffering material, and the temperature of the reaction region is between about 25°C and about 500°C; and (b) A step of forming a silicon insulating layer on a second layer of a patterned substrate by atomic layer deposition or chemical vapor deposition, covering only at least one metal region of the first layer, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. Methods that include...

[0039] Embodiment 30: Compounds containing silicon and sulfur are of formulas 1 to 8: [ka] Having one of the following, where n is an integer between approximately 1 and 4, m is an integer between approximately 1 and 6, and R1, R2, R3, R4, R5, R6, and R7 are each independently a hydrogen atom or an alkoxy group, alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group, or alkyl(dialkylamino) group having one to approximately 12 carbon atoms; or SiR 13 R 14 R 15 OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 It has a general formula, in which R 13, R 14 , and R 15 Each is independently a linear, branched, or cyclic, optionally substituted silyl group having hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms; and R 16 R8 is a linear or branched alkyl group having 1 to about 12 carbon atoms; R8 is hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group, or alkyl(dialkylamino) group; or a linear, branched, or cyclic, optionally substituted SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 A silyl group having the general formula; R9, R 10 and R 11 Each is independently a linear, branched, or cyclic alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms; R 12 OH, Cl, NR 17 R 18 , aryl or CN, where R 17 and R 18 Each is independently a hydrogen atom, or an alkyl, aryl, alkyne, alkene, ether, ester, or ketone having one to about 12 optionally substituted carbon atoms in a linear, branched, or cyclic chain; and X = Si(R3,R4)-(S-Si(R5,R6)) p or (CH2) q The method according to Embodiment 29, wherein p is an integer between 0 and approximately 3, and q is an integer between approximately 1 and approximately 4.

[0040] Embodiment 31: Compounds of formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8 are 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, 2,2-diethoxy-1-thia-2-silacyclopentane, bis(trimethylsilyl)sulfide, (mercaptomethyl)methyldiethoxysilane, trimethylsilanthol, 2,2-methyl-1-thia-2-silacyclopentane Tan, 2,2-dimethoxy-4-methyl-1-thia-2-silacyclopentane, 2,2-diethoxy-4-methyl-1-thia-2-silacyclopentane, silanthiol, triisopropylsilanthiol, trimethoxysilanthiol, triethoxysilanthiol, disilatian, trimethyl(methylthio)silane, trimethyl(ethylthio)silane, 2,2-dimethyl-1,3-dithia-2-silacyclopentane, 2,2,4, 4-Tetramethylcyclodisilatiane, 2,2,8,8-Tetramethyl-3,7-Dithia-2,8-Disilanonanane, Hexamethylcyclotrisilathiane, [(trimethylsilyl)thio]benzene, (3-mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2-(trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3-mercaptopropyl The method according to Embodiment 30, wherein the material is triethoxysilane, 4-(dimethoxymethylsilyl)-1-butanethiol, 3-(trimethoxysilyl)-1-propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl]tetrasulfide, 1,1'-thiobis(methylene)bis[1,1,1-trimethylsilane], or 1-(diethoxymethylsilyl)methanethiol.

[0041] Embodiment 32: The method according to Embodiment 31, wherein the silicon and sulfur-containing compound is 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, (mercaptomethyl)methyldiethoxysilane, or 2,2-diethoxy-1-thia-2-silacyclopentane.

[0042] Embodiment 33: The method according to any one of Embodiments 29 to 32, wherein at least one metallic region comprises copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold, and the buffer layer has a thickness of less than about 10 nm.

[0043] Embodiment 34: The method according to Embodiment 33, wherein at least one metallic region comprises copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold, and the buffer layer has a thickness of less than about 5 nm.

[0044] Embodiment 35: The method according to any one of Embodiments 29 to 34, wherein the buffer layer comprises a semiconductor, an oxide, a nitride, or a mixture thereof.

[0045] Embodiment 36: The method according to any one of Embodiments 29 to 35, wherein the buffer layer comprises silicon, germanium, aluminum oxide, silicon dioxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carboxynitride, silicon carbide, tantalum nitride, titanium nitride, copper oxide, cobalt oxide, ruthenium oxide, molybdenum oxide, tungsten oxide, or a mixture thereof.

[0046] Embodiment 37: The method according to any one of Embodiments 29 to 36, wherein the oxidizing agent is a plasma generated from a gas mixture comprising at least one of O2, H2O, H2O2, O3, CO2, N2O, and NO2, and optionally a carrier gas comprising N2, Ar, or He. [Brief explanation of the drawing]

[0047] The following detailed description of preferred embodiments of the present invention will be better understood in conjunction with the accompanying drawings. For the purpose of illustrating the present invention, currently preferred embodiments are shown in the drawings. However, it should be understood that the present invention is not limited to the exact configurations and means shown.

[0048] In the drawing: [Figure 1A]Figure 1A is a schematic representation of a method according to one embodiment of the present disclosure; [Figure 1B] Figure 1B is a schematic representation of a method according to a second embodiment of the present disclosure; [Figure 2A] Figure 2A is a schematic representation of a method according to a third embodiment of the present disclosure; [Figure 2B] Figure 2B is a schematic representation of a method according to the fourth embodiment of the present disclosure; [Figure 3] Figure 3 shows graphs of in-situ polarization analysis of the films prepared in Example 1 and Example 3, and Comparative Example 4; [Figure 4] Figure 4 shows the X-ray photoelectron spectroscopy (XPS) data of the film prepared on the copper substrate as described in Example 1; [Figure 5] Figure 5 shows the XPS depth profile data of the film prepared on the cobalt substrate described in Example 2; [Figure 6] Figure 6 shows the XPS data of the silicon dioxide layer on the cobalt substrate described in Example 5; [Figure 7] Figure 7 shows the XPS data of the silicon dioxide layer on the ruthenium substrate described in Example 6; [Figure 8] Figure 8 shows the XPS data of the silicon dioxide layer on the copper substrate described in Example 7; [Figure 9] Figure 9 shows the XPS data of the non-deposited silicon dioxide layer on a natural silicon oxide substrate as described in Example 8; [Figure 10] Figure 10 shows the XPS data of the silicon dioxide / silicon oxynitride layer on a copper substrate as described in Example 9; [Figure 11] Figure 11 shows the XPS data of the non-deposited silicon dioxide layer on the silicon nitride substrate described in Example 10 and Comparative Example 11. [Modes for carrying out the invention]

[0049] Aspects of this disclosure relate to the use of atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes for selectively depositing a silicon-containing insulating layer onto some or all of the metal regions of a substrate without significantly depositing additional insulating material on some or all of the existing insulating layers of the substrate. In particular, this specification describes a method for the selective and essential deposition of a silicon-based insulator onto a patterned metal surface compared to the insulating surface of a patterned substrate, by utilizing a silicon-based precursor containing both silicon and sulfur atoms in combination with an oxidizing agent.

[0050] In one embodiment, the present disclosure provides a method for selectively depositing a silicon-containing insulating layer on a patterned substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated non-metallic region, and the temperature of the reaction region is between approximately 25°C and approximately 500°C; and (b) A step of forming a silicon-containing insulating layer covering only the at least one metal region of the patterned substrate by atomic layer deposition or chemical vapor deposition, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. This includes methods.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the meanings generally understood by a person of ordinary skill in the art to which this invention pertains. Otherwise, any specific terms used herein have the meanings set forth herein. All patent documents, published patent applications, and published patent gazettes referenced herein are incorporated by reference as being fully described herein.

[0052] Insofar as used herein and in the appended claims, it should be noted that the singular forms “a,” “an,” and “the” include plural references unless otherwise specified.

[0053] Unless otherwise stated, any numerical value should be understood in all examples as being modified by the term "approximately." Therefore, numerical values ​​typically include ±10% of the stated value. For example, a temperature value such as 10°C includes 9°C and 11°C. Where used herein, unless otherwise specified, the use of a numerical range explicitly includes all possible partial ranges, integers and fractions within that range, and all individual numerical values ​​within that range.

[0054] For the purposes of this disclosure, the term “cover” with respect to a silicon-containing insulating layer covering only the at least one metallic region of the patterned substrate may be understood as synonymous with “cover” or “on,” that is, the silicon-containing insulating layer covering / covering / placing on at least one metallic region of the patterned substrate without covering / placing on at least one non-metallic region of the patterned substrate. The terms “isolated” and “separated” are synonymous. The term “cover” and its synonyms may be understood as meaning to cover directly or indirectly, that is, with or without at least one layer between them. The terms “upon” and “on” with respect to the formation of the silicon-containing insulating layer are synonymous.

[0055] In preferred embodiments, the silicon-containing insulating layer is formed on at least one metallic region of the patterned substrate with a thickness of at least about 2 nm, and not formed on at least one non-metallic region of the patterned substrate, or formed on at least one non-metallic region of the patterned substrate with a thickness of less than about 1 nm. All of these embodiments are expected to be insulating layers formed "only" on at least one metallic region.

[0056] In other preferred embodiments, as detailed below, at least one layer containing a buffering material (also referred to as a buffer layer) is present between the substrate and the silicon-containing insulating layer. The silicon-containing insulating layer is selectively formed on the region of the buffer layer that still covers only metallic regions, and not on the region of the buffer layer that covers non-metallic regions. Metallic regions of the substrate covered or overlaid by the buffer layer may be referred to as "buried" metallic regions. In other words, the silicon-containing insulating layer is formed in a region of the substrate near at least one buried metallic region, forming a silicon-containing film of at least about 2 nm on, adjacent to, or near the buried metallic region, and forming a silicon-containing film of less than about 1 nm on, adjacent to, or near the buried metallic region of the substrate.

[0057] The buffering material of the buffer layer may include, but is not limited to, semiconductors, oxides, nitrides, or mixtures thereof, such as germanium, aluminum oxide, silicon dioxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carboxynitride, silicon carbide, tantalum nitride, titanium nitride, copper oxide, cobalt oxide, ruthenium oxide, molybdenum oxide, tungsten oxide, or mixtures thereof. The buffer layer can reduce oxidation damage or plasma damage to the substrate region during the deposition process of the silicon-containing film, or can prevent the diffusion of atoms such as sulfur atoms from the growth film to the substrate, or the diffusion of atoms from the substrate to the growth film.

[0058] In the compounds relating to this disclosure, the silicon and sulfur moieties may be directly bonded to each other, separated by linear, branched, or cyclic, optionally substituted alkylenes, aryls, alkynes, alkenes, ethers, esters, or ketones containing 1 to about 12 carbon atoms, or may constitute part or all of a ring structure. According to embodiments of this disclosure, the silicon atom may be additionally bonded to an alkoxy group, alkyl group, aryl group, alkyne group, alkene group, alkylthio group, or alkylamino group having hydrogen and 1 to about 12 carbon atoms. Furthermore, the sulfur atom may be bonded to an alkyl group, aryl group, alkyne group, alkene group, alkylthio group, or alkylamino group having hydrogen and 1 to about 12 carbon atoms, and may be in the form of, for example, thiols, alkanethiols, sulfonic acids, sulfonamides, thiocyanates, or polysulfides such as disulfides or tetrasulfides, for example.

[0059] In preferred embodiments, the silicon and sulfur-containing compound has at least one direct silicon-sulfur bond, or silicon and sulfur atoms linked by a linear, branched, or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 6 carbon atoms, more preferably formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8: [ka] It holds.

[0060] As described in more detail below, in formulas 1 to 8, n is an integer between approximately 1 and 4, m is an integer between approximately 1 and 6, and R1, R2, R3, R4, R5, R6, and R7 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkoxy group, alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group, or alkyl(dialkylamino) group having 1 to approximately 12 carbon atoms (preferably between approximately 1 and approximately 4 carbon atoms); or SiR 13 R 14 R 15 OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 It has a general formula, in which R 13 , R 14 , and R 15 Each of these is independently a linear, branched, or cyclic, optionally substituted silyl group having hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms); and R 16 R8 is a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms); R8 is hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group, or alkyl(dialkylamino) group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms); or a linear, branched, or cyclic, optionally substituted SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15is a silyl group having the general formula; R9, R 10 and R 11 are each independently linear, branched or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester or ketone having 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms); R 12 is OH, Cl, NR 17 R 18 , aryl or CN, wherein R 17 and R 18 are each independently hydrogen, or linear, branched or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester or ketone having 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms); and X = Si(R3,R4)-(S-Si(R5,R6)) p or (CH2) q wherein p is an integer of 0 to about 3, and q is an integer of about 1 to 4.

[0061] Specific examples of silicon compounds within the scope of this disclosure include 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, 2,2-diethoxy-1-thia-2-silacyclopentane, bis(trimethylsilyl)sulfide, (mercaptomethyl)methyldiethoxysilane, trimethylsilanthol, 2,2-methyl-1-thia-2-silacyclopentane, and 2,2-dimethoxy -4-methyl-1-thia-2-silacyclopentane, 2,2-diethoxy-4-methyl-1-thia-2-silacyclopentane, silanthol, triisopropylsilanthol, trimethoxysilanthol, triethoxysilanthol, disilatian, trimethyl(methylthio)silane, trimethyl(ethylthio)silane, 2,2-dimethyl-1,3-dithia-2-silacyclopentane, 2,2,4,4-tetramethyl silanthol This includes rodisilathian, 2,2,8,8-tetramethyl-3,7-dithia-2,8-disilanonan, hexamethylcyclotrisilathian, [(trimethylsilyl)thio]benzene, (3-mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2-(trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3-mercaptopropyl)triethoxysilane, 4-(dimethoxymethylsilyl)-1-butanethiol, 3-(trimethoxysilyl)-1-propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl]tetrasulfide, 1,1'-thiobis(methylene)bis[1,1,1-trimethylsilane], and 1-(diethoxymethylsilyl)methanethiol, the chemical structures of which are shown below. Preferred compounds include 2,2,4-trimethyl-1-thia-2-silacyclopentane; 2,2-dimethoxy-1-thia-2-silacyclopentane; and 2,2-diethoxy-1-thia-2-silacyclopentane. [ka]

[0062] The silicon and sulfur-containing compounds relating to this disclosure are preferably substantially free of halides, metals, and metal ions. For example, with respect to chlorides such as chlorides, bromides, iodides, or fluorides, "substantially free" as used herein means less than about 3 ppm by mass of halides, more preferably less than about 1 ppm, as identified by inductively coupled plasma mass spectrometry (ICP-MS) or ion chromatography. With respect to metals and metal ions, "substantially free" as used herein means less than about 1 ppm of ionic or neutral lithium, sodium, magnesium, potassium, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, copper, zinc, or other transition metals with larger molecular weights, more preferably less than about 0.1 ppm of ionic or neutral metals.

[0063] In one embodiment, the present disclosure provides a method for selectively depositing a silicon-containing insulating layer on at least one existing metal region of a patterned substrate by employing an atomic layer deposition process, wherein the method: (a) A step of introducing a patterned substrate into a reaction region of a deposit tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated non-metallic region; and heating or cooling the reaction region between about 25°C and about 500°C; (b) A step of optionally performing annealing, cleaning, etching, or plasma treatment on a patterned substrate; (c) A step of optionally contacting a patterned substrate with a chemical blocking agent that selectively passivates one or more regions of the substrate; (d) A step of bringing a patterned substrate into contact with pulses of a compound containing silicon and sulfur; (e) The process of purging the storage tank; (f) A step of bringing the patterned substrate into contact with an oxidizing agent; (g) The process of purging the storage tank; (h) Repeat steps (d) through (g) until the desired film thickness is reached; (i) A step of optionally performing annealing, cleaning, etching, or plasma treatment on a patterned substrate; (j) A step of selectively contacting a patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate; and (k) The process of optionally repeating steps (d) through (j) until the desired thickness of the silicon-containing insulating layer is reached. The present invention relates to a method including the silicon-containing insulating layer covering only at least one metal region of the patterned substrate.

[0064] Each of these steps is described in further detail below. In this method, steps (a) to (c) represent surface preparation before deposition, steps (d) to (h) represent the ALD deposition process, and steps (i) to (k) represent a supercycle ALD process that periodically includes further cleaning or modification steps to improve selectivity by reconstructing suitable growth and non-growth surfaces or removing unwanted growth on non-growth surfaces, or to adjust the properties of the interface with the growth film or its adjacent layers.

[0065] Examples of silicon and sulfur-containing compounds that can be used as precursors according to the present invention are formulas 1, 2, 3, 4, 5, 6, 7, or 8: [ka] It holds.

[0066] In formulas 1 to 8, n is an integer between approximately 1 and 4, m is an integer between approximately 1 and 6, and R1, R2, R3, R4, R5, R6, and R7 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkoxy group, alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group, or alkyl(dialkylamino) group having 1 to approximately 12 carbon atoms (preferably approximately 1 to approximately 4 carbon atoms); or SiR 13 R14 R 15 , OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 having the general formula, wherein R 13 , R 14 , and R 15 are each independently hydrogen, or an alkyl or alkoxy group having from 1 to about 12 carbon atoms (preferably from 1 to about 4 carbon atoms), which is a linear, branched, or cyclic, optionally substituted silyl group; and R 16 is a linear or branched alkyl group having from 1 to about 12 carbon atoms (preferably from 1 to 4 carbon atoms); R8 is hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylthio, (alkyl)amino, (dialkyl)amino, alkyl(alkylamino) or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms (preferably from 1 to about 4 carbon atoms); or a linear, branched, or cyclic, optionally substituted silyl group having the general formula SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 having the general formula; R9, R 10 and R 11 are each independently a linear, branched, or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester, or ketone having from 1 to about 12 carbon atoms (preferably from 1 to about 4 carbon atoms); R 12 is OH, Cl, NR 17 R 18 , aryl or CN, wherein R 17 and R 18Each of these is independently a hydrogen atom, or an alkyl, aryl, alkyne, alkene, ether, ester, or ketone having one to about 12 (preferably about one to about 4) optionally substituted linear, branched, or cyclic atoms; and X = Si(R3,R4)-(S-Si(R5,R6)) p or (CH2) q In this equation, p is an integer between 0 and approximately 3, and q is an integer between approximately 1 and 4.

[0067] In a preferred embodiment, n and m are each 1; R1, R2, R3, R4, R5, and R6 are hydrogen, methyl, ethyl, isopropyl, methoxy, or ethoxy; R7 is hydrogen or methyl; R8 is hydrogen, methyl, ethyl, or phenyl; R9, R 10 and R 11 Each of these is an alkylene group having 1 to 4 carbon atoms (-CH2-, -CH2-CH2-, -CH(CH3)-, -CH2-CH2-CH2-, -CH(CH3)-CH 2、 -CH2-CH(CH3), -C(CH3)2-, -CH2-CH2-CH2-CH2-, -CH2-CH(CH3)-CH2, -CH(CH3)-CH2-CH2, -CH2-CH2-CH(CH3), -CH(CH3)-CH(CH3)-, -CH2-C(CH3)2 or -C(CH3)2-CH2), and R 12 is OH, Cl, phenyl, or NH2, and X is CH2CH2, Si(CH3) 2、 Alternatively, it is Si(CH3)2-S-Si(CH3)2.

[0068] The method according to the present disclosure includes the steps of: introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated non-metallic region; arranging the metallic and non-metallic regions in the reaction region of the deposition tank and heating or cooling the reaction region to about 25°C or more and about 500°C or less; and contacting the patterned substrate with the following series of steps repeated a number of times necessary to reach a desired film thickness: contacting the patterned substrate with pulses of a silicon- and sulfur-containing compound (preferably a compound having any one of formulas 1 to 8); purging the deposition tank; contacting the patterned substrate with an oxidizing agent; and purging the deposition tank. The resulting silicon-based insulating layer is selectively formed on the metallic region or on a region of the patterned substrate that covers only the metallic region of the patterned substrate. For the purposes of this disclosure, the terms “layer” and “film” may be understood to be synonymous. For the purposes of this disclosure, the reference to “compounds having formulas 1 to 8” should be understood to include any silicon and sulfur-containing compound, such as a compound having at least one silicon-sulfur bond, and in particular a compound having at least one of formulas 1 to 8.

[0069] Suitable non-metallic substrate regions include, but are not limited to, currently preferred silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, silicon nitride, silicon carbon nitride, silicon carbide, borosilicate, carbon, or alumina. Other possible and suitable substrates include, but are not limited to, substrates containing non-metallic regions including silicon, germanium, silicon-germanium alloys, titanium nitride, tantalum nitride, aluminum oxide, hafnium dioxide, titanium dioxide, and / or zinc oxide. Suitable metallic substrate regions include, but are not limited to, currently preferred copper, cobalt, and ruthenium, and tungsten, gold, and / or molybdenum.

[0070] The term “patterned substrate” should be understood to refer to a substrate having at least two isolated or separated regions of different materials. In some embodiments of the present invention, two or more materials are in contact on the substrate surface. In other embodiments of the present invention, two or more materials are “embedded” beneath one or more materials with a thickness of 10 nm or less, i.e., the substrate contains at least two layers: a first layer containing at least two isolated or separated regions (metallic and nonmetallic), and a second layer containing a buffer material with a thickness of less than about 10 nm. Various different types of patterned substrates are suitable for use in the methods described herein, as long as they contain both nonmetallic regions and either contacted metallic regions or embedded metallic regions. For example, depending on the application, the substrate may contain bulk layers of silicon, silicon dioxide, silicon-on-insulator, strained silicon, doped silicon, germanium, germanium arsenide, silicon carbide, glass, alumina, metal, or metal nitride. In addition to bulk layers, the substrate may contain multilayers of patterned thin films forming the device. Furthermore, the substrate may be substantially planar or may include three-dimensional structures such as lines, trenches, pillars, or vias. The outermost contacted surface includes the substrate, which must include at least one contacted or embedded metallic growth region and at least one non-metallic non-growth region as described herein.

[0071] These embodiments are illustrated by the diagrams in Figures 1 and 2. Figure 1A represents method 100A for deposition of a silicon-containing insulator on a patterned substrate 140 containing at least one non-metallic (insulating) region 110 and at least one isolated metallic region 130. The deposition process, which includes contact of the patterned substrate with a silicon- and sulfur-containing compound and an oxidizing agent, results in the selective formation of a silicon-containing insulating layer 120 covering only the metallic region 130 of the substrate 140. Figure 1B represents process 100B for deposition of a silicon-containing insulator on a patterned substrate 140 containing at least one non-metallic (insulating) region 110 and at least one isolated metallic region 130, as well as a natural oxide layer 150 on the insulating region and a natural oxide layer 170 on the metallic region. The deposition process, which includes contact of the patterned substrate with a silicon- and sulfur-containing compound and an oxidizing agent, results in the selective formation of a silicon-containing insulating layer 120 on the natural oxide layer 170 covering only the metallic region 130 of the substrate 140. Although not shown in the diagram, it is also possible that only one of the metallic or nonmetallic regions has a natural oxide layer.

[0072] Figure 2A illustrates a method 200A for depositing a silicon-containing insulator on a patterned substrate 140 containing at least one non-metallic (insulating region) 110 and at least one isolated metallic region 130. The first deposition step results in the formation of a buffer layer 160 on the substrate 140 containing the non-metallic (insulating) region 110 and the metallic region 130, which may also be referred to as a "buried" metallic region. The deposition step, which includes contact with a silicon- and sulfur-containing compound and an oxidizing agent, results in the selective formation of a silicon-containing insulating layer 120 on the buffer material 160 that covers only the metallic region 130 of the substrate 140. Figure 2B illustrates a process 200B for depositing a silicon-containing insulator on a patterned substrate 140 containing at least one non-metallic (insulating) region 110 and at least one isolated metallic region 130, as well as a natural oxide layer 150 on the insulating region and a natural oxide layer 170 on the metallic region. The first deposition step results in the formation of a buffer layer 160 on a substrate 140 containing a nonmetallic (insulating) region 110, a metallic region 130 which may also be referred to as a "buried" metallic region, and a natural oxide layer. A deposition step involving contact with a silicon- and sulfur-containing compound and an oxidizing agent results in the selective formation of a silicon-containing insulating layer 120 on the buffer layer 160 which covers only the metallic region 130 of the substrate 140. Although not shown in the figure, it is also possible that only one of the metallic and nonmetallic regions has a natural oxide layer.

[0073] In some aspects of this disclosure, the metal growth region of the patterned substrate is in contact with the substrate surface. The growth process according to the invention of the silicon-containing film starts directly at the interface between the metal region, which may contain metal oxides, and the deposited silicon-containing film.

[0074] Additional embodiments of the present disclosure may utilize a patterned substrate in which the metal growth regions are embedded and not on the surface of the contacted substrate. That is, (as shown in Figures 2A and 2B), the substrate comprises at least two layers: a first layer comprising at least two isolated or separated regions (metallic and nonmetallic) and a second layer comprising a buffering material having a thickness of less than about 10 nm, or in an alternative embodiment, less than about 5 nm (including all intermediate values ​​and intermediate ranges); the buffering layer may be as thin as about 2 angstroms, and therefore the thickness of the buffering layer may be between about 2 angstroms and about 10 nm, including all intermediate thicknesses. As a non-limiting example, a patterned substrate having contacted metallic and nonmetallic regions on the substrate surface may be coated with a buffering layer (buffering material) of 10 nm or less, comprising semiconductors, oxides, nitrides, or mixtures thereof, by atomic layer deposition, chemical vapor deposition, epitaxial deposition, physical vapor deposition, or other methods known in the art, to form embedded metallic regions. Preferred buffering materials include, but are not limited to, silicon, germanium, aluminum oxide, silicon dioxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carboxynitride, tantalum nitride, titanium nitride, copper oxide, cobalt oxide, ruthenium oxide, molybdenum oxide, and tungsten oxide. The area of ​​the substrate surface within about 10 nm of the buried metal region, preferably within about 6 nm, more preferably within about 5 nm, or even more preferably within about 4 nm (including all intermediate values ​​and intermediate ranges), should be understood as the growth region, and the area of ​​the substrate surface outside these distances from the buried metal region should be understood as the non-growth region.

[0075] In embodiments of the present invention in which the metal growth region is embedded, it should be understood that in a planar substrate, the growth surface may be positioned directly above the embedded metal region. In other words, the silicon-containing insulating layer is formed on the buffer layer of the patterned substrate and covers only the metal region; the silicon-containing insulating layer does not cover the non-metallic region (it does not cover the non-metallic region and is not positioned on the non-metallic region). In embodiments of the present invention relating to a three-dimensional substrate, the growth surface may be positioned adjacent to the embedded metal region, below the embedded metal region, around the embedded metal region, or in the vicinity of the embedded metal region.

[0076] In the first step, the reaction area of ​​the deposit tank is heated or cooled to a temperature between approximately 25°C and approximately 500°C, including both ends and encompassing all temperatures within this range. The preferred temperature of the reaction area is between approximately 75°C and approximately 300°C, encompassing all temperatures in between, including approximately 100°C, approximately 125°C, approximately 150°C, approximately 175°C, approximately 200°C, approximately 225°C, approximately 250°C, and approximately 275°C, etc.

[0077] The parameters of the purge cycle are not particularly limited and can be optimized based on specific reaction conditions, equipment, and reagents. Generally, any inert gas such as argon or nitrogen may be used; a typical purge cycle is at least about 2 seconds. In preferred embodiments, the purge is at least about 5 seconds and no more than about 15 seconds.

[0078] The temperature of the reaction region of the substrate and deposition tank is important for the production of the desired silicon-based insulating layer on the patterned substrate. In particular, as described below, the temperature of the reaction region of the substrate and deposition tank during pulse contact of the compound having formulas 1 to 8 is preferably between about 25°C and about 500°C, more preferably between about 75°C and about 300°C. The substrate temperature range includes all temperatures within that range, and therefore the temperature between about 75°C and about 300°C includes temperatures such as about 100°C, about 125°C, about 150°C, about 175°C, about 200°C, about 225°C, about 250°C, about 275°C, and temperatures in between all of these.

[0079] It is within the scope of this disclosure that the temperatures of the reaction zones of the substrate and the deposition tank may be the same or different. That is, the substrate chuck or substrate platen can be heated or cooled independently of the deposition tank, and these temperatures may be controlled independently by the deposition tool. However, it is also possible to raise the temperature of the substrate higher than that of the main part of the deposition tank, and the difference is usually small (approximately 10°C to approximately 30°C). Therefore, the above range applies to both the substrate and the reaction zone. In ALD, it is understood in the art that these are effectively the same when the reaction occurs on the substrate surface. In CVD, however, the reaction occurs both in the gas phase in the main deposition zone and on the substrate surface. In this case, a temperature difference between the reaction zone and the substrate may be incorporated.

[0080] The pulse length for each reaction may also be optimized based on specific reaction conditions and equipment, and is generally kept short within a practical range. For compounds having formulas 1 to 8, the pulse length is approximately 0.05 seconds to approximately 30 seconds, preferably approximately 1 second to approximately 15 seconds, more preferably approximately 3 seconds to approximately 10 seconds, more preferably approximately 2 seconds or more, even more preferably approximately 3 seconds, and even more preferably approximately 5 seconds. While longer pulse times may be effective for all compounds, they are not practical from the standpoint of material consumption or equipment utilization.

[0081] Optionally, within the scope of this disclosure, the patterned substrate may be subjected to annealing, cleaning, etching, or plasma treatment before contact of the substrate with a compound having formulas 1 to 8. For example, the substrate may be cleaned with ethanol for about 5 seconds before being placed in a deposition bath at a desired deposition temperature, and then treated with nitrogen plasma for about 1 minute by remote ICP at 2500 W power for 60 seconds before the start of the deposition process. Examples of other suitable wet pretreatment protocols, but not limited to those known in the art, include cleaning or etching with an organic solvent such as isopropanol or tetrahydrofuran, an organic acid such as citric acid or acetic acid, a mineral acid such as hydrogen fluoride, hydrogen chloride, or sulfuric acid, a base such as ammonia, or an oxidizing agent such as hydrogen peroxide, either alone, in mixtures, or in sequence, depending on the characteristics of the growing and non-growing surfaces of the patterned substrate. Dry pretreatment steps that may be used include annealing in the same or different baths, which may include reducing or oxidizing conditions, reactive ion etching, or plasma treatment. It can be understood that two or more pretreatment steps may be applied to the same patterned substrate if appropriate for a particular area of ​​the patterned substrate. Other similar substrate pretreatment processes known in the art are also applicable. Such processes can improve the selectivity of the process of the invention or the performance of the resulting film, and suitable pretreatment methods and conditions can be determined on a case-by-case basis depending on the specific substrate, equipment, reagents, and reaction conditions.

[0082] Optionally, before contacting the patterned substrate with pulses of compounds having formulas 1-8, the patterned substrate is contacted with a chemical blocking agent that selectively passivates one or more non-growth regions of the substrate. If such an optional step is performed, the chemical blocking agent may be removed once the desired insulating film thickness is achieved. Possible inhibitory compounds include, but are not limited to, chlorosilanes, alkoxysilanes, aminosilanes, cyclic azasilanes, alkanethiols, alkane phosphoric acids, phenols, organic acids, alkynes, alkenes, aldehydes, and ketones, and can be removed by dry processes, which are not limited to plasma etching, reactive ion etching, corona treatment, ozonolysis, UV / ozone, thermal decomposition, or thermal desorption, or by wet etching processes using formulations containing organic solvents, acids, bases, or hydrogen peroxide.

[0083] For the purposes of this disclosure, “oxidizing agent” may refer to oxygen, nitrogen, peroxide, ozone, or oxidizing plasma. The term “oxidizing plasma” may be understood to mean a plasma produced using a gas mixture containing at least one of O2, H2O, H2O2, O3, CO2, N2O, or NO2, and optionally a carrier gas containing N2, Ar, or He. In preferred embodiments, the plasma includes oxygen plasma supplied by a remote inductively coupled plasma (ICP) system. However, the use of other forms of plasma generation, such as capacitively coupled plasma or hollow cathode plasma, is within the scope of this disclosure.

[0084] Contact of the patterned substrate with the oxidizing agent may occur sequentially or simultaneously with contact with the silicon-containing compounds of formulas 1 to 8. In the case of alternating contact of the silicon compound and the oxidizing agent, this is generally referred to as atomic layer deposition (ALD), and the contact time with the oxidizing agent is preferably between about 0.5 seconds and about 60 seconds, most preferably between about 5 seconds and 20 seconds. Additional or extended pulses of the oxidizing agent may be added before the deposition process for surface cleaning or preparation, or after the deposition process for surface cleaning or preparation for subsequent processes in the manufacture of the desired semiconductor device. Within the scope of this disclosure, the term “pulse” may be understood to include both temporal and spatial methods of sequentially contacting the patterned substrate with the compounds of formulas 1 to 8 and the oxidizing agent. Examples of suitable methods for pulsing the compounds of formulas 1-8 according to the invention include, but are not limited to, an open vacuum system in which a precursor vessel, a reaction vessel, and a pump system are connected during the pulse; a closed vacuum system in which the pump system is isolated from the reaction vessel for a period or the entire duration of the pulse, thereby creating a residence time for the chemical precursor in the reaction vessel; or a system commonly referred to as “spatial ALD” in which contact with the compounds of formulas 1-8 is brought about by physically moving a patterned substrate from a spatial region in which the compound is present to a region in which it is not present. It should also be understood that pulsing of the oxidizing agent can be done by either a temporal or spatial method.

[0085] In the case of simultaneous contact of a substrate with a precursor and an oxidizer, commonly known as chemical vapor deposition (CVD), the duration of the process is determined by the growth rate of the process and the desired thickness of the deposited film, under specific conditions. It may be understood that the CVD process includes both cases where the introduction of the oxidizer and the precursor begins and ends simultaneously, and cases where one begins before or ends after the other, within the scope of this disclosure. Furthermore, a CVD process within the scope of this disclosure may consist of a single contact of the precursor and the oxidizer, or a series of shorter contacts separated by purging of the reaction region with an inert gas or cleaning, etching, annealing, or additional plasma treatment of the patterned substrate, known as "pulsed CVD."

[0086] In some embodiments of this disclosure, the oxidizing agent is a plasma generated using a gas mixture containing at least one of O2, H2O, H2O2, O3, CO2, N2O, or NO2, and optionally a carrier gas containing N2, Ar, or He. When plasma is used as the oxidizing agent, the process of the present invention can be understood as a plasma-induced atomic layer deposition (PEALD) or plasma-induced chemical vapor deposition (PECVD).

[0087] The duration of contact with the oxidizing agent is preferably about 1 second to about 300 seconds per 1 nm film growth, more preferably about 5 seconds to about 100 seconds. The phrase "per 1 nm film growth" is important in the CVD process because, unlike ALD where the film thickness can be controlled by the number of cycle iterations, in CVD the thickness is controlled by time. This is well understood in this field. CVD is generally a linear process, and therefore the film thickness can roughly double when the process length is doubled.

[0088] In some embodiments, after several repetitions (approximately 1 to 50 times, etc.) of contact / purging / oxidizing agent contact / purging of the compounds of formulas 1 to 8 are completed, the substrate is subjected to annealing, cleaning, etching, or plasma treatment as described above, and then to contact with an optional chemical blocking agent as described above.

[0089] The preparation of silicon-containing insulating films having a thickness of approximately 2 nm to 20 nm, particularly approximately 3 nm to 10 nm, is within the scope of this disclosure, and this thickness is currently desirable in the microelectronics industry. The desired film or layer thickness can be achieved by following the processes described repeatedly herein.

[0090] Silicon-containing insulating films produced by the methods described herein may have a dielectric constant of less than about 10, or in some embodiments, less than about 5.

[0091] The movement of the compounds of formulas 1 to 8 in a carrier gas is further within the scope of this disclosure. Suitable carrier gases include, but are not limited to, any noble gas such as argon, or an inert gas such as nitrogen. However, not using a carrier gas is also within the scope of this disclosure.

[0092] In a further embodiment of the present disclosure, a method for selectively depositing an insulating layer on an existing metal layer of a patterned substrate by employing a chemical vapor deposition (CVD) process or a pulsed vapor deposition process is: (a) A step of introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated nonmetallic region; and heating or cooling the reaction region to a temperature between about 25°C and about 500°C; (b) A step of optionally performing annealing, cleaning, etching, or plasma treatment on the substrate; (c) A step of selectively contacting a patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate; (d) A step of bringing the patterned substrate into contact with the compounds of formulas 1 to 8, while simultaneously bringing the patterned substrate into contact with an oxidizing agent; (e) A step of optionally purging the storage tank; (f) Repeat steps (d) through (e) until the desired film thickness is reached; (g) A step of optionally performing annealing, cleaning, etching, or plasma treatment on a patterned substrate; (h) A step of selectively contacting a patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate; and (i) A process in which steps (d) through (h) are optionally repeated until the desired thickness of the silicon-containing insulating layer is reached. The silicon-containing insulating layer covers only at least one metal region of the patterned substrate. Compounds having formulas 1 to 8 have been described previously, and the properties of the resulting silicon-containing insulating film have also been described previously.

[0093] Most of the steps of this method, except for step (d), relate to contact with the compounds of formulas 1-8 and the oxidizing agent described above. This simultaneous contact with the chemical compounds of formulas 1-8 and the oxidizing agent may be continued without interruption until the desired film thickness is reached, or it may be interrupted and restarted multiple times during the growth process of the target film, including cleaning, annealing, etching, or plasma treatment of the patterned substrate on which the film is deposited. When the contact with the compounds of formulas 1-8 and the oxidizing agent is simultaneous, it should be understood that within the scope of this disclosure, one contact may start before the other or end after the other.

[0094] In this method, steps (a) to (c) represent surface preparation before deposition, steps (d) to (f) represent CVD deposition steps, and steps (g) to (i) represent supercycle CVD or pulsed CVD steps that periodically include additional surface cleaning or modification steps to improve selectivity by reconstructing suitable growth and non-growth surfaces or removing unwanted growth on non-growth surfaces, or annealing steps to adjust the surface or bulk properties of the deposited film.

[0095] In some embodiments, silicon and sulfur-containing compounds may be used in ALD or CVD processes to form an insulating layer on, adjacent to, or near, a "buried" metal region on, or in the vicinity of, a "buried" metal region of a patterned substrate, in an essentially selective manner as described above. As used herein, the term "selective" means that a deposited film is formed on the target growth surface at a rate at least 5 times, preferably 10 times, or more preferably 20 times or more, than deposition on non-growth surfaces that are not intended. As used herein, an "essentially" selective process is one that does not require modification of at least one non-growth metal surface with an organic molecule or polymer film to suppress growth on the non-growth surface during the deposition process.

[0096] However, to further enhance process selectivity by suppressing growth on one or more non-growing surfaces, it is within the scope of this disclosure to employ organic molecules or polymer films known in the art. Such molecules known in the art include, but are not limited to, C1-C molecules such as dodecanethiol. 18 Thiols, dodecylsilanes, etc. C1-C 18 Silanes, ketones such as acetylacetone, phenols such as catechol, and C1-C phosphates such as octadecyl phosphate 18 These include phosphoric acid, amines such as aniline, cyclic azasilanes such as N-methyl-aza-2,2,4-trimethylsilacyclopentane, chlorosilanes such as trichloro(octadecyl)silane, aminosilanes such as (dimethylamino)(dimethyl)octadecylsilane or dimethylaminotrimethylsilane, alkoxysilanes such as triethoxy(octadecyl)silane, benzimidazolium N-heterocyclic carbenes, or imidazolium N-heterocyclic carbenes. These exemplary organic molecules can form self-assembled monolayers (SAMs) or cover non-growth regions with minimal molecular arrangement (small molecule inhibition, or SMI). The exemplary polymer films may be pre-formed polymers selectively deposited or cast onto non-growth regions, or polymer films selectively grown in situ onto non-growth regions. Small molecules, SAMs, or polymer blocking agents may be added before the ALD or CVD process is initiated, or once, multiple times, or both, during the ALD or CVD process, in order to achieve optimal selectivity with respect to all growing and non-growing surfaces on the substrate.

[0097] As used herein, the terms “growth” and “non-growth” should be understood to refer to areas of a patterned substrate where the growth of an insulating film is desired and areas where it is not desired, respectively, in relation to the manufacture of equipment structures. According to this disclosure, at least one growth area must be metallic. Non-limiting examples of exemplary metals that may be growth areas include copper, cobalt, ruthenium, molybdenum, tungsten, gold, and their bulk or natural oxide surfaces. Non-limiting examples of non-growth areas include silicon dioxide, silicon, silicon-germanium, alumina, germanium, SiOC low-k insulator, silicon nitride, tantalum nitride, titanium nitride, silicon carbide, and their natural oxides. As shown in Figures 1B and 2B and above, non-limiting examples of both growth and non-growth areas should be understood to include, for example, areas with any natural oxide layer and surfaces without a natural oxide layer or surfaces from which the natural oxide layer has been removed by means known in the art, such as chemical mechanical polishing, wet etching, plasma etching, or reactive ion etching.

[0098] The terms “atomic layer deposition” or “ALD” may be understood to mean a temporal process in which a precursor containing silicon and sulfur is introduced into a reaction vessel containing a substrate for a predetermined time, the reaction vessel is purged with an inert gas such as nitrogen, argon, or helium, the substrate is contacted with a second reactant or plasma for a predetermined time, and the reaction vessel is purged again with an inert gas. This four-step cycle is then repeated until the desired film thickness is achieved. Alternatively, “atomic layer deposition” or “ALD” may be understood to mean a spatial process in which the substrate is alternately moved between locations containing the silicon and sulfur precursor and locations containing the second reactant or plasma, and this process is repeated until the desired film thickness is achieved. While the ALD process described herein has four steps, it should be understood that adding additional steps is within the scope of the present invention.

[0099] The terms "chemical vapor deposition" or "CVD" may be understood to refer to a process in which a silicon and sulfur-containing precursor is introduced into a reaction vessel simultaneously with a second reactant or plasma, and contact is continued until a desired film thickness is reached.

[0100] According to this disclosure, both the ALD process and the CVD process may be understood to mean that the substrate may be brought into contact with one or more pretreatment processes in the same or different equipment before the commencement of the ALD or CVD process. These pretreatment processes may include wet etching or plasma etching, polishing, solvent washing, hydroxylation, oxidation, reduction, annealing, or ultraviolet irradiation or electron beam irradiation. The pretreatment processes may optionally include the use of blocking agents such as small molecule inhibitors, self-assembled monolayers, or polymer films to suppress growth on one or more non-growing surfaces.

[0101] The ALD and CVD processes described herein may be performed once or multiple times. If the ALD or CVD process is performed multiple times, processes including wet etching or plasma etching, polishing, solvent cleaning, hydroxylation, oxidation, reduction, annealing, and / or ultraviolet irradiation or electron beam irradiation may be performed between the ALD and CVD processes. Furthermore, processes including wet etching or plasma etching, polishing, solvent cleaning, hydroxylation, oxidation, reduction, annealing, and ultraviolet irradiation or electron beam irradiation may be performed after the last ALD or CVD process to remove unwanted film growth on non-growth surfaces, to remove particles or contaminants, to chemically or physically transform the deposited material, or to prepare the substrate surface for further equipment manufacturing processes.

[0102] The present invention will be described in conjunction with the following non-limiting embodiments. [Examples]

[0103] Example 1: Deposition of silicon dioxide on a copper substrate A silicon wafer with 500 nm copper deposited by physical vapor deposition (PVD) was washed with ethanol for 5 minutes and then placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 100 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. In-situ polarization analysis observed the growth of a film with a thickness of approximately 8 nm (Figure 3), and XPS identified the film as containing silicon dioxide (Figure 4). Figures 4 and 5-11, described below, include both measured and predicted data for the multilayer film stack with an effective X-ray transmission depth of 10 nm.

[0104] Example 2: Deposition of silicon dioxide on a cobalt substrate A silicon wafer with 50 nm cobalt deposited by physical vapor deposition (PVD) was placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 100 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. XPS was used to observe the growth of a silicon dioxide film of the same thickness as in Example 1 (Figure 5).

[0105] Example 3: Selective non-deposition of silicon dioxide on a silicon dioxide substrate A silicon wafer containing 1000 nm silicon dioxide due to thermal oxidation was placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 25 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. Film growth of less than 0.1 nm was observed by in-situ polarization analysis (Figure 3).

[0106] Comparative Example 4: Non-selective deposition using the corresponding compound A silicon wafer containing 1000 nm silicon dioxide produced by thermal oxidation was placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 25 ALD cycles of continuous exposure to N-methyl-aza-2,2,4-trimethylsilacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. Film growth of 0.04 nm per cycle was observed using in-situ polarization analysis (Figure 3).

[0107] Example 5: Deposition of a silicon dioxide layer on a cobalt substrate A silicon wafer with 50 nm cobalt deposited by physical vapor deposition (PVD) was placed in a reaction vessel at 175°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to (mercaptomethyl)methyldiethoxysilane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 5 seconds, respectively. XPS was used to observe the growth of a film approximately 11 nm thick, and the film was identified as containing silicon dioxide (Figure 6).

[0108] Example 6: Deposition of a silicon dioxide layer on a ruthenium substrate A silicon wafer containing 100 nm ruthenium deposited by physical vapor deposition (PVD) was placed in a reaction vessel at 175°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to (mercaptomethyl)methyldiethoxysilane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 5 seconds, respectively. XPS was used to observe the growth of a film approximately 6 nm thick, and the film was identified as containing silicon dioxide (Figure 7).

[0109] Example 7: Deposition of silicon dioxide layer on buried copper substrate A silicon wafer with 500 nm of copper deposited by physical vapor deposition (PVD) was coated with 3 nm of silicon dioxide by a non-selective thermal atomic layer deposition process. The embedded copper substrate was then placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. XPS was used to observe the growth of a film approximately 12 nm thick, and the presence of silicon dioxide in the film was identified (Figure 8). The total thickness of the silicon dioxide was approximately 15 nm.

[0110] Example 8: Non-deposit of silicon dioxide layer on buried natural silicon oxide substrate A silicon wafer having a natural oxide layer approximately 2 nm thick was coated with an additional 3 nm of silicon dioxide by the non-selective thermal atomic layer deposition process described in Example 7. The embedded natural oxide substrate was then placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. Film growth of less than 1 nm was observed by polarization analysis, and XPS identified that the substrate contained approximately 5.5 nm of silicon dioxide on silicon (Figure 9).

[0111] Example 9: Deposition of silicon dioxide layer on buried copper substrate A silicon wafer with 500 nm of copper deposited by physical vapor deposition (PVD) was coated with a 3 nm silicon oxynitride by a non-selective plasma atomic layer deposition (PLA) process. The embedded copper substrate was then placed in a reaction vessel at 150°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 50 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. XPS was used to observe the growth of a film with a thickness of approximately 4.5 nm, and the film was identified as containing silicon dioxide (Figure 10). The total thickness of silicon dioxide and silicon oxynitride was approximately 7.5 nm.

[0112] Example 10: Selective non-deposition of silicon dioxide on a silicon nitride substrate A silicon wafer with 100 nm silicon nitride deposited by thermal oxidation was placed in a reaction vessel at 175°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to 2,2,4-trimethyl-1-thia-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by purging for 15 seconds and 10 seconds, respectively. No silicon dioxide film growth was observed compared to the natural oxide layer on a silicon nitride substrate that had not undergone the deposition process (Figure 11).

[0113] Comparative Example 11: Non-inventive process without using a precursor A silicon wafer with 100 nm silicon nitride deposited by thermal oxidation was placed in a reaction vessel at 175°C. The wafer was exposed to nitrogen plasma for 1 minute, followed by 150 ALD cycles of continuous exposure to oxygen plasma (10 seconds), separated into 25-second intervals. No silicon dioxide film growth was observed compared to the natural oxide layer of a silicon nitride substrate without deposition, or to Example 10 (see Figure 11).

[0114] Figure 3 shows in-situ polarization analysis for Examples 1, 3, and Comparative Example 4. For Example 1, it shows cycle ALD growth on a copper substrate and no growth on a silicon dioxide substrate (Example 3) under the same conditions. Comparative Example 4 shows that a compound similar to those used in Examples 1, 2, and 3, but without both silicon and sulfur, results in silicon dioxide deposition on a silicon dioxide substrate. These examples therefore demonstrate the selectivity of the claimed precursor compound to the metallic region over the nonmetallic region and the importance of the claimed compound in the non-growth on the nonmetallic region.

[0115] Figure 4 shows X-ray photoelectron spectroscopy (XPS) data illustrating the deposition of a silicon dioxide layer on a copper substrate as described in Example 1.

[0116] Figure 5 shows X-ray photoelectron spectroscopy (XPS) data illustrating the deposition of a silicon dioxide layer on a cobalt substrate as described in Example 2.

[0117] Figure 6 shows X-ray photoelectron spectroscopy (XPS) data illustrating the deposition of a silicon dioxide layer on a cobalt substrate as described in Example 5.

[0118] Figure 7 shows X-ray photoelectron spectroscopy (XPS) data illustrating the deposition of a silicon dioxide layer on a ruthenium substrate as described in Example 6.

[0119] Figure 8 shows X-ray photoelectron spectroscopy (XPS) data indicating the deposition of a silicon dioxide layer on a copper substrate containing a silicon dioxide buffer layer as described in Example 7.

[0120] Figure 9 shows X-ray photoelectron spectroscopy (XPS) data indicating the absence of a silicon dioxide layer on a natural silicon oxide substrate, as described in Example 8.

[0121] Figure 10 shows X-ray photoelectron spectroscopy (XPS) data indicating the deposition of a silicon dioxide layer on a copper substrate containing a silicon oxynitride buffer layer as described in Example 9.

[0122] Figure 11 shows X-ray photoelectron spectroscopy (XPS) data indicating the non-deposition of the silicon dioxide layer on the silicon nitride substrate as described in Example 10 (inventive process) and Comparative Example 11 (non-inventive process using only an oxidizing agent), and on the substrate used in Example 10 before the inventive process. No additional silicon dioxide deposition was observed, regardless of the presence or absence of precursor contact.

[0123] Those skilled in the art will understand that modifications to the embodiments described above can be made without departing from the broader concept of the present invention. Therefore, it will be understood that the present invention is not limited to the specific embodiments disclosed, but is intended to include modifications within the spirit and scope of the invention as described in the appended claims.

Claims

1. A method for selectively depositing a silicon-containing insulating layer on a patterned substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposition tank, wherein the patterned substrate comprises at least one metallic region and at least one isolated non-metallic region, and the temperature of the reaction region is between approximately 25°C and approximately 500°C; and (b) A step of forming a silicon-containing insulating layer covering only the at least one metal region of the patterned substrate by an atomic layer deposition process or a chemical vapor deposition process, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. Methods that include...

2. The method according to claim 1, wherein the silicon-containing insulating layer is formed on the at least one metallic region of the patterned substrate with a thickness of at least about 2 nm and is not formed on the at least one non-metallic region of the patterned substrate, or is formed on the at least one non-metallic region of the patterned substrate with a thickness of less than about 1 nm.

3. The method according to claim 1 or 2, wherein the silicon and sulfur compound comprises silicon and sulfur atoms linked by at least one direct silicon-sulfur bond, or by a linear, branched, or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms.

4. The silicon and sulfur-containing compound is one of the following: Formula 1, Formula 2, Formula 3, Formula 4, Formula 5, Formula 6, Formula 7, or Formula 8: 【Chemistry 1】 having the formula, wherein n is an integer of from about 1 to about 4, m is an integer of from about 1 to about 6, R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , and R 7 are each independently hydrogen, or a linear, branched or cyclic, optionally substituted alkoxy group, alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms; or SiR 13 R 14 R 15 , OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 having the general formula, wherein R 13 , R 14 , and R 15 are each independently hydrogen or an alkyl or alkoxy group having from 1 to about 12 carbon atoms, which is a linear, branched or cyclic, optionally substituted silyl group; and R 16 is a linear or branched alkyl group having from 1 to about 12 carbon atoms; R 8 is hydrogen, or a linear, branched or cyclic, optionally substituted alkyl group, aryl group, alkyne group, alkene group, ether group, ester group, ketone group, alkylthio group, (alkyl)amino group, (dialkyl)amino group, alkyl(alkylamino) group or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms; or a linear, branched or cyclic, optionally substituted SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 silyl group having the general formula; R 9 , R 10 and R 11 Each is independently a linear, branched, or cyclic alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms; R 12 OH, Cl, NR 17 R 18 , aryl or CN, where R 17 and R 18 Each is independently a hydrogen atom, or an alkyl, aryl, alkyne, alkene, ether, ester, or ketone having one to about 12 optionally substituted, linear, branched, or cyclic carbon atoms; and X = Si(R 3 ,R 4 )-(S-Si(R 5 ,R 6 )) p or (CH 2 ) q The method according to any one of claims 1 to 3, wherein p is an integer between 0 and approximately 3, and q is an integer between approximately 1 and approximately 4.

5. The compounds of formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8 are 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, 2,2-diethoxy-1-thia-2-silacyclopentane, bis(trimethylsilyl)sulfide, (mercaptomethyl)methyldiethoxysilane, trimethylsilanthol, 2,2-methyl-1-thia-2-silacyclopentane, 2,2-Dimethoxy-4-methyl-1-thia-2-silacyclopentane, 2,2-Diethoxy-4-methyl-1-thia-2-silacyclopentane, Silanthol, Triisopropylsilanthol, Trimethoxysilanthol, Triethoxysilanthol, Disilatian, Trimethyl(methylthio)silane, Trimethyl(ethylthio)silane, 2,2-Dimethyl-1,3-Dithia-2-silacyclopentane, 2,2,4,4 The method according to claim 4, wherein the active ingredient is -tetramethylcyclodisilatian, 2,2,8,8-tetramethyl-3,7-dithia-2,8-disilanonan, hexamethylcyclotrisilathian, [(trimethylsilyl)thio]benzene, (3-mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2-(trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3-mercaptopropyl)triethoxysilane, 4-(dimethoxymethylsilyl)-1-butanethiol, 3-(trimethoxysilyl)-1-propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl]tetrasulfide, 1,1'-thiobis(methylene)bis[1,1,1-trimethylsilane], or 1-(diethoxymethylsilyl)methanethiol.

6. The method according to claim 5, wherein the silicon and sulfur-containing compound is 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, (mercaptomethyl)methyldiethoxysilane, or 2,2-diethoxy-1-thia-2-silacyclopentane.

7. The method according to any one of claims 1 to 6, wherein the patterned substrate is simultaneously brought into contact with the silicon and sulfur-containing compound and the oxidizing agent.

8. The method according to any one of claims 1 to 6, wherein the patterned substrate is sequentially brought into contact with the silicon and sulfur compound and the oxidizing agent.

9. The method according to any one of claims 1 to 8, further comprising the step of performing an annealing treatment, a cleaning treatment, an etching treatment, or a plasma treatment on the patterned substrate prior to step (b).

10. The method according to any one of claims 1 to 9, further comprising the step of contacting the patterned substrate with a chemical blocking agent before step (b) to selectively passivate at least one region of the substrate.

11. The oxidizing agent is O 2 H 2 O, H 2 O 2 , O 3 CO 2 , N 2 O and NO 2 At least one of the above, and optionally N 2 The method according to any one of claims 1 to 10, wherein the plasma is generated from a gas mixture containing a carrier gas containing Ar or He.

12. The method according to any one of claims 1 to 11, wherein the silicon-containing insulating layer has a thickness of about 2 nm or more and about 20 nm or less.

13. The method according to claim 12, wherein the silicon-containing insulating layer has a thickness of about 3 nm or more and about 10 nm or less.

14. The method according to any one of claims 1 to 13, wherein the temperature of the reaction vessel is approximately 75°C or more and approximately 300°C or less.

15. The method according to any one of claims 1 to 14, wherein the patterned substrate comprises silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, silicon nitride, silicon carbon nitride, silicon carbide borosilicate, carbon, or alumina.

16. The method according to any one of claims 1 to 15, wherein the silicon-containing insulating layer is selectively grown on at least one region of the patterned substrate comprising copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold.

17. The method according to any one of claims 1 to 16, wherein the deposited film has a dielectric constant of less than about 10.

18. The method according to claim 17, wherein the deposited film has a relative permittivity of less than about 5.

19. The method according to any one of claims 1 to 18, wherein an atomic layer deposition step is used to form the silicon-containing insulating layer.

20. The aforementioned atomic layer deposition process is: (b1) A step of bringing the patterned substrate into contact with pulses of a compound containing silicon and sulfur; (b2) A step of optionally purging the storage tank; (b3) A step of bringing the patterned substrate into contact with the oxidizing agent; (b4) A step of optionally purging the storage tank; and (b5) A process that repeats steps (b1) through (b4) until the desired layer thickness is reached. The method according to claim 19, including the method described in claim 19.

21. The method according to claim 20, further comprising the step of performing an annealing treatment, a cleaning treatment, an etching treatment, or a plasma treatment on the patterned substrate prior to step (b1), and / or contacting the patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate.

22. The method according to claim 20 or 21, further comprising, after step (b5), annealing, cleaning, etching, or plasma treatment of the patterned substrate, and / or contacting the patterned substrate with a chemical blocking agent to selectively passivate at least one region of the substrate.

23. The method according to any one of claims 20 to 22, wherein the pulse of the silicon and sulfur compound has a duration of about 0.05 seconds or more and about 30 seconds or less.

24. The method according to claim 23, wherein the pulse of the silicon and sulfur compound has a duration of about 3 seconds or more and about 10 seconds or less.

25. The method according to any one of claims 20 to 22, wherein the patterned substrate is brought into contact with the oxidizing agent for a period of approximately 0.5 seconds to approximately 60 seconds.

26. The method according to claim 25, wherein the patterned substrate is brought into contact with the oxidizing agent for a period of approximately 5 seconds to approximately 20 seconds.

27. The method according to any one of claims 1 to 18, wherein a chemical vapor deposition process or a pulsed chemical vapor deposition process is used to form the silicon-containing insulating layer.

28. The chemical vapor deposition process or pulsed chemical vapor deposition process is: (b1) A step of contacting the patterned substrate with the silicon and sulfur compound and the oxidizing agent until the desired layer thickness is reached; and (b2) Repeat step (b1) until the second desired layer thickness is reached. The method according to claim 27, including the method described in claim 27.

29. A method for selectively depositing a silicon-containing insulating layer on a substrate, wherein the method is: (a) A step of introducing a patterned substrate into a reaction region of a deposit tank, wherein the patterned substrate has a first layer and a second layer, the first layer comprising at least one metallic region and at least one isolated non-metallic region, the second layer comprising a buffering material, and the temperature of the reaction region being between about 25°C and about 500°C; and (b) A step of forming a silicon insulating layer on the second layer of the patterned substrate by an atomic layer deposition process or a chemical vapor deposition process, covering only the at least one metal region of the first layer, wherein the patterned substrate is brought into contact with a compound containing silicon and sulfur, and the patterned substrate is brought into contact with an oxidizing agent. Methods that include...

30. The silicon and sulfur-containing compounds are given by formulas 1 to 8: 【Chemistry 2】 The formula has one of the following: where n is an integer between approximately 1 and 4, m is an integer between approximately 1 and 6, and R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , and R 7 Each is independently a hydrogen, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylthio, (alkyl)amino, (dialkyl)amino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or SiR 13 R 14 R 15 OSiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 It has a general formula, in which R 13 , R 14 , and R 15 Each is independently a linear, branched, or cyclic, optionally substituted silyl group having hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms; and R 16 R is a linear or branched alkyl group having 1 to about 12 carbon atoms; 8 is hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylthio, (alkyl)amino, (dialkyl)amino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or a linear, branched, or cyclic, optionally substituted SiR 13 R 14 R 15 , or R 16 SiR 13 R 14 R 15 is a silyl group having the general formula; R 9 , R 10 and R 11 are each independently linear, branched or cyclic, optionally substituted alkylene, aryl, alkyne, alkene, ether, ester or ketone having from 1 to about 12 carbon atoms; R 12 is OH, Cl, NR 17 R 18 , aryl or CN, wherein R 17 and R 18 are each independently hydrogen, or linear, branched or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester or ketone having from 1 to about 12 carbon atoms; and X = Si(R 3 ,R 4 )-(S-Si(R 5 ,R 6 )) p or (CH 2 ) q , wherein p is an integer of from 0 to about 3, and q is an integer of from about 1 to 4. The method according to claim 29.

31. The compounds of formula 1, formula 2, formula 3, formula 4, formula 5, formula 6, formula 7, or formula 8 are 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, 2,2-diethoxy-1-thia-2-silacyclopentane, bis(trimethylsilyl)sulfide, (mercaptomethyl)methyldiethoxysilane, trimethylsilanthol, 2,2-methyl-1-thia-2-silacyclopentane, 2,2-Dimethoxy-4-methyl-1-thia-2-silacyclopentane, 2,2-Diethoxy-4-methyl-1-thia-2-silacyclopentane, Silanthol, Triisopropylsilanthol, Trimethoxysilanthol, Triethoxysilanthol, Disilatian, Trimethyl(methylthio)silane, Trimethyl(ethylthio)silane, 2,2-Dimethyl-1,3-Dithia-2-silacyclopentane, 2,2,4,4- Tetramethylcyclodisilatian, 2,2,8,8-tetramethyl-3,7-dithia-2,8-disilanonan, hexamethylcyclotrisilathian, [(trimethylsilyl)thio]benzene, (3-mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2-(trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3-mercaptopropyl The method according to claim 30, wherein the member is triethoxysilane, 4-(dimethoxymethylsilyl)-1-butanethiol, 3-(trimethoxysilyl)-1-propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl]tetrasulfide, 1,1'-thiobis(methylene)bis[1,1,1-trimethylsilane], or 1-(diethoxymethylsilyl)methanethiol.

32. The method according to claim 31, wherein the silicon and sulfur-containing compound is 2,2,4-trimethyl-1-thia-2-silacyclopentane, 2,2-dimethoxy-1-thia-2-silacyclopentane, (mercaptomethyl)methyldiethoxysilane, or 2,2-diethoxy-1-thia-2-silacyclopentane.

33. The method according to any one of claims 29 to 32, wherein the at least one metallic region comprises copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold, and the buffer layer has a thickness of less than about 10 nm.

34. The method according to claim 33, wherein the at least one metallic region comprises copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold, and the buffer layer has a thickness of less than about 5 nm.

35. The method according to any one of claims 29 to 34, wherein the buffer layer comprises a semiconductor, an oxide, a nitride, or a mixture thereof.

36. The method according to any one of claims 29 to 35, wherein the buffer layer comprises silicon, germanium, aluminum oxide, silicon dioxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carboxynitride, silicon carbide, tantalum nitride, titanium nitride, copper oxide, cobalt oxide, ruthenium oxide, molybdenum oxide, tungsten oxide, or a mixture thereof.

37. The oxidizing agent is O 2 H 2 O, H 2 O 2 , O 3 CO 2 , N 2 O and NO 2 At least one of the above, and optionally N 2 The method according to any one of claims 29 to 36, wherein the plasma is generated from a gas mixture containing a carrier gas containing Ar or He.

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