Drive unit and display unit

Abstract

The drive unit can drive the light-emitting element using at least two or more clock signals having different clock speeds. This allows for independent control of data input and light emission time, thereby reducing power consumption and improving brightness.

Description

[Technical Field]

[0001] The examples relate to a drive unit and a display unit. [Background technology]

[0002] The display market is growing year by year, and its range of applications is continuously expanding. Along with this expansion of applications, the resolution and characteristics of products are becoming more diverse.

[0003] As product specifications become more diverse, the methods for driving displays are also becoming more complex.

[0004] In the case of driver ICs used to drive display devices, they are designed to fit that specific purpose. Therefore, the range of applications for the design is limited, and a driver IC that fits each product is required if necessary.

[0005] Conventional display devices employ various methods to ensure uniformity. For example, internal compensation is performed by configuring light-emitting circuits in pixels (or subpixels), or external compensation is performed using specific methods.

[0006] On the other hand, the majority of the circuit configuration for the operation of the light-emitting circuit includes its own capacitors, ensuring constant current characteristics.

[0007] Figure 1 is a circuit diagram illustrating a conventional light-emitting circuit.

[0008] As shown in Figure 1, a conventional light-emitting circuit includes a drive transistor M1, a scan transistor M2, a sensing transistor M3, and a capacitor CSTG.

[0009] When the scan transistor M2 turns on in response to the scan signal SCAN, the data signal VDATA is supplied to the drive transistor M1 via the scan transistor M2. The drive transistor M1 supplies a light-emitting current corresponding to the data signal VDATA to the light-emitting element ED, causing the light-emitting element ED to emit light.

[0010] The capacitor CSTG ensures that the light-emitting current is supplied to the light-emitting element ED as a constant current.

[0011] When the sensing transistor M3 turns on in response to the sensing control signal SEN, the light-emitting current flowing through the driving transistor M1 is detected as the sensing signal VSEN. The characteristics of the light-emitting circuit are calibrated or compensated using the sensing signal VSEN.

[0012] On the other hand, the light-emitting circuit of an active-matrix display device either applies the PWM (pulse amplitude modulation) method itself, or uses a PWM method that utilizes the PAM (pulse amplitude modulation) method to adjust brightness. In such cases, a capacitor is always provided inside every pixel (or subpixel).

[0013] If the light-emitting circuit is designed so that a capacitor is provided inside every pixel, constraints such as area limitations may arise, and additional problems may occur due to the capacitors inside each pixel. [Overview of the project] [Problems that the invention aims to solve]

[0014] The embodiments aim to solve the aforementioned problems and other problems.

[0015] Another objective of the embodiment is to provide a drive device and a display device having a novel structure.

[0016] Another objective of the embodiment is to provide a drive device and a display device that offer a new driving method.

[0017] Another objective of the embodiment is to provide a display device in which the light-emitting circuit is not equipped with a capacitor.

[0018] Another objective of the embodiment is to provide a drive unit and a display unit that do not include a converter for converting digital data to analog data.

[0019] Another objective of the embodiment is to provide a drive unit and a display unit that can reduce power consumption.

[0020] Another objective of the embodiment is to provide a drive device and a display device that can improve image quality.

[0021] The technical problems of the embodiments are not limited to those described in this section, but also include those that can be understood from the description of the invention. [Means for solving the problem]

[0022] To achieve the aforementioned or other objective, according to one aspect of the embodiment, the drive device drives the light-emitting element using at least two or more clock signals having different clock speeds from each other.

[0023] The aforementioned two or more clock signals may include a first clock signal and a second clock signal. The first clock speed of the first clock signal is 2 times faster than the second clock speed of the second clock signal. 4 It can have a speed more than twice as high.

[0024] The input of data for causing the light-emitting element to emit light is controlled using the first clock signal, and the illumination time of the light-emitting element is controlled using the second clock signal.

[0025] The drive device may include a first counting block that counts based on the first clock signal, a first control block that controls the input of the data using the counted value, a second counting block that counts based on the second clock signal, and a second control block that controls the light emission time of the light-emitting element using the counted value.

[0026] The first counting block may include a first counter that outputs a first count value FC for controlling the input of the data using the first clock signal and the first reset signal. The first reset signal may represent a reference time for controlling the input of the data. The first control block may control the input of the data using the first count value.

[0027] The second counting block may include a second counter that outputs a second count value using the second clock signal and the second reset signal, and a third counter that outputs a third count value for causing the light-emitting element to light up using the second clock signal. The second count value prepares the light-emitting element to light up. The second control block may use the third count value to cause the light-emitting element to light up after a certain period of time has elapsed since the second reset signal was received.

[0028] The second reset signal can represent a reference time for causing the light-emitting element to emit light. The first control block can output the second reset signal based on the first count value.

[0029] The second control block may include a clock controller that outputs a third clock signal using the second clock signal when the second count value is a predetermined value, a bit generator that outputs a light emission termination signal using a light emission control signal, and a comparator that outputs a light emission stop signal using the third count value and the light emission termination signal. The light emission termination signal may represent the end of the light emission time of the light-emitting element.

[0030] The third counter can output the third count value using the third clock signal.

[0031] The light emission stop signal may be generated in response to the third count value becoming the same as the value of the light emission end signal.

[0032] The drive device may further include a light-emitting drive circuit that causes the light-emitting element to emit light using the light-emitting stop signal.

[0033] To achieve the aforementioned or other objective, according to another aspect of the embodiment, a display device including a plurality of subpixels may include, for each of the plurality of subpixels, at least one or more light-emitting elements and a drive device for driving the at least one or more light-emitting elements using at least two or more clock signals having different clock speeds.

[0034] The aforementioned two or more clock signals may include a first clock signal and a second clock signal. The first clock speed of the first clock signal is 2 times faster than the second clock speed of the second clock signal. 4 It can have a speed more than twice as high.

[0035] The input of data for causing the light-emitting element to emit light is controlled using the first clock signal, and the illumination time of the light-emitting element is controlled using the second clock signal. [Effects of the Invention]

[0036] The effects of the drive unit and display device according to the embodiment are as follows:

[0037] According to at least one of the embodiments, since the light-emitting circuit does not have a capacitor, it is not subject to area constraints, which has the advantage of increasing the aperture ratio and improving brightness.

[0038] According to at least one of the embodiments, a display driver that includes a converter for converting digital data to analog data is not required, which has the advantage of simplifying the circuit structure, reducing the occupied area, and saving costs.

[0039] According to at least one of the embodiments, the data input and the adjustment of the illumination time are controlled independently of each other by using at least two or more clock signals having different clock speeds, which has the advantage of reducing power consumption and improving brightness.

[0040] According to at least one of the embodiments, there is an advantage in that the first counting block and the second counting block, which can operate independently of each other, are designed to operate optimally, thereby improving image quality.

[0041] The additional scope of applicability of the examples will become apparent from the detailed description below. However, since various changes and modifications within the concept and scope of the examples will be clearly understood by those skilled in the art, the detailed description and specific examples, such as preferred examples, should be understood as merely illustrative. [Brief explanation of the drawing]

[0042] [Figure 1] Figure 1 is a circuit diagram illustrating a conventional light-emitting circuit. [Figure 2] Figure 2 schematically illustrates a display device according to an embodiment. [Figure 3]Figure 3 is a block diagram illustrating in detail a display device according to an embodiment. [Figure 4] Figure 4 is a block diagram illustrating the drive device according to the embodiment. [Figure 5] Figure 5 is a signal waveform diagram for operating the drive device according to the embodiment. [Figure 6] Figure 6 is a block diagram illustrating the light-emitting drive circuit according to the embodiment. [Figure 7] Figure 7 is a circuit diagram illustrating a light-emitting drive circuit according to an embodiment.

[0043] The size, shape, and numerical values ​​of the components shown in the drawings do not necessarily match those of the actual components. Furthermore, even if the same component is shown with different sizes, shapes, and numerical values ​​in different drawings, this is merely one example on the drawing, and the same component can have the same size, shape, and numerical values ​​across different drawings. [Modes for carrying out the invention]

[0044] The embodiments disclosed herein will be described in detail below with reference to the attached drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are given or used interchangeably to facilitate the writing of the specification and do not have any mutually distinguishing meaning or role in themselves. The attached drawings are provided to facilitate the understanding of the embodiments disclosed herein and do not limit the technical ideas disclosed herein. Furthermore, when elements such as layers, regions, or substrates are referred to as being “on” other components, this includes those that are directly on other elements or where other intermediate elements may exist between them.

[0045] In the following, "~module," "block," "~part," etc., can be composed of "~circuit" or "integrated circuit." "~module," "block," "~part," etc., can be used interchangeably with "~circuit" or "integrated circuit."

[0046] Figure 2 schematically illustrates a display device according to an embodiment.

[0047] Referring to Figure 2, the display device according to the embodiment may include a drive unit 100 and a plurality of light-emitting elements 120-1 to 120-N.

[0048] The display device according to the embodiment may include a display panel. The display panel may include multiple pixels. The display panel may include multiple subpixels SP-1 to SP-N. A single pixel may contain multiple subpixels SP-1 to SP-N.

[0049] A display panel may include a display area containing multiple pixels and a non-display area excluding the display area. In a display panel, the light-emitting area may correspond to each of the multiple subpixels SP-1 to SP-N, and the non-light-emitting area may be the area between the multiple subpixels SP-1 to SP-N.

[0050] In this embodiment, the drive device 100 may be located in a non-light-emitting region, but is not limited to this.

[0051] Multiple subpixels SP-1 to SP-N may include multiple red subpixels, multiple green subpixels, and multiple blue subpixels. A unit pixel is formed by adjacent red, green, and blue subpixels. In the drawing, the first subpixel SP-1 may be a red subpixel, the second subpixel SP-2 a green subpixel, and the third subpixel SP-3 a blue subpixel, but this is not limited to this.

[0052] Each of the multiple subpixels SP-1 to SP-N may contain at least one or more light-emitting elements 120-1 to 120-N. For example, the first subpixel may contain at least one or more red light-emitting elements for emitting red light. For example, the second subpixel may contain at least one or more green light-emitting elements for emitting green light. For example, the third subpixel may contain at least one or more blue light-emitting elements for emitting blue light. The multiple light-emitting elements 120-1 to 120-N may include organic semiconductor light-emitting elements, inorganic semiconductor light-emitting elements, micro-class semiconductor light-emitting elements, nano-class semiconductor light-emitting elements, and the like.

[0053] The drawing shows multiple subpixels SP-1 to SP-N arranged in a single row along the vertical direction, but the multiple subpixels SP-1 to SP-N may be arranged in a single row along the vertical direction or in a matrix configuration.

[0054] On the other hand, the drive unit 100 can drive multiple light-emitting elements 120-1 to 120-N to emit light. The drive unit 100 can control each of the multiple light-emitting elements 120-1 to 120-N to generate a light-emitting current. The light-emitting current causes the light-emitting elements 120-1 to 120-N to emit light.

[0055] The drive unit 100 can provide control signals to multiple light-emitting elements 120-1 to 120-N that adjust the light emission time for each period (or frame). The light emission time of each of the multiple light-emitting elements 120-1 to 120-N may be adjusted differently by the control signals. The brightness of each light-emitting element 120-1 to 120-N changes according to the differently adjusted light emission times, and an image with different gradations is displayed.

[0056] The drive unit 100 can drive the light-emitting elements 120-1 to 120-N using at least two or more clock signals having different clock speeds. The drive unit 100 can also receive data corresponding to each of the multiple light-emitting elements 120-1 to 120-N.

[0057] For example, the drive unit 100 can be controlled to input multiple data using the first clock signal. For example, the drive unit 100 can be controlled to adjust the illumination time of the light-emitting elements 120-1 to 120-N using the second clock signal. The first clock speed of the first clock signal is 2 times faster than the second clock speed of the second clock signal. 4 It can have a speed more than twice as high.

[0058] In the embodiment, the data used for the light emission of the light-emitting elements 120-1 to 120-N may be digital data. In such a case, the input of the digital data may be controlled using a high-speed clock signal, for example, a first clock signal. Alternatively, the light emission time of the light-emitting elements may be controlled using a low-speed clock signal, for example, a second clock signal.

[0059] If data input and the driving of multiple light-emitting elements 120-1 to 120-N are performed using only the first clock signal, the adjustment of both the data input speed and the light emission speed will be fixed. In other words, the light-emitting elements will be adjusted to match the data input speed that requires high-speed driving. In such a case, multiple light-emitting elements 120-1 to 120-N that require low-speed driving will also be driven at high speed, which may increase power consumption.

[0060] For example, if we try to represent a time of 120Hz using a 30MHz first clock signal, then 30000 / 0.12 = 250,000 ≈ 2 18 An 18-bit counter capable of counting the number of counts is required. Since the 18-bit counter needs to operate continuously not only for data input but also for adjusting the illumination time, it must perform counting at 30MHz. Therefore, power consumption may increase.

[0061] Furthermore, since the illumination time is adjusted to match the data input speed, there is a risk that effective or proactive brightness adjustment may be limited.

[0062] According to the embodiment, by using at least two clock signals having different clock speeds to independently control data input and light emission time, power consumption can be reduced and brightness can be improved.

[0063] For example, when using a 30MHz first clock signal and a 400kHz second clock signal, the 30MHz first clock signal is used for time representations of 5μs or less, and the 400kHz second clock signal is used for time representations of 5μs or more. Therefore, if time representations of 5μs or less are unnecessary, the operation of the 3-MHz first clock signal is stopped, and only the 400kHz second clock signal operates. In other words, the high-speed clock signal becomes unnecessary. This dramatically reduces dynamic power dissipation.

[0064] Dynamic power consumption (DPD) can be expressed by equation 1.

[0065] [Formula 1]

number

[0066] α represents the activity factor, C L V can represent capacitance, V can represent voltage, and f can represent operating frequency.

[0067] The operating frequency f is related to the clock speed of the first or second clock signal. Therefore, as in the embodiment, by using a second clock signal with a significantly lower clock speed than the first clock signal, dynamic power consumption can be dramatically reduced.

[0068] Figure 3 is a block diagram illustrating in detail a display device according to an embodiment.

[0069] As shown in Figure 3, the drive unit 100 may be provided between a plurality of light-emitting elements 120-1 to 120-N.

[0070] Multiple light-emitting elements 120-1 to 120-N may be divided into a first light-emitting group 120-A and a second light-emitting group 120-B. The first light-emitting group 120-A includes the first light-emitting element 120-1 to the K-th light-emitting element 120-K, and the second light-emitting group 120-B includes the K+1-th light-emitting element 120-(K+1) to the N-th light-emitting element 120-N. The first light-emitting group 120-A and the second light-emitting group 120-B may contain the same number of light-emitting elements, but are not limited to this.

[0071] The first light-emitting element 120-1 to the K-light-emitting element 120-K may be mounted on the first side of the drive unit 100, and the K+1-light-emitting element 120-(K+1) to the N-light-emitting element 120-N may be mounted on the second side of the drive unit 100.

[0072] Although not shown, multiple light-emitting groups may be provided around the drive unit 100. That is, the multiple light-emitting elements 120-1 to 120-N may be divided into a first light-emitting group 120-A, a second light-emitting group 120-B, a third light-emitting group, and a fourth light-emitting group, provided on the first side, second side, third side, and fourth side of the drive unit 100, respectively. The first and second sides may be located on opposite sides of the drive unit 100, and the third and fourth sides may be located on opposite sides of the drive unit 100.

[0073] The drive unit 100 may include a first counting block 200, a first control block 300, a second counting block 400, a second control block 500, light emission drive circuits 105A, 105B, and the like.

[0074] Data, clock signal CK F CK S Control signals such as ETC are received by the drive unit 100. Control signals such as ETC may be omitted. Power supply voltages PVDD and PVSS are supplied to the drive unit 100.

[0075] Data, clock signal CK F , CK S and the like may be output from the driving device 100. When a plurality of driving devices 100 are provided, data, the clock signal CK F , CK S and the like are transmitted from the driving device 100 illustrated in FIG. 3 to another driving device. For example, part of the data received by the driving device 100 can be used to cause a plurality of light-emitting elements 120-1 to 120-N connected to the driving device 100 to emit light. The remaining data is transmitted together with the clock signal CK F , CK S to another driving device, and can be used to cause a plurality of light-emitting elements connected to the other driving device to emit light.

[0076] In an embodiment, the clock signal CK F , CK S may include at least two or more clock signals having different clock speeds from each other. For example, the clock signals may include a first clock signal CK F , a second clock signal CK S and the like.

[0077] The first clock signal CK F is used for controlling data input, and the second clock signal CK S may be used for controlling the light-emitting time of the light-emitting elements 120-1 to 120-N. As described above, while data input is driven at high speed, the light emission of the light-emitting elements 120-1 to 120-N is driven at low speed. Accordingly, the first clock signal CK is used for data input that requires high-speed driving, and the second clock signal CK is used for light emission of the light-emitting elements 120-1 to 120-N that require low-speed driving. F is used, and for the light emission of the light-emitting elements 120-1 to 120-N that require low-speed driving, the second clock signal CK S is used.

[0078] On the other hand, a first counting block 200 receives the first clock signal CK FBased on this, the first control block 300 can control the data input using the value counted by the first counting block 200. The second counting block 400 controls the second clock signal CK S Based on this, the second control block 500 can use the values ​​counted by the second counting block 400 to control the light emission time of the light-emitting elements 120-1 to 120-N.

[0079] According to the embodiment, a first counting block 200 and a second counting block 400 may be provided, which are separated and drivable independently of each other. The first counting block 200 receives a first clock signal CK F This can be used to control the input of data that requires high-speed operation by counting. The second counting block 400 receives the second clock signal CK S This can be used to count the light emission time of light-emitting elements 120-1 to 120-N, which require low-speed drive, in order to control their emission time.

[0080] This allows a first clock signal CK with a high frequency to control the light emission time of the light-emitting elements 120-1 to 120-N. F Without using a second clock signal CK with a low frequency S By utilizing this, power consumption is reduced. Furthermore, the first counting block 200 and the second counting block 400, which can operate independently of each other, are designed to operate optimally, thereby improving image quality.

[0081] Figure 4 is a block diagram illustrating the drive device 100 according to the embodiment. Figure 5 is a signal waveform diagram for operating the drive device according to the embodiment.

[0082] Figure 5 shows the signal waveform for emitting light from, for example, the first light-emitting element 120-1 among the multiple light-emitting elements 120-1 to 120-N. The remaining light-emitting elements, i.e., the second to the Nth light-emitting elements 120-N, can also emit light in response to signal waveforms that are the same as or similar to the signal waveforms shown in Figure 5.

[0083] In the following, "light-emitting element" can refer to the first light-emitting element 120-N.

[0084] As shown in Figures 4 and 5, the first counting block 200 may include a first counter 210, etc. The first counter 210 receives a first clock signal CK F Furthermore, a first count signal FC for data input can be output using a first reset signal RS. The first count signal FC may be accumulated until it is initialized to a value of 0. The first count signal FC may, but is not limited to, be initialized in response to the first reset signal RS.

[0085] The first counter 210 receives the first clock signal CK. F The first reset signal RS can be received. The first reset signal RS can represent a reference time for controlling data input.

[0086] The first counter 210 receives a first reset signal RS of a predetermined width at a high level and in response to receiving a first clock signal CK F The first count signal FC can be counted using this method, and the counted first count signal FC can be output. Subsequently, if a high-level first reset signal RS is received again, the first count signal FC is initialized to a value of 0 or ignored, and the first clock signal CK is received again. F The first count signal FC is counted using this method.

[0087] The first control block 300 can control data input using the first count signal FC. For example, the first control block 300 can process data input in series in parallel. The parallel processed data may be temporarily stored, but is not limited to this. Multiple light-emitting elements 120-1 to 120-N can be illuminated simultaneously using the parallel processed data, but is not limited to this.

[0088] The second counting block 400 may include a second counter 410, a third counter 420, and so on.

[0089] The second counter 410 receives the second clock signal CK. S and the second reset signal RS EM The second count signal QA can be output using this. The second count signal QA may be accumulated until it is initialized to 0. The second count signal QA is controlled by the second reset signal RS EM The second counter 410 may be initialized in response to, but is not limited to, this. In addition, the second counter 410 can output the signals LPC and LEZ necessary for the light emission of the light-emitting element 120-N.

[0090] Second reset signal RS EM This can represent a reference time for emitting light from the light-emitting element 120-N. The first control block 300 can control data input based on the first count signal FC. When data input is complete, the first control block 300 signals a second reset signal RS. EM This can generate a second reset signal RS. For example, the first control block 300 may be set in advance to recognize that data input is complete when the first count signal FC reaches a predetermined value. Therefore, when the first count signal FC reaches a predetermined value, the first control block 300 will generate a second reset signal RS. EM It can generate [this].

[0091] The second count signal QA prepares the light-emitting element 120-N for illumination. That is, a high-level second reset signal RSEM Even if this occurs, the second reset signal RS is triggered by the second count signal QA. EM When this occurs, the light-emitting element 120-N can emit light after a certain period of time has elapsed. That is, a high-level second reset signal RS EM Even if this occurs, the light-emitting element 120-N will not emit light until the second count signal QA reaches a predetermined value. The light-emitting element 120-N can emit light in response to the second count signal QA reaching a predetermined value.

[0092] The second counter 410 receives a high-level second reset signal RS having a predetermined width. EM In response to receiving the second clock signal CK S The second count signal QA can be counted using this method, and the counted second count signal QA can be output. The second count signal QA is provided to the clock controller 520 to output the third clock signal CK SE It can be used to generate [something].

[0093] Meanwhile, the third counter 420 receives the second clock signal CK. S A third count signal SC can be output to cause the light-emitting element 120-N to emit light using this signal. The third count signal SC may be accumulated until it is initialized to zero. The third count signal SC is controlled by the second reset signal RS EM It may be initialized in response to, but is not limited to.

[0094] The third counter 420 receives a high-level second reset signal RS having a predetermined width. EM In response to receiving the second clock signal CK S This allows the output of the third count signal SC.

[0095] By the way, as shown in Figure 5, the third counter 420 receives a high-level second reset signal RS. EM It can be seen that even if the signal is received, the third count signal SC will not be generated for a certain period of time. Here, the certain period of time may be the time required to prepare the light-emitting element 120-N for illumination.

[0096] For this purpose, the third counter 420 receives the third clock signal CK generated by the clock controller 520. SE It can receive the third clock signal CK. SE This is a high-level second reset signal RS EM The signal is received and then, after a certain period of time has elapsed, is received by the third counter 420. The third counter 420 receives the third clock signal CK. SE This triggers a high-level second reset signal RS. EM The third count signal SC can be counted after a certain period of time has elapsed since the initial signal was received.

[0097] On the other hand, the light-emitting element 120-N can operate in cycles having an ON period (or light-emitting period) and an OFF period (or non-light-emitting period). The light-emitting element 120-N emits light during the ON period and stops emitting light during the OFF period. Here, the ON period can correspond to the light-emitting time of the light-emitting element 120-N. Therefore, the ON period, light-emitting period, and light-emitting time can be mixed together. Controlling the light-emitting time of the light-emitting element 120-N can mean controlling (or adjusting) the ON period (light-emitting time) in cycles.

[0098] In the embodiment, the ON interval is variable in accordance with the gradation (or brightness) of the data.

[0099] For example, the width of the ON interval may increase as the grayscale of the data increases. For instance, if the width of the ON interval increases in response to data with high grayscale, the light-emitting element 120-N will emit light during the increased ON interval, thus increasing the brightness of the light-emitting element 120-N.

[0100] As another example, the width of the ON interval may decrease as the grayscale of the data decreases. For example, if the width of the ON interval decreases in response to low-grayscale data, the light-emitting element 120-N will emit light during the reduced ON interval, thus decreasing the brightness of the light-emitting element 120-N.

[0101] In a fixed period, increasing the width of the ON interval reduces the OFF interval, and decreasing the width of the ON interval increases the OFF interval.

[0102] In this way, the emission time of the light-emitting element 120-N, i.e., the periodic ON interval, can be controlled (or adjusted) by the second control block 500 according to the gradation of the data.

[0103] Referring again to Figures 4 and 5, the second control block 500 may include a clock controller 520, a bit generator 530, a comparator 540, and so on.

[0104] The clock controller 520, if the second count signal QA received from the second counter 410 is a predetermined value, will generate the second clock signal CK S Using the third clock signal CK SE It can output.

[0105] The clock controller 520 may include an AND gate arithmetic unit. Therefore, the clock controller 520 may have a second count signal QA and a second clock signal CK S The AND gate operation is performed to obtain the third clock signal CK. SE It can output.

[0106] The clock controller 520 receives the second clock signal CK S The second count signal QA can be received. The clock controller 520 will receive the third clock signal CK until the second count signal QA reaches a predetermined value. SE It is not necessary to output the second clock signal CK. In other words, the clock controller 520 outputs the second clock signal CK in response to the second count signal QA reaching a predetermined value. S Using the third clock signal CK SE Therefore, the clock controller 520 outputs the third clock signal CK from the time the second count signal QA is first received until the second count signal QA reaches a predetermined value. SE It is not necessary to output the third clock signal CK. SEThe clock speed is determined by the second clock signal CK. S The clock speed may be the same as, but is not limited to. Third clock signal CK SE The clock speed of the second clock signal CK S If the clock speed is the same as that of the first clock, the clock controller 520 will, in response to the second count signal QA reaching a predetermined value, send the second clock signal CK S The third clock signal CK is used as is. SE It can be output to [this location].

[0107] As mentioned above, the third counter 420 receives the third clock signal CK. SE This allows for the output of a third count signal SC. Based on the third count signal SC, the light-emitting element 120-N can emit light.

[0108] During the interval from when the 2-count signal is first received by the clock controller 520 until the second count signal QA reaches a predetermined value (hereinafter referred to as the light emission preparation interval), the third counter 420 does not need to generate the third count signal SC. In other words, the third counter 420 does not need to operate during the light emission preparation interval. In other words, the third counter 420 can operate after the light emission preparation interval has elapsed. The third counter 420 receives a high-level second reset signal RS. EM The third clock signal CK is received from the time it is received. SE Since it does not operate during the interval until the signal is received, it is not necessary to generate the third count signal SC.

[0109] The bit generator 530 can output a light emission termination signal BW using a light emission control signal ETC. The light emission control signal ETC may be provided externally, for example, from a set-top box, host, processor, data processing device, etc. The light emission control signal ETC may include, but is not limited to, grayscale information, light emission termination information, etc.

[0110] The light emission termination signal BW can indicate the end of the light emission time. The point at which the light emission time ends varies depending on the value of the light emission type signal.

[0111] On the other hand, the light-emitting element 120-N can emit light based on the third count signal SC. The light-emitting element 120-N can emit light during ON intervals at regular intervals. The start time of the ON interval may be determined using the third count signal SC. The end time of the ON interval may be determined by the light emission control signal ETC.

[0112] As the value of the light emission termination signal BW increases, the on-interval period lengthens and the brightness increases. As the value of the light emission termination signal BW increases, the time difference between the end of the on-interval and the start of the on-interval period becomes larger. Therefore, the light emission termination signal BW changes according to the light emission control signal ETC, and the on-interval period changes as a result of the change in the light emission termination signal BW, resulting in a variety of gradations (or brightness levels) being expressed.

[0113] For example, if the light emission termination signal BW is composed of 12 bits, then 4096 (=2 12 ) is expressed in gradations. In this embodiment, the light emission termination signal BW may consist of a number of bits other than 12 bits.

[0114] In Figure 4, a first count signal FC consisting of 8 bits, a second count signal QA consisting of 3 bits, a third count signal SC consisting of 12 bits, a light emission control signal ETC consisting of 4 bits, and a light emission termination signal BW consisting of 12 bits are shown. However, this is merely an example, and each signal may be configured with other numbers of bits.

[0115] Meanwhile, the comparator 540 uses the third count signal SC and the light emission termination signal BW to generate the light emission stop signal EM. DThe output can be made. The third count signal SC and the light emission termination signal BW may consist of the same number of bits, for example, 12 bits. The light emission termination signal BW has a specific value, while the third count signal SC may be a value accumulated from 1. The third count signal SC can accumulate over time and its value can increase. Therefore, after a predetermined time has elapsed since the third count signal SC was initialized, the third count signal SC can become the same value as the light emission termination signal BW.

[0116] Comparator 540, in response to the third count signal SC becoming identical to the value of the light emission termination signal BW, issues a light emission stop signal EM. D A signal is generated to stop the light emission EM. D It can output.

[0117] On the other hand, the light-emitting drive circuits 105A and 105B receive a light-emitting stop signal EM. D The light-emitting element 120-N can be made to emit light using this method.

[0118] Specifically, the drive device 100 of the embodiment emits a light emission stop signal EM D This can be used to generate a drive control signal, and the generated drive control signal can be transmitted to the light-emitting drive circuits 105A and 105B.

[0119] The light-emitting drive circuits 105A and 105B cause the light-emitting element 120-N to emit light during periodic ON intervals in response to the drive control signal, thereby displaying an image with a desired gradation (or brightness).

[0120] On the other hand, the second control block 500 may include an OR gate arithmetic unit 510. The OR gate arithmetic unit 510 receives a second clock signal CK S and light emission stop signal EM D The OR gate operation can be performed on this, and the calculated output value can be transmitted to the clock controller 520.

[0121] The light-emitting drive circuits 105A and 105B will be described in detail with reference to Figures 6 and 7.

[0122] Figure 6 is a block diagram illustrating a light-emitting drive circuit according to an embodiment. Figure 6 shows the light-emitting drive circuits 105A and 105B of Figure 3 and a plurality of light-emitting elements 120-1 to 120-N.

[0123] Referring to Figure 6, the light-emitting drive circuit according to the embodiment may include a plurality of light-emitting circuits 130-1 to 130-N, a reference current generation circuit 110, a voltage generation circuit 150, and the like. The reference current generation circuit 110 and the voltage generation circuit 150 may each be provided as one. The plurality of light-emitting circuits 130-1 to 130-N may be the same as or less than the number of plurality of light-emitting elements 120-1 to 120-N.

[0124] Multiple light-emitting circuits 130-1 to 130-N may be included in multiple subpixels SP-1 to SP-N. Multiple light-emitting circuits 130-1 to 130-N can drive multiple light-emitting elements 120-1 to 120-N of the multiple subpixels SP-1 to SP-N to emit multiple colored light. For this purpose, in the multiple subpixels SP-1 to SP-N, multiple light-emitting circuits 130-1 to 130-N are electrically connected to multiple light-emitting elements 120-1 to 120-N.

[0125] Multiple light-emitting circuits 130-1 to 130-N can generate multiple light-emitting currents IEM1 to IEMN to supply to multiple light-emitting elements 120-1 to 120-N. These light-emitting currents IEM1 to IEMN can be called drive currents.

[0126] For example, in the first subpixel SP-1, the first light-emitting circuit 130-1 is electrically connected to the first light-emitting element 120-1 and can be driven to emit a first light-emitting current IEM1 from at least the first light-emitting element 120-1 so that a first color light is emitted. For example, in the second subpixel SP-2, the second light-emitting circuit 130-2 is electrically connected to at least one second light-emitting element 120-2 and can be driven to emit a second color light from the second light-emitting element 120-2 by supplying a second light-emitting current IEM2 from the second light-emitting element 120-2. In the third subpixel SP-3, the third light-emitting circuit 130-3 is electrically connected to the third light-emitting element 120-3 and can be driven to emit a third color light from the second light-emitting element 120-3 by supplying a third light-emitting current IEM3 from the third light-emitting element 120-3. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light, but this is not a limitation.

[0127] In the embodiment, the light-emitting circuits 130-1 to 130-N may be embodied as an integrated circuit (hereinafter referred to as IC), a chip, or a package, or they may be directly formed on a panel using semiconductor processes. Multiple light-emitting circuits 130-1 to 130-N may be embodied as individual ICs or as a single integrated IC.

[0128] In the embodiment, in each subpixel SP-1 to SP-N, the light-emitting elements 120-1 to 120-N may be included in the light-emitting circuits 130-1 to 130-N. That is, the light-emitting circuits 130-1 to 130-N may include the light-emitting elements 120-1 to 120-N and be embodied as an IC, chip, or package.

[0129] In each subpixel SP-1 to SP-N, the light-emitting elements 120-1 to 120-N and the light-emitting circuits 130-1 to 130-N are electrically connected between the first power line 141 and the second power line 142. For example, one side of the light-emitting elements 120-1 to 120-N is electrically connected to the first power line 141, the other side of the light-emitting elements 120-1 to 120-N is connected to one side of the light-emitting circuits 130-1 to 130-N, and the other side of the light-emitting circuits 130-1 to 130-N is electrically connected to the second power line 142.

[0130] A first power supply voltage EVDD is supplied to the first power supply line 141, and a second power supply voltage EVSS is supplied to the second power supply line 142. The first power supply voltage EVDD is a high potential voltage and is greater than the second power supply voltage EVSS, which is a low potential voltage. The second power supply voltage EVSS may be, for example, grounded or 0V, but is not limited to these.

[0131] On the other hand, the reference current generation circuit 110 can generate a reference current IREF. The reference current generation circuit 110 is electrically connected to multiple subpixels SP-1 to SP-N.

[0132] The reference current IREF can be used to generate multiple light-emitting currents IEM1 to IEMN that flow through multiple subpixels SP-1 to SP-N. That is, multiple light-emitting currents IEM1 to IEMN that flow through multiple subpixels SP-1 to SP-N are generated using the reference current IREF. In the embodiment, a current mirror method is used to generate light-emitting currents IEM1 to IEMN corresponding to the reference current IREF in each of the multiple subpixels SP-1 to SP-N. For this purpose, a current mirror circuit may be configured by the transistor of the reference current generation circuit 110 and the transistors of each of the multiple light-emitting circuits 130-1 to 130-N. The transistor of the reference current generation circuit 110 is connected to a diode. The transistor of the reference current generation circuit 110 and the transistors of each of the multiple light-emitting circuits 130-1 to 130-N may be connected to a common gate.

[0133] The reference current IREF and the light-emitting currents IEM1 to IEMN may be constant currents. A constant current means that a constant current flows even if the voltage across its terminals changes.

[0134] The light-emitting currents IEM1 to IEMN may correspond to the reference current IREF. The multiple light-emitting currents IEM1 to IEMN flowing through multiple subpixels SP-1 to SP-N may be the same as or greater than the reference current IREF. That is, multiple light-emitting circuits 130-1 to 130-N can generate light-emitting currents IEM1 to IEMN that are the same as or greater than the reference current IREF according to a predetermined ratio, i.e., the copy ratio.

[0135] The copy ratio may be determined by designing the aspect ratios of each transistor in the multiple light-emitting circuits 130-1 to 130-N to be different from the aspect ratio of the transistor in the reference current generation circuit 110.

[0136] For example, if the aspect ratio of the transistors in the light-emitting circuits 130-1 to 130-N is the same as the aspect ratio of the transistors in the reference current generation circuit 110, the copy ratio can be set to 1, and the light-emitting currents IEM1 to IEMN generated by the multiple light-emitting circuits 130-1 to 130-N can be the same as the reference current IREF. For example, if the aspect ratio of the transistors in the light-emitting circuits 130-1 to 130-N is greater than the aspect ratio of the transistors in the reference current generation circuit 110, the copy ratio will be greater than 1, and the light-emitting currents IEM1 to IEMN generated by the light-emitting circuits 130-1 to 130-N can be greater than the reference current IREF.

[0137] Therefore, by freely designing the aspect ratio of each transistor in the multiple light-emitting circuits 130-1 to 130-N, the light-emitting currents IEM1 to IEMN required for the subpixel SP-1 can be obtained accurately and easily.

[0138] In this embodiment, the aspect ratio of the transistors in the light-emitting circuits 130-1 to 130-N is designed to be larger than the aspect ratio of the transistors in the reference current generation circuit 110. Therefore, by designing the transistors in the reference current generation circuit 110 to have a smaller aspect ratio, a relatively small reference current IREF is generated, reducing the burden on generating the reference current IREF, decreasing the size of the reference current generation circuit 110, and saving power consumption. In addition, since the multiple light-emitting currents IEM1 to IEMN of the multiple light-emitting circuits 130-1 to 130-N have large values, the contrast ratio is improved, and high brightness can be achieved.

[0139] On the other hand, the reference current generation circuit 110 is electrically connected between the third power supply line 143 and the second power supply line 142. The third power supply voltage PVDD is supplied to the third power supply line 143. The third power supply voltage PVDD can be similar to the first power supply voltage EVDD as a high potential voltage. For example, the third power supply voltage PVDD may be smaller than the first power supply voltage EVDD, but is not limited to this.

[0140] The second power supply line 142 may be connected in common to the reference current generation circuit 110 and the multiple light-emitting circuits 130-1 to 130-N. In this case, the transistors of the reference current generation circuit 110 and the multiple transistors of the multiple light-emitting circuits 130-1 to 130-N that constitute the current mirror circuit can use the second power supply voltage EVSS supplied to the second power supply line 142 in common. Therefore, since the transistors of the reference current generation circuit 110 and the multiple transistors of the multiple light-emitting circuits 130-1 to 130-N are simultaneously affected by the IR drop associated with the second power supply voltage EVSS, they are not affected by the changes in the respective light-emitting currents IEM1 to IEMN of the multiple subpixels SP-1 to SP-N, thus preventing image quality defects.

[0141] On the other hand, while the second power supply line 142 is commonly connected to the reference current generation circuit 110 and the multiple light-emitting circuits 130-1 to 130-N, the third power supply line 143 is connected only to the reference current generation circuit 110 and does not need to be electrically connected to the multiple light-emitting circuits 130-1 to 130-N. As a result, the reference current IREF is not affected by the IR drop associated with the second power supply voltage EVSS supplied to the second power supply line 142, so an accurate and constant reference current IREF can be obtained.

[0142] On the other hand, multiple light-emitting circuits 130-1 to 130-N each use digital data and program signals to adjust the ON intervals of light-emitting elements 120-1 to 120-N in a periodic manner, enabling gradation expression for images. For example, the digital data can include signals related to the emission / non-emission of light-emitting elements 120-1 to 120-N. For example, the digital data can include "1" as a signal representing emission of light-emitting elements 120-1 to 120-N and "0" as a signal representing non-emission of light-emitting elements 120-1 to 120-N, but is not limited to this.

[0143] When the light-emitting elements 120-1 to 120-N are turned on, they emit light, and when they are turned off, they stop emitting light. For example, the program signal can include grayscale information as a control signal for writing input data.

[0144] The light-emitting elements 120-1 to 120-N emit light according to digital data, and the ON interval of the light-emitting elements 120-1 to 120-N is adjusted according to the program signal, thereby displaying an image with a desired gradation. The ON interval can mean the period in which the light-emitting elements 120-1 to 120-N emit light. For example, the larger the ON interval, the higher the gradation of the displayed image. For the same subpixel SP-1, the light-emitting elements 120-1 to 120-N emit light in different ON intervals per frame, thereby displaying an image with different gradations per frame.

[0145] In the drawing, the G node may be one node between the gate of the transistor of the reference current generation circuit 110 that constitutes the current mirror circuit and the gates of each of the transistors of the multiple light-emitting circuits 130-1 to 130-N.

[0146] A reference current IREF generated by the reference current generation circuit 110 generates a predetermined voltage at the G node via the transistor of the reference current generation circuit 110. This predetermined voltage generates multiple light-emitting currents IEM1 to IEMN in the transistors of the multiple light-emitting elements 120-1 to 120-N. In this case, as described above, by designing the aspect ratios of the transistors of the light-emitting elements 120-1 to 120-N to be the same as or different from the aspect ratios of the transistors of the reference current generation circuit 110, the same or different light-emitting currents IEM1 to IEMN are generated in each of the transistors of the multiple light-emitting elements 120-1 to 120-N based on the voltage on the G node.

[0147] On the other hand, in the embodiment, multiple subpixels SP-1 to SP-N may be driven simultaneously. That is, multiple subpixels SP-1 to SP-N are driven simultaneously within one frame, and the ON intervals of each light-emitting element 120-1 to 120-N of the multiple subpixels SP-1 to SP-N are adjusted so that images with different gradations are displayed on each subpixel SP-1 to SP-N.

[0148] On the other hand, the voltage generation circuit 150 can provide a reference voltage VREF to the reference current generation circuit 110. The voltage generation circuit 150 is connected to the reference current generation circuit 110 and can provide the reference voltage VREF to the reference current generation circuit 110. The reference current generation circuit 110 can generate a reference current IREF based on the reference voltage VREF.

[0149] Figure 7 is a circuit diagram illustrating a light-emitting drive circuit according to an embodiment. The diagram shows one of the multiple subpixels SP-1 to SP-N shown in Figure 6, SP-1, but the other subpixels SP-2 to SP-N may have the same or similar circuit structure as SP-1.

[0150] Referring to Figure 7, the light-emitting drive circuit according to the embodiment may include a voltage generation circuit 150, a reference current generation circuit 110, a light-emitting circuit 130-1, and at least one or more light-emitting elements 120-1.

[0151] The voltage generation circuit 150 may include a plurality of first transistors T31 to T33 connected in series with each other between the third power supply line 143 and the fourth power supply line 144. Although three first transistors T31 to T33 are shown in the drawing, four or more may be provided.

[0152] The first transistors T31-T33 may be PMOS transistors or NMOS transistors.

[0153] Multiple first transistors T31 to T33 are each connected to a diode. A predetermined voltage corresponding to a threshold voltage may be applied to the first transistors T31 to T33 connected to the diodes. As a result, a constant current can flow through the voltage generation circuit 150 corresponding to a voltage obtained by adding the predetermined voltages for each of the first transistors T31 to T33.

[0154] On the other hand, one of the multiple first transistors T31 to T33, transistor T31, can form a current mirror circuit with the fourth transistor T24 of the reference current generation circuit 110. That is, the gate of one of the multiple first transistors T31 to T33, transistor T31, and the gate of the fourth transistor T24 of the reference current generation circuit 110 may be commonly connected to the X node. One of the multiple first transistors T31 to T33, transistor T31, can output a reference voltage VREF to the X node using a constant current. The fourth transistor T24 of the reference current generation circuit 110 can generate a reference current IREF based on the reference voltage VREF.

[0155] The more first transistors T31 to T33 in the voltage generation circuit 150 there are, the greater the reference voltage VREF becomes, and the larger the reference current IREF generated by the reference current generation circuit 110 can become. Therefore, when the target reference current IREF to be obtained by the reference current generation circuit 110 is determined, the number of first transistors T31 to T33 in the voltage generation circuit 150 and the threshold voltage are determined so that the target reference current IREF is generated.

[0156] On the other hand, the reference current generation circuit 110 may include a first transistor T21, first control switches 113-1 and 113-2, a fourth transistor T24, and the like.

[0157] The first control switches 113-1 and 113-2 may include a second transistor T22 and a third transistor T23. One of the transistors, T22 or T23, may be omitted. The second transistor T22 is connected between the first transistor T21 and the second power line 142, and the third transistor T23 is connected between the first transistor T21 and the fourth transistor T24. The fourth transistor T24 is connected between the third power line 143 and the third transistor T23.

[0158] For example, the first transistor T21 and the second transistor T22 may be NMOS transistors, and the third transistor T23 and the fourth transistor T24 may be PMOS transistors, but this is not a limitation.

[0159] The second transistor T22 and the third transistor T23 can be simultaneously turned on and off by the first control signals D1 and D2. When the second transistor T22 and the third transistor T23 are open by the first control signals D1 and D2, the reference current IREF does not flow to the first transistor T1, which can be interpreted as the reference current IREF being off. When the second transistor T22 and the third transistor T23 are closed by the first control signals D1 and D2, the reference current IREF flows to the first transistor T1, which can be interpreted as the reference current IREF being on. The time interval during which the reference current IREF flows to the first transistor T1 can be defined as the on interval. The time interval during which the reference current IREF does not flow to the first transistor T1 can be defined as the off interval.

[0160] For example, the circuit may be divided into on-periods and off-periods according to its cycle. The cycle may be, for example, one frame, but is not limited to this. During the on-period, the second transistor T22 and the third transistor T23 are in a closed state, so the reference current IREF can flow through the first transistor T1. During the off-period, the second transistor T22 and the third transistor T23 are in an open state, so the reference current IREF does not flow through the first transistor T1.

[0161] Although not shown in the figures, the reference current generation circuit 110 may include a reference current adjustment circuit that can adjust the reference current IREF. The reference current adjustment circuit may include multiple constant current sources and multiple selector switches. The multiple constant current sources are connected to the first transistor. The fourth transistor T24 may be one of the multiple constant current sources.

[0162] Multiple constant current sources are not connected in parallel to each other to generate a constant current. Multiple selection switches are connected in series to multiple constant current sources, respectively, to select at least one of the multiple constant current sources. In such a case, the reference current IREF may be generated based on at least one of the constant currents selectively generated from the multiple constant current sources. For example, the reference current IREF may be the sum of the selected at least one of the multiple constant current sources.

[0163] The first transistor T21 is connected between the second transistor T22 and the third transistor T23, and can form a current mirror circuit with the first transistor T21 of the light-emitting circuit 130-1.

[0164] The first transistor T21 of the reference current generation circuit 110 is connected to a diode, and the gate of the first transistor T21 of the reference current generation circuit 110 and the gate of the first transistor T11 of the light-emitting circuit 130-1 may be commonly connected to the G node. In addition, the source of the first transistor T21 of the reference current generation circuit 110 and the source of the first transistor T11 of the light-emitting circuit 130-1 may be commonly connected to the second power supply line 142.

[0165] In this case, the reference current IREF flowing through the reference current generation circuit 110 can be expressed by equation 2, and the light-emitting current IEM1 flowing through the light-emitting circuit 130-1 can be expressed by equation 3.

[0166] [Formula 2]

number

[0167] [Formula 3]

number

[0168] According to equation 2, the voltage V at the G node is Gis calculated. That is, the first transistor T21 of the reference current generation circuit 110 converts the reference current IREF into the voltage V of the G node G It may be a conversion element that performs conversion.

[0169] The first transistor T11 of the light emitting circuit 130-1 converts the voltage V of the G node G It may be a conversion element that converts into the light emitting current IEM1.

[0170] From Equation 2 and Equation 3, in the first transistor T21 of the reference current generation circuit 110 and the first transistor T11 of the light emitting circuit 130-1, the process constant μ, C ox and the aspect ratio W D / L D , W E / L E are the same, the reference current IREF and the light emitting current IEM1 can be the same. In such a case, the reference current IREF is copied as it is and generated as the light emitting current IEM1 in the light emitting circuit 130-1.

[0171] In contrast to this, in the first transistor T21 of the reference current generation circuit 110 and the first transistor T11 of the light emitting circuit 130-1, the process constant μ, C ox are the same, but the aspect ratio W D / L D , W E / L E are different, the reference current IREF and the light emitting current IEM1 will be different. For example, the aspect ratio W of the first transistor T11 of the light emitting circuit 130-1 E / L E is larger than the aspect ratio W of the first transistor T21 of the reference current generation circuit 110 D / L D , the light emitting current IEM1 can be larger than the reference current IREF. For convenience, the aspect ratio W of the first transistor T21 of the reference current generation circuit 110 D / L D is named the first aspect ratio, and the aspect ratio W of the first transistor T11 of the light emitting circuit 130-1 E / L EThis can be named the second aspect ratio.

[0172] Therefore, the first aspect ratio W D / L D By being designed to be small, a small reference current IREF is generated in the reference current generation circuit 110. This reduces the burden on reference current generation, decreases the size of the reference current generation circuit 110, and saves power consumption.

[0173] Also, the second aspect ratio W E / L E By designing it to be large, a large light-emitting current IEM1 is generated in the light-emitting circuit 130-1. As a result, the light-emitting element 120-1 emits light due to the large light-emitting current IEM1, improving the contrast ratio and enabling high brightness.

[0174] On the other hand, the light-emitting circuit 130-1 may include a first transistor T11, second control switches SW11 and SW12, digital storage 135-1, and the like.

[0175] The digital storage 135-1 can use the digital data DM-1 to generate second control signals C11 and C12 for switching the second control switches SW11 and SW12.

[0176] The second control switches SW11 and SW12 are connected to the first transistor T11 and can control the on / off state of the light-emitting current IEM1. The switches may include a first-first control switch SW11 and a first-second control switch SW12. The first-first control switch SW11 is connected between the first transistor T11 and the second power supply line 142, and the first-second control switch SW12 is connected between the light-emitting element 120-1 and the first transistor T11.

[0177] Control switch SW11 and the first-to-second control switch SW12 can be simultaneously turned on and off by the second control signals C11 and C12. When the first-to-first control switch SW11 and the first-to-second control switch SW12 are open by the second control signals C11 and C12, the light-emitting current IEM1 does not flow to the first transistor T11, which can be interpreted as the light-emitting current IEM1 being off. When the first-to-first control switch SW11 and the first-to-second control switch SW12 are closed by the second control signals C11 and C12, the light-emitting current IEM1 flows to the first transistor T11, which can be interpreted as the light-emitting current IEM1 being on. The time interval during which the light-emitting current IEM1 flows to the first transistor T11 can be defined as the on-interval. The time interval during which the light-emitting current IEM1 does not flow to the first transistor T11 can be defined as the off-interval.

[0178] The first control signals D1 and D2 and the second control signals C11 and C12 may be included in the drive control signals generated by the drive device (100 in Figures 3 and 4), but are not limited to this.

[0179] For example, the period may be divided into on-periods and off-periods. The period may be, for example, one frame, but is not limited to this. During the on-period, the 1-1 control switch SW11 and the 1-2 control switch SW12 are in the closed state, so the light-emitting current IEM1 can flow through the first transistor T11. During the off-period, the 1-1 control switch SW11 and the 1-2 control switch SW12 are in the open state, so the light-emitting current IEM1 does not flow through the first transistor T11.

[0180] For the sake of clarity, the ON section in which the reference current IREF flows through the first transistor T21 of the reference current generation circuit 110 may be named the first ON section SS1, and the ON section in which the light-emitting current IEM1 flows through the first transistor T11 of the light-emitting circuit 130-1 may be named the second ON section SS2.

[0181] In the above, the drive unit 100 and the plurality of light-emitting elements 120-1 to 120-N are considered as one block (or module), and the display device or display panel according to the embodiment may be composed of multiple blocks.

[0182] The detailed description above should not be interpreted restrictively in any way, but should be considered illustrative. The scope of the examples should be determined by a reasonable analysis of the attached claims, and all modifications within the equivalent scope of the examples are included within the scope of the examples.

Claims

1. A drive device that drives a light-emitting element using at least two or more clock signals having different clock speeds.

2. The aforementioned two or more clock signals include a first clock signal and a second clock signal. The first clock speed of the first clock signal is 2 times the second clock speed of the second clock signal. ４ The drive device according to claim 1, which is more than twice as large.

3. The input of data for causing the light-emitting element to emit light is controlled using the first clock signal. The drive device according to claim 2, wherein the emission time of the light-emitting element is controlled using the second clock signal.

4. A first counting block that counts based on the first clock signal, A first control block that controls the input of the data using the counted value, A second counting block that counts based on the second clock signal, The drive device according to claim 1, further comprising a second control block that controls the light emission time of the light-emitting element using the counted value.

5. The first counting block is, Includes a first counter that outputs a first count value for controlling the input of the data using the first clock signal and the first reset signal, The first reset signal represents a reference time for controlling the input of the data, The drive device according to claim 4, wherein the first control block controls the input of the data using the first count value.

6. The second counting block is, A second counter that outputs a second count value using the second clock signal and the second reset signal, The system includes a third counter that outputs a third count value for causing the light-emitting element to light up using the second clock signal, The second count value prepares the light-emitting element for illumination. The drive device according to claim 4, wherein the second control block uses the third count value to cause the light-emitting element to light up after a certain period of time has elapsed since the second reset signal was received.

7. The second reset signal represents a reference time for causing the light-emitting element to emit light. The drive device according to claim 6, wherein the first control block outputs the second reset signal based on the first count value.

8. The second control block is, A clock controller that outputs a third clock signal using the second clock signal when the second count value is a predetermined value, A bit generator that outputs a light emission termination signal using a light emission control signal, Includes a comparator that outputs a light emission stop signal using the third count value and the light emission end signal, The drive device according to claim 6, wherein the light emission termination signal indicates the end of the light emission time of the light-emitting element.

9. The drive device according to claim 8, wherein the third counter outputs the third count value using the third clock signal.

10. The drive device according to claim 8, wherein the light emission stop signal is generated in response to the third count value becoming the same as the value of the light emission end signal.

11. The drive device according to claim 6, further comprising a light-emitting drive circuit that causes the light-emitting element to emit light using the light-emitting stop signal.

12. In a display device containing multiple subpixels, Each of the plurality of subpixels is provided with at least one light-emitting element, A display device comprising a drive device that drives at least one or more light-emitting elements using at least two or more clock signals having different clock speeds.

13. The aforementioned two or more clock signals include a first clock signal and a second clock signal. The first clock speed of the first clock signal is 2 times the second clock speed of the second clock signal. ４ A display device according to claim 12, which is more than twice as large.

14. The input of data for causing the light-emitting element to emit light is controlled using the first clock signal. The display device according to claim 13, wherein the light emission time of the light-emitting element is controlled using the second clock signal.

Images