Display with vertically stacked components

Abstract

A display may include an array of pixels, such as pixels of light-emitting diodes. A pixel may include multiple circuit configuration decks, each containing one or more circuit components, such as transistors, capacitors, and / or resistors. The circuit configuration decks may be stacked vertically. Each circuit configuration deck may include a planarization layer formed from a siloxane material that conforms to the components below and provides a flat top surface. In this way, the circuit components may be stacked vertically to reduce the size of each pixel footprint. The circuit components may include capacitors that include both high-k dielectric layers and low-k dielectric layers. Display pixels may include vias having a width of less than 1 micron.

Description

Technical Field

[0001] This application claims the benefit of priority from U.S. Patent Application No. 18 / 755,498 filed on June 26, 2024 and U.S. Provisional Patent Application No. 63 / 580,628 filed on September 5, 2023, the entire contents of which are incorporated herein by reference.

Background Art

[0002] Electronic devices often include a display. For example, cellular telephones and portable computers include a display for presenting information to a user. An electronic device may have an organic light emitting diode display based on organic light emitting diode pixels or a liquid crystal display based on liquid crystal pixels.

[0003] Display pixels include circuit components such as capacitors and transistors. However, these components may have a larger footprint than desired, limiting the maximum pixel density of the display.

[0004] The embodiments described herein were developed against this background.

Summary of the Invention

[0005] A display pixel may be configured to emit light in a first direction. The display pixel may include a substrate, a first transistor formed on the substrate, a first planarization layer overlapping the first transistor in the first direction, a component including a capacitor or a transistor overlapping the first transistor in the first direction, a second planarization layer overlapping the component in the first direction, and an anode overlapping the first transistor and the component in the first direction.

[0006] The display pixel may include a first power terminal, a second power terminal, a light-emitting diode, a drive transistor, a switching transistor connected to the gate of the drive transistor, a substrate, a first deck on the substrate including the switching transistor and a first planarization layer overlapping the switching transistor, and a second deck on the first deck including the drive transistor and a second planarization layer overlapping the drive transistor. The drive transistor and the light-emitting diode may be connected in series between the first and second power terminals.

[0007] The display may include an array of display pixels having a pixel density of more than 1,000 pixels per inch. The display pixels in the array of display pixels may include a light-emitting diode configured to emit light vertically, a driver transistor having a first gate that is vertically superimposed by the light-emitting diode, and an additional transistor having a second gate that is vertically superimposed by the light-emitting diode and the first gate. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram of an exemplary electronic device having a display, according to several embodiments.

[0009] [Figure 2] This is a schematic diagram of an exemplary display according to several embodiments.

[0010] [Figure 3A] This is a schematic diagram of an exemplary display pixel having six transistors and one capacitor, according to several embodiments.

[0011] [Figure 3B] This is a schematic diagram of an exemplary display pixel having four transistors and two capacitors, according to several embodiments.

[0012] [Figure 4]This is a side view of an exemplary display pixel having a first deck with transistors and a second deck with capacitors, according to some embodiments.

[0013] [Figure 5] This is a side view of an exemplary display pixel having a first deck with transistors and a second deck with capacitors and transistors, according to several embodiments.

[0014] [Figure 6] This is a side view of an exemplary display pixel, according to several embodiments, having a first deck with two transistors, a second deck with two transistors, and a third deck with at least one capacitor.

[0015] [Figure 7A] This is a side view of partially overlapping vias according to several embodiments.

[0016] [Figure 7B] Side views of nested vias according to several embodiments.

[0017] [Figure 8] This is a side view of an exemplary capacitor having two electrodes and one high-k dielectric layer sandwiched between two low-k dielectric layers between the two electrodes, according to some embodiments.

[0018] [Figure 9] This is a side view of an exemplary capacitor, according to several embodiments, having three planar electrodes and one high-k dielectric layer sandwiched between two low-k dielectric layers between each adjacent electrode pair.

[0019] [Figure 10] This is a side view of an exemplary capacitor having three non-planar electrodes and one high-k dielectric layer sandwiched between two low-k dielectric layers between each adjacent electrode pair, according to several embodiments.

[0020] [Figure 11] It is a side view of an exemplary capacitor having electrodes with adjacent portions at non-orthogonal, non-parallel angles, according to some embodiments. MODE FOR CARRYING OUT THE INVENTION

[0021] An exemplary electronic device of the type that may comprise a display is shown in FIG. 1. The electronic device 10 may be a computing device such as a laptop computer, a computer monitor including an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch-type device, a pendant-type device, a headphone or earphone-type device, an augmented reality (AR) headset and / or a virtual reality (VR) headset, a device embedded in glasses or other equipment worn on a user's head, or another wearable or small device, a display, a computer display including an embedded computer, a computer display not including an embedded computer, a gaming device, a navigation device, an embedded system such as a system with electronic equipment having a display mounted in a kiosk or a vehicle, or other electronic equipment.

[0022] As shown in Figure 1, the electronic device 10 may have a control circuit configuration 16. The control circuit configuration 16 may include a storage and processing circuit configuration to support the operation of the device 10. The storage and processing circuit configuration may include storage devices such as hard disk drive storage devices, non-volatile memory (e.g., flash memory, or other electrically programmable read-only memory configured to form a solid-state drive), and volatile memory (e.g., static or dynamic random-access memory). The processing circuit configuration within the control circuit configuration 16 can be used to control the operation of the device 10. The processing circuit configuration may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc.

[0023] Input / output circuit configurations within device 10, such as input / output devices 18, can be used to enable data to be supplied to device 10 and to enable data to be supplied from device 10 to external devices. Input / output devices 18 may include buttons, joysticks, scroll wheels, touchpads, keypads, keyboards, microphones, speakers, sound sources, vibrators, cameras, sensors, light-emitting diodes, and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands via input / output devices 18 and can receive status information and other outputs from device 10 using the output resources of input / output devices 18.

[0024] The input / output device 18 may include one or more displays, such as a display 14. The display 14 may be a touchscreen display including a touch sensor for collecting touch input from the user, or the display 14 may not be touch-sensitive. The touch sensor for the display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, an optical touch sensor, or other suitable touch sensor configuration.

[0025] The control circuit configuration 16 can be used to run software such as operating system code and applications on device 10. While device 10 is operating, the software running on the control circuit configuration 16 can display images on the display 14.

[0026] The display 14 may be an organic light-emitting diode display, a display formed from an array of individual light-emitting diodes, each formed from a crystalline semiconductor die, or any other suitable type of display. In this specification, a configuration in which the pixels of the display 14 include light-emitting diodes is sometimes described as an example. However, this is merely illustrative. Any suitable type of display (e.g., a liquid crystal display) may be used for the device 10 if desired.

[0027] In some cases, the electronic device 10 may be a wristwatch device. The display 14 of the wristwatch device may be located within the housing. It is also possible to attach a wristwatch strap to the housing.

[0028] Figure 2 is an illustrative diagram of a display. As shown in Figure 2, the display 14 may include layers such as a substrate layer 26. The substrate layer, such as layer 26, may be formed from a rectangular, flat material layer or a material layer having another shape (e.g., a circular shape or other shape with one or more curved and / or straight edges). The substrate layer of the display 14 may include a glass layer, a polymer layer, a composite film containing polymer and inorganic materials, a metal foil, and the like.

[0029] The display 14 may have an array of pixels 22 for displaying an image to the user, such as a pixel array 28. The pixels 22 in the array 28 may be arranged in rows and columns. The edges of the array 28 (also called the active region 28) may be straight or curved (i.e., each row and / or column of pixels 22 in the array 28 may have the same length or different lengths). There may be any suitable number of rows and columns in the array 28 (e.g., 10 or more, 100 or more, or 1000 or more). The display 14 may include pixels 22 of different colors. For example, the display 14 may include red pixels, green pixels, and blue pixels. If desired, a backlight unit may provide backlight illumination to the display 14.

[0030] A display driver circuit configuration 20 may be used to control the operation of the pixels 28. The display driver circuit configuration 20 may be formed from an integrated circuit, a thin-film transistor circuit, and / or other suitable circuit configurations. The exemplary display driver circuit configuration 20 in Figure 2 includes a display driver circuit configuration 20A and additional display driver circuit configurations such as a gate driver circuit configuration 20B. The gate driver circuit configuration 20B may be formed along one or more edges of the display 14. For example, the gate driver circuit configuration 20B may be located along the left and right sides of the display 14 in the non-active area of ​​the display, as shown in Figure 2. The gate driver circuit configuration 20B may include a gate driver and a light-emitting driver.

[0031] As shown in Figure 2, the display driver circuit configuration 20A (e.g., one or more display driver integrated circuits, thin-film transistor circuit configurations, etc.) may include a communication circuit configuration for communicating with the system control circuit configuration via a signal path 24. The path 24 may be formed from traces on a flexible printed circuit or from other cables. The control circuit configuration may be located on one or more printed circuits within the electronic device 10. During operation, the control circuit configuration (e.g., the control circuit configuration 16 in Figure 1) may supply image data of the image displayed on the display 14 to a circuit configuration such as a display driver integrated circuit in the circuit configuration 20. The display driver circuit configuration 20A in Figure 2 is located at the top of the display 14. This is merely an example. The display driver circuit configuration 20A may be located both at the top and bottom of the display 14, or in other parts of the device 10.

[0032] To display an image on the pixels 22, the display driver circuit configuration 20A may supply corresponding image data to data lines D (e.g., vertical signal lines) while issuing control signals to supporting display driver circuit configurations such as the gate driver circuit configuration 20B via the signal path 30. In the exemplary configuration of Figure 2, the data lines D extend vertically through the display 14 and are associated with each column of pixels 22. During compensation operation, the column driver circuit configuration 20 may supply a reference voltage using paths such as data lines D.

[0033] The gate driver circuit configuration 20B (sometimes called the gate line driver circuit configuration or horizontal control signal circuit configuration) may be implemented using one or more integrated circuits and / or using thin-film transistor circuit configurations on the substrate 26. Horizontal control lines G (sometimes called gate lines, scan lines, output control lines, etc.) extend horizontally through the display 14. Each gate line G is associated with an individual row of pixels 22. If desired, there may be multiple horizontal control lines, such as gate lines G, associated with each row of pixels. Individually controlled and / or global signal paths within the display 14 may also be used to distribute other signals (e.g., power signals). The number of horizontal signal lines in each row may be determined by the number of transistors in the display pixels 22 that are individually controlled by the horizontal signal lines. Display pixels with different configurations may be operated by different numbers of control lines, data lines, power lines, etc.

[0034] The gate driver circuit configuration 20B can assert control signals on gate lines G in the display 14. For example, the gate driver circuit configuration 20B can receive a clock signal and other control signals from circuit configuration 20A on path 30, and in response to the received signals, can sequentially assert gate line signals on gate lines G, starting with the gate line signal G in the first row of pixels 22 in array 28. Once each gate line is asserted, data from data lines D can be loaded into the corresponding row of pixels. In this way, control circuit configurations such as display driver circuit configurations 20A and 20B can provide the pixels 22 with signals instructing them to display a desired image on the display 14. Each pixel 22 may have a light-emitting diode and circuit configuration (e.g., a thin-film circuit configuration on the substrate 26) that responds to control signals and data signals from the display driver circuit configuration 20.

[0035] Figure 3 is a schematic diagram of an exemplary organic light-emitting diode display pixel 22 in the display 14. As shown in Figure 3A, the display pixel 22 may include a storage capacitor Cst, a driving transistor T2, switching transistors such as transistors T1, T3, and T6, and light-emitting transistors such as T4 and T5.

[0036] Generally, each transistor within pixel 22 may be formed using semiconductor oxide or silicon. Semiconductor oxide transistors may have channels formed from semiconductor oxides such as indium gallium zinc oxide (IGZO). Silicon transistors may have polysilicon channels deposited using low-temperature processes. Polysilicon deposited using low-temperature processes is sometimes called low-temperature polysilicon (LTPS).

[0037] In general, the transistors within pixel 22 may include n-type (i.e., n-channel) transistors and / or p-type (i.e., p-channel) transistors. In one exemplary example, each of transistors T1, T2, T3, T4, T5, and T6 is an n-channel semiconductor oxide transistor. Because semiconductor oxide transistors have lower leakage than silicon transistors, implementing the transistors in display pixel 22 as semiconductor oxide transistors can reduce flicker (for example, by preventing current leakage from the gate terminal of the driving transistor T2).

[0038] Transistor T2 functions as the drive transistor for pixel 22 and has a threshold voltage (Vth) that affects the light-emitting current of pixel 22. Since the threshold voltage of transistor Tdrive can experience hysteresis, forming the drive transistor as a top-gate semiconductor oxide transistor can help reduce hysteresis (for example, top-gate IGZO transistors experience lower Vth hysteresis than silicon transistors).

[0039] The display pixel 22 may include an organic light-emitting diode (OLED) 42. A positive power supply voltage ELVDD can be supplied to the positive power supply terminal 44, and a ground power supply voltage ELVSS can be supplied to the ground power supply terminal 46. The positive power supply voltage ELVDD may be 3V, 4V, 5V, 6V, 7V, 2-8V, or any suitable positive power supply voltage level. The ground power supply voltage ELVSS may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, or any suitable ground or negative power supply voltage level. The state of the drive transistor T2 controls the amount of light emitted 48 from the display pixel 22 by controlling the amount of current flowing from terminal 44 to terminal 46 through the diode 42.

[0040] Terminal 50 may be used to supply an initialization voltage VINIT (a negative voltage such as -1V, -2V, -3V, -4V, -5V, -6V, or any other suitable voltage) to help turn off diode 42 when it is not in use. Therefore, terminal 50 may also be called the initialization line.

[0041] Control signals from a display driver circuit configuration, such as the gate driver circuit configuration 20B in Figure 2, are supplied to control terminals such as row control terminals 52, 54, 56, and 58. Row control terminals 52 and 58 can function as light emission control terminals (sometimes called light emission lines or light emission control lines). Row control terminals 54 and 56 can function as first and second scan control terminals (sometimes called scan lines, scan control lines, switching lines, switching control lines, etc.). Row control terminals 52, 54, 56, and 58 are sometimes referred to as row control lines or gate lines themselves. Alternatively, row control terminals may be said to be coupled to their respective row control lines or gate lines.

[0042] The light emission control signal EMT may be supplied to terminal 52. The light emission control signal EMB may be supplied to terminal 58. The scan control signal INIT may be supplied to scan terminal 54. The scan control signal SEL may be supplied to scan terminal 56. Data input terminals, such as the data signal terminal 60, are coupled to separate data lines D to receive image data for the display pixels 22. The data terminal 60 is also sometimes referred to as a data line.

[0043] The control signals EMT, INIT, SEL, and EMB for modulating n-type semiconductor oxide transistors T4, T3, T6, T1, and T5 can be driven high to turn them on and low to turn them off (because n-type transistors are "active high" devices). When asserted, the control signals EMT, INIT, SEL, and EMB can generally be driven to a voltage level higher than ELVDD to overdrive the transistors. For example, if ELVDD is equal to 5V, the signals EMT, INIT, SEL, and EMB can be driven to 12V when asserted. When deasserted, the control signals EMT, INIT, SEL, and EMB can generally be driven to a voltage level lower than ELVSS to minimize leakage current through the transistors. For example, if ELVSS is equal to -2V, the signals EMT, INIT, SEL, and EMB can be driven to -6V when deasserted. The high and low voltage levels disclosed for each of these line control signals are merely illustrative and can be adjusted to other suitable voltage levels to support the desired operating mode.

[0044] The "source" and "drain" terminals of a transistor can sometimes be used interchangeably, and are therefore sometimes referred to as "source-drain" terminals.

[0045] In the example shown in Figure 3A, transistors T4, T2, T5, and OLED42 are connected in series (in this order) to power supply terminals 44 and 46. Specifically, the first light emission control transistor T4 may have a first source-drain terminal connected to the positive power supply terminal 44, a gate terminal that receives the light emission control signal EMT, and a second source-drain terminal connected to node N1.

[0046] The drive transistor 2 may have a first source-drain terminal connected to node N1, a gate terminal connected to node N2, and a second source-drain terminal connected to node N3. The second light emission control transistor T5 may have a first source-drain terminal connected to node N3, a gate terminal that receives the light emission control signal EMB, and a second source-drain terminal connected to node N4. Node N4 is connected to the ground power supply terminal 46 via the light-emitting diode 42. Node N4 is also connected to transistor T6 and capacitor Cst. With this configuration, it may be possible to assert the light emission control signals EMT and EMB during the light emission phase to turn on transistors T4 and T5 and allow current to flow through the light-emitting diode 42.

[0047] The storage capacitor Cst may have a first terminal (e.g., a first plate of the capacitor) coupled to node N2 and a second terminal (e.g., a second plate of the capacitor) coupled to node N4. Image data loaded into pixel 22 can be at least partially stored in pixel 22 using capacitor Cst to hold the charge throughout the light emission stage.

[0048] Transistor T3 may have a first source-drain terminal connected to node N1, a second source-drain terminal connected to node N2, and a gate terminal that receives the control signal INIT. When the signal INIT is asserted, transistor T3 turns on, and the gate of the drive transistor T2 (node ​​N2) can be short-circuited to the source-drain terminal of the drive transistor T2 (node ​​N1).

[0049] Transistor T1 (sometimes called data loading transistor T1) may have a first source-drain terminal coupled to data line D, a gate terminal configured to receive a scan control signal SEL, and a second source-drain terminal coupled to node N3. This configuration may allow the signal SEL to be asserted to turn on transistor T1, loading the data voltage from data line D to node N3.

[0050] As shown in Figure 3A, pixel 22 also includes transistor T6 having a first source-drain terminal connected to node N4, a gate terminal configured to receive a scan control signal INIT, and a second source-drain terminal connected to an initialization line 50 to which an initialization voltage VINIT is supplied. Both transistors T3 and T6 are controlled by the control signal INIT and are therefore controlled in parallel.

[0051] The configuration of pixel 22 in Figure 3A is merely illustrative. In general, one or more additional transistors may be included (for example, to support intra-pixel threshold voltage compensation, external threshold voltage compensation, and / or other desired operations). The example using all n-type semiconductor oxide transistors is merely illustrative. If desired, one or more transistors in pixel 22 in Figure 3A may be formed using p-type silicon transistors. One or more transistors may also be optionally omitted from the pixel in Figure 3A.

[0052] Figure 3B is a schematic diagram of an exemplary display pixel having four transistors and two capacitors. In this configuration, the light-emitting transistor T5 in Figure 3A is omitted. Therefore, there is only one light-emitting transistor T4 controlled by the row control signal EM.

[0053] In Figure 3B, transistor T1 has a first source-drain terminal coupled to data line D, a gate terminal that receives control signal SEL, and a second source-drain terminal coupled to the gate of drive transistor T2 at node N2.

[0054] Pixel 22 in Figure 3B has a first capacitor C1 and a second capacitor C2. The first capacitor has a first terminal (sometimes called a first plate) coupled to the gate of the drive transistor T2 at node N2. The first capacitor has a second terminal (sometimes called a second plate) coupled to node N3. The second capacitor has a first terminal (sometimes called a first plate) coupled to node N3 and a second terminal (sometimes called a second plate) coupled to the initialization voltage terminal 50 or some other fixed reference voltage.

[0055] Transistor T3 has a first source-drain terminal connected to the initialization voltage terminal 50, a gate terminal that receives the control signal INIT from the row control terminal 54, and a second source-drain terminal connected to N3.

[0056] In certain devices, a small footprint for each pixel is desirable. Smaller pixels can enable a high pixel density or PPI (pixels per inch). Transistors and capacitors can contribute to the overall footprint of each display pixel. In some cases, transistors and capacitors may be formed on a single substrate without any lateral overlap. In this case, the overall footprint of the pixel needs to accommodate the footprint of each transistor / capacitor. To reduce the overall footprint of a pixel, one or more components within a pixel may be stacked. For example, one or more transistors and / or capacitors may be stacked vertically such that the footprints of their components overlap. By stacking components in this way, the overall footprint requirement of the pixel is reduced.

[0057] In this specification, the display 14 may also be referred to as having an active device and a passive device. The active device may include a transistor containing a semiconductor channel (e.g., an n-type semiconductor oxide transistor, a p-type silicon transistor, etc.). The passive device may include a capacitor (formed from two or more parallel conductive layers) and a resistor (formed from a single conductive layer).

[0058] Various combinations of active and passive devices may be stacked vertically within the display 14. Figure 4 is a side view of an exemplary pixel 22 having an active device and a stacked passive device.

[0059] As shown in Figure 4, the pixel 22 may include a substrate 82. The passive component 72 and the active component 84 may be stacked vertically on the substrate 82. In this specification, vertical stacking may mean that the components overlap in a direction parallel to direction 65. Light may be shone from the pixel (e.g., from the light-emitting diode 42) in direction 65 (e.g., toward the observer). In this example, the passive component 72 is a capacitor and the active component 84 is a transistor. The substrate 82 may be formed from an insulating material such as polyimide or glass, or from a conductive material (e.g., a material containing one or more of aluminum, titanium, molybdenum, etc.).

[0060] One or more interlayer dielectric layers 74 may be formed on the substrate 82. In the example in Figure 4, the conductive layer 80-2 is formed on the substrate 82. The interlayer dielectric layer 74 is interposed between the conductive layer 80-2 and the substrate 82. The channel region 76 of the transistor 84 (sometimes called the active region, semiconductor oxide channel, silicon channel, etc.) is formed on the conductive layer 80-2 and is separated from the conductive layer 80-2 by the interlayer dielectric layer 74. The channel region 76 includes LTPS if the transistor 84 is a silicon transistor, and includes semiconductor oxide if the transistor 84 is a semiconductor oxide transistor.

[0061] The conductive layer 86 (sometimes called the source-drain terminal) may be electrically connected to the active region 76. The conductive layer 86 may form the first source-drain terminal of the transistor 84. The conductive layer 88 (sometimes called the source-drain terminal) may be electrically connected to the active region 76. The conductive layer 88 may form the second source-drain terminal of the transistor 84. The conductive layer 88 may be electrically connected to the substrate 82.

[0062] The gate 78 of transistor 84 may be formed on an active region 76. The gate 78 may be isolated from the active region 76 by an interlayer dielectric layer 74. More specifically, a gate insulating layer may be interposed between the active region 76 and the gate 78.

[0063] Each plane of the components within a display is sometimes called a deck or circuit configuration deck. Thus, each deck has at least one circuit component (e.g., an active circuit component or a passive circuit component). Each deck may be formed on a flat surface (such as having a flat bottom surface) and may have a planarizing layer to provide a deck with a flat top surface. Active circuit components are sometimes simply called active components. Passive circuit components are sometimes simply called passive components.

[0064] In the example in Figure 4, the first deck 90-1 includes an active component 84, and the second deck 90-2 includes a passive component 72.

[0065] The planarization layer 70-1 for the first deck 90-1 is formed on and may be in direct contact with the interlayer dielectric layer(s) 74, conductive layer 86, and conductive layer 88. The planarization layer conforms to the underlying components and has a flat top surface. The planarization layer may be formed from a siloxane material, a polyimide polymer material, or any other desired material.

[0066] The conductive layer 80-1 may be formed on the upper surface of the planarization layer 70-1. One or more interlayer dielectric layers may be formed on the conductive layer 80-1. The passive component 72 is formed on the conductive layer 80-1. The passive component 72 includes first and second conductive layers 72-1 and 72-2 separated by an interlayer dielectric layer 74. The first and second conductive layers 72-1 and 72-2 may form first and second plates for a capacitor, respectively. As shown in Figure 4, the conductive layer 72-1 may be electrically connected to the conductive layer 86 via a via (92-1) in the planarization layer 70-1.

[0067] The planarization layer 70-2 for the second deck 90-2 is formed on the interlayer dielectric layer(s) 74 and the conductive layer 72-1 and may be in direct contact with them. The planarization layer conforms to the underlying components and has a flat top surface. The planarization layer may be formed from a siloxane material or any other desired material.

[0068] A light-emitting diode 42 may be formed on the planarization layer 70-2. The light-emitting diode includes an anode 62, an organic light-emitting diode (OLED) layer 68, and a cathode 66. The OLED layer 68 is interposed between the anode 62 and the cathode 66. A pixel delimiting layer 64 that defines the aperture for the pixel may also be included in the pixel 22. The example in Figure 4 where the LED 42 is an OLED is for illustrative purposes only. In general, the LED 42 may be any desired type of LED (e.g., an inorganic LED or an OLED).

[0069] An example is described in which the planarization layers 70-1 and 70-2 are formed from a siloxane material (e.g., a material having Si-O-Si chains). The planarization layers may have dielectric constants such as 2.6 to 3.2, greater than 2, or less than 3.5. By using a siloxane material for the planarization layer, the upper surface of the planarization layer can be made to have a variation of less than 0.3 microns in the thickness direction (e.g., parallel to direction 65 in Figure 4). The siloxane material may also have favorable properties with respect to adhesion and gas release.

[0070] Figure 4 shows an example in which pixel 22 includes a first via 92-1 and a second via 92-2. The conductive layer 72-2 extends through via 92-1 in the planarization layer 70-1 to contact the conductive layer 86. The anode 62 extends through via 92-2 in the planarization layer 70-2 to contact the conductive layer 72-1.

[0071] Vias 92-1 and 92-2 can be characterized by their width. Via 92-1 has a width 94-1, and via 92-1 has a width 94-2. In the case of vias, the width may refer to the width at the narrowest part of the via (e.g., the bottom of the via). Relaxing the via width can reduce the footprint requirements of pixel 22. Widths 94-1 and 94-2, respectively, may be less than 1 micron, less than 0.8 microns, less than 0.6 microns, 0.2 to 0.8 microns, etc. To manufacture vias with a width of less than 1 micron (sometimes called submicron vias), photoresist patterning can first be used to obtain vias with a width greater than 1 micron. Then, an aqueous resolution enhancement treatment (RET) may be performed. During the aqueous resolution enhancement treatment, the aqueous polymer material bonds with the photoresist to reduce the overall width of the via (e.g., to a width of less than 1 micron). This embodiment is merely illustrative, and submicron vias can be created using other processes if desired.

[0072] As shown in Figure 4, the pixel density of the display 14 can be increased by stacking the components of the pixel 22 (for example, exceeding 600 PPI, 800 PPI, or 1000 PPI).

[0073] The example in Figure 4, where passive components are stacked on top of active components, is for illustrative purposes only. In another possible example shown in Figure 5, the first deck contains active components, and the second deck contains stacked active and passive components. Deck 90-1 in Figure 5 is the same as in Figure 4, and therefore, for brevity, will not be described again.

[0074] Deck 90-2 in Figure 5 includes a conductive layer 80-1 (similar to that in Figure 4). The transistor 96 (sometimes called the active component 96) is formed on the conductive layer 80-1. The transistor 96 includes a channel region 98 (sometimes called the active region, channel, etc.). The channel region 98 is separated from the conductive layer 80-1 by an interlayer dielectric layer 74.

[0075] The conductive layer 102 (sometimes called the source-drain terminals) may be electrically connected to the active region 98. The conductive layer 102 may form the source-drain terminals of the transistor 96.

[0076] The gate 100 of transistor 96 may be formed on an active region 98. The gate 100 may be isolated from the active region 98 by an interlayer dielectric layer 74. More specifically, a gate insulating layer may be interposed between the active region 98 and the gate 100.

[0077] A conductive layer 104 may be formed on the transistor 96. The conductive layer 104 can be isolated from the gate 100 and the conductive layer 102 by an interlayer dielectric layer 74. The conductive layer 104 is electrically connected to the conductive layer 86 via vias 92-1.

[0078] Capacitor 72 may be stacked on top of transistor 96 in deck 90-2. As shown in Figure 5, capacitor 72 includes a first conductive layer 72-2 and a second conductive layer 72-1. An interlayer dielectric layer 74 is interposed between conductive layer 72-1 and conductive layer 72-2. An interlayer dielectric layer 74 is interposed between conductive layer 72-2 and conductive layer 104. Conductive layer 104 can optionally form a third electrode of capacitor 72.

[0079] As shown in Figure 5, the conductive layer 72-2 is electrically connected to the active region 98. Furthermore, the anode 62 is electrically connected to the conductive layer 72-2 via via 02-2 in the planarization layer 70-2.

[0080] Another example of a pixel having vertically stacked components is shown in Figure 6. In the example in Figure 6, the pixel comprises three decks (90-1, 90-2, 90-3), each containing at least one component. In Figure 6, deck 90-1 contains transistors 128 and 130, deck 90-2 contains transistors 142 and 144, and deck 90-3 contains one or more capacitors 152. Each of transistors 128, 130, 142, and 144 may be a semiconductor oxide transistor or a silicon transistor.

[0081] The transistor 128 in deck 90-1 includes an active region 112, a gate 114, a first source-drain terminal 116, and a second source-drain terminal 118. The conductive layer 80-1 may be formed beneath the channel region 112 and may be separated from the channel region 112 by an interlayer dielectric layer 74. An interlayer dielectric layer (e.g., a gate insulating layer) may be formed between the channel region 112 and the gate 114.

[0082] The transistor 130 in deck 90-1 includes an active region 120, a gate 122, a first source-drain terminal 124, and a second source-drain terminal 126. The conductive layer 80-2 may be formed beneath the channel region 120 and may be separated from the channel region 120 by an interlayer dielectric layer 74. An interlayer dielectric layer (e.g., a gate insulating layer) may be formed between the channel region 120 and the gate 122.

[0083] The planarization layer 70-1 is formed on and conforms to the interlayer dielectric layer(s) 74 and the source-drain terminals 116, 118, 124, and 126. The upper surface of the planarization layer 70-1 serves as a planar substrate for the deck 90-2. The planarization layer 70-1 may be formed from siloxane or polyimide, as described above.

[0084] The transistor 142 in deck 90-2 includes a channel region 132, a gate 134, and source-drain terminals 136. The conductive layer 80-3 may be formed beneath the channel region 132 and may be separated from the channel region 132 by an interlayer dielectric layer 74. An interlayer dielectric layer (e.g., a gate insulating layer) may be formed between the channel region 132 and the gate 134.

[0085] The transistor 144 in deck 90-2 includes a channel region 132, a gate 138, and source-drain terminals 140. The conductive layer 80-4 may be formed beneath the channel region 132 and may be separated from the channel region 132 by an interlayer dielectric layer 74. An interlayer dielectric layer (e.g., a gate insulating layer) may be formed between the channel region 132 and the gate 138.

[0086] The example in Figure 6, showing transistors 142 and 144 sharing a channel region, is for illustrative purposes only. If desired, transistors 142 and 144 may each have their own separate channel regions.

[0087] The planarization layer 70-2 is formed on and conforms to the interlayer dielectric layer(s) 74 and the source-drain terminals 136 and 140. The upper surface of the planarization layer 70-2 serves as a planar substrate for the deck 90-3. The planarization layer 70-2 may be formed from siloxane or polyimide, as described above.

[0088] A capacitor (one or more) 152 may include two capacitors. The first capacitor is formed using conductive layers 146 and 148. The second capacitor is formed using conductive layers 148 and 150. Interlayer dielectric layers may be interposed between the conductive layers 146, 148, and 150. Alternatively, the conductive layers 146, 148, and 150 may function as three electrodes of a single capacitor.

[0089] As shown in Figure 6, the conductive layer 146 may be electrically connected to the gate 138 of transistor 144 via vias in the planarization layer 70-2. The conductive layer 148 may be electrically connected to the channel region 132 via vias in the planarization layer 70-2.

[0090] The planarization layer 70-3 is formed on and conforms to the interlayer dielectric layer(s) 74 and the conductive layer 150. The upper surface of the planarization layer 70-3 serves as a planar substrate for the anode 62. The anode 62 may be electrically connected to the conductive layer 148 via vias within the planarization layer 70-3. The planarization layer 70-3 may be formed from siloxane or polyimide, as described above.

[0091] It should be noted that the conductive layers 80 in Figures 4 to 6 can function as shields for the components on which they overlap. For example, conductive layer 80-1 may function as a shield for transistor 128, and conductive layer 80-2 may function as a shield for transistor 130. The conductive layers 80 may have a planar top surface to ensure the planarity of the components placed on top of them.

[0092] In general, the transistors and capacitors shown as examples in Figures 4 to 6 may correspond to any desired transistors and capacitors within the display pixel 22 or within the display driver circuit configuration (e.g., the data driver circuit configuration 20A or the gate driver circuit configuration 20B in Figure 2). In other words, the circuit configuration outside the light-emitting area of ​​the display may include active and / or passive components stacked vertically within multiple decks (as in Figures 4 to 6). In general, the concept of vertically stacked active and / or passive components may be applied to any desired active and / or passive components within the electronic device 10.

[0093] Capacitor 72 in Figure 4 may correspond to Cst in Figure 3A, C1 in Figure 3B, or C2 in Figure 3B. Transistor 84 in Figure 4 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B.

[0094] As a specific example, transistor 84 in Figure 4 may correspond to the drive transistor T2 in Figure 3A, and capacitor 72 may correspond to capacitor Cst in Figure 3A. As another specific example, transistor 84 in Figure 4 may correspond to the drive transistor T2 in Figure 3B, and capacitor 72 may correspond to capacitor C1 in Figure 3B.

[0095] Capacitor 72 in Figure 5 may correspond to Cst in Figure 3A, C1 in Figure 3B, C2 in Figure 3B, or C1 and C2 in Figure 3B. Transistor 84 in Figure 5 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B. Transistor 96 in Figure 5 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B.

[0096] As a specific example, transistor 96 in Figure 5 may correspond to the drive transistor T2 in Figure 3A, transistor 84 in Figure 5 may correspond to transistor T6 in Figure 3A, and capacitor 72 may correspond to capacitor Cst in Figure 3A. As another specific example, transistor 96 in Figure 5 may correspond to the drive transistor T2 in Figure 3B, transistor 84 in Figure 5 may correspond to transistor T3 in Figure 3B, and capacitor 72 may correspond to capacitor C1 in Figure 3B.

[0097] The capacitor(s) 152 in Figure 6 may correspond to Cst in Figure 3A, C1 in Figure 3B, C2 in Figure 3B, or C1 and C2 in Figure 3B. The transistor 128 in Figure 6 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B. The transistor 130 in Figure 6 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B. The transistor 142 in Figure 6 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B. Transistor 144 in Figure 6 may correspond to any one of T1, T2, T3, T4, T5, or T6 in Figure 3A, or any one of T1, T2, T3, or T4 in Figure 3B.

[0098] As a specific example, transistor 128 in Figure 6 may correspond to transistor T6 in Figure 3A, transistor 130 in Figure 6 may correspond to transistor T1 in Figure 3A, transistor 142 in Figure 6 may correspond to transistor T4 in Figure 3A, transistor 144 in Figure 6 may correspond to transistor T2 in Figure 3A, and capacitor(s) 152 in Figure 6 may correspond to capacitor Cst in Figure 3A. As another specific example, transistor 128 in Figure 6 may correspond to transistor T3 in Figure 3B, transistor 130 in Figure 6 may correspond to transistor T1 in Figure 3B, transistor 142 in Figure 6 may correspond to transistor T4 in Figure 3B, transistor 144 in Figure 6 may correspond to transistor T2 in Figure 3B, and capacitor(s) 152 in Figure 6 may correspond to capacitors C1 and C2 in Figure 3B.

[0099] These examples are merely illustrative. In general, any desired number of components may be stacked vertically on multiple decks. Active components may include top-gate transistors, bottom-gate transistors, and / or dual-gate transistors. Each deck may contain any desired number of active and / or passive components.

[0100] As shown in Figures 4 to 6, the display pixel 22 may include one or more vias for electrically connecting components on different decks. To reduce the footprint required for vias, vias can be partially overlapping (as in Figure 7A) or fully overlapping (as in Figure 7B). As shown in the partially overlapping vias of Figure 7A, via 202-2 may house the conductive layer 204-2, and via 202-1 may house the conductive layer 204-1. In the partially overlapping vias of Figure 7A, the conductive layer 204-2 of via 202-2 overlaps with the edge surface 206 of the conductive layer 204-1 of via 202-1. Thus, the conductive layer 204-2 has a portion that is in direct contact with the upper surface of the conductive layer 204-1, a portion that is in direct contact with the edge surface 206 of the conductive layer 204-1, and a portion that is in direct contact with the underlying insulating layer 208 (e.g., an interlayer dielectric layer or another insulating substrate). In another possible configuration shown in Figure 7B, the conductive layer 204-2 extends into via 202-1 such that the center of via 202-1 is completely overlapped by the conductive layer 204-2. Via 202-2 is sometimes referred to as being nested within via 202-1. In this example, via 202-2 has a smaller width than via 202-1 in order to be nested within via 202-1.

[0101] By using the types of vias shown in Figures 7A and 7B, the footprint requirements of the display pixels 22 can be reduced. For example, Figures 4 and 5 show via 92-1 that contacts the source-drain terminal 86. The source-drain terminal 86 has a via for electrical connection to the active region 76. These two vias may be formed as partially overlapping vias (as in Figure 7A) or fully overlapping vias (as in Figure 7B) to reduce the overall via footprint.

[0102] Capacitors within pixel 22 may be desirable to have high capacitance density and low current leakage. Generally, including a thin dielectric layer can improve the capacitor's storage capacitance (and therefore capacitance density). However, a thin dielectric layer can also cause higher current leakage from the capacitor. To achieve high capacitance density while maintaining low current leakage, alternating layers of high dielectric constant material (sometimes called high-k material) and low dielectric constant material (sometimes called low-k material) may be formed between the capacitor electrodes. Figures 8 to 11 illustrate this type of capacitor.

[0103] Figure 8 is a side view of an exemplary capacitor 210. The capacitor 210 includes first and second conductive electrodes 212-1 and 212-2 (sometimes called plates 212-1 and 212-2). Multiple dielectric layers are interposed between electrodes 212-1 and 212-2. The multiple dielectric layers include one or more high-k dielectric layers 216 and one or more low-k dielectric layers 214. In the configuration of Figure 8, one high-k dielectric layer 216 is interposed between low-k dielectric layers 214-1 and 214-2.

[0104] The low-k dielectric layer 214 may have dielectric constants such as less than 10, less than 8, less than 6, less than 4, less than 2, greater than 1.5, and between 1.5 and 10. The high-k dielectric layer 216 may have dielectric constants such as greater than 10, greater than 12, greater than 15, and greater than 20.

[0105] Each electrode within the capacitor 210 may be formed from a metal or an alloy of two or more metals (e.g., titanium, titanium nitride, copper, aluminum, aluminum alloy, silver, tungsten, etc.). The high-k dielectric layer within the capacitor 210 may be formed from aluminum oxide, hafnium oxide, titanium oxide, or another desired material. The low-k dielectric material within the capacitor 210 may be formed from silicon nitride, silicon dioxide, etc.

[0106] Each low-k dielectric layer within a single capacitor may be made of the same material, or different low-k dielectric layers within a single capacitor may be made of different materials. Each high-k dielectric layer within a single capacitor may be made of the same material, or different high-k dielectric layers within a single capacitor may be made of different materials.

[0107] By including both a high-k dielectric layer and a low-k dielectric layer in the capacitor between the capacitor electrodes (as shown in Figure 8), a high capacitance density can be achieved while maintaining low current leakage.

[0108] In the example in Figure 8, two low-k dielectric layers and one high-k dielectric layer are sandwiched between the capacitor electrodes, but this is merely an example. In general, two or more alternating low-k and high-k dielectric layers can be arranged between the capacitor electrodes (e.g., two dielectric layers, three dielectric layers as in Figure 8, four dielectric layers, five dielectric layers, or more than five dielectric layers).

[0109] In Figure 8, the upper electrode 212-2 has an upper portion extending in a first direction and first and second edge portions extending in a second direction perpendicular to the first direction. In this way, the upper electrode 212-2 surrounds the lower electrode 212-1. This example is merely illustrative. If desired, the upper electrode 212-2 may be simply formed as a patch on the dielectric layer 214-2, as indicated by the dashed line 218.

[0110] Figure 8 shows an example with two capacitor electrodes. If desired, capacitor 210 may include three capacitor electrodes. Figure 9 shows an example of this type. A high-k dielectric layer 216-1 sandwiched between low-k dielectric layers 214-1 and 214-2 interposes between electrodes 212-1 and 212-2. A high-k dielectric layer 216-2 sandwiched between low-k dielectric layers 214-3 and 214-4 interposes between electrodes 212-2 and 212-3. The additional electrodes in Figure 9 compared to Figure 8 can further increase the capacitance density of capacitor 210. Alternatively, two capacitors can be formed using the type of structure shown in Figure 9.

[0111] In the example in Figure 9, each electrode is formed as a patch on its respective dielectric layer. This example is merely illustrative. If desired, each electrode may surround one or more electrodes below it, as shown in Figure 10. In Figure 10, the intermediate electrode 212-2 has an upper portion extending in a first direction and first and second edges extending in a second direction perpendicular to the first direction. In this way, the intermediate electrode 212-2 surrounds the lower electrode 212-1. In Figure 10, the upper electrode 212-3 has an upper portion extending in a first direction and first and second edges extending in a second direction perpendicular to the first direction. In this way, the upper electrode 212-3 surrounds electrodes 212-1 and 212-2.

[0112] Furthermore, it should be noted that the capacitor may have any desired geometric shape. As shown in Figure 11, the capacitor electrodes 212-1 and 212-2 may be formed as vias (both electrodes extending downward through openings in the substrate). Electrode 212-1 has portions adjacent to each other at non-orthogonal and non-parallel angles. Electrode 212-2 has portions adjacent to each other at non-orthogonal and non-parallel angles. By using a non-planar structure for one or more of the capacitor electrodes in this way, the flexibility of the arrangement of the capacitor structure in the display 14 can be increased.

[0113] To form a capacitor, a plasma process can be used to enhance the adhesion between one or more high-k dielectric layers and the low-k dielectric layers on top of them. The plasma process may be applied to one or more high-k dielectric layers before forming the subsequent low-dielectric-constant dielectric layers.

[0114] Any of the capacitor structures described in relation to Figures 8 to 11 can be used as capacitors shown and described in relation to Figures 3 to 7.

[0115] According to one embodiment, a display pixel configured to irradiate light in a first direction is provided, the display pixel comprising: a substrate; a first transistor formed on the substrate; a first planarization layer overlapping the first transistor in a first direction; a component overlapping the first transistor in a first direction, the component including a component selected from the group consisting of capacitors and transistors; a second planarization layer overlapping the component in a first direction; and an anode overlapping the first transistor and the component in a first direction.

[0116] In another embodiment, the component is a capacitor.

[0117] According to another embodiment, the capacitor includes a first electrode and a second electrode.

[0118] According to another embodiment, the capacitor includes first and second dielectric layers between a first electrode and a second electrode, wherein the first dielectric layer has a greater dielectric constant than the second dielectric layer.

[0119] According to another embodiment, the first dielectric layer has a first dielectric constant greater than 10, and the second dielectric layer has a second dielectric constant between 1.5 and 10.

[0120] According to another embodiment, the capacitor further includes a third dielectric layer between a first electrode and a second electrode, wherein the second and third dielectric layers are formed from the same material, and the first dielectric layer is interposed between the second dielectric layer and the third dielectric layer.

[0121] According to another embodiment, the first dielectric layer comprises a material selected from the group consisting of aluminum oxide, hafnium oxide, and titanium oxide.

[0122] According to another embodiment, the capacitor further includes a third electrode.

[0123] In another embodiment, the component is a transistor, and the transistor is a second transistor.

[0124] According to another embodiment, the first and second transistors include first and second channel regions, respectively, formed from a semiconductor oxide.

[0125] According to another embodiment, the display pixel includes a capacitor that overlaps with the second transistor in a first direction, and the capacitor is interposed between the second transistor and the second planarization layer.

[0126] According to another embodiment, the display pixel includes a capacitor that overlaps with the second transistor in a first direction, and the second planarization layer is interposed between the capacitor and the second transistor.

[0127] According to another embodiment, the display pixel includes a third planarization layer that overlaps with the capacitor in a first direction, the third planarization layer being interposed between the anode and the capacitor.

[0128] According to another embodiment, the display pixel includes a conductive via extending through a first planarization layer, the conductive via having a width of less than 1 micron.

[0129] According to another embodiment, the first and second planarization layers include a siloxane material.

[0130] According to another embodiment, the display pixel includes a light-emitting diode including an anode.

[0131] According to one embodiment, a display pixel is provided, comprising a first power terminal, a second power terminal, a light-emitting diode, a drive transistor, wherein the drive transistor and the light-emitting diode are connected in series between the first power terminal and the second power terminal, a switching transistor connected to the gate of the drive transistor, a substrate, a first deck on the substrate including the switching transistor and a first planarization layer overlapping the switching transistor, and a second deck on the first deck including the drive transistor and a second planarization layer overlapping the drive transistor.

[0132] According to another embodiment, the display pixel includes a capacitor connected to the gate of a driving transistor, and a third deck on a second deck which includes a capacitor and a third planarization layer overlapping the capacitor.

[0133] According to another embodiment, the display pixel includes an anode for a light-emitting diode on a third planarization layer.

[0134] According to one embodiment, a display is provided that includes an array of display pixels having a pixel density of more than 1,000 pixels per inch, wherein each display pixel in the array of display pixels includes a light-emitting diode configured to emit light perpendicularly, and a drive transistor having a first gate that is perpendicularly superimposed by the light-emitting diode. The system includes a light-emitting diode and an additional transistor having a second gate that is vertically superimposed on the first gate.

[0135] The above are merely illustrative examples, and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The embodiments described above may be implemented individually or in any combination.

Claims

1. A display pixel configured to emit light in a first direction, The aforementioned display pixels are circuit board and A first transistor formed on the substrate, A first planarization layer that overlaps with the first transistor in the first direction, A second transistor that overlaps with the first transistor in the first direction, A second planarization layer overlapping the second transistor in the first direction, A capacitor that overlaps with the second transistor in the first direction, A display pixel comprising an anode that overlaps with the first transistor and the second transistor in the first direction.

2. A first conductive via extending through the first planarization layer, A second conductive via extending through the second planarization layer, The display pixel according to claim 1, further comprising:

3. The display pixel according to claim 1, wherein the capacitor includes first and second electrodes.

4. The display pixel according to claim 3, wherein the capacitor includes first and second dielectric layers between the first electrode and the second electrode, and the first dielectric layer has a greater dielectric constant than the second dielectric layer.

5. The display pixel according to claim 4, wherein the first dielectric layer has a first dielectric constant greater than 10, and the second dielectric layer has a second dielectric constant between 1.5 and 10.

6. The display pixel according to claim 4, wherein the capacitor further includes a third dielectric layer between the first electrode and the second electrode, the second and third dielectric layers are formed from the same material, and the first dielectric layer is interposed between the second dielectric layer and the third dielectric layer.

7. The display pixel according to claim 4, wherein the first dielectric layer comprises a material selected from the group consisting of aluminum oxide, hafnium oxide, and titanium oxide.

8. The display pixel according to claim 3, wherein the capacitor further comprises a third electrode.

9. The display pixel according to claim 1, wherein the first and second transistors each include first and second channel regions, and at least one of the first or second channel regions is formed of polysilicon.

10. The display pixel according to claim 1, wherein the first and second transistors each include first and second channel regions formed from a semiconductor oxide.

11. The display pixel according to claim 1, wherein the capacitor is interposed between the second transistor and the second planarization layer.

12. The display pixel according to claim 1, wherein the second planarization layer is interposed between the capacitor and the second transistor.

13. The present invention further comprises a third planarization layer that overlaps with the capacitor in the first direction, the third planarization layer being interposed between the anode and the capacitor, The display pixel according to claim 12.

14. The present invention further comprises conductive vias extending through the first planarization layer, wherein the conductive vias have a width of less than 1 micron. The display pixel according to claim 1.

15. The display pixel according to claim 1, wherein the first and second planarization layers comprise a siloxane material.

16. Light-emitting diode including the anode, The display pixel according to claim 1, further comprising:

17. Display pixels, The first power terminal and The second power terminal and Light-emitting diodes and A drive transistor, wherein the drive transistor and the light-emitting diode are connected in series between the first power supply terminal and the second power supply terminal, A switching transistor connected to the gate of the aforementioned drive transistor, circuit board and The switching transistor and the first deck on the substrate including a first planarization layer overlapping the switching transistor, A display pixel comprising a second deck on the first deck, which includes the drive transistor and a second planarization layer overlapping the drive transistor.

18. A capacitor connected to the gate of the drive transistor, A third deck on the second deck, including the capacitor and a third planarization layer overlapping the capacitor, The display pixel according to claim 17, further comprising:

19. The anode of the light-emitting diode is placed on the third planarization layer. The display pixel according to claim 18, further comprising:

20. It is a display, It includes an array of display pixels having a pixel density greater than 1,000 pixels per inch, and the display pixels within the array of display pixels are A light-emitting diode that emits light vertically, A drive transistor having a first gate that is vertically superimposed by the light-emitting diode, A display comprising the light-emitting diode and an additional transistor having a second gate that is vertically superimposed by the first gate.

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