Display boards and display devices

Abstract

The display board comprises a base and a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13 located in a first display area A1. At least one first pixel circuit 11 is electrically connected to at least two first light-emitting elements 13. At least one first pixel circuit 11 includes at least one reset transistor T1, T7, T8. The orthographic projection of at least one first light-emitting element 13 on the base at least partially overlaps with the orthographic projection of the reset transistor T1, T7, T8 of at least one first pixel circuit 11 on the base.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly relates to a display substrate and a display device.

Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices, and have advantages such as autonomous light emission, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, bendability, and low cost.

Summary of Invention

[0003] The following is a summary of the subject matter detailed in the present text. This summary is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In one aspect, the present embodiment provides a display substrate, comprising a base, a plurality of first pixel circuits located in a first display area, and a plurality of first light-emitting elements. At least one first pixel circuit is electrically connected to at least two first light-emitting elements. At least one first pixel circuit includes at least one reset transistor. An orthographic projection of at least one first light-emitting element on the base at least partially overlaps an orthographic projection of the reset transistor of at least one first pixel circuit on the base.

[0006] In some exemplary embodiments, the plurality of first light-emitting elements include a plurality of first light-emitting elements that emit light of different colors. Orthographic projections of the plurality of first light-emitting elements emitting light of the same color on the base at least partially overlap orthographic projections of reset transistors of the plurality of first pixel circuits on the base.

[0007] In some exemplary embodiments, the orthogonal projection of the anode of the at least one first light-emitting element onto the base includes the orthogonal projection of the active layer of the at least one reset transistor onto the base.

[0008] In some exemplary embodiments, the at least one first pixel circuit includes a first reset transistor and a second reset transistor. The orthographic projection of the first reset transistor of the at least one first pixel circuit on its base at least partially overlaps with the orthographic projection of one first light-emitting element on its base, and the orthographic projection of the second reset transistor of the at least one first pixel circuit on its base at least partially overlaps with the orthographic projection of another first light-emitting element on its base that emits light of the same color.

[0009] In some exemplary embodiments, the orthographic projection of the first light-emitting element on the base that overlaps with the second reset transistor does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element on the base.

[0010] In some exemplary embodiments, the plurality of first light-emitting elements are divided into a plurality of light-emitting units, each light-emitting unit including a first light-emitting element that emits one first color of light, a first light-emitting element that emits one second color of light, and a first light-emitting element that emits two third colors of light. The first light-emitting element that emits the first color of light is electrically connected to one first pixel circuit, the first light-emitting element that emits the second color of light is electrically connected to one first pixel circuit, and the two first light-emitting elements that emit the third colors of light are electrically connected to the same first pixel circuit.

[0011] In some exemplary embodiments, the first light-emitting element emitting the first color of light and the first light-emitting element emitting the second color of light in the light-emitting unit are arranged in the same row, the two first light-emitting elements emitting the third color of light are arranged in the same row, and the four first light-emitting elements in the light-emitting unit are arranged in different columns. The first color of light is red light, the second color of light is blue light, and the third color of light is green light.

[0012] In some exemplary embodiments, the first display area includes a plurality of circuit island areas arranged in an array spaced apart from each other, each circuit island area including three first pixel circuits arranged sequentially along a first direction, with two adjacent rows of circuit island areas being offset from each other. The three first pixel circuits of the circuit island areas are electrically connected to four first light-emitting elements in a single light-emitting unit.

[0013] In some exemplary embodiments, any two adjacent first pixel circuits in the circuit island area are arranged symmetrically with respect to a median line along the first direction between the two adjacent first pixel circuits.

[0014] In some exemplary embodiments, data lines connected to a first pixel circuit connected to a first light-emitting element that emits the third color of light are configured to provide data signals to a plurality of first pixel circuits arranged in rows.

[0015] In some exemplary embodiments, a first pixel circuit connected to a first light-emitting element that emits two third-color light in the light-emitting unit is located between a first pixel circuit connected to a first light-emitting element that emits the first color light and a first pixel circuit connected to a first light-emitting element that emits the second color light.

[0016] In some exemplary embodiments, each first pixel circuit in the circuit island area includes a drive transistor, a first reset transistor, a second reset transistor, and a third reset transistor, wherein the first reset transistor is configured to reset the second electrode of the drive transistor, the second reset transistor is configured to reset the anode of a first light-emitting element connected to the first pixel circuit, and the third reset transistor is configured to reset the first electrode of the drive transistor. The active layers of the first reset transistors of the three first pixel circuits in the circuit island area are integrated structures connected to each other, the active layers of the second reset transistors of the three first pixel circuits are integrated structures connected to each other, and the active layers of the third reset transistors of the three first pixel circuits are integrated structures connected to each other.

[0017] In some exemplary embodiments, the orthographic projections on the base of the integrated active layer structure of the first reset transistors of the three first pixel circuits in the circuit island area, the integrated active layer structure of the second reset transistors of the three first pixel circuits, and the integrated active layer structure of the third reset transistors of the three first pixel circuits, at least partially overlap with the orthographic projections on the base of different first light-emitting elements emitting a third color of light.

[0018] In some exemplary embodiments, the orthographic projection on the base of the integrated active layer structure of three second reset transistors in one circuit island area and the integrated active layer structure of three first reset transistors in adjacent circuit island areas in the second direction at least partially overlaps with the orthographic projection on the base of the same first light-emitting element emitting a third color of light, the first light-emitting element emitting the third color of light is electrically connected to a first pixel circuit in the circuit island area and does not overlap with the orthographic projection on the base of transistors other than the second reset transistors in the first pixel circuit, and the second and first directions intersect.

[0019] In some exemplary embodiments, each first pixel circuit in the circuit island area includes at least a drive transistor, a first reset transistor, and a second reset transistor, wherein the first reset transistor is configured to reset the second electrode of the drive transistor, and the second reset transistor is configured to reset the anode of a first light-emitting element connected to the first pixel circuit. In the circuit island area, the active layers of the first reset transistor and the second reset transistor of a third first pixel circuit along the first direction are aligned in the second direction, and the second and first directions intersect. The orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on its base at least partially overlaps with the orthographic projection of the base of a first light-emitting element emitting one third color of light, and the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on its base at least partially overlaps with the orthographic projection of the base of a first light-emitting element emitting another third color of light.

[0020] In some exemplary embodiments, the orthographic projection of the anode of a first light-emitting element emitting one third color of light onto its base includes the orthographic projection of the active layer of a first reset transistor of a third first pixel circuit onto its base, and the orthographic projection of the anode of a first light-emitting element emitting another third color of light onto its base includes the orthographic projection of the active layer of a second reset transistor of a third first pixel circuit onto its base.

[0021] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer mounted on the base. The sixth conductive layer includes at least a plurality of auxiliary electrodes, and the orthographic projection of the auxiliary electrodes on the base includes the orthographic projection of the light-emitting region of the first light-emitting element on the base.

[0022] In some exemplary embodiments, the multiple auxiliary electrodes are connected via multiple auxiliary connection bars to form a mesh structure, which is connected to a first voltage signal.

[0023] In another embodiment, this embodiment provides a display device comprising the above-mentioned display substrate and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0024] In other embodiments, this embodiment provides a display board comprising a base, a plurality of first pixel circuits located in a first display area, and a plurality of first light-emitting elements. At least one of the plurality of first pixel circuits is electrically connected to one first light-emitting element, and at least one first pixel circuit is electrically connected to at least two first light-emitting elements. The first pixel circuit includes at least one reset transistor. The orthographic projection on the base of at least two first light-emitting elements electrically connected to the same first pixel circuit at least partially overlaps with the orthographic projection on the base of the reset transistors of the plurality of first pixel circuits.

[0025] In some exemplary embodiments, the orthogonal projection of the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the base includes the orthogonal projection of the active layer of at least one reset transistor on the base.

[0026] In some exemplary embodiments, the first pixel circuit includes a first reset transistor and a second reset transistor. The orthographic projection of the base of one of two first light-emitting elements electrically connected to the same first pixel circuit at least partially overlaps with the orthographic projection of the base of the first reset transistor, and the orthographic projection of the base of the other of the at least two first light-emitting elements at least partially overlaps with the orthographic projection of the base of the base of the second reset transistor.

[0027] In some exemplary embodiments, the orthographic projection on the base of the first light emitting element overlapping the second reset transistor does not overlap the orthographic projection on the base of the first pixel circuit connected to the first light emitting element.

[0028] Other aspects can be understood after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings are provided for understanding the technical solution of the present application, constitute a part of the specification, are used to interpret the technical solution of the present application together with the embodiments of the present application, and are not intended to limit the technical solution of the present application.

[0030] [Figure 1] It is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] It is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 3] It is an operation timing diagram of the pixel circuit according to FIG. 2. [Figure 4A] It is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 4B] It is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 5] It is a schematic circuit layout diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 6] It is a partial top schematic view of a first display area according to at least one embodiment of the present disclosure. [Figure 7A] It is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG. 6. [Figure 7B] It is a schematic diagram of one circuit island area in FIG. 7A. [Figure 8A] It is a schematic diagram of the first display area after the first conductive layer is formed in FIG. 6. [Figure 8B] It is a schematic diagram of the first conductive layer in FIG. 8A. [Figure 8C]This is a schematic diagram of one circuit island area in Figure 8A. [Figure 9A] Figure 6 is a schematic diagram of the first display area after the formation of the second conductive layer. [Figure 9B] This is a schematic diagram of the second conductive layer in Figure 9A. [Figure 9C] This is a schematic diagram of one circuit island area in Figure 9A. [Figure 10A] Figure 6 is a schematic diagram of the first display area after the formation of the second semiconductor layer. [Figure 10B] This is a schematic diagram of one circuit island area in Figure 10A. [Figure 11A] Figure 6 is a schematic diagram of the first display area after the formation of the third conductive layer. [Figure 11B] This is a schematic diagram of the third conductive layer in Figure 11A. [Figure 11C] This is a schematic diagram of one circuit island area in Figure 11A. [Figure 12] Figure 6 is a schematic diagram of one circuit island area after the formation of the fifth insulating layer. [Figure 13A] Figure 6 is a schematic diagram of the first display area after the formation of the fourth conductive layer. [Figure 13B] This is a schematic diagram of the fourth conductive layer in Figure 13A. [Figure 13C] This is a schematic diagram of one circuit island area in Figure 13A. [Figure 14] Figure 6 is a schematic diagram of one circuit island area after the formation of the seventh insulating layer. [Figure 15A] Figure 6 is a schematic diagram of the first display area after the formation of the fifth conductive layer. [Figure 15B] This is a schematic diagram of the fifth conductive layer in Figure 15A. [Figure 15C] This is a schematic diagram of one circuit island area in Figure 15A. [Figure 16] Figure 6 is a schematic diagram of one circuit island area after the formation of the eighth insulating layer. [Figure 17A] Figure 6 is a schematic diagram of the first display area after the formation of the sixth conductive layer. [Figure 17B]This is a schematic diagram of the sixth conductive layer in Figure 17A. [Figure 18] Figure 6 is a schematic diagram of the first display area after the formation of the 10th insulating layer. [Figure 19A] This is a schematic diagram of the first display area after the formation of the anode layer in Figure 6. [Figure 19B] This is a schematic diagram of the anode layer in Figure 19A. [Figure 20] Figure 6 is a schematic diagram of the stacking of the first semiconductor layer, the sixth conductive layer, and the anode layer. [Figure 21] This is another local top schematic view of the circuit structure layer of the first display area according to at least one embodiment of the present disclosure. [Figure 22A] Figure 21 is a schematic diagram of the first display area after the formation of the first semiconductor layer. [Figure 22B] This is a schematic diagram of one circuit island area in Figure 22A. [Figure 23A] Figure 21 is a schematic diagram of the first display area after the formation of the first conductive layer. [Figure 23B] This is a schematic diagram of one circuit island area in Figure 23A. [Figure 24A] Figure 21 is a schematic diagram of the first display area after the formation of the second conductive layer. [Figure 24B] This is a schematic diagram of one circuit island area in Figure 24A. [Figure 25A] This is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 21. [Figure 25B] This is a schematic diagram of one circuit island area in Figure 25A. [Figure 26A] Figure 21 is a schematic diagram of the first display area after the formation of the third conductive layer. [Figure 26B] This is a schematic diagram of one circuit island area in Figure 26A. [Figure 27] Figure 21 is a schematic diagram of one circuit island area after the formation of the fifth insulating layer. [Figure 28A] Figure 21 is a schematic diagram of the first display area after the formation of the fourth conductive layer. [Figure 28B]This is a schematic diagram of the fourth conductive layer in Figure 28A. [Figure 28C] This is a schematic diagram of one circuit island area in Figure 28A. [Figure 29] Figure 21 is a schematic diagram of one circuit island area after the formation of the seventh insulating layer. [Figure 30] This is a schematic diagram of the fifth conductive layer in Figure 21. [Figure 31] This is a schematic diagram of the first display area after the sixth conductive layer has been formed on the side of the fifth conductive layer away from the base in Figure 21. [Figure 32] Figure 21 is a schematic diagram showing the positional relationship between the first pixel circuit of the circuit structure layer and the anode layer of the light-emitting structure layer. [Figure 33] This is a schematic diagram of another local top view of the first display area according to at least one embodiment of the present disclosure. [Figure 34A] This is a schematic diagram of the first display area after the formation of the first semiconductor layer in Figure 33. [Figure 34B] This is a schematic diagram of one circuit island area in Figure 34A. [Figure 35A] Figure 33 is a schematic diagram of the first display area after the formation of the first conductive layer. [Figure 35B] This is a schematic diagram of one circuit island area in Figure 35A. [Figure 36A] Figure 33 is a schematic diagram of the first display area after the formation of the second conductive layer. [Figure 36B] This is a schematic diagram of one circuit island area in Figure 36A. [Figure 37A] Figure 33 is a schematic diagram of the first display area after the formation of the second semiconductor layer. [Figure 37B] This is a schematic diagram of one circuit island area in Figure 37A. [Figure 38A] Figure 33 is a schematic diagram of the first display area after the formation of the third conductive layer. [Figure 38B] This is a schematic diagram of one circuit island area in Figure 38A. [Figure 39] Figure 33 is a schematic diagram of one circuit island area after the formation of the fifth insulating layer. [Figure 40A] Figure 33 is a schematic diagram of the first display area after the formation of the fourth conductive layer. [Figure 40B] This is a schematic diagram of the fourth conductive layer in Figure 40A. [Figure 40C] This is a schematic diagram of one circuit island area in Figure 40A. [Figure 41] Figure 33 is a schematic diagram of one circuit island area after the formation of the seventh insulating layer. [Figure 42A] Figure 33 is a schematic diagram of the first display area after the formation of the fifth conductive layer. [Figure 42B] This is a schematic diagram of the fifth conductive layer in Figure 42A. [Figure 42C] This is a schematic diagram of one circuit island area in Figure 42A. [Figure 43] Figure 33 is a schematic diagram of one circuit island area after the formation of the eighth insulating layer. [Figure 44A] Figure 33 is a schematic diagram of the first display area after the formation of the sixth conductive layer. [Figure 44B] This is a schematic diagram of the sixth conductive layer in Figure 44A. [Figure 45] Figure 33 is a schematic diagram of the stacking of the first semiconductor layer, first conductive layer, second conductive layer, second semiconductor layer, third conductive layer, and anode layer. [Figure 46] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0031] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments can be carried out in many different forms. The methods and content can be converted to other forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0032] In the drawings, for clarity, the size, layer thickness, or area of ​​one or more components may be shown in an enlarged manner. Therefore, one embodiment of the present disclosure is not limited to such size, and the shape and size of one or more components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically represent ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0033] In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion of constituent elements and do not limit them in terms of quantity. The term “plural” in this disclosure refers to two or more quantities.

[0034] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of components may be appropriately changed depending on the orientation of the component being described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0035] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or a connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the meaning of these terms in this disclosure depending on the specific circumstances.

[0036] In this specification, “electrically connected” includes cases where components are connected via an element having an electrical function. The “element having an electrical function” is not particularly limited and only needs to be capable of transmitting electrical signals between the connected components. Examples of “elements having an electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and many other types of elements with functions.

[0037] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When transistors with opposite polarity are used, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" may be converted to each other. The gate electrode may also be referred to as the control electrode.

[0039] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0040] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons, and small deformations due to tolerances may exist, such as chamfers, arcs, and other deformations.

[0041] In this disclosure, "light transmittance" refers to the ability of light rays to pass through a medium, and is the percentage of the light beam passing through a transparent or translucent object compared to the incident light beam.

[0042] In this disclosure, "approximately" and "about" do not strictly define boundaries and allow for tolerances within the process and measurement error range. In this disclosure, "same" may include exact matches or approximate matches, and "approximately the same" means that the numerical difference is within 10%.

[0043] In this disclosure, "A extends along direction B" means that A includes a main body and secondary parts connected to the main body, the main body is a line, line segment or elongated object, the main body extends along direction B, and the length of the main body extending along direction B is greater than the length of the secondary parts extending in other directions. In all instances in this disclosure, "A extends along direction B" means "the main body of A extends along direction B."

[0044] With the continuous development of display technology, display equipment is typically equipped with cameras to meet the demands of image capture or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, drop-shaped displays, and punch-hole displays have emerged. These technologies create a perforation in a localized area of ​​the display area and place the camera below the perforation, thereby reducing the area occupied by the camera and improving screen-to-body ratio. However, these technologies require the removal of a portion of the display area, resulting in a portion of the screen being unusable and preventing further improvement of screen-to-body ratio. To achieve true full-screen display while avoiding perforation of the display area and ensuring the practicality of the display substrate, the bottom camera area typically employs either an external pixel circuit placement method or an internal pixel circuit placement method.

[0045] The external pixel circuit placement method refers to a method of improving the light transmittance of the camera area below the screen by placing the pixel circuit, which is connected to the light-emitting element in the camera area below the screen, in the display area, thereby separating the light-emitting element and the pixel circuit. Since the pixel circuit is not installed in the camera area below the screen, there are no other shielding layers in this area other than the anode of the light-emitting element, and high light transmittance can be achieved. However, in this method, the pixel circuit and the light-emitting element must be electrically connected via conductive connection lines, and the size (e.g., hole diameter) of the camera area below the screen of a display substrate using the external pixel circuit placement method is limited by the space available for the conductive connection lines. Increasing the hole diameter of the camera area below the screen requires the addition of a masking process for the conductive connection lines, which increases costs. Furthermore, the material used for the conductive connection lines is usually a transparent conductive material, such as indium tin oxide (ITO). Because ITO has a high sheet resistance, the conductive connection lines are heavily loaded, which easily affects the brightness of the light-emitting element in the camera area below the screen, reducing the brightness of the camera area below the screen and causing display defects in the camera area below the screen, such as vertical display defects (Mura).

[0046] The pixel circuit integration method refers to the placement of light-emitting elements and pixel circuits connected to them in the camera area below the screen. Compared to the external pixel circuit placement method, the integrated method eliminates the need for long conductive connection wires between the pixel circuits and light-emitting elements in the camera area below the screen, thus avoiding display defects in the camera area caused by conductive connection wires. Furthermore, the integrated method does not limit the size of the camera area below the screen, and can support camera areas with large aperture diameters. However, as the pixel density (Pixels Per Inch, PPI) of the camera area below the screen increases, the pixel circuit integration method struggles to satisfy high transmittance and good display effects.

[0047] This embodiment provides a display board and a display device, which can increase the light transmittance of the camera area below the screen of a display board using a pixel circuit integration method.

[0048] This embodiment provides a display substrate comprising a base, a plurality of first pixel circuits located in a first display area, and a plurality of first light-emitting elements. At least one first pixel circuit is electrically connected to at least two first light-emitting elements. At least one first pixel circuit includes at least one reset transistor. The orthographic projection of at least one first light-emitting element on the base at least partially overlaps with the orthographic projection of the reset transistor of at least one first pixel circuit on the base.

[0049] In some examples, the multiple first pixel circuits may be divided into two groups. The first pixel circuits of the first group are connected to the first light-emitting element in a one-to-one driving manner, that is, each first pixel circuit of the first group may be electrically connected to one first light-emitting element and configured to drive the light emission of the connected first light-emitting element. The first pixel circuits of the second group may be connected to the first light-emitting element in a one-to-many driving manner, that is, each first pixel circuit of the second group may be electrically connected to at least two first light-emitting elements and configured to drive the light emission of the connected at least two first light-emitting elements. However, this embodiment is not limited to this. In other examples, all of the multiple first pixel circuits may be connected to the first light-emitting element in a one-to-many driving manner, that is, each first pixel circuit may be connected to at least two first light-emitting elements and drive the light emission of the connected at least two first light-emitting elements.

[0050] In some examples, the orthographic projection at the base of the first light-emitting element may at least partially overlap with the orthographic projection at the base of one reset transistor in one first pixel circuit. Alternatively, for example, the orthographic projection at the base of the first light-emitting element may at least partially overlap with the orthographic projections at the bases of reset transistors in multiple first pixel circuits. This embodiment is not limited to this.

[0051] The display board according to this embodiment employs a pixel circuit integration method, driving the first light-emitting element by the first pixel circuit in at least one-to-many driving mode in the first display area. This allows the number of first pixel circuits in the first display area to be less than the number of first light-emitting elements, contributing to an improvement in the light transmittance of the first display area. In some examples, when the pixel density of the first display area increases, the solution of this embodiment can increase the light transmission area by reducing the number of first pixel circuits, thereby increasing the light transmittance of the first display area and ensuring the display effect of the first display area.

[0052] In some exemplary embodiments, the plurality of first light-emitting elements may include a plurality of first light-emitting elements that emit light of different colors. The orthographic projection at the base of at least one of the plurality of first light-emitting elements that emit light of the same color overlaps at least partially with the orthographic projection at the base of the reset transistor of at least one first pixel circuit. For example, the orthographic projection at the base of at least one first light-emitting element may overlap at least partially with the orthographic projection at the base of the reset transistor of an electrically unconnected first pixel circuit. Alternatively, the orthographic projection at the base of at least one first light-emitting element may overlap at least partially with the orthographic projection at the base of the corresponding electrically connected first pixel circuit's reset transistor. In this example, the reset transistor of the first pixel circuit can be positioned below the first light-emitting elements that emit light of the same color to optimize the circuit layout and increase the light-transmitting area of ​​the first display area.

[0053] In some exemplary embodiments, the orthographic projection of the anode of at least one first light-emitting element on the base may include the orthographic projection of the active layer of at least one reset transistor on the base. For example, the orthographic projection of the anode of at least one first light-emitting element on the base may include the orthographic projection of the active layer of one reset transistor on the base. In this example, shielding for the reset transistor is achieved by positioning the anode of the first light-emitting element to cover the active layer of the reset transistor, thereby increasing the light-transmitting area of ​​the first display area.

[0054] In some exemplary embodiments, at least one first pixel circuit may include a first reset transistor and a second reset transistor. The orthographic projection at the base of the first reset transistor of at least one first pixel circuit at least partially overlaps with the orthographic projection at the base of one first light-emitting element, and the orthographic projection at the base of the second reset transistor of at least one first pixel circuit at least partially overlaps with the orthographic projection at the base of another first light-emitting element emitting light of the same color. In this example, the optimization of the circuit layout is achieved by positioning the first and second reset transistors of the same first pixel circuit to be obscured by different first light-emitting elements, thereby increasing the light-transmitted area of ​​the first display area. In some examples, the orthographic projection at the base of a first light-emitting element overlapping with the second reset transistor does not have to overlap with the orthographic projection at the base of the first pixel circuit connected to the first light-emitting element. For example, one first pixel circuit may be electrically connected to at least two first light-emitting elements, and one of the at least two first light-emitting elements may not overlap with the orthographic projection at the base of the first pixel circuit to which it is connected, and may be used to shield the reset transistor (e.g., a second reset transistor) of the other first pixel circuit. This optimizes the shielding effect of the first light-emitting elements on the first pixel circuit and increases the light transmission area of ​​the first display area.

[0055] In some exemplary embodiments, the multiple first light-emitting elements may be divided into multiple light-emitting units, each light-emitting unit may include a first light-emitting element that emits one first color of light, a first light-emitting element that emits one second color of light, and a first light-emitting element that emits two third colors of light. The first light-emitting element that emits the first color of light is electrically connected to one first pixel circuit, the first light-emitting element that emits the second color of light is electrically connected to one first pixel circuit, and the first light-emitting elements that emit two third colors of light are electrically connected to the same first pixel circuit. In this example, by reducing the number of first pixel circuits electrically connected to the first light-emitting element that emits the third color of light, the number of first pixel circuits in the first display area can be reduced, which contributes to improving the light transmittance of the first display area.

[0056] In some exemplary embodiments, the first light-emitting element emitting a first color of light and the first light-emitting element emitting a second color of light in the light-emitting unit may be arranged in the same row, the two first light-emitting elements emitting a third color of light may be arranged in the same row, and the four first light-emitting elements in the light-emitting unit may be arranged in different columns. The first color of light may be red light, the second color of light may be blue light, and the third color of light may be green light. However, this embodiment is not limited to these. The arrangement of the first light-emitting elements and the connection method of the first pixel circuit in this example can maximize the light transmittance of the first display area in order to ensure light emission white balance.

[0057] In some exemplary embodiments, the first display area may include a plurality of circuit island areas arranged in an array at intervals from one another, each circuit island area including three first pixel circuits sequentially arranged along a first direction, with two adjacent rows of circuit island areas offset from each other. The three first pixel circuits of the circuit island areas are electrically connected to four first light-emitting elements in a single light-emitting unit. The arrangement of the first pixel circuits in this example contributes to increasing the light-transmitting area of ​​the first display area.

[0058] The method of this embodiment will be explained below with examples.

[0059] Figure 1 is a schematic diagram of a display board according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display board may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display board may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the periphery of the first display area A1. The peripheral area BB may surround the periphery of the second display area A2, but is not limited thereto in this embodiment.

[0060] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area and may be referred to as the Full Display With Camera (FDC) area. The second display area A2 may be referred to as the normal display area. For example, the orthographic projection of a sensor (e.g., hardware such as a camera) on the display board may be located within the first display area A1 of the display board. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display board may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display board may be less than or equal to the size of the inscribed circle of the first display area A1.

[0061] In some examples, as shown in Figure 1, the first display area A1 may be located in the middle of the top of the display area AA. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located in other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 may surround at least one side of the first display area A1.

[0062] In some examples, as shown in Figure 1, the display area AA may be a rectangle, for example, a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited to these shapes. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shape.

[0063] In some examples, display area AA may have multiple subpixels. At least one subpixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light emission of the light-emitting element. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0064] In some examples, the light-emitting element may be any one of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element may be an OLED, which can emit red, green, blue, or white light under the drive of the corresponding pixel circuit. The emission color of the light-emitting element can be determined according to the requirements. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit, however, this is not limited in this embodiment.

[0065] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The present example will be described as having an 8T1C structure for the pixel circuit. In some examples, as shown in Figure 2, the present pixel circuit may include eight transistors (i.e., first transistors T1 to eighth transistors T8) and one storage capacitor Cst. The first transistor T1 may be called the first reset transistor, the second transistor T2 may be called the threshold compensation transistor, the third transistor T3 may be called the drive transistor, the fourth transistor T4 may be called the data writing transistor, the fifth transistor T5 may be called the first light emission control transistor, the sixth transistor T6 may be called the second light emission control transistor, the seventh transistor T7 may be called the second reset transistor, and the eighth transistor T8 may be called the third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer placed between the anode and the cathode.

[0066] In some examples, the first transistor T1 and the third to eighth transistors T3 to T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as an N-type transistor. However, this embodiment is not limited to this. For example, all of the transistors in the pixel circuit may be P-type transistors or N-type transistors.

[0067] In some examples, the first type of transistors in the pixel circuit (e.g., including the first transistor T1 and the third to eighth transistors T8) may be low-temperature polysilicon film transistors, and the second type of transistors in the pixel circuit (e.g., including the second transistor T2) may be oxide film transistors. The active layer of the low-temperature polysilicon film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide film transistor is made of oxide semiconductor. Low-temperature polysilicon film transistors have advantages such as high mobility and fast charging, while oxide film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon film transistors and oxide film transistors onto a single display substrate, a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can be formed, and by utilizing the advantages of both, low-frequency driving can be achieved, power consumption can be reduced, and display attributes can be improved.

[0068] In some examples, as shown in Figure 2, the pixel circuit may be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 may be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 may be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL may be configured to provide a data signal to the pixel circuit. The light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0069] In some examples, as shown in Figure 2, the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate electrode of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate electrode of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate electrode of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate electrode of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate electrode of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 may be configured to reset the third node N3. The gate electrode of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 may be configured to reset the fourth node N4. The gate electrode of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 may be configured to reset the second node N2.The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0070] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2, and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0071] Figure 3 is an operation timing diagram of the pixel circuit shown in Figure 2. The operation process of the pixel circuit shown in Figure 2 will be explained below with reference to Figure 3. The first transistor T1 and the third to eighth transistors T3-T8 of the pixel circuit are P-type transistors, while the second transistor T2 is an N-type transistor.

[0072] In some examples, as shown in Figures 2 and 3, the operation process of the pixel circuit during the display time of one frame may include at least a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4.

[0073] The first stage S1 is called the first reset stage. The second reset control signal RESET2 from the second reset control line RST2 is a low-level signal that turns on the seventh transistor T7 and the eighth transistor T8, and the second scan signal SCAN2 from the second scan line GL2 is a high-level signal that turns on the second transistor T2. The eighth transistor T8 turns on and provides the third initial signal from the third initial signal line INIT3 to the second node N2. The seventh transistor T7 turns on and provides the second initial signal from the second initial signal line INIT2 to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 from the first scan line GL1 is a high-level signal, the first reset control signal RESET1 from the first reset control line RST1 is a high-level signal, and the light emission control signal EM from the light emission control line EML is a high-level signal that turns off the fourth transistor T4, the first transistor T1, the fifth transistor T5 and the sixth transistor T6. The light-emitting element EL does not emit light at this stage.

[0074] The second stage S2 is called the second reset stage. The first reset control signal RESET1 from the first reset control line RST1 is a low-level signal, and the first transistor T1 turns on. The second scan signal SCAN2 from the second scan line GL2 is a high-level signal, and the second transistor T2 turns on. The first transistor T1 and the second transistor T2 turn on and provide the first initial signal line INIT1 to the first node N1, initializing the first node N1. The second reset control signal RESET2 from the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 from the first scan line GL1 is a high-level signal, and the light emission control signal EM from the light emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light at this stage.

[0075] The third stage S3 is referred to as the data writing stage or threshold compensation stage. The first scan signal SCAN1 from the first scan line GL1 is a low-level signal, and the fourth transistor T4 turns on. The second scan signal SCAN2 from the second scan line GL2 is a high-level signal, and the second transistor T2 turns on. At this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 turns on. With the second transistor T2, the fourth transistor T4, and the third transistor T3 turning on, the data voltage Vdata output from the data line DL is provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is stored in the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 from the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 from the second reset control line RST2 is a high-level signal, and the light emission control signal EM from the light emission control line EML is a high-level signal, which turns off the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6.

[0076] In the fourth stage S4, the light emission control signal EM from the light emission control line EML may be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 from the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 from the first scan line GL1, the first reset control signal RESET1 from the first reset control line RST1, and the second reset control signal RESET2 from the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output from the first power line PL1 may provide a drive voltage to the anode of the light-emitting element EL via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light emission of the light-emitting element EL.

[0077] During the pixel circuit drive process, the drive current flowing through the third transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the first node N1 is Vdata - |Vth|, the drive current of the third transistor T3 is given by the following equation.

[0078] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2

[0079] In the equation, I is the drive current flowing through the third transistor T3, i.e., the drive current that drives the light-emitting element; K is a constant; Vgs is the voltage difference between the gate electrode of the third transistor T3 and the first electrode; Vth is the threshold voltage of the third transistor T3; Vdata is the data voltage output by the data line DL; and VDD is the first voltage signal output by the first power line PL1.

[0080] As can be seen from the above equation, the current flowing through the light-emitting element is not related to the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Furthermore, the pixel circuit of this embodiment can improve the display performance of the light-emitting element by improving the display failure situation caused by low frequencies.

[0081] Figures 4A and 4B are local schematic diagrams of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 1, 4A, and 4B, the first display area A1 of the display substrate may include a plurality of first light-emitting elements 13 and a plurality of first pixel circuits 11. The plurality of first pixel circuits 11 are electrically connected to the plurality of first light-emitting elements 13. The second display area A2 may include a plurality of second light-emitting elements 14 and a plurality of second pixel circuits 12. The circuit structures of the first pixel circuits 11 and the second pixel circuits 12 in this example may be the same, for example, the 8T1C structure described above.

[0082] In some examples, as shown in Figure 1, at least one second pixel circuit 12 is electrically connected to at least one second light-emitting element 14. For example, multiple second pixel circuits 12 and multiple second light-emitting elements 14 may be electrically connected in a one-to-one correspondence, and one second pixel circuit 12 may be configured to drive the emission of light from one second light-emitting element 14. The orthographic projection of the base of the second light-emitting element 14 may at least partially overlap with the orthographic projection of the base of the connected second pixel circuit 12, but this is not limited to this embodiment. In other examples, multiple second pixel circuits may be configured to drive one second light-emitting element, or one second pixel circuit may be configured to drive multiple second light-emitting elements.

[0083] In some examples, as shown in Figures 4A and 4B, the plurality of first light-emitting elements 13 in the first display area may include a first light-emitting element 13a that emits a plurality of first-color light, a first light-emitting element 13c that emits a plurality of second-color light, and a first light-emitting element 13b, 13d that emit a plurality of third-color light. In some examples, the first-color light may be red light (R), the second-color light may be blue light (B), and the third-color light may be green light (G). This embodiment is not limited thereto.

[0084] In some examples, as shown in Figures 4A and 4B, multiple first light-emitting elements 13 in the first display area may be arranged according to a pentile structure. First light-emitting elements 13b and 13d that emit a third color of light may be arranged alternately in the k-th row at regular intervals, and first light-emitting elements 13a that emit a first color of light and first light-emitting elements 13c that emit a second color of light may be arranged alternately in the k+1-th row. First light-emitting elements 13b and 13d that emit a third color of light may be arranged alternately in the k+2-th row adjacent to the k+1-th row at regular intervals. In the k+3-th row adjacent to the k+2-th row, first light-emitting elements 13a that emit a first color of light and first light-emitting elements 13c that emit a second color of light may be arranged alternately. According to the above rules, multiple rows of first light-emitting elements 13 can be arranged repeatedly. First light-emitting elements 13a that emit a first color of light and first light-emitting elements 13c that emit a second color of light may be arranged alternately in the j-th column. The first light-emitting elements 13b and 13d that emit a third color of light may be arranged at regular intervals in the (j+1) column adjacent to the (j) column. The first light-emitting elements 13a that emit a first color of light and the first light-emitting elements 13c that emit a second color of light may be arranged alternately in the (j+2) column adjacent to the (j+1) column. The first light-emitting elements 13b and 13d that emit a third color of light may be arranged at regular intervals in the (j+3) column. According to the above rules, multiple columns of first light-emitting elements 13 can be arranged repeatedly. Both k and j are integers. In this disclosure, multiple first light-emitting elements 13 arranged along a first direction X may be referred to as a row of first light-emitting elements, and multiple first light-emitting elements 13 arranged along a second direction Y may be referred to as a column of first light-emitting elements.

[0085] In some examples, as shown in Figures 4A and 4B, one light-emitting unit P in the first display area may include four first light-emitting elements 13, namely, a first light-emitting element 13a that emits light of one first color, a first light-emitting element 13c that emits light of one second color, and first light-emitting elements 13b and 13d that emit light of two third colors. The first light-emitting element 13a that emits light of the first color and the first light-emitting element 13c that emits light of the second color in the light-emitting unit P may be arranged in the same row, the first light-emitting elements 13b and 13d that emit light of two third colors may be arranged in the same column, and the four first light-emitting elements 13 included in the light-emitting unit P may be arranged in different columns. As shown in Figure 4A, the row in which the first light-emitting element 13a that emits a first color of light and the first light-emitting element 13c that emits a second color of light are located in one light-emitting unit P may be located in the row before the row in which the first light-emitting elements 13b and 13d that emit two third colors of light are located. As shown in Figure 4B, the row in which the first light-emitting element 13a that emits a first color of light and the first light-emitting element 13c that emits a second color of light are located in one light-emitting unit P may be located in the row after the row in which the first light-emitting elements 13b and 13d that emit two third colors of light are located. However, this embodiment is not limited to this.

[0086] In some examples, as shown in Figures 4A and 4B, a first light-emitting element 13a that emits a first color of light has a first light-emitting region 130a, a first light-emitting element 13c that emits a second color of light has a second light-emitting region 130c, a first light-emitting element 13b that emits a third color of light has a third light-emitting region 130b, and a first light-emitting element 13d that emits a third color of light has a fourth light-emitting region 130d. The first light-emitting region 130a, second light-emitting region 130c, third light-emitting region 130b, and fourth light-emitting region 130d may be approximately circular or elliptical. The first light-emitting region 130a of the first light-emitting element 13a that emits a first color of light may be smaller than the second light-emitting region 130c of the first light-emitting element 13c that emits a second color of light. The second light-emitting region 130c of the first light-emitting element 13c, which emits a second color of light, may be larger than the third light-emitting region 130b of the first light-emitting element 13b, which emits a third color of light, and the fourth light-emitting region 130d of the first light-emitting element 13d. The third light-emitting region 130b and the fourth light-emitting region 130d may be approximately the same. In this example, the light-emitting region of the light-emitting element may be the portion located at the pixel aperture of the pixel definition layer of the light-emitting element.

[0087] Figure 5 is a schematic diagram of the circuit arrangement of a first display area according to at least one embodiment of the present disclosure. Figure 5 shows a schematic diagram of the arrangement of first pixel circuits in a local area of ​​the first display area in Figures 4A and 4B. In some examples, as shown in Figure 5, the first display area may include a plurality of spaced circuit island areas A11. Each circuit island area A11 may include a plurality of first pixel circuits 11, for example, three first pixel circuits 11. In a plane parallel to the display board, the plurality of circuit island areas A11 may be arranged in multiple rows and multiple columns. A plurality of circuit island areas A11 arranged along a first direction X may be referred to as a single row of circuit island areas, and a plurality of circuit island areas A11 arranged along a second direction Y may be referred to as a single column of circuit island areas. The midlines of the plurality of circuit island areas A11 in a single column of circuit island areas in the first direction X may be substantially aligned. Two adjacent circuit island areas A11 in a single row of circuit island areas may be arranged with one column between them. For example, if one circuit island area A11 in the i-th row is located in the m+2th column, then one circuit island area adjacent to that circuit island area A11 in the i-th row may be located in the m-th column or the m+4th column. Two adjacent circuit island areas A11 in a single column may be spaced one row apart. For example, if one circuit island area A11 in the m-th column is located in the i-th row, then one circuit island area adjacent to that circuit island area in the m-th column may be located in the i-2nd row or the i+2nd row. Both i and m are integers. In this example, adjacent circuit island areas A11 in rows may be shifted in the second direction Y, and adjacent circuit island areas A11 in columns may be shifted in the first direction X.

[0088] In some examples, as shown in Figures 4A, 4B, and 5, a single circuit island area A11 of a first display area may include three first pixel circuits 11 (e.g., including first pixel circuits 11a, 11b, and 11c) arranged sequentially along a first direction X. The three first pixel circuits 11 are electrically connected to four first light-emitting elements 13, and the four first light-emitting elements 13 connected to the three first pixel circuits 11 may belong to a single light-emitting unit P. A first pixel circuit 11a may be electrically connected to a first light-emitting element 13a that emits light of one first color and is configured to drive the emission of light from the first light-emitting element 13a. A first pixel circuit 11b may be electrically connected to first light-emitting elements 13b and 13d that emit light of two third colors and is configured to drive the emission of light from the first light-emitting elements 13b and 13d that emit light of the same color. The first pixel circuit 11c may be electrically connected to a first light-emitting element 13c that emits a single second color of light, and is configured to drive the emission of light from the first light-emitting element 13c that emits the second color of light.

[0089] In some examples, as shown in Figures 4A to 5, the gap between adjacent circuit island areas A11 in a single row of circuit island areas may be greater than or equal to the length along the first direction X of one first pixel circuit. For example, the displacement distance L1 between two adjacent rows of circuit island areas may be greater than 1 times the length along the first direction X of the first pixel circuit and less than 3 times the length along the first direction X of the first pixel circuit, for example, about 2 times or 1.5 times. However, this embodiment is not limited to this.

[0090] In some examples, as shown in Figures 4A and 4B, in the first display area, the first light-emitting element 13a may at least partially overlap the orthographic projection on the base of the connected first pixel circuit 11a, and the first light-emitting element 13c may at least partially overlap the orthographic projection on the base of the connected first pixel circuit 11c. The first light-emitting element 13b may at least partially overlap the orthographic projection on the base of the connected first pixel circuit 11b, and the first light-emitting element 13d may not overlap the orthographic projection on the base of the connected first pixel circuit 11b.

[0091] In this example, by installing identical first pixel circuits and driving two first light-emitting elements that emit a third color of light, the number of first pixel circuits required in the circuit island area can be reduced, saving space occupied by the first pixel circuits in the first display area, saving wiring space, and increasing the light transmittance of the first display area.

[0092] Figure 6 is a schematic local top view of a first display area according to at least one embodiment of the present disclosure. Figure 6 is a schematic local top view of the first display area shown in Figure 4A. In some examples, as shown in Figure 6, the first display area may include a first light-transmitting area A12a, a second light-transmitting area A12b, and a third light-transmitting area A12c. The first light-transmitting area A12a may be located in a gap region between adjacent circuit island areas along a first direction X, and may be surrounded by a first light-emitting element 13c of one light-emitting unit, a first light-emitting element 13a of an adjacent light-emitting unit along the first direction X of the light-emitting unit, a first light-emitting element 13d of the light-emitting unit, a first light-emitting element 13b adjacent to the first light-emitting element 13d along a second direction Y, and connecting wiring between two adjacent circuit island areas along the first direction X. The second light-transmitting area A12b and the third light-transmitting area A12c may be located in the gap region between adjacent circuit island areas along the second direction Y, and the second light-transmitting area A12b may be surrounded by the first light-emitting elements 13b, 13c, and 13d of one light-emitting unit, the first light-emitting element 13a of an adjacent light-emitting unit along the second direction Y, and the connecting wiring between adjacent circuit island areas. The third light-transmitting area A12c may be surrounded by the first light-emitting element 13d of one light-emitting unit, the first light-emitting elements 13b and 13a of an adjacent light-emitting unit along the first direction X of the light-emitting unit, the first light-emitting element 13c of an adjacent light-emitting unit along the second direction Y of the light-emitting unit, and the connecting wiring between adjacent circuit island areas.

[0093] In some examples, in a direction perpendicular to the display substrate, the display substrate may include a base, and a circuit structure layer and a light-emitting structure layer mounted on the base. The light-emitting structure layer may be located on the side of the circuit structure layer away from the base. The circuit structure layer of the first display area may include a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include a plurality of first light-emitting elements.

[0094] In some examples, the circuit structure layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, which are placed on the base. A first insulating layer may be placed between the first semiconductor layer and the first conductive layer, a second insulating layer may be placed between the first conductive layer and the second conductive layer, a third insulating layer may be placed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be placed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be placed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be placed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be placed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer and a tenth insulating layer may be placed on the side of the sixth conductive layer away from the base. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to tenth insulating layers may be organic insulating layers. This embodiment is not limited to these. In other examples, one insulating layer may be placed between the fourth conductive layer and the fifth conductive layer. In other examples, one insulating layer may be placed on the side of the sixth conductive layer that is away from the base.

[0095] In some examples, the light-emitting structure layer may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially installed on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light rays of the corresponding color under the driving of the anode and cathode layers.

[0096] The structure of a display substrate will be described below with an example of the manufacturing process of the display substrate. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, but is not limited to these. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” is also referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. Each "layer" after the patterning process contains at least one "pattern".

[0097] In this disclosure, “A and B are placed on the same layer” means that A and B are formed simultaneously by the same patterning process, or that the distance between the base-side surfaces of A and B and the base is essentially the same, or that the base-side surfaces of A and B are in direct contact with the same film layer. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In this disclosure, “the shape of A” means the shape of the orthographic projection of A on the base.

[0098] The following describes the circuit structure layers using three first pixel circuits in one circuit island area of ​​the first display area as an example. In this example, the first pixel circuit is described as having the 8T1C structure. The first first pixel circuit (i.e., the first pixel circuit 11a) may include a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor. The second first pixel circuit (i.e., the first pixel circuit 11b) may include a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The third first pixel circuit (i.e., the first pixel circuit 11c) may include a first transistor 31c, a second transistor 32c, a third transistor 33c, a fourth transistor 34c, a fifth transistor 35c, a sixth transistor 36c, a seventh transistor 37c, an eighth transistor 38c, and a storage capacitor. For the connection relationships between the eight transistors and the storage capacitor in each first pixel circuit, refer to the equivalent circuit diagram shown in Figure 2.

[0099] In some cases, the manufacturing process of a display board may include the following operations:

[0100] (1) A base is provided. In some examples, the base may be a rigid base or a flexible base. For example, the rigid base may be one or more of glass and quartz, but is not limited to these. The flexible base may be one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber, but is not limited to these. In some examples, the flexible base includes a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer that are laminated together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the base.

[0101] (2) A first semiconductor layer is formed. In some examples, a first semiconductor thin film is deposited on a base, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer to be placed on the base. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene.

[0102] Figure 7A is a schematic diagram of the first display area after the formation of the first semiconductor layer in Figure 6. Figure 7B is a schematic diagram of one circuit island area in Figure 7A.

[0103] In some examples, as shown in Figures 7A and 7B, the first semiconductor layer of the first display area is the active layer of at least several first type transistors of several first pixel circuits (for example, the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor and the eighth active layer 380a of the eighth transistor, the first active layer 310b of the first transistor of the first pixel circuit 11b, and the third transistor It may include the third active layer 330b, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor, the first active layer 310c of the first transistor of the first pixel circuit 11c, the third active layer 330c of the third transistor, the fourth active layer 340c of the fourth transistor, the fifth active layer 350c of the fifth transistor, the sixth active layer 360c of the sixth transistor, the seventh active layer 370c of the seventh transistor, and the eighth active layer 380c of the eighth transistor.

[0104] In some examples, as shown in Figure 7B, the first semiconductor layer patterns of the first pixel circuits 11a and 11b in one circuit island area may be substantially symmetric with respect to the first median O1, and the first semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric with respect to the second median O2. As shown in Figure 7A, the first semiconductor layer patterns of different circuit island areas may be independent of each other.

[0105] In some examples, as shown in FIG. 7B, the first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b may be an integrated structure connected to each other. The shape of the integrated structure of the first active layers 310a and 310b may be substantially in the shape of the Chinese character "ji". The third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, the sixth active layer 360b, and the seventh active layer 370b of the first pixel circuit 11b, and the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, the sixth active layer 360c, and the seventh active layer 370c of the first pixel circuit 11c may be an integrated structure connected to each other, and the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer 350c of the first pixel circuit 11c may be directly connected.

[0106] In some examples, as shown in FIG. 7B, the first semiconductor layer pattern of the first pixel circuit 11a is taken as an example for description. The first active layer 310a and the fourth active layer 340a of the first pixel circuit 11a may be located on a side of the third active layer 330a along the second direction Y, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be located on an opposite side of the third active layer 330a along the second direction Y. The first active layer 310a and the seventh active layer 370a may be aligned and disposed in the second direction Y. In some examples, the shape of the third active layer 330a is substantially U-shaped, the shapes of the fourth active layer 340a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a are substantially I-shaped, and the shape of the fifth active layer 350a may be substantially L-shaped, however, the present embodiment is not limited thereto. The arrangement and shape of the first semiconductor layer patterns of the first pixel circuits 11b and 11c are similar to those of the first semiconductor layer pattern of the first pixel circuit 11a, so repeated descriptions are omitted herein.

[0107] In some examples, the active layer of each transistor includes a first area, a second area, and a channel area located between the first and second areas. The material of the first semiconductor layer may include, for example, polysilicon. The channel area may not be doped with impurities and may have semiconductor properties. The first and second areas may be doped regions located on either side of the channel area and are conductive because they are doped with impurities. The impurities may be changed depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as impurity-doped wiring and may be used for the electrical connection of the transistors. This embodiment is not limited thereto.

[0108] (3) A first conductive layer is formed. In some examples, a first insulating thin film and a first conductive thin film are sequentially deposited on the base on which the above structure is formed, and the first conductive thin film is patterned by a patterning process to form a first insulating layer and a first conductive layer placed on the first insulating layer. In some examples, the first conductive layer may be called a first gate metal layer, and the first insulating layer may be called a first gate insulating layer.

[0109] Figure 8A is a schematic diagram of the first display area after the formation of the first conductive layer in Figure 6. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A. Figure 8C is a schematic diagram of one circuit island area in Figure 8A.

[0110] In some examples, as shown in Figures 8A to 8C, the first conductive layer of the first display area may include at least several first scan lines (e.g., including first scan lines GL1(i) and GL1(i+1)), several light emission control lines (e.g., including light emission control lines EML(i) and EML(i+1)), several first reset control lines (e.g., including first reset control lines RST1(i) and RST1(i+1)), several second reset control lines (e.g., including second reset control lines RST2(i) and RST2(i+1)), and first electrodes of storage capacitors of several first pixel circuits (e.g., including first electrodes 391a, 391b, and 391c).

[0111] In some examples, the first scan line GL1(i) may be located on the side of the first electrode (e.g., 391a, 391b, 391c) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1(i) may be located on the side of the first scan line GL1(i) in the second direction Y. The light emission control line EML(i) may be located on the side of the first electrode (e.g., 391a, 391b, 391c) of the storage capacitor of the first pixel circuit in the opposite direction Y, and the second reset control line RST2(i) may be located on the side of the light emission control line EML(i) in the opposite direction Y.

[0112] In some examples, the first reset control line RST1(i), the first scan line GL1(i), the second reset control line RST2(i), and the light emission control line EML(i) can be bent to bypass the gap region between adjacent circuit island areas in the first direction X. For example, the first reset control line RST1(i) and the first scan line GL1(i) may be bent from the side along the second direction Y of the gap region between the circuit island areas, and the second reset control line RST2(i) and the light emission control line EML(i) may be bent from the side along the opposite direction of the second direction Y of the gap region. In this example, by installing the wiring of the first conductive layer so that it bends to bypass the gap region between the circuit island areas, it contributes to improving the light transmittance of the first display area.

[0113] In some examples, the shape of the first reset control line RST1(i) may be a bent shape extending approximately along the first direction X. In the circuit island area, the overlapping region between the first reset control line RST1(i) and the first active layer of the three first pixel circuits may be the gate electrodes of the first transistors of the three first pixel circuits (for example, including the gate electrode of the first transistor 31a, the gate electrode of the first transistor 31b, and the gate electrode of the first transistor 31c).

[0114] In some examples, the shape of the first scan line GL1(i) may be a bent shape extending approximately along the first direction X. In the circuit island area, the overlapping region between the first scan line GL1(i) and the fourth active layer of the three first pixel circuits may be the gate electrodes of the fourth transistors of the three first pixel circuits (e.g., including the gate electrodes of the fourth transistor 34a, the fourth transistor 34b, and the fourth transistor 34c).

[0115] In some examples, the shape of the light emission control line EML(i) may be a bent shape extending approximately along the first direction X. In the circuit island area, the overlapping region of the light emission control line EML(i) and the fifth active layer of the three first pixel circuits may be the gate electrodes of the fifth transistors of the three first pixel circuits (e.g., including the gate electrodes of the fifth transistors 35a, 35b, and 35c), and the overlapping region of the light emission control line EML(i) and the sixth active layer of the three first pixel circuits may be the gate electrodes of the sixth transistors of the three first pixel circuits (e.g., including the gate electrodes of the sixth transistors 36a, 36b, and 36c).

[0116] In some examples, the shape of the second reset control line RST2(i) may be a bent shape extending approximately along the first direction X. In the circuit island area, the overlapping region of the second reset control line RST2(i) and the seventh active layer of the three first pixel circuits may be the gate electrodes of the seventh transistors of the three first pixel circuits (e.g., including the gate electrodes of the seventh transistors 37a, 37b, and 37c), and the overlapping region of the second reset control line RST2(i) and the eighth active layer of the three first pixel circuits may be the gate electrodes of the eighth transistors of the three first pixel circuits (e.g., including the gate electrodes of the eighth transistors 38a, 38b, and 38c).

[0117] In some examples, the first electrode 391a of the storage capacitor in the first pixel circuit 11a may also serve as the gate electrode of the third transistor 33a, the first electrode 391b of the storage capacitor in the first pixel circuit 11b may also serve as the gate electrode of the third transistor 33b, and the first electrode 391c of the storage capacitor in the first pixel circuit 11c may also serve as the gate electrode of the third transistor 33c. The orthographic projection of the first electrodes 391a, 391b, and 391c on the base may be substantially rectangular, for example, a rounded rectangle or a rectangle with chamfers. This embodiment is not limited to this.

[0118] (4) A second conductive layer is formed. In some examples, a second insulating thin film and a second conductive thin film are sequentially deposited on the base on which the above structure is formed, and the second conductive thin film is patterned by a patterning process to form a second insulating layer and a second conductive layer placed on the second insulating layer. In some examples, the second conductive layer may be called a second gate metal layer, and the second insulating layer may be called a second gate insulating layer.

[0119] Figure 9A is a schematic diagram of the first display area after the formation of the second conductive layer in Figure 6. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. Figure 9C is a schematic diagram of one circuit island area in Figure 9A.

[0120] In some examples, as shown in Figures 9A to 9C, the second conductive layer of the first display area may include at least several second scanning guide lines (e.g., including second scanning guide lines GL2b(i), GL2b(i+1)) and second electrodes of storage capacitors of several first pixel circuits (e.g., including second electrodes 392a, 392b, 392c).

[0121] In some examples, the shape of the second scanning guide line GL2b(i) may be a bent shape extending approximately along the first direction X. In the circuit island area, the second scanning guide line GL2b(i) may be located on the side of the second electrode (e.g., 392a, 392b, 392c) of the storage capacitor of the first pixel circuit in the second direction Y. The second scanning guide line GL2b(i) may bypass the spacing region of the circuit island area from the side in the second direction Y and be located on the side of the first scanning line GL1(i) in the opposite direction of the second direction Y.

[0122] In some examples, in the circuit island area, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit at its base may be a rectangular structure having approximately one hollow area, and the orthographic projection of the hollow area at its base may be approximately rectangular, and the rectangle may have rounded corners or chamfers. The second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c may be an integrated structure connected to each other. The second electrodes 392a and 392b may be approximately symmetric with respect to the first midline O1, and the second electrodes 392b and 392c may be approximately symmetric with respect to the second midline O2.

[0123] (5) A second semiconductor layer is formed. In some examples, a third insulating thin film and a second semiconductor thin film are sequentially deposited on the base on which the above pattern is formed, and the second semiconductor thin film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer placed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may be called a third gate insulating layer.

[0124] Figure 10A is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 6. Figure 10B is a schematic diagram of one circuit island area in Figure 10A.

[0125] In some examples, as shown in Figures 10A and 10B, the second semiconductor layer of the first display area may include the active layers of at least several first pixel circuits of a second type of transistor (for example, the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c).

[0126] In some examples, in the circuit island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetric with respect to the first median O1, and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric with respect to the second median O2.

[0127] In some examples, the shapes of the second active layers 320a, 320b, and 320c may be approximately L-shaped. The overlapping region of the second scanning guide line GL2b(i) and the second active layer 320a may serve as the bottom gate of the second transistor 32a, the overlapping region of the second scanning guide line GL2b(i) and the second active layer 320b may serve as the bottom gate of the second transistor 32b, and the overlapping region of the second scanning guide line GL2b(i) and the second active layer 320c may serve as the bottom gate of the second transistor 32c.

[0128] (6) A third conductive layer is formed. In some examples, a fourth insulating thin film and a third conductive thin film are sequentially deposited on the base on which the above pattern is formed, and the third conductive thin film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer placed on the fourth insulating layer. In some examples, the third conductive layer may be called a third gate metal layer, and the fourth insulating layer may be called a fourth gate insulating layer.

[0129] Figure 11A is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 6. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. Figure 11C is a schematic diagram of one circuit island area in Figure 11A.

[0130] In some examples, the third conductive layer of the first display area may include at least a plurality of second scan lines (e.g., including second scan lines GL2(i), GL2(i+1)), a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(i), INIT1(i+1)), a plurality of second initial signal lines (e.g., including second initial signal lines INIT2(i), INIT2(i+1)), and a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(i), INIT3(i+1)). The shapes of the first initial signal lines, second scan lines, second initial signal lines, and third initial signal lines may each be bent lines extending substantially along a first direction X.

[0131] In some examples, in the circuit island area, the first initial signal line INIT1(i) may be located on the side of the second scan line GL2(i) in the second direction Y, the third initial signal line INIT3(i) and the second initial signal line INIT2(i) may be located on the side of the second scan line GL2(i) opposite to the second direction Y, and the second initial signal line INIT2(i) may be located on the side of the third initial signal line INIT3(i) opposite to the second direction Y.

[0132] In some examples, the orthographic projection of the first initial signal line INIT1(i) at base may at least partially overlap with the orthographic projection of the first reset control line RST1(i) at base. For example, the orthographic projection of the first initial signal line INIT1(i) at base may include the orthographic projection of the first reset control line RST1(i) at base. The orthographic projection of the second scan line GL2(i) at base may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) at base. For example, the orthographic projection of the second scan line GL2(i) at base may include the orthographic projection of the second scan auxiliary line GL2b(i) at base. The orthographic projection of the third initial signal line INIT3(i) at base may at least partially overlap with the orthographic projection of the light emission control line EML(i) at base. For example, the orthographic projection of the third initial signal line INIT3(i) at base may include the orthographic projection of the light emission control line EML(i) at base. The orthographic projection of the second initial signal line INIT2(i) on the base may at least partially overlap with the orthographic projection of the second reset control line RST2(i) on the base. For example, the orthographic projection of the second initial signal line INIT2(i) on the base may include the orthographic projection of the second reset control line RST2(i) on the base. In this example, by laminating the wiring of different conductive layers (e.g., the first conductive layer, the second conductive layer, and the third conductive layer), the occupancy of a large amount of wiring space can be avoided, contributing to the saving of wiring space and increasing the light transmittance of the first display area.

[0133] (7) A fifth insulating layer is formed. In some examples, a fifth insulating thin film is deposited on the base on which the above pattern is formed, and the fifth insulating thin film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may be called an interlayer insulating layer.

[0134] Figure 12 is a schematic diagram of one circuit island area after the formation of the fifth insulating layer in Figure 6. In some examples, as shown in Figure 12, multiple vias may be opened in the fifth insulating layer of the first indicated area, for example, including vias V1 to V24, vias V26 to V29, vias V31 to V44, vias V46 to V49, and vias V52 to V56.

[0135] In some examples, the fifth insulating layer, fourth insulating layer, third insulating layer, second insulating layer, and first insulating layer in vias V1 to V24 and V26 to V29 may be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and fourth insulating layer in vias V31 to V36 may be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, fourth insulating layer, third insulating layer, and second insulating layer in vias V37 to V39 may be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, fourth insulating layer, and third insulating layer in vias V40 to V44 may be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in vias 46 (V46) to 49 (V49) and 52 (V52) to 56 (V56) may be removed, exposing a portion of the surface of the third conductive layer.

[0136] (8) A fourth conductive layer is formed. In some examples, a fourth conductive thin film is deposited on the base on which the above pattern is formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may be referred to as the first source-drain metal layer.

[0137] Figure 13A is a schematic diagram of the first display area after the formation of the fourth conductive layer in Figure 6. Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. Figure 13C is a schematic diagram of one circuit island area in Figure 13A.

[0138] In some examples, as shown in Figures 13A to 13C, the fourth conductive layer of the first display area may include at least a number of connecting electrodes (e.g., including the first connecting electrode 401 to the 18th connecting electrode 418, and the 20th connecting electrode 420 to the 28th connecting electrode 428).

[0139] In some examples, the shape of the first connecting electrode 401 may be an elongated structure extending approximately along the second direction Y. One end of the first connecting electrode 401 may be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a via a first via V1, the other end may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via a 32 via V32, and the other end may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via a fourth via V4. The first connecting electrode 401 may be electrically connected to the second electrode of the first transistor 31a, the second electrode of the second transistor 32a, the second electrode of the third transistor 33a, and the first electrode of the sixth transistor 36a, and the first connecting electrode 401 may be the third node of the first pixel circuit 11a.

[0140] In some examples, the shape of the second connecting electrode 402 may be an elongated structure extending substantially along the second direction Y. One end of the second connecting electrode 402 may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via the 31st via V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a via the 37th via V37. The second connecting electrode 402 may be electrically connected to the first electrode of the second transistor 32a, the gate electrode of the third transistor 33a, and the first electrode 391a of the storage capacitor, and the second connecting electrode 402 may serve as the first node of the first pixel circuit 11a.

[0141] In some examples, the shape of the third connecting electrode 403 may be substantially rectangular. The third connecting electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a via the second via V2.

[0142] In some examples, the shape of the fourth connecting electrode 404 may be a bent shape extending approximately along the second direction Y. One end of the fourth connecting electrode 404 may be electrically connected to the third active layer 330a of the third transistor 33a of the first pixel circuit 11a via the third via V3, and the other end may be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a via the ninth via V9. The fourth connecting electrode 404 is electrically connected to the first electrode of the third transistor 33a, the second electrode of the fourth transistor 34a, the second electrode of the fifth transistor 35a, and the first electrode of the eighth transistor 38a, and the fourth connecting electrode 404 may be the second node of the first pixel circuit 11a.

[0143] In some examples, the shape of the fifth connecting electrode 405 may be an elongated structure extending approximately along the second direction Y. One end of the fifth connecting electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a via the fifth via V5, and the other end may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 40th via V40.

[0144] In some examples, the shape of the sixth connecting electrode 406 may be substantially rectangular. The sixth connecting electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via the sixth via V6.

[0145] In some examples, the shape of the seventh connecting electrode 407 may be approximately dumbbell-shaped. One end of the seventh connecting electrode 407 may be electrically connected to the seventh active layer 370a of the seventh transistor 37a of the first pixel circuit 11a via the seventh via V7, and the other end may be electrically connected to the second initial signal line INIT2(i) via the 52nd via V52.

[0146] In some examples, the shape of the eighth connecting electrode 408 may be a bent shape extending substantially along the second direction Y. One end of the eighth connecting electrode 408 may be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a via the eighth via V8, and the other end may be electrically connected to the third initial signal line INIT3(i) via the 47th via V47.

[0147] In some examples, the shape of the ninth connecting electrode 409 may be an elongated structure extending substantially along the first direction X. One end of the ninth connecting electrode 409 may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 41st via V41, and the other end may be electrically connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b via the 42nd via V42.

[0148] In some examples, the shape of the tenth connecting electrode 410 may be an arch shape extending substantially along the first direction X. The tenth connecting electrode 410 may be electrically connected at both ends to the first initial signal line INIT1(i) via the 55th via V55 and the 56th via V56, respectively, and at the other end may be electrically connected to the integrated structure of the first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b via the tenth via V10.

[0149] In some examples, the shape of the 11th connecting electrode 411 may be an elongated structure extending substantially along the second direction Y. The 11th connecting electrode 411 may have one end electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b via the 11th via V11, the other end electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 34th via V34, and electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b via the 14th via V14. The 11th connecting electrode 411 may be electrically connected to the second electrode of the first transistor 31b, the second electrode of the second transistor 32b, the second electrode of the third transistor 33b, and the first electrode of the sixth transistor 36b, and the 11th connecting electrode 411 may be the third node of the first pixel circuit 11b.

[0150] In some examples, the shape of the 12th connecting electrode 412 may be an elongated structure extending approximately along the second direction Y. One end of the 12th connecting electrode 412 may be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 33rd via V33, and the other end may be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b via the 38th via V38. The 12th connecting electrode 412 may be electrically connected to the first electrode of the second transistor 32b, the gate electrode of the third transistor 33b, and the first electrode 391b of the storage capacitor, and the 12th connecting electrode 412 may serve as the first node of the first pixel circuit 11b.

[0151] In some examples, the shape of the 13th connecting electrode 413 may be substantially rectangular. The 13th connecting electrode 413 may be electrically connected to the 4th active layer 340b of the 4th transistor 34b of the 1st pixel circuit 11b via the 12th via V12.

[0152] In some examples, the shape of the 14th connecting electrode 414 may be a bent shape extending substantially along the second direction Y. One end of the 14th connecting electrode 414 may be electrically connected to the third active layer 330b of the third transistor 33b of the first pixel circuit 11b via the 13th via V13, and the other end may be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b via the 19th via V19. The 14th connecting electrode 414 may be electrically connected to the first electrode of the third transistor 33b, the second electrode of the fourth transistor 34b, the second electrode of the fifth transistor 35b, and the first electrode of the eighth transistor 38b, and the 14th connecting electrode 414 may be the second node of the first pixel circuit 11b.

[0153] In some examples, the shape of the 15th connecting electrode 415 may be an elongated structure extending approximately along the second direction Y. One end of the 15th connecting electrode 415 may be electrically connected via the 15th via V15 to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c, and the other end may be electrically connected via the 43rd via V43 to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c.

[0154] In some examples, the shape of the 16th connecting electrode 416 may be substantially rectangular. The 16th connecting electrode 416 may be electrically connected to the 6th active layer 360b of the 6th transistor 36b of the 1st pixel circuit 11b via the 16th via V16.

[0155] In some examples, the shape of the 17th connecting electrode 417 may be approximately dumbbell-shaped. The 17th connecting electrode 417 may have one end electrically connected to the 7th active layer 370b of the 7th transistor 37b of the 1st pixel circuit 11b via the 17th via V17, and the other end electrically connected to the 2nd initial signal line INIT2(i) via the 53rd via V53.

[0156] In some examples, the shape of the 18th connecting electrode 418 may be a bent shape extending substantially along the second direction Y. One end of the 18th connecting electrode 418 may be electrically connected to the 8th active layer 380b of the 8th transistor 38b of the first pixel circuit 11b via the 18th via V18, and the other end may be electrically connected to the 3rd initial signal line INIT3(i) via the 48th via V48.

[0157] In some examples, the shape of the 20th connecting electrode 420 may be a bent shape extending substantially along the first direction X. The 20th connecting electrode 420 may have one end electrically connected to the first active layer 310c of the first transistor 31c of the first pixel circuit 11c via a 20th via V20, and the other end electrically connected to the first initial signal line INIT1(i) via a 46th via V46.

[0158] In some examples, the shape of the 21st connecting electrode 421 may be an elongated structure extending approximately along the second direction Y. The 21st connecting electrode 421 may have one end electrically connected to the first active layer 310c of the first transistor 31c of the first pixel circuit 11c via the 21st via V21, the other end electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 36th via V36, and the 24th via V24 to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c. The 21st connecting electrode 421 may be electrically connected to the second electrode of the first transistor 31c, the second electrode of the second transistor 32c, the second electrode of the third transistor 33c, and the first electrode of the sixth transistor 36c, and the 21st connecting electrode 421 may also serve as the third node of the first pixel circuit 11c.

[0159] In some examples, the shape of the 22nd connecting electrode 422 may be an elongated structure extending approximately along the second direction Y. One end of the 22nd connecting electrode 422 may be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 35th via V35, and the other end may be electrically connected to the first electrode 391c of the storage capacitor of the first pixel circuit 11c via the 39th via V39. The 22nd connecting electrode 422 may be electrically connected to the first electrode of the second transistor 32c, the gate electrode of the third transistor 33c, and the first electrode 391c of the storage capacitor, and the 22nd connecting electrode 422 may also serve as the first node of the first pixel circuit 11c.

[0160] In some examples, the shape of the 23rd connecting electrode 423 may be approximately rectangular. The 23rd connecting electrode 423 may be electrically connected to the 4th active layer 340c of the 4th transistor 34c of the 1st pixel circuit 11c via the 22nd via V22.

[0161] In some examples, the shape of the 24th connecting electrode 424 may be a bent shape extending approximately along the second direction Y. One end of the 24th connecting electrode 424 may be electrically connected to the third active layer 330c of the third transistor 33c of the first pixel circuit 11c via the 23rd via V23, and the other end may be electrically connected to the eighth active layer 380c of the eighth transistor 38c of the first pixel circuit 11c via the 29th via V29. The 24th connecting electrode 424 is electrically connected to the first electrode of the third transistor 33c, the second electrode of the fourth transistor 34c, the second electrode of the fifth transistor 35c, and the first electrode of the eighth transistor 38c, and the 24th connecting electrode 424 may also serve as the second node of the first pixel circuit 11c.

[0162] In some examples, the shape of the 25th connecting electrode 425 may be an elongated structure extending substantially along the first direction X. The 25th connecting electrode 425 may be electrically connected to the second electrode 392c of the storage capacitor of the first pixel circuit 11c via the 44th via V44.

[0163] In some examples, the shape of the 26th connecting electrode 426 may be substantially rectangular. The 26th connecting electrode 426 may be electrically connected to the 6th active layer 360c of the 6th transistor 36c of the 1st pixel circuit 11c via the 26th via V26.

[0164] In some examples, the shape of the 27th connecting electrode 427 may be approximately dumbbell-shaped. The 27th connecting electrode 427 may be electrically connected at one end to the 7th active layer 370c of the 7th transistor 37c of the 1st pixel circuit 11c via the 27th via V27, and at the other end to the 2nd initial signal line INIT2(i) via the 54th via V54.

[0165] In some examples, the shape of the 28th connecting electrode 428 may be a bent shape extending substantially along the second direction Y. One end of the 28th connecting electrode 428 may be electrically connected to the 8th active layer 380c of the 8th transistor 38c of the first pixel circuit 11c via the 28th via V28, and the other end may be electrically connected to the 3rd initial signal line INIT3(i) via the 49th via V49.

[0166] In some examples, in a circuit island area, the first pixel circuits 11a and 11b may be approximately symmetric with respect to the first median O1, and the first pixel circuits 11b and 11c may be approximately symmetric with respect to the second median O2. Any two adjacent first pixel circuits in the circuit island area of ​​this example may be installed approximately symmetrically with respect to their respective medians, thereby contributing to saving the space occupied by the circuits.

[0167] In some examples, the first pixel circuits in a row of circuit island areas arranged along a first direction X may be aligned in the first direction X, while the first pixel circuits in a column of circuit island areas arranged along a second direction Y may be offset in the second direction Y. For example, the space between two adjacent circuit island areas in a row of circuit island areas may be aligned in the second direction Y with the second first pixel circuit of one circuit island area in the next row of circuit island areas. This example shows three circuit island areas in column m, row i, column m+2, row i, and column m+1, row i+1, as well as the third first pixel circuit in the column m-1, row i+1 circuit island area and the first first pixel circuit in the column m+1, row i+1 circuit island area.

[0168] (9) Form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating film is deposited on the base on which the above pattern is formed, then the seventh insulating film is applied, and the seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may be called a passivation layer, and the seventh insulating layer may be called a first flat layer.

[0169] Figure 14 is a schematic diagram of one circuit island area after the formation of the seventh insulating layer in Figure 6. In some examples, as shown in Figure 14, multiple vias may be opened in the seventh insulating layer of the first indicated area, for example, including via 61 to via 68. The seventh and sixth insulating layers within vias 61 to via 68 may be removed to expose a portion of the surface of the fourth conductive layer.

[0170] (10) A fifth conductive layer is formed. In some examples, a fifth conductive thin film is deposited on the base on which the above pattern is formed, and the fifth conductive thin film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may be referred to as the second source-drain metal layer.

[0171] Figure 15A is a schematic diagram of the first display area after the formation of the fifth conductive layer in Figure 6. Figure 15B is a schematic diagram of the fifth conductive layer in Figure 15A. Figure 15C is a schematic diagram of one circuit island area in Figure 15A.

[0172] In some examples, as shown in Figures 15A to 15C, the fifth conductive layer of the first display area may include at least several data lines (e.g., data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), several first anode connection electrodes (e.g., first anode connection electrodes 451a, 451b, 451c), several first shield electrodes (e.g., first shield electrodes 511a, 511b, 511c), and several first power connection lines (e.g., first power connection lines 512a, 512b, 512c).

[0173] In some examples, multiple data lines may be bent in shape, extending approximately along the second direction Y. Data lines DL(j) and DL(j+1) may be adjacent, and data lines (j+2) and DL(j+3) may be adjacent. Data line DL(j+1) may be electrically connected to the third connection electrode 403 via the 61st via V61 to realize an electrical connection with the first electrode of the fourth transistor 34a of the first pixel circuit 11a. Data line DL(j+2) may be electrically connected to the 13th connection electrode 413 via the 64th via V64 to realize an electrical connection with the first electrode of the fourth transistor 34b of the first pixel circuit 11b. Data line DL(j+3) may be electrically connected to the 23rd connection electrode 423 via the 66th via V66 to realize an electrical connection with the first electrode of the fourth transistor 34c of the first pixel circuit 11c.

[0174] In some examples, four data lines may be drilled into each circuit island area, and three of these four data lines may be electrically connected to three first pixel circuits in the circuit island area. The four data lines DL(j), DL(j+1), DL(j+2), and DL(j+3) may pass through the i-th row, m-th column circuit island area, and three of these data lines DL(j+1), DL(j+2), and DL(j+3) may be electrically connected to three first pixel circuits in the i-th row, m-th column circuit island area. The four data lines DL(j+4), DL(j+5), DL(j+6), and DL(j+7) may pass through the i-th row, m+2-column circuit island area, and three of these data lines DL(j+5), DL(j+6), and DL(j+7) may be electrically connected to three first pixel circuits in the i-th row, m+2-column circuit island area. The four data lines DL(j+2), DL(j+3), DL(j+4), and DL(j+5) may pass through the circuit island area in row i+1 and column m+1, and three of these data lines, DL(j+3), DL(j+4), and DL(j+5), may be electrically connected to three first pixel circuits in the circuit island area in row i+1 and column m+1, respectively. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) may be configured to provide data signals to a first pixel circuit (e.g., first pixel circuit 11b) connected to a first light-emitting element that emits a third color of light. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) may be configured to provide data signals to a plurality of first pixel circuits that are arranged in rows. For example, data lines DL(j) and DL(j+4) are not electrically connected to the first pixel circuit in the i-th row circuit island area, but are electrically connected to the first pixel circuit in the i+1-th row circuit island area. Data lines DL(j+2) and DL(j+6) are electrically connected to the first pixel circuit in the i-th row circuit island area, but are not electrically connected to the first pixel circuit in the i+1-th row circuit island area. In this example, the data lines that provide data signals to the first pixel circuit (e.g., the first pixel circuit 11b) connected to the first light-emitting element that emits a third color of light are electrically connected to multiple first pixel circuits arranged in rows, and provide data signals to multiple first pixel circuits arranged in rows.The data line installation method in this example contributes to the wiring layout.

[0175] In some examples, the shapes of the first shield electrodes 511a, 511b, and 511c may be irregular polygons. The first shield electrodes 511a and 511b may be substantially symmetric with respect to the first midline O1, and the first shield electrodes 511b and 511c may be substantially symmetric with respect to the second midline O2. The first shield electrodes 511a and 511b may be an integrated structure connected to each other. The first shield electrodes 511a and 511b may be located between the data lines DL(j+1) and DL(j+2). The integrated structure of the first shield electrodes 511a and 511b may be electrically connected to the ninth connecting electrode 409 via the 63rd via V63 to realize an electrical connection with the second electrode of the storage capacitor of the first pixel circuits 11b and 11c. The first shield electrode 511c may be located on the side of the data line DL(j+3) away from the data line DL(j+2). The first shield electrode 511c may be electrically connected to the 25th connecting electrode 425 via the 68th via V68 to achieve an electrical connection with the second electrode of the storage capacitor of the first pixel circuit 11c.

[0176] In some examples, the orthographic projection at the base of the first shield electrode 511a may cover the orthographic projection at the base of the second connecting electrode 402, thereby achieving shielding for the first node of the first pixel circuit 11a. The orthographic projection at the base of the first shield electrode 511b may cover the orthographic projection at the base of the twelfth connecting electrode 412, thereby achieving shielding for the first node of the first pixel circuit 11b. The orthographic projection at the base of the first shield electrode 511c may cover the orthographic projection at the base of the 22nd connecting electrode 422, thereby achieving shielding for the first node of the first pixel circuit 11c. This prevents the remaining signals from influencing the first nodes of the first pixel circuits 11a, 11b, and 11c.

[0177] In some examples, the orthographic projection at the base of the first shield electrode 511a may cover the orthographic projection at the base of the first connection electrode 401, thereby achieving shielding for the third node of the first pixel circuit 11a. The orthographic projection at the base of the first shield electrode 511b may cover the orthographic projection at the base of the eleventh connection electrode 411, thereby achieving shielding for the third node of the first pixel circuit 11b. The orthographic projection at the base of the first shield electrode 511c may cover the orthographic projection at the base of the twentieth connection electrode 421, thereby achieving shielding for the thirteenth node of the first pixel circuit 11c. This prevents the remaining signals from influencing the third nodes of the first pixel circuits 11a, 11b, and 11c.

[0178] In some examples, the first shield electrodes of adjacent circuit island areas may be electrically connected via first power supply lines. The shape of the first power supply lines 512a, 512b, and 512c may all be bent lines extending substantially along the second direction Y. The first power supply line 512a may be located on the side away from the data line DL(j+3) of the first shield electrode 511c. The first power supply line 512a may be connected to the first shield electrode 511b in an adjacent circuit island area in the same column. For example, one end of a first power supply line 512a may be connected to the first shield electrode 511b in the circuit island area of ​​row i-1, column m+1, and after bypassing one side of the first shield electrode 511c in the circuit island area of ​​row i, column m, the other end may be connected to the first shield electrode 511b in the circuit island area of ​​row i+1, column m+1. The first power supply connection line 512a and the first shield electrode 511b to which it is connected may be integrated into a single structure that connects them to each other.

[0179] In some examples, the first power supply connection line 512b may connect the first shield electrode 511a in one circuit island area (for example, the circuit island area in row i and column m) to the first shield electrode 511c in the circuit island area in the leftmost column of the adjacent row (for example, the circuit island area in row i+1 and column m-1). The first power supply connection line 512a and the first shield electrode to be connected may be an integrated structure connected to each other.

[0180] In some examples, the first power supply connection line 512c may connect the first shield electrode 511c in one circuit island area (for example, the circuit island area in row i and column m) to the first shield electrode 511a in the circuit island area in the rightmost column of the adjacent row (for example, the circuit island area in row i+1 and column m+1). The first power supply connection line 512c and the first shield electrode to be connected may be an integrated structure connected to each other.

[0181] In this example, the connection between the first shield electrode and the first power supply connection line enables transport of the first voltage signal along the second direction Y, and the connection between the second electrode of the storage capacitor of the first pixel circuit and the connection electrode enables transport of the first voltage signal along the first direction X.

[0182] In some examples, the shapes of the first anode connection electrodes 451a, 451b, and 451c may be approximately rectangular. The first anode connection electrode 451a may be located between the first power connection lines 512a and 512b, and the first anode connection electrode 451b may be located between the first power connection line 512a and the data line DL(j+2). The first anode connection electrode 451c may be located between the data line DL(j+3) and the first power connection line 512c.

[0183] In some examples, the first anode connection electrode 451a may be electrically connected to the sixth connection electrode 406 via the 62nd via V62 to realize an electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b may be electrically connected to the 16th connection electrode 416 via the 65th via V65 to realize an electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c may be electrically connected to the 26th connection electrode 426 via the 67th via V67 to realize an electrical connection with the sixth transistor of the first pixel circuit 11c.

[0184] (11) A 8th insulating layer is formed. In some examples, the 8th insulating layer is applied to the base on which the above pattern is formed, and the 8th insulating layer is patterned by a patterning process to form the 8th insulating layer. In some examples, the 8th insulating layer may be referred to as the 2nd flat layer.

[0185] Figure 16 is a schematic diagram of one circuit island area after the formation of the eighth insulating layer in Figure 6. In some examples, as shown in Figure 16, multiple vias may be opened in the eighth insulating layer of the first indicated area, for example, including via 71 to via 73. The eighth insulating layer within vias 71 to 73 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0186] (12) A sixth conductive layer is formed. In some examples, a sixth conductive thin film is deposited on the base on which the above pattern is formed, and the sixth conductive thin film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may be referred to as the third source-drain metal layer.

[0187] Figure 17A is a schematic diagram of the first display area after the formation of the sixth conductive layer in Figure 6. Figure 17B is a schematic diagram of the sixth conductive layer in Figure 17A.

[0188] In some examples, as shown in Figures 17A and 17B, the sixth conductive layer of the first display area may include at least a plurality of auxiliary electrodes (e.g., including auxiliary electrodes 461a, 461b, 461c, and 461d), a plurality of auxiliary connection bars (e.g., including auxiliary connection bars 462a, 462b, 462c, 462d, and 462f), a plurality of second anode connection electrodes (e.g., second anode connection electrodes 452a, 452b, 452c, and 452d), and a plurality of anode connection bars 453.

[0189] In some examples, the shapes of the second anode connection electrodes 452a, 452b, 452c, and 452d may all be approximately rectangular. The second anode connection electrode 452a may be electrically connected to the first anode connection electrode 451a via the 71st via V71 to realize an electrical connection with the sixth transistor of the first pixel circuit 11a. The second anode connection electrode 452c may be electrically connected to the first anode connection electrode 451c via the 73rd via V73 to realize an electrical connection with the sixth transistor of the first pixel circuit 11c. The second anode connection electrode 452b may be electrically connected to the first anode connection electrode 451b via the 72nd via V72 to realize an electrical connection with the sixth transistor of the first pixel circuit 11b.

[0190] In some examples, the second anode connection electrode 452b may be electrically connected to the second anode connection electrode 452d via the anode connection bar 453. The second anode connection electrodes 452b, 452d and the anode connection bar 453 may be an integrated structure connected to each other. The second anode connection electrode 452d connected to the second anode connection electrode 452b in the circuit island area of ​​row i and column m may be located in the circuit island area of ​​row i+1 and column m+1. The anode connection bar 453 may be a roughly L-shaped bent wire.

[0191] In some examples, the shapes of the auxiliary electrodes 461a, 461b, 461c, and 461d may be approximately circular or elliptical. The auxiliary electrode 461a may be located below the anode of the first light-emitting element 13a, the auxiliary electrode 461b may be located below the anode of the first light-emitting element 13b, the auxiliary electrode 461c may be located below the anode of the first light-emitting element 13c, and the auxiliary electrode 461d may be located below the anode of the first light-emitting element 13d. The auxiliary electrodes exert a planarizing effect on the anode, ensuring the flatness of the surface on the side of the anode closer to the base, reducing color shift due to irregularities in the anode, and blocking the influence of the lower pixel circuit on the anode.

[0192] In some examples, adjacent auxiliary electrodes may be connected via auxiliary connection bars. The shape of the auxiliary connection bar 462a may be a long, cross-shaped bar extending approximately along a first direction X and a second direction Y. The auxiliary connection bar 462a is located in the circuit island area, and its four ends may be connected to four auxiliary electrodes 461a, 461b, 461c, and 461d, respectively. Each of the auxiliary connection bars 462b, 462c, 462d, and 462f may be a long, elongated structure extending along one direction. The auxiliary connection bars 462b, 462c, 462d, and 462f may be located in the spacing between adjacent circuit island areas in a row of circuit island areas. Auxiliary connection bar 462b may connect adjacent auxiliary electrodes 461c and 461d, auxiliary connection bar 462c may connect adjacent auxiliary electrodes 461c and 461b, auxiliary connection bar 462d may connect adjacent auxiliary electrodes 461b and 461a, and auxiliary connection bar 462f may connect adjacent auxiliary electrodes 461a and 461d. In the spacing region between adjacent circuit island areas, the four auxiliary connection bars 462b, 462c, 462d, and 462f, and the four auxiliary electrodes 461a, 461b, 461c, and 461d may be connected sequentially to form a grid.

[0193] In some examples, multiple auxiliary electrodes and multiple auxiliary connection blocks are electrically connected to form a mesh structure. Multiple auxiliary electrodes and multiple auxiliary connection blocks may also be integrated structures that are connected to each other. The integrated structure of auxiliary electrodes and auxiliary connection blocks is electrically connected to a first power supply connection line located in the fifth conductive layer in the surrounding area (or second display area) to realize the transport of a first voltage signal and to equalize the first voltage signal in the first display area. However, this embodiment is not limited to this. In other examples, the integrated structure of auxiliary electrodes and auxiliary connection blocks can be electrically connected to a first power supply connection line or a first shield electrode located in the fifth conductive layer via vias opened in the eighth insulating layer of the first display area to realize the transport of a first voltage signal.

[0194] (13) Form the ninth insulating layer and the tenth insulating layer. In some examples, the ninth insulating layer is applied to the base on which the above pattern is formed, and the ninth insulating layer is patterned by a patterning process to form the ninth insulating layer. Then, the tenth insulating layer is applied to the base on which the above pattern is formed, and the tenth insulating layer is patterned by a patterning process to form the tenth insulating layer. In some examples, the ninth insulating layer may be referred to as the third flat layer, and the tenth insulating layer may be referred to as the fourth flat layer.

[0195] Figure 18 is a schematic diagram of the first display area after the formation of the tenth insulating layer in Figure 6. In some examples, as shown in Figure 18, multiple vias may be formed in the tenth insulating layer of the first display area, for example, including vias 81 V81 to 84 V84. The tenth insulating layer and the ninth insulating layer within vias 81 V81 to 84 V84 may be removed to expose a portion of the surface of the sixth conductive layer.

[0196] The manufacturing of the circuit structure layer is now complete. The film layer structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be explained again here.

[0197] In this example, the flatness of the anode layer can be further ensured by installing the ninth and tenth insulating layers.

[0198] (14) A light-emitting structure layer is formed. In some examples, an anode thin film is deposited on a base on which the above pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer.

[0199] Figure 19A is a schematic diagram of the first display area after the anode layer is formed in Figure 6. Figure 19B is a schematic diagram of the anode layer in Figure 19A. In some examples, as shown in Figures 19A and 19B, the anode layer of the first display area may include at least anodes of a plurality of first light-emitting elements (e.g., including anode 131a of the first light-emitting element 13a, anode 131b of the first light-emitting element 13b, anode 131c of the first light-emitting element 13c, and anode 131d of the first light-emitting element 13d), and a plurality of third anode connecting electrodes (e.g., including third anode connecting electrodes 132a, 132b, 132c, and 132d).

[0200] In some examples, the shapes of the anodes 131a, 131b, 131c, and 131d may be approximately circular or elliptical. The shapes of the third anode connecting electrodes 132a, 132b, 132c, and 132d may be approximately rectangular. The anode 131a and the third anode connecting electrode 132a may be an integrated structure connected to each other. The third anode connecting electrode 132a may be electrically connected to the second anode connecting electrode 452a via the 81st via V81 to realize an electrical connection with the first pixel circuit 11a. The anode 131b and the third anode connecting electrode 132b may be an integrated structure connected to each other. The third anode connecting electrode 132b may be electrically connected to the second anode connecting electrode 452b via the 82nd via V82 to realize an electrical connection with the first pixel circuit 11b. The anode 131c and the third anode connecting electrode 132c may be an integrated structure connected to each other. The third anode connection electrode 132c may be electrically connected to the second anode connection electrode 452c via the 83rd via V83 to achieve electrical connection with the first pixel circuit 11c. The anode 131d and the third anode connection electrode 132d may be an integrated structure connected to each other. The third anode connection electrode 132d may be electrically connected to the second anode connection electrode 452d via the 84th via V84. Since the second anode connection electrodes 452d and 452b are an integrated structure, they achieve electrical connection between the third anode connection electrode 132d and the first pixel circuit 11b.

[0201] In some examples, the orthographic projection of anode 131a at the base may include the orthographic projection of auxiliary electrode 461a at the base. The orthographic projection of anode 131b at the base may include the orthographic projection of auxiliary electrode 461b at the base. The orthographic projection of anode 131c at the base may include the orthographic projection of auxiliary electrode 461c at the base. The orthographic projection of anode 131d at the base may include the orthographic projection of auxiliary electrode 461d at the base. In this example, by placing the auxiliary electrode below the anode, not only can the flatness of the anode be ensured, but the influence of the pixel circuit on the anode layer can also be blocked. However, this embodiment is not limited to this. In other examples, the orthographic projection of the auxiliary electrode at the base may overlap with the orthographic projection of the corresponding anode at the base.

[0202] Figure 20 is a schematic diagram of the stacking of the first semiconductor layer, the sixth conductive layer, and the anode layer in Figure 6. In some examples, as shown in Figure 20, the orthographic projection of the anode 131b of the first light-emitting element 13b on the base may partially overlap with the orthographic projection of the seventh active layer of the seventh transistor (i.e., the second reset transistor) and the eighth active layer of the eighth transistor (i.e., the third reset transistor) of the connected first pixel circuit 11b. The orthographic projection of the anode 131d of the first light-emitting element 13d on the base may not overlap with the orthographic projection of the base of the connected first pixel circuit 11b. The orthographic projection of the anode 131d of the first light-emitting element 13d on the base may partially overlap with the orthographic projection of the integrated structure of the first active layer of the first transistor (i.e., the first reset transistor) of the two first pixel circuits on the base.

[0203] In some examples, a pixel definition thin film is applied to a base on which the above pattern is formed, and a pixel definition layer is formed by the processes of masking, exposure, and development. Multiple pixel apertures that expose the anode layer may be formed in the pixel definition layer (as shown in Figure 6). An organic light-emitting layer is formed within the formed pixel apertures, and the organic light-emitting layer is connected to the anode layer. Then, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.

[0204] In some examples, a sealing structure layer may be formed on the cathode after the light-emitting structure layer has been manufactured. In some examples, the sealing structure layer may include a first sealing layer, a second sealing layer, and a third sealing layer which are stacked together. The first and third sealing layers may be made of inorganic materials, the second sealing layer may be made of organic materials, and the second sealing layer may be placed between the first and third sealing layers, forming a stacked structure of inorganic material / organic material / inorganic material that prevents external water vapor from entering the light-emitting structure layer. In some possible realizations, the display substrate may include other film layers, such as a touch structure layer, a color filter layer, etc., and this embodiment is not limited to these.

[0205] In some examples, the first, second, third, fourth, fifth, and sixth conductive layers may be made of metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth insulating layers may be made of one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and may be a single layer, multi-layer structure, or composite layer. The seventh, eighth, ninth, and tenth insulating layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode may be made of a transparent conductive material. However, this embodiment is not limited to these materials.

[0206] The structure of the display board and its manufacturing process in this embodiment are merely illustrative descriptions. In some exemplary embodiments, the structure can be modified or the patterning process can be increased or decreased according to actual demand. The manufacturing process according to this exemplary embodiment can be implemented using currently mature manufacturing equipment, is highly compatible with conventional manufacturing processes, is easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0207] In this example, the display board reduces the number of first pixel circuits in the first display area, employs a one-to-two drive design for the first light-emitting element that emits the third color of light (i.e., one first pixel circuit simultaneously drives two first light-emitting elements that emit the third color of light), and employs a wiring design that avoids light-transmitting areas in the spacing region between adjacent circuit island areas. This contributes to improving the light transmittance of the first display area, ensuring the emission white balance of the first display area, and supporting the improvement of PPI in the first display area.

[0208] Figure 21 is a schematic top view of another local area of ​​the circuit structure layer of the first display area according to at least one embodiment of the present disclosure. Figure 21 shows as an example a portion of the structure in a 2x5 circuit island area (the i-th and i+1-th rows, the m-th to m+2-th columns, and the m-1-th and m+3-th columns). The number and order of film layers of the display substrate in this example are the same as those in the above embodiment. For the manufacturing process of the display substrate in this example, refer to the description of the above embodiment. Compared to the above embodiment, in this example the reset transistors (including the first, seventh, and eighth transistors) of the three first pixel circuits in the circuit island area are disassembled and reassembled. Similar structures between the display substrate in this example and the display substrate in the above embodiment are omitted or briefly described, and refer to the description of the above embodiment.

[0209] Figure 22A is a schematic diagram of the first display area after the formation of the first semiconductor layer in Figure 21. Figure 22B is a schematic diagram of one circuit island area in Figure 22A. In some examples, as shown in Figures 22A and 22B, the first semiconductor layer of the first display area may include active layers of at least several first pixel circuits and several first type transistors. The first, seventh, and eighth transistors of three first pixel circuits in one circuit island area were disassembled and reassembled. The first active layer 310a of the first pixel circuit 11a, the first active layer 310b of the first pixel circuit 11b, and the first active layer 310c of the first pixel circuit 11c may be an integrated structure connected to each other, the orthographic projection of the integrated structure on the base may be a substantially comb-like structure, and the integrated structure may be located on the side of the third active layers 330a and 330b in the second direction Y.

[0210] In some examples, the seventh active layer 370a of the first pixel circuit 11a, the seventh active layer 370b of the first pixel circuit 11b, and the seventh active layer 370c of the first pixel circuit 11c may be an integrated structure connected to each other, and the orthographic projection of the base of the integrated structure may be a substantially comb-like structure. The integrated structure of three seventh active layers in the i-th row, m-th column circuit island area may be adjacent to the integrated structure of three first active layers in the i+1-th row, m+1-column circuit island area. The comb teeth of the integrated structure of three seventh active layers in the i-th row, m-column circuit island area are positioned in the opposite direction to the comb teeth of the integrated structure of three first active layers in the i+1-th row, m+1-column circuit island area.

[0211] In some examples, the eighth active layer 380a of the first pixel circuit 11a, the eighth active layer 380b of the first pixel circuit 11b, and the eighth active layer 380c of the first pixel circuit 11c may be an integrated structure connected to each other, and this integrated structure may be located on the side opposite to the first direction X of the integrated structure of the three seventh active layers. The integrated structure of the three seventh active layers in the circuit island area may be located in the spacing region between adjacent circuit island areas.

[0212] In some examples, the third active layer 330b, fourth active layer 340b, fifth active layer 350b, and sixth active layer 360b of the first pixel circuit 11b and the third active layer 330c, fourth active layer 340c, fifth active layer 350c, and sixth active layer 360c of the first pixel circuit 11c may be an integrated structure connected to each other, and the fifth active layers 350b and 350c may be directly connected.

[0213] In some examples, the third active layer 330b, fourth active layer 340b, fifth active layer 350b, and sixth active layer 360b of the first pixel circuit 11a may be approximately symmetric with respect to the first median O1 with respect to the third active layer 330b, fourth active layer 340b, fifth active layer 350b, and sixth active layer 360b of the first pixel circuit 11b. The third active layer 330b, fourth active layer 340b, fifth active layer 350b, and sixth active layer 360b of the first pixel circuit 11b may be approximately symmetric with respect to the second median O2 with respect to the third active layer 330c, fourth active layer 340c, fifth active layer 350c, and sixth active layer 360c of the first pixel circuit 11c.

[0214] Figure 23A is a schematic diagram of the first display area after the formation of the first conductive layer in Figure 21. Figure 23B is a schematic diagram of one circuit island area in Figure 23A. In some examples, as shown in Figures 23A and 23B, the first conductive layer of the first display area may include at least a plurality of first scan lines (e.g., including first scan lines GL1(i), GL1(i+1)), a plurality of light emission control lines (e.g., including light emission control lines EML(i), EML(i+1)), a plurality of first reset control lines (e.g., including first reset control lines RST1(i), RST1(i+1)), a plurality of second reset control lines (e.g., including second reset control lines RST2(i), RST2(i+1)), and first electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including first electrodes 391a, 391b, 391c). The shape of the light emission control line may be a straight line extending approximately along the first direction X, and the shapes of the first scan line, the first reset control line, and the second reset control line may be a bent line extending approximately along the first direction X.

[0215] Figure 24A is a schematic diagram of the first display area after the formation of the second conductive layer in Figure 21. Figure 24B is a schematic diagram of one circuit island area in Figure 24A. In some examples, as shown in Figures 24A and 24B, the second conductive layer of the first display area may include at least a plurality of second scanning guide lines (e.g., including second scanning guide lines GL2b(i), GL2b(i+1)), second electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including second electrodes 392a, 392b, 392c), and a first connecting line 393. The shape of the first connecting line 393 may be an elongated structure extending along a first direction X. The first connecting line 393 may be configured to provide an electrical connection between the sixth transistor and the seventh transistor of the first pixel circuit 11a.

[0216] Figure 25A is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 21. Figure 25B is a schematic diagram of one circuit island area in Figure 25A. In some examples, as shown in Figures 25A and 25B, the second semiconductor layer of the first display area may include active layers of at least several first pixel circuits of a second type of transistor (e.g., the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c). In the circuit island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetric with respect to the first median O1, and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric with respect to the second median O2.

[0217] Figure 26A is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 21. Figure 26B is a schematic diagram of one circuit island area in Figure 26A. In some examples, as shown in Figures 26A and 26B, the third conductive layer of the first display area may include at least a plurality of second scan lines (e.g., including second scan lines GL2(i), GL2(i+1)), a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(i), INIT1(i+1)), a plurality of second initial signal lines (e.g., including second initial signal lines INIT2(i), INIT2(i+1)), and a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(i), INIT3(i+1)). The shapes of the first initial signal lines, second scan lines, and second initial signal lines may each be bent lines extending approximately along a first direction X. The shape of the third initial signal line may be a straight line extending approximately along the first direction X.

[0218] Figure 27 is a schematic diagram of one circuit island area after the formation of the fifth insulating layer in Figure 21. In some examples, as shown in Figure 27, multiple vias may be opened in the fifth insulating layer of the first indicated area, for example, including vias V2 to V6, V12 to V16, V22 to V25, V31 to V45, V47 to V50, and V103 to V104.

[0219] In some examples, the fifth insulating layer, fourth insulating layer, third insulating layer, second insulating layer, and first insulating layer in vias V2 to V6, V12 to V16, V22 to V25, and V91 to V102 may be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and fourth insulating layer in vias V31 to V36 may be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, fourth insulating layer, third insulating layer, and second insulating layer in vias V37 to V39 may be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in vias 40 V40 to 44 V44 and 103 V103 to 104 V104 may be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in vias 45 V45 and 47 V47 to 50 V50 may be removed to expose a portion of the surface of the third conductive layer.

[0220] Figure 28A is a schematic diagram of the first display area after the formation of the fourth conductive layer in Figure 21. Figure 28B is a schematic diagram of the fourth conductive layer in Figure 28A. Figure 28C is a schematic diagram of one circuit island area in Figure 28A.

[0221] In some examples, as shown in Figures 28A to 28C, the fourth conductive layer of the first display area may include at least a number of connecting electrodes (for example, including the first to sixth connecting electrodes 401 to 406, the ninth connecting electrode 409, the eleventh to sixteenth connecting electrodes 411 to 416, the twentieth connecting electrodes 421 to 26th connecting electrodes 426, and the thirty-first to thirty-seventh connecting electrodes 431 to 37th connecting electrodes 437).

[0222] In some examples, the shape of the first connecting electrode 401 may be a bent shape extending substantially along the second direction Y. The first connecting electrode 401 may have one end electrically connected to the first active layer 310a via the 92nd via V92, and the other end may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via the 32nd via V32, and electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via the fourth via V4.

[0223] In some examples, the shape of the second connecting electrode 402 may be an elongated structure extending substantially along the second direction Y. One end of the second connecting electrode 402 may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via the 31st via V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a via the 37th via V37.

[0224] In some examples, the shape of the third connecting electrode 403 may be substantially rectangular. The third connecting electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a via the second via V2.

[0225] In some examples, the shape of the fourth connecting electrode 404 may be a bent shape extending substantially along the second direction Y. One end of the fourth connecting electrode 404 may be electrically connected to the third active layer 330a of the third transistor 33a of the first pixel circuit 11a via the third via V3, and the other end may be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a via the 95th via V95.

[0226] In some examples, the shape of the fifth connecting electrode 405 may be an elongated structure extending approximately along the second direction Y. One end of the fifth connecting electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a via the fifth via V5, and the other end may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 40th via V40.

[0227] In some examples, the shape of the sixth connecting electrode 406 may be approximately rectangular. The sixth connecting electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via the sixth via V6, or it may be electrically connected to one end of the first connecting line 393 via the 103rd via V103. The other end of the first connecting line 393 may be electrically connected to the 35th connecting electrode 435 via the 104th via V104, and the 35th connecting electrode 435 may be electrically connected to the seventh active layer 370b via the 100th via V100. In this example, the sixth connecting electrode 406, the first connecting line 393, and the 35th connecting electrode 435 enable the connection between the sixth transistor and the seventh transistor of the first pixel circuit 11a.

[0228] In some examples, the shape of the ninth connecting electrode 409 may be an elongated structure extending substantially along the first direction X. One end of the ninth connecting electrode 409 may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 41st via V41, and the other end may be electrically connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b via the 42nd via V42.

[0229] In some examples, the shape of the 11th connecting electrode 411 may be a bent shape extending substantially along the second direction Y. The 11th connecting electrode 411 may have one end electrically connected to the first active layer 310b of the first pixel circuit 11b via the 93rd via V93, the other end electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 34th via V34, and electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b via the 14th via V14.

[0230] In some examples, the shape of the 12th connecting electrode 412 may be an elongated structure extending substantially along the second direction Y. One end of the 12th connecting electrode 412 may be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 33rd via V33, and the other end may be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b via the 38th via V38.

[0231] In some examples, the shape of the 13th connecting electrode 413 may be substantially rectangular. The 13th connecting electrode 413 may be electrically connected to the 4th active layer 340b of the 4th transistor 34b of the 1st pixel circuit 11b via the 12th via V12.

[0232] In some examples, the shape of the 14th connecting electrode 414 may be a bent shape extending substantially along the second direction Y. One end of the 14th connecting electrode 414 may be electrically connected to the third active layer 330b of the third transistor 33b of the first pixel circuit 11b via the 13th via V13, and the other end may be electrically connected to the eighth active layer 380b of the first pixel circuit 11b via the 97th via V97.

[0233] In some examples, the shape of the 15th connecting electrode 415 may be an elongated structure extending approximately along the second direction Y. One end of the 15th connecting electrode 415 may be electrically connected via the 15th via V15 to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c, and the other end may be electrically connected via the 43rd via V43 to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c.

[0234] In some examples, the shape of the 16th connecting electrode 416 may be substantially rectangular. The 16th connecting electrode 416 may be electrically connected to the 6th active layer 360b of the 6th transistor 36b of the 1st pixel circuit 11b via the 16th via V16. The 16th connecting electrode 416 and the 34th connecting electrode 434 may be an integrated structure connected to each other. The 34th connecting electrode 434 may be an elongated structure extending substantially along the 1st direction X. The 34th connecting electrode 434 may have one end connected to the 16th connecting electrode 416 and the other end electrically connected to the 7th active layer 370b via the 101st via V101.

[0235] In some examples, the shape of the 21st connecting electrode 421 may be approximately L-shaped. The 21st connecting electrode 421 may have one end electrically connected to the first active layer 310c via the 94th via V94, and the other end may be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 36th via V36, and electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c via the 24th via V24.

[0236] In some examples, the shape of the 22nd connecting electrode 422 may be an elongated structure extending substantially along the second direction Y. One end of the 22nd connecting electrode 422 may be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 35th via V35, and the other end may be electrically connected to the first electrode 391c of the storage capacitor of the first pixel circuit 11c via the 39th via V39.

[0237] In some examples, the shape of the 23rd connecting electrode 423 may be approximately rectangular. The 23rd connecting electrode 423 may be electrically connected to the 4th active layer 340c of the 4th transistor 34c of the 1st pixel circuit 11c via the 22nd via V22.

[0238] In some examples, the shape of the 24th connecting electrode 424 may be a bent shape extending substantially along the second direction Y. One end of the 24th connecting electrode 424 may be electrically connected to the third active layer 330c of the third transistor 33c of the first pixel circuit 11c via the 23rd via V23, and the other end may be electrically connected to the eighth active layer 380c of the eighth transistor 38c of the first pixel circuit 11c via the 98th via V98.

[0239] In some examples, the shape of the 25th connecting electrode 425 may be an elongated structure extending substantially along the first direction X. The 25th connecting electrode 425 may be electrically connected to the second electrode 392c of the storage capacitor of the first pixel circuit 11c via the 44th via V44.

[0240] In some examples, the shape of the 26th connection electrode 426 may be an elongated structure extending substantially along the first direction X. The 26th connection electrode 426 may be electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c via the 25th via V25, and may also be electrically connected to the seventh active layer 370c via the 99th via V99.

[0241] In some examples, the shape of the 31st connection electrode 431 may be substantially dumbbell-shaped. One end of the 31st connection electrode 431 may be electrically connected to an integrated structure of three first active layers via the 91st via V91, and the other end may be electrically connected to the first initial signal line INIT1(i) via the 45th via V45.

[0242] In some examples, the shape of the 32nd connection electrode 432 may be an elongated structure extending substantially along the second direction Y. One end of the 32nd connection electrode 432 may be electrically connected to an integrated structure of three eighth active layers via the 96th via V96, and the other end may be electrically connected to the third initial signal line INIT3(i) via the 48th via V48.

[0243] In some examples, the shape of the 33rd connection electrode 433 may be substantially L-shaped. One end of the 33rd connection electrode 433 may be electrically connected to an integrated structure of three seventh active layers via the 102nd via V102, and the other end may be electrically connected to the second initial signal line INIT2(i) via the 50th via V50.

[0244] In some examples, the shapes of the 36th connection electrode 436 and the 37th connection electrode 437 may be substantially rectangular. The 36th connection electrode 436 may be electrically connected to the third initial signal line INIT3(i) via the 47th via V47, and the 37th connection electrode 437 may be electrically connected to the third initial signal line INIT3(i) via the 49th via V49. In this example, providing the 36th connection electrode and the 37th connection electrode contributes to uniformization of the film layer pattern.

[0245] FIG. 29 is a schematic diagram of one circuit island area after forming the seventh insulating layer in FIG. 21. In some examples, as shown in FIG. 29, a plurality of vias may be opened in the seventh insulating layer of the first display area, and may include, for example, a 61st via V61 to a 68th via V68. The seventh insulating layer and the sixth insulating layer in the 61st via V61 to the 68th via V68 may be removed to expose a partial surface of the fourth conductive layer.

[0246] FIG. 30 is a schematic diagram of the fifth conductive layer in FIG. 21. In some examples, as shown in FIG. 21 and FIG. 30, the fifth conductive layer of the first display area includes at least a plurality of data lines (e.g., including data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), a plurality of first anode connection electrodes (e.g., including first anode connection electrodes 451a, 451b, 451c), a plurality of first shield electrodes (e.g., including first shield electrodes 511a, 511b, 511c), and a plurality of second power connection lines (e.g., including second power connection lines 513a, 513b, 513c).

[0247] In some examples, the second power supply connection lines 513a, 513b, and 513c may be broken segments extending along the second direction Y. One end of the second power supply connection line 513a may be connected to the integrated structure of the first shield electrodes 511a and 511b in one circuit island area, and the other end may be connected to the first shield electrode 511c in another circuit island area. One end of the second power supply connection line 513b may be connected to the first shield electrode 511c in one circuit island area, and the other end may be connected to the first shield electrode 511a in another circuit island area. One end of the second power supply connection line 513c may be connected to the first shield electrode 511c in one circuit island area, and the other end may be connected to the first shield electrode 511b in another circuit island area. The first shield electrode and the second power supply connection line to which it is connected may be an integrated structure that connects to each other. In this example, the connection between the first shield electrode and the first power supply connection line enables transport of the first voltage signal along the second direction Y, and the connection between the second electrode of the storage capacitor of the first pixel circuit and the connection electrode enables transport of the first voltage signal along the first direction X.

[0248] In some examples, the first anode connection electrode 451a may be electrically connected to the sixth connection electrode 406 via the 62nd via V62 to realize an electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b may be electrically connected to the 16th connection electrode 416 via the 65th via V65 to realize an electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c may be electrically connected to the 26th connection electrode 426 via the 67th via V67 to realize an electrical connection with the sixth transistor of the first pixel circuit 11c.

[0249] Figure 31 is a schematic diagram of the first display area after the sixth conductive layer has been formed on the side away from the base of the fifth conductive layer in Figure 21. In some examples, as shown in Figure 31, the sixth conductive layer of the first display area may include at least a plurality of auxiliary electrodes (e.g., including auxiliary electrodes 461a, 461b, 461c, 461d), a plurality of auxiliary connecting bars connecting the plurality of auxiliary electrodes, a plurality of second anode connecting electrodes (e.g., second anode connecting electrodes 452a, 452b, 452c, 452d), and a plurality of anode connecting bars 453.

[0250] Figure 32 is a schematic diagram of the positional relationship between the first pixel circuit of the circuit structure layer shown in Figure 21 and the anode layer of the light-emitting structure layer. In some examples, as shown in Figure 32, the orthographic projection of the anode 131a of the first light-emitting element 13a at the base may at least partially overlap with the orthographic projection of the base of the connected first pixel circuit 11a. The orthographic projection of the anode 131c of the first light-emitting element 13c at the base may at least partially overlap with the orthographic projection of the base of the connected first pixel circuit 11c.

[0251] In some examples, the orthographic projection of the anode 131b of the first light-emitting element 13b at the base overlaps at least partially with the orthographic projection of the eighth transistor of the three first pixel circuits in one circuit island area. For example, the orthographic projection of the anode 131b of the first light-emitting element 13b at the base overlaps with the orthographic projection of the integrated structure of the eighth active layer of the three eighth transistors at the base.

[0252] In some examples, the orthographic projection of the anode 131d of the first light-emitting element 13d at the base overlaps at least partially with the orthographic projection of the seventh transistor of three first pixel circuits in one circuit island area, and the first transistor of three first pixel circuits in another circuit island area. The orthographic projection of the anode 131d of the first light-emitting element 13d at the base overlaps at least partially with the orthographic projection of the integrated structure of the seventh active layer of three first pixel circuits at the base, and may further overlap at least partially with the orthographic projection of the integrated structure of the first active layer of three other first pixel circuits at the base. The orthographic projection of the anode 131d of the first light-emitting element 13d at the base does not overlap with the orthographic projection of the transistors other than the second reset transistor (i.e., the seventh transistor) of the connected first pixel circuit.

[0253] In this example, multiple reset transistors (including the first, seventh, and eighth transistors) of the first pixel circuit in the first display area are disassembled and reassembled. Multiple first and seventh transistors are placed below the anode of a first light-emitting element that emits the same green light, and multiple eighth transistors are placed below the anode of another first light-emitting element that emits green light. By disassembling and reassembling the reset transistors in this example, the first pixel circuit in the first display area can be rationally laid out, and the light transmittance of the first display area can be further increased when ensuring the emission white balance, thereby improving the performance of the display board.

[0254] The remaining details regarding the display board in this embodiment can be found in the description of the embodiment above, so they will not be repeated here.

[0255] FIG. 33 is another schematic top view of a local part of the first display area according to at least one embodiment of the present disclosure. FIG. 33 is a schematic top view of a local part of the first display area shown in FIG. 4B. The number and order of film layers of the display substrate of this example are the same as the number and order of film layers of the foregoing embodiment. For the manufacturing process of the display substrate of this example, reference may be made to the description of the foregoing embodiment. Compared with the foregoing embodiment, in this example, the reset transistor (including the first transistor and the seventh transistor) of the third first pixel circuit in the circuit island area is split. Similar structures between the display substrate of this example and the display substrate of the foregoing embodiment are omitted or briefly described, and reference may be made to the description of the foregoing embodiment.

[0256] FIG. 34A is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG. 33. FIG. 34B is a schematic diagram of one circuit island area in FIG. 34A. In some examples, as shown in FIG. 34A and FIG. 34B, the first semiconductor layer in the first display area may include active layers of a plurality of first-type transistors of at least a plurality of first pixel circuits. The first active layer 310c of the first transistor and the seventh active layer 370c of the seventh transistor of the third first pixel circuit (i.e., the first pixel circuit 11c) in one circuit island area are split and reconfigured.

[0257] In some examples, the first active layer 310c and the seventh active layer 370c of the first pixel circuit 11c may be aligned and arranged in the second direction Y. The first active layer 310c and the seventh active layer 370c of the first pixel circuits 11c in one column of circuit island areas may be aligned and arranged in the second direction. The first active layer 310c of the first pixel circuit 11c in one row of circuit island areas and the seventh active layer 370c of the first pixel circuit 11c in an adjacent row of circuit island areas may be aligned and arranged in the first direction X. The first active layer 310c and the seventh active layer 370c may be located on a side of the sixth active layer 360c away from the third active layer 330c. The shape of the first active layer 310c may be substantially half of a "ji"-shape. The shape of the seventh active layer 370c may be substantially I-shaped.

[0258] In some examples, the third active layer 330a, the fourth active layer 340a, the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a of the first pixel circuit 11a, the third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, the sixth active layer 360b, the seventh active layer 370b of the first pixel circuit 11b, and the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, the sixth active layer 360c of the first pixel circuit 11c may be of an integrated structure connected to each other. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b may be directly connected, and the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer 350c of the first pixel circuit 11c may be directly connected. The first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b may be of an integrated structure connected to each other, and the shape of the integrated structure may be substantially a "ji"-shape. The eighth active layer 380b of the first pixel circuit 11b and the eighth active layer 380c of the first pixel circuit 11c may be of an integrated structure connected to each other, and the shape of the integrated structure may be substantially U-shaped.

[0259] In some examples, the first semiconductor layer patterns of the first pixel circuits 11a and 11b in one circuit island area may be substantially symmetrical about the first center line O1. The third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, the sixth active layer 360b, and the eighth active layer 380b of the first pixel circuit 11b may be substantially symmetrical with the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, the sixth active layer 360c, and the eighth active layer 380c of the first pixel circuit 11c about the second center line O2. As shown in FIG. 34A, the first semiconductor layer patterns in different circuit island areas may be independent of each other. The seventh active layer 370c of the first pixel circuit 11c in one circuit island area is close to the integrated structure of the first active layers of the first pixel circuits 11a and 11b in the circuit island area of the adjacent column in the next row, and the first active layer 310c of the first pixel circuit 11c in one circuit island area is close to the seventh active layer 370b and the eighth active layer 380b of the circuit island area of the adjacent column in the previous row, for example, may be located between the seventh active layer 370b and the eighth active layer 380b.

[0260] Figure 35A is a schematic diagram of the first display area after the formation of the first conductive layer in Figure 33. Figure 35B is a schematic diagram of one circuit island area in Figure 35A. In some examples, as shown in Figures 35A and 35B, the first conductive layer of the first display area may include at least a plurality of first scan lines (e.g., including first scan lines GL1(i), GL1(i+1)), a plurality of light emission control lines (e.g., including light emission control lines EML(i), EML(i+1)), a plurality of first reset control lines (e.g., including first reset control lines RST1(i), RST1(i+1)), a plurality of second reset control lines (e.g., including second reset control lines RST2(i), RST2(i+1)), and first electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including first electrodes 391a, 391b, 391c). The shape of the light emission control line, the first reset control line, the first scan line, and the second reset control line may be a bent shape extending approximately along the first direction X. The first reset control line and the first scan line are bent toward the side away from the seventh active layer 370c, and the light emission control line and the second reset control line are bent toward the side away from the first active layer 310c, thereby the first reset control line, the first scan line, the light emission control line, and the second reset control line avoid the first light-transmitting area and secure the area of ​​the first light-transmitting area.

[0261] Figure 36A is a schematic diagram of the first display area after the formation of the second conductive layer in Figure 33. Figure 36B is a schematic diagram of one circuit island area in Figure 36A. In some examples, as shown in Figures 36A and 36B, the second conductive layer of the first display area may include at least a plurality of second scanning guide lines (e.g., including second scanning guide lines GL2b(i), GL2b(i+1)) and second electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including second electrodes 392a, 392b, 392c). The shape of the second scanning guide lines may be a bent shape extending substantially along the first direction X. The second scanning guide line GL2b(i) is bent toward the side away from the seventh active layer 370c and is located toward the side opposite to the second direction Y of the first scanning line GL1(i), thereby the second scanning guide line avoids the first transparent area.

[0262] Figure 37A is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 33. Figure 37B is a schematic diagram of one circuit island area in Figure 37A. In some examples, as shown in Figures 37A and 37B, the second semiconductor layer of the first display area may include the active layers of at least several first pixel circuits of a second type of transistor (e.g., the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c). In the circuit island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetric with respect to the first median O1, and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric with respect to the second median O2.

[0263] Figure 38A is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 33. Figure 38B is a schematic diagram of one circuit island area in Figure 38A. In some examples, as shown in Figures 38A and 38B, the third conductive layer of the first display area may include at least a plurality of second scan lines (e.g., including second scan lines GL2(i), GL2(i+1)), a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(i), INIT1(i+1)), a plurality of second initial signal lines (e.g., including second initial signal lines INIT2(i), INIT2(i+1)), and a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(i), INIT3(i+1)). The shapes of the first initial signal lines, second scan lines, second initial signal lines, and third initial signal lines may each be bent lines extending approximately along a first direction X. The orthographic projections of the first initial signal line and the first reset control line on the base may overlap at least partially, the orthographic projections of the second scan line and the second scan auxiliary line on the base may overlap at least partially, the orthographic projections of the third initial signal line and the light emission control line on the base may overlap at least partially, and the orthographic projections of the second initial signal line and the second reset control line on the base may overlap at least partially. In this example, by stacking the wiring of different conductive layers, wiring space can be saved, which contributes to improving the light transmittance of the first display area.

[0264] FIG. 39 is a schematic view of one circuit island area after the fifth insulating layer is formed in FIG. 33. In some examples, as shown in FIG. 39, a plurality of vias may be opened in the fifth insulating layer of the first display area, which may include, for example, a first via V1 to a sixteenth via V16, an eighteenth via V18 to a twenty-eighth via V28, and a thirty-first via V31 to a fifty-first via V51.

[0265] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via V1 to the sixteenth via V16 and the eighteenth via V18 to the twenty-eighth via V28 may be removed to expose a partial surface of the first semiconductor layer. The fifth insulating layer and the fourth insulating layer in the thirty-first via V31 to the thirty-sixth via V36 may be removed to expose a partial surface of the second semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the thirty-seventh via V37 to the thirty-ninth via V39 may be removed to expose a partial surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer and the third insulating layer in the fortieth via V40 to the forty-fourth via V44 may be removed to expose a partial surface of the second conductive layer. The fifth insulating layer in the forty-fifth via V45 to the fifty-first via V51 may be removed to expose a partial surface of the third conductive layer.

[0266] FIG. 40A is a schematic view of the first display area after the fourth conductive layer is formed in FIG. 33. FIG. 40B is a schematic view of the fourth conductive layer in FIG. 40A. FIG. 40C is a schematic view of one circuit island area in FIG. 40A.

[0267] In some examples, as shown in FIGS. 40A to 40C, the fourth conductive layer of the first display area may include at least a plurality of connection electrodes (for example, including a first connection electrode 401 to a sixteenth connection electrode 416, a twenty-second connection electrode 422 to a twenty-sixth connection electrode 426, and a thirty-eighth connection electrode 438 to a forty-first connection electrode 441).

[0268] In some examples, the shape of the first connecting electrode 401 may be a bent shape extending substantially along the second direction Y. The first connecting electrode 401 may have one end electrically connected to the first active layer 310a via the first via V1, and the other end may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via the 32nd via V32, and electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via the fourth via V4.

[0269] In some examples, the shape of the second connecting electrode 402 may be an elongated structure extending substantially along the second direction Y. One end of the second connecting electrode 402 may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a via the 31st via V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a via the 37th via V37.

[0270] In some examples, the shape of the third connecting electrode 403 may be substantially rectangular. The third connecting electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a via the second via V2.

[0271] In some examples, the shape of the fourth connecting electrode 404 may be a bent shape extending substantially along the second direction Y. One end of the fourth connecting electrode 404 may be electrically connected to the third active layer 330a of the third transistor 33a of the first pixel circuit 11a via the third via V3, and the other end may be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a via the ninth via V9.

[0272] In some examples, the shape of the fifth connecting electrode 405 may be an elongated structure extending approximately along the second direction Y. One end of the fifth connecting electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a via the fifth via V5, and the other end may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 40th via V40.

[0273] In some examples, the shape of the sixth connecting electrode 406 may be substantially rectangular. The sixth connecting electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a via the sixth via V6.

[0274] In some examples, the shape of the seventh connecting electrode 407 may be roughly dumbbell-shaped. One end of the seventh connecting electrode 407 may be electrically connected to the integrated structure of the seventh active layers 370a and 370b via the seventh via V7, and the other end may be electrically connected to the second initial signal line INIT2(i) via the 51st via V51.

[0275] In some examples, the shape of the eighth connecting electrode 408 may be approximately L-shaped. One end of the eighth connecting electrode 408 may be connected to the eighth active layer 380a via the eighth via V8, and the other end may be electrically connected to the third initial signal line INIT3(i) via the 47th via V47.

[0276] In some examples, the shape of the ninth connecting electrode 409 may be an elongated structure extending substantially along the first direction X. One end of the ninth connecting electrode 409 may be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a via the 41st via V41, and the other end may be electrically connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b via the 42nd via V42.

[0277] In some examples, the shape of the tenth connecting electrode 410 may be approximately dumbbell-shaped. One end of the tenth connecting electrode 410 may be connected to the integrated structure of the first active layers 310a and 310b via the tenth via V10, and the other end may be electrically connected to the first initial signal line INIT1(i) via the 45th via V45.

[0278] In some examples, the shape of the 11th connecting electrode 411 may be a bent shape extending substantially along the second direction Y. One end of the 11th connecting electrode 411 may be electrically connected to the first active layer 310b of the first pixel circuit 11b via the 11th via V11, and the other end may be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 34th via V34, and electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b via the 14th via V14.

[0279] In some examples, the shape of the 12th connecting electrode 412 may be an elongated structure extending substantially along the second direction Y. One end of the 12th connecting electrode 412 may be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via the 33rd via V33, and the other end may be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b via the 38th via V38.

[0280] In some examples, the shape of the 13th connecting electrode 413 may be substantially rectangular. The 13th connecting electrode 413 may be electrically connected to the 4th active layer 340b of the 4th transistor 34b of the 1st pixel circuit 11b via the 12th via V12.

[0281] In some examples, the shape of the 14th connecting electrode 414 may be a bent shape extending substantially along the second direction Y. One end of the 14th connecting electrode 414 may be electrically connected to the third active layer 330b of the third transistor 33b of the first pixel circuit 11b via the 13th via V13, and the other end may be electrically connected to the eighth active layer 380b of the first pixel circuit 11b via the 19th via V19.

[0282] In some examples, the shape of the 15th connecting electrode 415 may be an elongated structure extending approximately along the second direction Y. One end of the 15th connecting electrode 415 may be electrically connected via the 15th via V15 to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c, and the other end may be electrically connected via the 43rd via V43 to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c.

[0283] In some examples, the shape of the 16th connecting electrode 416 may be substantially rectangular. The 16th connecting electrode 416 may be electrically connected to the 6th active layer 360b of the 6th transistor 36b of the 1st pixel circuit 11b via the 16th via V16.

[0284] In some examples, the shape of the 22nd connecting electrode 422 may be an elongated structure extending substantially along the second direction Y. One end of the 22nd connecting electrode 422 may be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 35th via V35, and the other end may be electrically connected to the first electrode 391c of the storage capacitor of the first pixel circuit 11c via the 39th via V39.

[0285] In some examples, the shape of the 23rd connecting electrode 423 may be approximately rectangular. The 23rd connecting electrode 423 may be electrically connected to the 4th active layer 340c of the 4th transistor 34c of the 1st pixel circuit 11c via the 22nd via V22.

[0286] In some examples, the shape of the 24th connecting electrode 424 may be a bent shape extending substantially along the second direction Y. One end of the 24th connecting electrode 424 may be electrically connected to the third active layer 330c of the third transistor 33c of the first pixel circuit 11c via the 23rd via V23, and the other end may be electrically connected to the eighth active layer 380c of the eighth transistor 38c of the first pixel circuit 11c via the 28th via V28.

[0287] In some examples, the shape of the 25th connecting electrode 425 may be an elongated structure extending substantially along the first direction X. The 25th connecting electrode 425 may be electrically connected to the second electrode 392c of the storage capacitor of the first pixel circuit 11c via the 44th via V44.

[0288] In some examples, the shape of the 26th connecting electrode 426 may be an elongated structure extending substantially along the first direction X. The 26th connecting electrode 426 may be electrically connected to the 6th active layer 360c of the 6th transistor 36c of the 1st pixel circuit 11c via the 25th via V25, and may also be electrically connected to the 7th active layer 370c via the 26th via V26.

[0289] In some examples, the shape of the 38th connecting electrode 438 may be approximately U-shaped. The 38th connecting electrode 438 may have one end electrically connected to the integrated structure of the 8th active layers 380b and 380c via the 18th via V18, the other end electrically connected to the 3rd initial signal line INIT3(i) via the 48th via V48, and the remaining end electrically connected to the 3rd initial signal line INIT3(i) via the 49th via V49.

[0290] In some examples, the shape of the 39th connecting electrode 439 may be approximately dumbbell-shaped. The 39th connecting electrode 439 may have one end electrically connected to the first active layer 310c via the 20th via V20, and the other end electrically connected to the first initial signal line INIT1(i) via the 46th via V46.

[0291] In some examples, the shape of the 40th connecting electrode 440 may be a bent shape extending substantially along the second direction Y. One end of the 40th connecting electrode 440 may be connected to the first active layer 310c via the 21st via V21, and the other end may be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via the 36th via V36, and electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c via the 24th via V24.

[0292] In some examples, the shape of the 41st connecting electrode 441 may be roughly dumbbell-shaped. The 41st connecting electrode 441 may have one end connected to the 7th active layer 370c via the 27th via V27, and the other end electrically connected to the 2nd initial signal line INIT2(i) via the 50th via V50.

[0293] Figure 41 is a schematic diagram of one circuit island area after the formation of the seventh insulating layer in Figure 33. In some examples, as shown in Figure 41, multiple vias may be opened in the seventh insulating layer of the first indicated area, for example, including via 61 to via 68. The seventh insulating layer and the sixth insulating layer within vias 61 to via 68 may be removed to expose a portion of the surface of the fourth conductive layer.

[0294] Figure 42A is a schematic diagram of the first display area after the formation of the fifth conductive layer in Figure 33. Figure 42B is a schematic diagram of the fifth conductive layer in Figure 42A. Figure 42C is a schematic diagram of one circuit island area in Figure 42A.

[0295] In some examples, as shown in Figures 42A to 42C, the fifth conductive layer of the first display area may include at least several data lines (e.g., data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), several first anode connection electrodes (e.g., first anode connection electrodes 451a, 451b, 451c), and several first shield electrodes (e.g., first shield electrodes 511a, 511b, 511c).

[0296] In some examples, the first anode connection electrodes 451a, 451b, and 451c may be roughly dumbbell-shaped. The first anode connection electrode 451a may be electrically connected to the sixth connection electrode 406 via the 62nd via V62 to realize an electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b may be electrically connected to the 16th connection electrode 416 via the 65th via V65 to realize an electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c may be electrically connected to the 26th connection electrode 426 via the 67th via V67 to realize an electrical connection with the sixth transistor of the first pixel circuit 11c.

[0297] In some examples, the first shield electrodes 511a and 511b may be an integrated structure connected to each other. The first shield electrodes 511a and 511b may be substantially symmetrical with respect to the first midline O1. The orthogonal projection of the base of the first shield electrode 511a can cover the orthogonal projection of the base of the second connecting electrode 402, thereby realizing shielding for the first node of the first pixel circuit 11a. The orthogonal projection of the base of the first shield electrode 511b may also cover the orthogonal projection of the base of the twelfth connecting electrode 412, thereby realizing shielding for the first node of the first pixel circuit 11b. The orthogonal projection of the base of the first shield electrode 511c may also cover the orthogonal projection of the base of the 22nd connecting electrode 422, thereby realizing shielding for the first node of the first pixel circuit 11c. This prevents the influence of remaining signals on the first nodes of the first pixel circuits 11a, 11b, and 11c.

[0298] In some examples, multiple data lines may be bent in shape, extending approximately along the second direction Y. Data lines DL(j) and DL(j+1) may be adjacent, and data lines (j+2) and DL(j+3) may be adjacent. Data line DL(j+1) may be electrically connected to the third connection electrode 403 via the 61st via V61 to realize an electrical connection with the first electrode of the fourth transistor 34a of the first pixel circuit 11a. Data line DL(j+2) may be electrically connected to the 13th connection electrode 413 via the 64th via V64 to realize an electrical connection with the first electrode of the fourth transistor 34b of the first pixel circuit 11b. Data line DL(j+3) may be electrically connected to the 23rd connection electrode 423 via the 66th via V66 to realize an electrical connection with the first electrode of the fourth transistor 34c of the first pixel circuit 11c.

[0299] In some examples, four data lines may be drilled in each circuit island area, and three of the four data lines may be electrically connected to three first pixel circuits in the circuit island area, respectively. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) may be configured to provide data signals to first pixel circuits (e.g., first pixel circuit 11b) connected to a first light-emitting element that emits a third color of light. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) may be configured to provide data signals to a plurality of first pixel circuits arranged in rows. For example, the data lines DL(j) and DL(j+4) are not electrically connected to the first pixel circuit in the i-th row circuit island area, but are electrically connected to the first pixel circuit in the i+1-th row circuit island area. Data lines DL(j+2) and DL(j+6) are electrically connected to the first pixel circuit in the i-th row circuit island area, but not to the first pixel circuit in the i+1-th row circuit island area. In this example, the data lines that provide data signals to the first pixel circuit (e.g., first pixel circuit 11b) connected to the first light-emitting element that emits a third color of light are electrically connected to multiple first pixel circuits arranged in rows, and provide data signals to multiple first pixel circuits arranged in rows. The data line arrangement in this example contributes to the wiring layout.

[0300] Figure 43 is a schematic diagram of one circuit island area after the formation of the eighth insulating layer in Figure 33. In some examples, as shown in Figure 43, multiple vias may be opened in the eighth insulating layer of the first indicated area, for example, including vias 71 V71 to 75 V75. The eighth insulating layer within vias 71 V71 to 75 V75 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0301] Figure 44A is a schematic diagram of the first display area after the formation of the sixth conductive layer in Figure 33. Figure 44B is a schematic diagram of the sixth conductive layer in Figure 44A. In some examples, as shown in Figures 44A and 44B, the sixth conductive layer of the first display area may include at least a third power supply connection line 463, a plurality of second anode connection electrodes (e.g., second anode connection electrodes 452a, 452b, 452c, 452d), and a plurality of anode connection bars 453.

[0302] In some examples, the shapes of the second anode connection electrodes 452a and 452c may be approximately dumbbell-shaped, and the shapes of the second anode connection electrodes 452b and 452d may both be approximately rectangular. The second anode connection electrode 452a may be electrically connected to the first anode connection electrode 451a via the 71st via V71 to realize an electrical connection with the sixth transistor of the first pixel circuit 11a. The second anode connection electrode 452c may be electrically connected to the first anode connection electrode 451c via the 73rd via V73 to realize an electrical connection with the sixth transistor of the first pixel circuit 11c. The second anode connection electrode 452b may be electrically connected to the first anode connection electrode 451b via the 72nd via V72 to realize an electrical connection with the sixth transistor of the first pixel circuit 11b. The second anode connection electrode 452b may be electrically connected to the second anode connection electrode 452d via the anode connection bar 453. The second anode connection electrodes 452b and 452d and the anode connection bar 453 may be an integrated structure connected to each other. The second anode connection electrode 452d connected to the second anode connection electrode 452b in the circuit island area of ​​row i and column m may be located between the circuit island area of ​​row i and column m and the circuit island area of ​​row i and column m+2, and close to the circuit island area of ​​row i-1. The anode connection bar 453 may be a roughly L-shaped bent line.

[0303] In some examples, the third power supply connection line 463 may have a mesh structure, for example, including a portion extending along the second direction Y and a portion extending in a direction that intersects both the first direction X and the second direction Y. The third power supply connection line 463 may be electrically connected to the integrated structure of the first shield electrodes 511a and 511b via the 74th via V74, and may also be electrically connected to the first shield electrode 511c via the 75th via V75. In this example, the third power supply connection line 463 enables mesh-like transport of the first voltage signal in the first display area, thereby ensuring the uniformity of the first voltage signal.

[0304] Figure 45 is a schematic diagram of the stacking of the first semiconductor layer, first conductive layer, second conductive layer, second semiconductor layer, third conductive layer and anode layer in Figure 33. In some examples, as shown in Figures 33 and 45, the anode layer of the first display area may include at least anodes of multiple first light-emitting elements (e.g., anode 131a of the first light-emitting element 13a, anode 131b of the first light-emitting element 13b, anode 131c of the first light-emitting element 13c and anode 131d of the first light-emitting element 13d), and multiple third anode connecting electrodes (e.g., third anode connecting electrodes 132a, 132b, 132c, 132d).

[0305] In some examples, the shapes of the anodes 131a, 131b, 131c, and 131d may be approximately circular or elliptical. The shapes of the third anode connecting electrodes 132a, 132b, 132c, and 132d may be approximately rectangular. The anode 131a and the third anode connecting electrode 132a may be an integrated structure connected to each other. The third anode connecting electrode 132a may be electrically connected to the second anode connecting electrode 452a to realize an electrical connection with the first pixel circuit 11a. The anode 131b and the third anode connecting electrode 132b may be an integrated structure connected to each other. The third anode connecting electrode 132b may be electrically connected to the second anode connecting electrode 452b to realize an electrical connection with the first pixel circuit 11b. The anode 131c and the third anode connecting electrode 132c may be an integrated structure connected to each other. The third anode connection electrode 132c may be electrically connected to the second anode connection electrode 452c to achieve electrical connection with the first pixel circuit 11c. The anode 131d and the third anode connection electrode 132d may be an integrated structure connected to each other. The third anode connection electrode 132d may be electrically connected to the second anode connection electrode 452d. Since the second anode connection electrodes 452d and 452b are an integrated structure, they achieve electrical connection between the third anode connection electrode 132d and the first pixel circuit 11b.

[0306] In some examples, the first light-emitting element 13d does not overlap with the orthographic projection at the base of the connected first pixel circuit 11b, and the first light-emitting element 13d at least partially overlaps with the orthographic projection at the base of one first transistor. The first light-emitting element 13b may not overlap with the orthographic projection at the base of the connected first pixel circuit 11b, or it may partially overlap, and the first light-emitting element 13b may at least partially overlap with the orthographic projection at the base of one seventh transistor. The first light-emitting element 13a at least partially overlaps with the orthographic projection at the base of the connected first pixel circuit 11a, and the first light-emitting element 13c at least partially overlaps with the orthographic projection at the base of the connected first pixel circuit 11c.

[0307] In some examples, as shown in Figures 33 and 45, the first transistor 31c of the first pixel circuit 11c may be located below one first light-emitting element 13d, and the seventh transistor 37c of the first pixel circuit 11c may be located below one first light-emitting element 13b. The first transistor 31c and the seventh transistor 37c of the first pixel circuit 11c are located below first light-emitting elements that emit different green light. The orthographic projection of the anode 131b of the first light-emitting element 13b on its base may cover the orthographic projection of the first active layer 310c of the first transistor of the first pixel circuit 11c on its base, and the orthographic projection of the anode 131d of the first light-emitting element 13d on its base may cover the orthographic projection of the seventh active layer 370c of the seventh transistor of the first pixel circuit 11c on its base.

[0308] In this example, the display board disassembles the reset transistor of the third first pixel circuit in the circuit island area and places it below a different first light-emitting element. This avoids the effect on the light transmittance of the first display area caused by the reset transistor not being obstructed by the anode of the light-emitting element. This example contributes to improving the light transmittance of the first display area. Compared to the two embodiments described above, the display board of this embodiment can obtain better light transmittance.

[0309] The remaining details regarding the display board in this example can be found in the description of the above embodiment, so they will not be repeated here.

[0310] The above embodiments are merely illustrative. Some features of the above embodiments can be combined with each other. This embodiment is not limited to such combinations.

[0311] In another example, the reset transistor of the first first pixel circuit in the circuit island area may be removed, and for example, the first transistor of the first first pixel circuit may be placed below the first light-emitting element that emits green light, and the seventh transistor of the first first pixel circuit may be placed below another first light-emitting element that emits green light.

[0312] In another example, the reset transistors of two first pixel circuits in a circuit island area (for example, the first and second first pixel circuits, or the first and third first pixel circuits, or the second and third first pixel circuits) may be disassembled and reassembled. For example, the first transistor of the two reassembled first pixel circuits may be placed below the first light-emitting element that emits green light, and the seventh transistor of the two reassembled first pixel circuits may be placed below the other first light-emitting element that emits green light.

[0313] In other examples, the reset transistor of at least one first pixel circuit in the circuit island area may be disassembled (or disassembled and reassembled), and the disassembled or reassembled at least one reset transistor may be placed below a first light-emitting element that emits red light, or below a first light-emitting element that emits blue light, or some of the reset transistors may be placed below a first light-emitting element that emits red light and other some of the reset transistors may be placed below a first light-emitting element that emits blue light.

[0314] In other examples, the reset transistor of at least one first pixel circuit in the circuit island area may be disassembled (or disassembled and reassembled), and the disassembled or reassembled reset transistors may be placed below the same first light-emitting element. For example, the number of reset transistors placed below first light-emitting elements that emit green light may differ, and each of the disassembled or reassembled reset transistors may be placed below a first light-emitting element that emits different green light. For example, a reset transistor may be placed below each of two first light-emitting elements that emit green light and are electrically connected to the same first pixel circuit, with one reset transistor below one of the first light-emitting elements and two or three reset transistors below the other first light-emitting element.

[0315] In this embodiment, the display board drives the first light-emitting element by a first pixel circuit in a one-to-many drive system in the first display area. This allows the number of first pixel circuits in the first display area to be less than the number of first light-emitting elements, contributing to an improvement in the light transmittance of the first display area. Furthermore, by adjusting the position of the reset transistor in the first pixel circuit of the first display area, the anode of the first light-emitting element contributes to shielding the first pixel circuit, thereby improving the light transmittance of the first display area.

[0316] This embodiment further provides a display board comprising a base, a plurality of first pixel circuits located in a first display area, and a plurality of first light-emitting elements. At least one of the plurality of first pixel circuits is electrically connected to one first light-emitting element, and at least one first pixel circuit is electrically connected to at least two first light-emitting elements. Each first pixel circuit includes at least one reset transistor. The orthographic projection on the base of at least two first light-emitting elements electrically connected to the same first pixel circuit at least partially overlaps with the orthographic projection on the base of the reset transistors of the plurality of first pixel circuits.

[0317] In some exemplary embodiments, the orthogonal projection of the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the base includes the orthogonal projection of the active layer of at least one reset transistor on the base.

[0318] In some exemplary embodiments, the first pixel circuit includes a first reset transistor and a second reset transistor. The orthographic projection of the base of one of two first light-emitting elements electrically connected to the same first pixel circuit at least partially overlaps the orthographic projection of the base of the first reset transistor, and the orthographic projection of the base of the other of the at least two first light-emitting elements at least partially overlaps the orthographic projection of the base of the base of the second reset transistor.

[0319] In some exemplary embodiments, the orthographic projection of the base of the first light-emitting element overlapping with the second reset transistor does not have to overlap with the orthographic projection of the base of the first pixel circuit connected to the first light-emitting element.

[0320] The details regarding the display board in this example can be found in the description of the above embodiment, so they will not be repeated here.

[0321] Figure 46 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 46, this embodiment provides a display device comprising a display substrate 91 and a sensor 92 located on the light-emitting side of a light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0322] In some examples, the display board 91 may be a flexible OLED display board, a QLED display board, a Micro-LED display board, or a Mini-LED display board. The display device may be a product having an image display function (including static or dynamic images, where dynamic images may be video). For example, the display device may be any one of the following products: a display, a television, a sign, a digital frame, a laser printer with a display function, a telephone, a mobile phone, a paint screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (e.g., a business query device for e-government offices, banks, hospitals, power companies, etc.), a monitor, etc. The display device may also be any one of the following products: a microdisplay, a VR device or AR device including a microdisplay, etc.

[0323] The drawings in this disclosure relate only to the structures relating to this disclosure; for other structures, conventional designs may be referenced. Where there are no conflicts, new embodiments can be obtained by combining the embodiments and features of these embodiments. The embodiments or designs described above are illustrative and not restrictive. Therefore, this disclosure is not limited to what is described in detail herein. Various modifications, substitutions, or omissions can be made to the embodiments and details without departing from the scope of this disclosure.

Claims

1. A display board comprising a base, a plurality of first pixel circuits, and a plurality of first light-emitting elements, The base includes a first display area, The plurality of first pixel circuits and the plurality of first light-emitting elements are located in the first display area, and at least one of the plurality of first pixel circuits is electrically connected to at least two first light-emitting elements. The at least one first pixel circuit includes at least one reset transistor, The display substrate wherein the orthographic projection of at least one of the plurality of first light-emitting elements on the base at least partially overlaps with the orthographic projection of the reset transistor of the at least one first pixel circuit on the base.

2. The plurality of first light-emitting elements include a plurality of first light-emitting elements that emit light of different colors, The display substrate according to claim 1, wherein the orthographic projection on the base of a plurality of first light-emitting elements emitting light of the same color at least partially overlaps with the orthographic projection on the base of a plurality of reset transistors of first pixel circuits.

3. The display substrate according to claim 1 or 2, wherein the orthographic projection of the anode of the at least one first light-emitting element on the base includes the orthographic projection of the active layer of the at least one reset transistor on the base.

4. The at least one first pixel circuit includes a first reset transistor and a second reset transistor. The display substrate according to claim 2, wherein the orthographic projection of the first reset transistor of the at least one first pixel circuit on its base at least partially overlaps with the orthographic projection of the base of one first light-emitting element, and the orthographic projection of the second reset transistor of the at least one first pixel circuit on its base at least partially overlaps with the orthographic projection of the base of another first light-emitting element emitting light of the same color.

5. The display substrate according to claim 4, wherein the orthographic projection of the first light-emitting element on the base that overlaps with the second reset transistor does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element on the base.

6. The plurality of first light-emitting elements are divided into a plurality of light-emitting units, each light-emitting unit includes a first light-emitting element that emits one first color of light, a first light-emitting element that emits one second color of light, and a first light-emitting element that emits two third colors of light. The display substrate according to any one of claims 1 to 5, wherein the first light-emitting element that emits light of the first color is electrically connected to one first pixel circuit, the first light-emitting element that emits light of the second color is electrically connected to one first pixel circuit, and the two first light-emitting elements that emit light of the third color are electrically connected to the same first pixel circuit.

7. In the light-emitting unit, the first light-emitting element that emits the first color of light and the first light-emitting element that emits the second color of light are arranged in the same row, the two first light-emitting elements that emit the third color of light are arranged in the same row, and the four first light-emitting elements in the light-emitting unit are arranged in different columns. The display substrate according to claim 6, wherein the first color of light is red light, the second color of light is blue light, and the third color of light is green light.

8. The first display area includes a plurality of circuit island areas arranged in an array at intervals from each other, each circuit island area includes three first pixel circuits sequentially installed along a first direction, and two adjacent rows of circuit island areas are installed with a staggered position. The display board according to claim 6 or 7, wherein the three first pixel circuits of the circuit island area are electrically connected to four first light-emitting elements in one light-emitting unit.

9. The display board according to claim 8, wherein any two adjacent first pixel circuits in the circuit island area are arranged symmetrically with respect to the median line along the first direction of the two adjacent first pixel circuits.

10. The display board according to claim 8, wherein data lines connected to a first pixel circuit connected to a first light-emitting element that emits the third color of light are configured to provide data signals to a plurality of first pixel circuits arranged in rows.

11. The display substrate according to claim 8, wherein the first pixel circuit connected to the first light-emitting element that emits two third-color light in the light-emitting unit is located between the first pixel circuit connected to the first light-emitting element that emits the first color light and the first pixel circuit connected to the first light-emitting element that emits the second color light.

12. Each first pixel circuit in the circuit island area includes a drive transistor, a first reset transistor, a second reset transistor, and a third reset transistor, wherein the first reset transistor is configured to reset the second electrode of the drive transistor, the second reset transistor is configured to reset the anode of a first light-emitting element connected to the first pixel circuit, and the third reset transistor is configured to reset the first electrode of the drive transistor. The display substrate according to claim 8, wherein the active layers of the first reset transistors of the three first pixel circuits in the circuit island area are an integrated structure connected to each other, the active layers of the second reset transistors of the three first pixel circuits are an integrated structure connected to each other, and the active layers of the third reset transistors of the three first pixel circuits are an integrated structure connected to each other.

13. The display substrate according to claim 12, wherein the orthographic projection on the base of the integrated active layer structure of the first reset transistors of the three first pixel circuits in the circuit island area, the integrated active layer structure of the second reset transistors of the three first pixel circuits, and the integrated active layer structure of the third reset transistors of the three first pixel circuits at least partially overlaps with the orthographic projection on the base of different first light-emitting elements emitting a third color of light.

14. The display substrate according to claim 12, wherein the orthographic projection on the base of the integrated active layer structure of three second reset transistors in one circuit island area and the integrated active layer structure of three first reset transistors in adjacent circuit island areas in the second direction at least partially overlaps with the orthographic projection on the base of the same first light-emitting element that emits a third color of light, the first light-emitting element that emits a third color of light is electrically connected to one first pixel circuit in the circuit island area and does not overlap with the orthographic projection on the base of transistors other than the second reset transistors in the first pixel circuit, and the second direction and the first direction intersect.

15. Each first pixel circuit in the circuit island area includes at least a drive transistor, a first reset transistor, and a second reset transistor, wherein the first reset transistor is configured to reset the second electrode of the drive transistor, and the second reset transistor is configured to reset the anode of a first light-emitting element connected to the first pixel circuit. In the circuit island area, the active layer of the first reset transistor and the active layer of the second reset transistor of the third first pixel circuit along the first direction are aligned in the second direction, and the second direction and the first direction intersect. The display substrate according to claim 8, wherein the orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the base at least partially overlaps with the orthographic projection of the base of a first light-emitting element that emits one third color of light, and the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the base at least partially overlaps with the orthographic projection of the base of a first light-emitting element that emits another third color of light.

16. The display substrate according to claim 15, wherein the orthographic projection of the anode of a first light-emitting element emitting one third color of light on the base includes the orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the base, and the orthographic projection of the anode of a first light-emitting element emitting another third color of light on the base includes the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the base.

17. In a direction perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, which are installed on the base. The display substrate according to any one of claims 1 to 16, wherein the sixth conductive layer includes at least a plurality of auxiliary electrodes, and the orthographic projection of the auxiliary electrodes on the base includes the orthographic projection of the light-emitting region of the first light-emitting element on the base.

18. The display board according to claim 17, wherein the plurality of auxiliary electrodes are connected via a plurality of auxiliary connection bars to form a mesh structure, and the mesh structure is connected to a first voltage signal.

19. A display device comprising a display board according to any one of claims 1 to 18, and a sensor located on the non-display side of the display board, wherein the orthographic projection of the sensor on the display board at least partially overlaps with the first display area of ​​the display board.

20. A display board, Base including the first display area, The system comprises a plurality of first pixel circuits and a plurality of first light-emitting elements located in the first display area, At least one of the plurality of first pixel circuits is electrically connected to one first light-emitting element, and at least one first pixel circuit is electrically connected to at least two first light-emitting elements. The first pixel circuit includes at least one reset transistor, The display substrate wherein the orthographic projections of the bases of at least two first light-emitting elements electrically connected to the same first pixel circuit overlap at least partially with the orthographic projections of the bases of the reset transistors of the plurality of first pixel circuits.

21. The display substrate according to claim 20, wherein the orthographic projection of the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the base includes the orthographic projection of the active layer of at least one reset transistor on the base.

22. The first pixel circuit includes a first reset transistor and a second reset transistor. The display substrate according to claim 20, wherein the orthographic projection on the base of one of two first light-emitting elements electrically connected to the same first pixel circuit at least partially overlaps with the orthographic projection on the base of the first reset transistor, and the orthographic projection on the base of the other of the at least two first light-emitting elements at least partially overlaps with the orthographic projection on the base of the second reset transistor.

23. The display substrate according to claim 22, wherein the orthographic projection of the first light-emitting element on the base that overlaps with the second reset transistor does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element on the base.

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