Selective capping for gate-all-around field-effect transistors

Abstract

Embodiments of the present disclosure include a method for forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method includes removing material from the surface of a feature formed within the surface of the substrate, wherein the substrate comprises a plurality of features, each comprising a plurality of source / drain contact surfaces; selectively forming a reaction product material on each of the plurality of source / drain contact surfaces; heating the substrate to a first temperature to remove the reaction product material from each of the plurality of contacts; selectively forming a first metal layer on each of the plurality of contacts; selectively forming a second metal layer on the first metal layer; and filling the feature with a conductive material, wherein the conductive material comprises tungsten (W) or molybdenum (Mo).

Description

[Technical Field]

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more particularly to systems and methods for forming gate contact structures within gate-all-around field-effect transistors. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain billions of transistors, capacitors, and resistors on a single chip. Throughout the evolution of integrated circuits, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while shape dimensions (i.e., the smallest component (or line) that can be fabricated using a manufacturing process) have decreased.

[0003] Microelectronic devices are manufactured on semiconductor substrates as integrated circuits, with various conductive layers interconnected to enable the propagation of electronic signals within the device. Examples of such devices can include high-performance computing devices, mobile devices, Internet of Things (IoT) devices, memory (e.g., DRAM (Dynamic Random Access Memory)), and logic devices, and can include both planar and three-dimensional structures. Three-dimensional structures include finFET (fin field-effect transistor), MOSFET (metal-oxide-semiconductor field-effect transistor) devices, or GAA FET (gate-all-around field-effect transistor) devices.

[0004] GAA FETs are an advanced transistor design that offers improved performance and power efficiency compared to conventional FETs such as finFETs (finnish field-effect transistors) and MOSFETs (metal-oxide-semiconductor field-effect transistors). GAA FETs consist of a channel region surrounded on all sides by a gate structure, providing superior control over electron flow. The GAA architecture enables enhanced electrostatic control and reduced leakage current, resulting in faster switching speeds, lower power consumption, and improved scalability. Due to its three-dimensional gate configuration, GAA FETs exhibit superior control over short-channel effects, enabling the design of extremely small and efficient electronic devices for a wide range of applications, including high-performance computing, mobile devices, and Internet of Things (IoT) devices.

[0005] An example of a GAA FET device includes a channel region where all sides are surrounded by a gate structure, which provides excellent control over electron flow. Source / drain regions are provided at both ends of the gate structure. The source and drain regions are generally highly doped regions of the semiconductor substrate. Typically, a silicon compound layer, such as a titanium-silicon compound layer, is required to form a reliable contact structure in the formed source and drain regions.

[0006] In conventional middle-end-of-line (MEOL) contact junction formation processes, features such as vias or trenches are fabricated within the semiconductor substrate. Contact regions containing silicon (Si) or silicon / germanium (SiGe) are formed at the bottom of the trench or via. MEOL contact junctions enable connections between front-end-of-line (FEOL) semiconductor structures and back-end-of-line (BEOL) interconnects. Low-resistivity contacts are desirable within semiconductor devices. However, when MEOL contact junctions have relatively high resistance, insufficient connections are created, reducing the overall performance of the packaged semiconductor structure.

[0007] In 3D device structures such as finFETs, silicon compound contacts must be formed on the exposed portions of silicon-based source / drain layers formed on the sidewalls of deep high aspect ratio (HAR) holes or deep HAR trenches, leaving little or no space to ensure the formation of the GAA gate contact structure. Conventional deposition techniques typically form silicon compound layers at one specific optimized depth, but the gradient of chemical species concentrations that arise during transport within deep holes / trenches inherently causes deposition heterogeneity. In HAR holes or deep HAR trenches, deposition heterogeneity is further amplified. This conventional method for forming silicon compound layers in these features leads to variability in the properties of the silicon compound layer, and in particular, variability in the electrical properties of the 3D device.

[0008] Therefore, there is a need in the art for a selective process used to efficiently and rapidly form reliable low-resistance contact structures for GAA FET devices. [Overview of the initiative]

[0009] The embodiments described herein generally relate to semiconductor device manufacturing, and more particularly to systems and methods for forming gate contact structures within gate-all-around field-effect transistors. This method includes the following:

[0010] A method for removing material from the surface of a feature formed within the surface of a substrate is provided, the feature comprising a plurality of contact structures disposed within the feature formed within the substrate, each of which comprises a plurality of contacts, each comprising silicon (Si) or silicon germanium (SiGe), and each of the plurality of contacts being separated in a first direction by a dielectric layer. A method for removing material comprises selectively forming a reaction product material on the surface of each of the plurality of contacts, and then heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts.

[0011] A first metal layer is selectively formed on the surface of each of a plurality of contacts. Forming a second metal layer on the first metal layer, and forming the second metal layer on the first metal layer, involves selectively depositing the second metal layer on the first metal layer, and selectively forming the second metal layer involves exposing the surface of the selectively formed first metal layer to a fluorine-free metal-containing precursor to form the second metal layer.

[0012] The features are filled with a conductive material, which contains tungsten (W) or molybdenum (Mo), and a capping layer is deposited on the conductive material.

[0013] To gain a more detailed understanding of the features of this disclosure described above, a more specific description of the disclosure, which is briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and are therefore not to be considered an limitation of the scope, and other equally valid embodiments may also be recognized. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic top view of a multi-chamber processing system according to an embodiment described herein. [Figure 2] This is a process flow diagram of a method for forming a semiconductor structure according to the embodiments described herein. [Figure 3] This is a schematic isometric view of an exemplary GAA FET semiconductor structure according to the embodiments described herein. [Figure 4A-4J] This is a schematic cross-sectional view of a portion of a semiconductor structure according to the embodiments described herein. [Modes for carrying out the invention]

[0015] For ease of understanding, the same reference numerals have been used to refer to identical elements common to these figures, where possible. It is intended that elements and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0016] The following disclosure may refer to one or more embodiments. However, it will be understood by those skilled in the art that this disclosure is not particularly limited to the embodiments described. Conversely, any combination of features and elements, whether relating to different embodiments or not, is possible to implement and perform one or more embodiments provided by this disclosure. Furthermore, one or more embodiments presented in this disclosure may achieve advantages over other possible solutions, prior art (if any), and combinations thereof, but this disclosure does not limit whether a particular advantage is achieved by a given embodiment. The aspects, features, embodiments, and advantages provided are for illustrative purposes only. They shall not be considered elements or limitations of the appended claims unless explicitly stated in one or more of the claims. Similarly, those skilled in the art should not interpret any reference to “this disclosure” as a generalization of any disclosed subject matter.

[0017] When used in this application, "substrate" may refer to a substrate or a material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, the substrate surfaces that can be treated are not limited to metals, metal nitrides, and metal alloys, depending on the application, but include silicon (Si), silicon dioxide (SiO2), strained Si, Si-on insulator (SOI), and carbon-doped silicon dioxide (SiO2). xIt may be composed of materials such as amorphous Si, doped Si, pre-amorphization implantation (PAI) Si, germanium (Ge), PAI-SiGe, gallium arsenide (GaAs), glass, sapphire, and any other conductive materials. By way of example and not limitation, the substrate includes a semiconductor wafer. The substrate may be exposed to treatment processes for polishing, etching, reduction, oxidation, or annealing of a substrate surface.

[0018] The terms "precursor", "reactant", "reactive gas", and similar such terms referring to chemical species, as used in the present application, may refer to one or more chemical species capable of reacting with one or more exposed surfaces of a substrate, or one or more chemical species that react with each other and the result thereof then reacts with the exposed surface of the substrate.

[0019] The terms "CPU", "processor", "at least one processor", or "one or more processors" generally refer to a single processor configured to perform one or more operations, or a plurality of processors configured to collectively perform one or more operations. In the case of a plurality of processors, performance of one or more operations may be divided among different processors, but a single processor may also perform a plurality of operations, and a plurality of processors may collectively perform a single operation. Similarly, "memory", "at least one memory", or "one or more memories" generally refers to a single memory configured to store data and / or instructions, and a plurality of memories configured to collectively store data and / or instructions. Similarly, "memory", "at least one memory", or "one or more memories" generally refers to a single memory configured to store data and / or instructions, and a plurality of memories configured to collectively store data and / or instructions.

[0020] Example Processing System FIG. 1 shows a schematic diagram of a processing system 100 for use with one or more embodiments of the present disclosure. In one or more embodiments, the processing system 100 can be utilized to implement all or a portion of the method 200 of FIG. 2.

[0021] As described in detail below, substrates within the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to an ambient environment external to the processing system 100 (e.g., an atmospheric ambient environment that may be present in a manufacturing facility). For example, substrates can be processed in various chambers and transferred between various chambers while maintained at a low pressure such as a vacuum environment (e.g., about 300 Torr or less), that is, below atmospheric pressure, without breaking the reduced relative pressure or vacuum environment between various processes performed on substrates within the processing system 100. Accordingly, the processing system 100 can provide an integrated solution for some processing of substrates.

[0022] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include the Endura® integrated processing system, or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California (CA), United States. It will be appreciated that other processing systems, including those from other manufacturers, can be adapted to benefit from the aspects described herein.

[0023] Figure 1 is a schematic top view of a processing system 100 (also called the “processing platform”) according to an embodiment described herein. The processing system 100 generally includes, as will be described in detail below, an equipment front module (EFEM) 102 for loading substrates into the processing system 100, a first load lock chamber 104 coupled to the EFEM 102, a transfer chamber 108 coupled to the first load lock chamber 104, and a number of other chambers coupled to the transfer chamber 108. The EFEM 102 generally includes one or more robots 105 configured to transfer substrates from a forward-opening unified pod (FOUP) 103 to at least one of the first load lock chamber 104 or the second load lock chamber 106. Around the transfer chamber 108, counterclockwise from the buffer portion 108A of the first load lock chamber 104, the processing system 100 includes a first dedicated degassing chamber 109, a first pre-cleaning chamber 110, a first pass-through chamber 112, a second pass-through chamber 113, a second pre-cleaning chamber 114, a second degassing chamber 116, and a second load lock chamber 106. The buffer portion 108A of the transfer chamber 108 includes a first robot 115 configured to transfer substrates to the load lock chambers 104 and 106, the degassing chambers 109 and 116, the pre-cleaning chambers 110 and 114, and the pass-through chambers 112 and 113, respectively.

[0024] The rear end portion 108B of the transfer chamber 108 includes a second robot 135 configured to transfer substrates to the passage chambers 112, 113 and the processing chambers coupled to the rear end portion 108B of the processing system 100. The processing chambers may include a first processing chamber 132, a second processing chamber 134, a third processing chamber 136, a fourth processing chamber 138, and a fifth processing chamber 140. Generally, the processing chambers 132, 134, 136, 138, and 140 may include at least one of atomic layer deposition (ALD) chambers, chemical vapor deposition (CVD) chambers, physical vapor deposition (PVD) chambers, etching chambers, degassing chambers, annealing chambers, and other types of semiconductor substrate processing chambers. In some embodiments, one or more of the processing chambers 132, 134, 136, 138, and 140 are PVD chambers. In some examples, processing chamber 110 may be capable of performing an etching process, processing chamber 114 may be capable of performing a cleaning or annealing process, and processing chambers 132, 134, 136, 138, and 140 may be capable of performing their respective CVD or ALD deposition processes. In one example, processing chamber 110 or 114 may be a Selectra® etching chamber available from Applied Materials, Santa Clara, California. In one example, processing chamber 110 or 114 may be a SiCoNi® pre-cleaning chamber available from Applied Materials, Santa Clara, California. In one example, processing chambers 132, 134, 136, 138, or 140 may be a Volta® CVD / ALD chamber or an Encore® PVD chamber available from Applied Materials, Santa Clara, California.

[0025] The buffer portion 108A and the rear end portion 108B of the transfer chamber 108, as well as each chamber coupled to the transfer chamber 108, can be maintained under vacuum. As used herein, the term "vacuum" can refer to a pressure of less than 760 Torr, typically about 10 -5 Tor (that is, about 10 -3 It is maintained at a pressure of Pa. However, some high vacuum systems are about 10 -7 Tor (that is, about 10 -5 It can operate at less than Pa. In certain embodiments, vacuum is provided using rough pumps and / or turbomolecular pumps coupled to each of the transfer chamber 108 and one or more process chambers (e.g., process chambers 109-140). However, other types of vacuum pumps are also intended.

[0026] A system controller 126, such as a programmable computer, is coupled to the processing system 100 to control one or more of the components within the processing system 100. For example, the system controller 126 can control the operation of one or more of the processing chambers, such as processing chambers 132, 134, 136, 138, and 140. During operation, the system controller 126 enables the acquisition and feedback of data from each component to coordinate the processing within the processing system 100.

[0027] The system controller 126 includes a programmable central processing unit (CPU) 126A, which can operate together with memory 126B (e.g., non-volatile memory) and support circuits 126C. Conventionally, support circuits 126C (e.g., cache, clock circuit, input / output subsystem, power supply, etc., and combinations thereof) are coupled to the CPU 126A and then to various components within the processing system 100.

[0028] In some embodiments, the CPU 126A is one of any form of general-purpose computer processor, such as a programmable logic control unit (PLC), used in an industrial environment to control various monitoring system components and subprocessors. The memory 126B is coupled to the CPU 126A, is non-temporary, and is typically one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of local or remote digital storage.

[0029] In this specification, memory 126B is in the form of a computer-readable storage medium (e.g., non-volatile memory) containing instructions that, when executed by the CPU 126A, facilitate the operation of the processing system 100. The instructions in memory 126B are in the form of a program product (e.g., middleware application, device software application, etc.) such as a program that implements the method of this disclosure. The program code may conform to one of several different programming languages. In one example, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program of the program product defines the function of the embodiment (including the method described herein). Exemplary computer-readable storage media include, but are not limited to, (i) non-writable storage media on which information is permanently stored (e.g., read-only memory devices in a computer, such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid non-volatile semiconductor memory), and (ii) writable storage media on which modifiable information is stored (e.g., floppy disks in a diskette drive, or hard disk drives, or any type of solid random-access semiconductor memory). Such computer-readable storage media are embodiments of the disclosure when they have computer-readable instructions that direct the functions of the methods described herein. The various methods disclosed herein can generally be implemented by the CPU 126A executing computer instruction code stored in memory 126B (or memory of a particular processing chamber) as, for example, software routines, under the control of the CPU 126A. When the computer instruction code is executed by the CPU 126A, the CPU 126A controls the chamber to carry out the process in various ways.

[0030] Gate-all-around field-effect transistor structure The exemplary gate-all-around field-effect transistor (GAA FET) semiconductor structure 300 in Figure 3 includes a substrate 302 on which a first GAA FET module TR1 and a second GAA FET module TR2 are formed. GAA FET modules TR1 and TR2 are electrically isolated from each other by an intermodule insulating layer 304, and also from other GAA FET modules within the semiconductor structure 300 that are not shown in Figure 3. A cross-sectional view of a portion of GAA FET module TR3 is shown, and TR3 is supposed to share a portion of the substrate 302 with TR1 and TR2, forming an opening between TR2 and TR3 as described later.

[0031] As used herein, the term “substrate” refers to a material layer that serves as a basis for subsequent processing operations, and this layer includes the surface to be cleaned. The substrate 302 may be a silicon-based material, or any suitable insulating or conductive material as needed. The substrate 302 may be crystalline silicon (e.g., Si <100> Or Si <111> The materials may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The intermodule insulating layer 304 can be formed from a silicon-containing dielectric material such as silicon oxide or silicon nitride.

[0032] Each of the GAA FET modules TR1 and TR2 shown in Figure 3 includes a channel region CH and a source / drain region SD separated in the X direction by the channel region CH. The source / drain region SD can be wider in the Y direction than the channel region CH. The source / drain region SD can be isolated from other source / drain regions SD in the X, Y, and / or Z directions by an intermodule insulating layer 304.

[0033] For the purposes of discussion, the source / drain (SD) region shown in Figure 3 includes the exposed portion of the silicon-containing contact structure 308 that is exposed to a HAR opening (e.g., opening 401 in Figures 4A and 4G) formed on a region of the substrate 302 within the semiconductor structure 300. In this example, the GAA FET modules TR1 and TR2 each consist of three SD regions, but various types of FET devices may have more or fewer SD regions. In some embodiments, there may be only one SD region, or there may be hundreds of SD regions oriented in the X, Y, and / or Z directions. Silicon-containing contacts, such as the silicon-containing contact 308, may include materials useful for forming contacts, such as silicon-based materials or silicon-containing materials, such as silicon / germanium (SiGe) materials. One or more of the silicon-containing contacts 308 may, in addition or otherwise, include materials containing dopant atoms, such as n-type or p-type dopants.

[0034] Each channel region CH of the GAA FET modules TR1 and TR2 may include adjacent parallel gate structures 310 extending along the X direction within the intermodule insulating layer 304. Each gate structure 310 may include a gate metal layer and a gate dielectric layer, the gate dielectric layer being positioned between the channel region CH and the gate metal layer. In some embodiments, the gate dielectric may include a dielectric material (e.g., hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and / or titanium dioxide (TiO2)) whose dielectric constant (κ) is higher than that of silicon dioxide (SiO2) (e.g., κ = 3.9). In some embodiments, the dielectric material may be called a high-κ dielectric. In some embodiments, the gate metal layer itself may be formed from a plurality of metal layers, each composed of a conductive material. Conductive materials are not limited to these, but can include a variety of metallic alloys, metals, or conductive ceramics, including aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and one or more combinations thereof.

[0035] Example processing sequence Embodiments of this disclosure, constructed from the processing system 100 and information provided in Figures 1, 2, and 3, include a method 200 for forming a semiconductor device. Figures 4A to 4F are schematic side cross-sectional views of the portion of the semiconductor substrate shown in Figure 3 that is undergoing the process disclosed in method 200. Cross-sectional views, Figures 4A to 4F, show a portion of the semiconductor structure 300 from 4X-4X' in Figure 3, viewed along the Y direction. The process flow diagram of method 200 shown in Figure 2 can be best understood by referring to Figures 4A to 4F. Alternative embodiments utilizing method 200 in Figure 2 can be best understood by referring to Figures 4G to 4I and 4J.

[0036] Prior to the first operation 210 of Method 200, surface contamination may be present at the interface of the device features. These surface contaminations, such as native oxides, may form on one or more of the surfaces of the device features, such as silicon dioxide formed on the exposed surface. The thickness of the surface contaminants may also vary depending on the conditions of formation, such as exposure to air or oxygen when the substrate is at a high temperature.

[0037] The first operation 210 of method 200 includes exposing each contact structure 308 within a plurality of stacked contact structures 308 located within an opening 401 (Figure 4A) formed in a semiconductor substrate to a pre-cleaning process, wherein the exposed surface comprises silicon, and each of the plurality of stacked contact structures 308 is spaced apart in a first direction within the opening 401.

[0038] Exposure of each contact structure 308 within a plurality of stacked contact structures is initiated by a cleaning process carried out during a first operation 210 of Method 200, which can be carried out in a process chamber such as a processing chamber 110 or 114 within a processing system 100. In one example, the cleaning process converts all exposed silicon dioxide-containing material, including silicon dioxide of the semiconductor substrate exposed within the device features, into a reaction product material of the cleaning process, which includes a silica salt hydrate-containing material. For the sake of simplicity, the silica salt hydrate-containing material will be simply referred to as “silica salt” for the remainder of this application. In another example, the cleaning process carried out in the first operation 210 of Method 200 includes utilizing an etching process, such as an ammonium fluoride dry etching process. Both ammonium fluoride and ammonium hydrogen fluoride react with silicon dioxide using a dry etching process in the range of about -30°C to about 100°C, compared to other silicon-containing materials. For the purposes of this disclosure, the utilization of either or both ammonium fluoride (NH4F) or ammonium hydrogen fluoride (NH4F·HF) will be collectively referred to as “ammonium fluoride.” Similarly, the use of either or both ammonium fluoride or ammonium hydrogen fluoride in an etching process is referred to as the "ammonium fluoride etching process."

[0039] In one example, the cleaning process performed in the first operation 210 of Method 200 includes introducing both a hydrogen-containing precursor and a fluorine-containing precursor into the plasma / carrier gas. For example, ammonia (NH3) can be introduced as the hydrogen-containing precursor and nitrogen trifluoride (NF3) as the fluorine-containing precursor into the plasma / carrier gas mixture. By introducing both the hydrogen-containing precursor and the fluorine-containing precursor into the plasma / carrier gas, both precursors are activated at the molecular level. In this activated state, dissociation of these precursors occurs in the carrier gas to form a first plasma-dissociated hydrogen-containing precursor and a first plasma-dissociated fluorine-containing precursor. The dissociated atomic species then recombine in the carrier gas (gas phase) to form one or both of the species ammonium fluoride (NH4F) or ammonium hydrogen fluoride (NH4F·HF). In one or more embodiments, the total flow rates of the hydrogen-containing precursor and the fluorine-containing precursor, including endpoint values ​​and all values ​​in between, are in the range of about 1 volume percent (vol%) to 70 volume percent of the overall mixed gas, and the remainder of the mixed gas includes, consists of, or essentially consists of a carrier gas. In one or more embodiments, the reactive gas is provided after a purging or carrier gas is introduced into the plasma generation region.

[0040] In one example, a cleaning process such as the first operation 210 of Method 200 includes maintaining the etching rate of the ammonium fluoride etching process based on the ratio of a hydrogen-containing precursor to a fluorine-containing precursor. The larger the amount of fluorine-containing precursor relative to the hydrogen-containing precursor, the more reactive the ammonium fluoride etching solution obtained. In one or more embodiments, the molar ratio of the hydrogen-containing precursor to the fluorine-containing precursor introduced is in the range of about 1:3 to 3:1, including the endpoint value and all values ​​in between, for example, about 1:3, 1:2.5, 1:2, 1:1.5, or 1:1 to about 1.5:1, 2:1, 2.5:1, or 3:1. The molar ratio of the hydrogen-containing precursor to the fluorine-containing precursor in the etching mixed gas can be set to uniformly remove silicon oxide from the trench junction surface of all different types of semiconductor substrates.

[0041] In one or more embodiments, a cleaning process, such as the first operation 210 of Method 200, further includes maintaining the semiconductor substrate at a first deposition temperature. The first deposition temperature allows the ammonium fluoride etchant to condense from the plasma / carrier gas and deposit as a solid within the device features, including along the sidewalls and bottom of the features. In one or more embodiments, the first deposition temperature may be set to a value that prevents substantial reaction between the deposited ammonium fluoride etchant and native oxides present during deposition. The temperature of the semiconductor substrate can then be increased after deposition to facilitate control of the reaction rate of the deposited ammonium fluoride etchant. In one or more embodiments, the first deposition temperature may be set to a value that allows the ammonium fluoride etchant to deposit on the semiconductor substrate surface and react immediately or nearly immediately with silicon oxide present on the surface. The first deposition temperature may also depend on other process conditions, such as the pressure around the semiconductor substrate. In one or more embodiments, the semiconductor substrate can be maintained at a first deposition temperature, including endpoint values ​​and all values ​​in between, below 120°C, for example, in the range of about -30°C to 120°C, for example, about -30°C, -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, and 60°C to 70°C, 75°C, 80°C, 85°C, 90°C, 95°C, 100°C, 105°C, 110°C, 115°C, and 120°C, as well as in the range of about 0°C to 75°C.

[0042] Silica salts are formed during the reaction between ammonium fluoride etching solution and native oxides. One example of the silica salts formed is ammonium hexafluorosilicate hydrate ((NH4)2SiF6·H2O), which is present on the surface of the semiconductor substrate as a reaction product resulting from the presence of the native oxide layer and bare silicon dioxide. Depending on the carrier gas / reactant ratio introduced into the plasma, water, molecular hydrogen, and ammonia may also be present in the gas phase with the carrier gas. In some embodiments, silica salts formed on exposed surfaces are removed by heating the substrate to cause sublimation of the formed silica salt material and the removal of the undesirable material formed on it.

[0043] In another example, the cleaning process performed in the first operation 210 of Method 200 includes generating a plasma formed by a carrier gas. The plasma / carrier gas combination can then be introduced onto the surface of a semiconductor substrate with or without bias. In one or more embodiments, the carrier gas may include, consist of, or essentially consist of, noble gases such as argon, neon, and helium, and combinations thereof. In some examples, a hydrogen-containing gas such as H2 and a carrier gas such as argon (Ar) are introduced onto the surface of a semiconductor substrate while a bias is applied to the substrate.

[0044] Following the end of the first operation 210 of Method 200, the second operation 220 of Method 200, shown in Figure 4B, includes forming a metallic silicon compound layer on each exposed surface of the plurality of laminated contact structures 308, and forming a metallic silicon compound layer on the exposed surface includes selectively depositing the first metal layer on the exposed surface.

[0045] Figure 4B shows the metallic silicon compound layer 402 formed on the contact structure 308 and the substrate 302 by the first metal deposition process. Forming the metallic silicon compound layer 402 on each exposed surface of the laminated contact structure involves selectively depositing the first metal layer on the exposed contact structure 308. In one or more embodiments, the first metal used in the first metal deposition process includes titanium (Ti). In other embodiments, where the source / drain regions of the laminated contact structure 308 can be silicon germanium (SiGe) or other p-type material, the first metal used in the first metal deposition process is a molybdenum silicon compound (MoSi x ) may be included. In other embodiments, Mo or W can be substituted, or a combination of both materials can be used.

[0046] In one or more embodiments that can be combined with other embodiments, the first metal deposition process, such as the second operation 220 of Method 200, includes selectively depositing a metallic silicon compound layer 402, such as titanium, by any preferred chemical deposition technique, including but not limited to CVD or ALD processes. In some embodiments, the metal-containing precursor is selected from the group including titanium chloride (TiCl4), molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), molybdenum tetrachloride oxide (MoOCl4), tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or tris(3-hexine)tungsten carbonyl (W(CO)(CH3CH2C≡CCH2CH3)3). In some embodiments, the first metal deposition process is selective for the surface of the contact structure 308 compared to the dielectric material of the intermodule insulating layer 304, which can be formed from a silicon-containing dielectric material such as silicon oxide or silicon nitride. While not wishing to be constrained by theory, selective metal-silicon compound deposition processes are found in the range of about 1.5:1 to greater than 30:1, with silicon oxide (SiO2) and silicon nitride (Si x N y It is thought to have selectivity for silicon (Si) or silicon / germanium (SiGe) compared to [another material].

[0047] In one or more embodiments, the metal silicon compound layer 402 may comprise a metal such as titanium (Ti), molybdenum (Mo), cobalt (Co), nickel (Ni), or tungsten (W) formed on the surface of the contact structure 308, and such metal may have a thickness in the range of about 1 to 30 nm (about 10 to 300 Å), such as in the range of about 3 to 20 nm (about 30 to 200 Å), such as in the range of about 4 to about 25 nm (about 40 to 260 Å for the method 200A), such as in the range of about 5 to about 20 nm (about 50 to 200 Å), such as about 10 nm (about 100 Å). In one or more embodiments, which may be combined with other embodiments, the thickness of the metal silicon compound-containing material layer located on the silicon dioxide substrate may be in the range of about 0.1 to 3 nm (about 1 to 30 Å). In one or more embodiments, the target thickness of the metal silicon compound layer 402, which is the first metal layer formed on the exposed contact structure 308, is about 3 nanometers or more. In one or more embodiments, the target thickness of the metal silicon compound layer 402 formed on the contact structure 308 may be determined based on a desired corresponding Schottky barrier height. In one or more embodiments, the target thickness of the metal silicon compound layer 402 formed on the contact structure 308 may be determined based on a desired corresponding gate structure contact resistance (R c ).

[0048] In some embodiments, as part of the process of depositing the metal silicon compound layer 402, a reducing agent that reacts with the metal-containing precursor is introduced into a carrier gas together with the metal-containing precursor. The reducing agent may be a hydrogen-containing composition such as molecular hydrogen (H2), ammonia (NH3), hydrazine (N2H4), silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ), or a combination of the foregoing. The reducing agent acts as a proton donor that causes the metal-containing precursor to form a metal film containing metal on the contact structure 308.

[0049] Following the end of the second operation 220 of Method 200, the third operation 230 of Method 200, shown in Figure 4C, includes forming a second metal layer on the metallic silicon compound layer 402, and forming the second metal layer on the first metal layer includes selectively depositing the second metal layer 404 on the metallic silicon compound layer 402. In one or more embodiments, the thickness of the second metal layer 404 formed on the metallic silicon compound layer 402 can be at least about 3 nm. In one or more embodiments, the second metal layer 404 acts as a seed layer to improve the formation of one or more layers placed on the second metal layer 404, for example, as a seed layer to improve the formation of a third metal layer or conductive material placed on the second metal layer 404.

[0050] In Figure 4C, the second metal layer 404 shown is formed on the metallic silicon compound layer 402 by a second metal deposition process. In one or more embodiments, the metal used in the second metal deposition process may include a precursor containing fluorine-free tungsten (FFW). In one or more embodiments, the FFW-containing precursor may include tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten tetrachloride oxide (WOCl4), tungsten dichloride oxide (WO2Cl2), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or a combination thereof. In one or more embodiments, the metal-containing precursor may include a fluorine-free metallic organic compound such as tris(3-hexine)tungsten carbonyl (W(CO)(CH3CH2C≡CCH2CH3)3). In further embodiments, the metal used in the second metal deposition process may include molybdenum (Mo) formed by the use of a molybdenum-containing precursor such as molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), or molybdenum tetrachloride (MoOCl4).

[0051] In one or more embodiments that can be combined with other embodiments, a second metal deposition process, such as the third operation 230 of Method 200, includes selectively depositing a second metal layer 404, such as FFW, by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the chemical deposition technique may include halide-based CVD or ALD, such as WCl5 + diatomic hydrogen (H2). In one or more embodiments that can be combined with other embodiments, a second metal deposition process, such as the second operation 220 of Method 200, includes selectively depositing a second metal layer 404 by utilizing plasma together with a carrier gas. The plasma / carrier gas can then be introduced toward the surface of the semiconductor substrate. In one or more embodiments that can be combined with other embodiments, the carrier gas includes, consists of, or essentially consists of, noble gases such as argon, neon, and helium, and combinations thereof.

[0052] Following the end of the third operation 230 of Method 200, the fourth operation 240 of Method 200, shown in Figure 4D, includes forming a third metal layer 409 on the second metal layer 404, which includes conformal deposition of the third metal layer 409 onto the second metal layer 404.

[0053] In Figure 4D, the third metal layer 409 shown is formed on the second metal layer 404 by a third metal deposition process. In one or more embodiments, the metal used in the third metal deposition process may consist of a conductive material. The conductive material may include, but is not limited to, a variety of metal alloys, metals, or conductive ceramics, including aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and one or more combinations thereof.

[0054] In one or more embodiments that can be combined with other embodiments, a third metal deposition process, such as the fourth operation 240 of Method 200, includes selectively depositing the third metal layer 409 by any preferred chemical conformal deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the thickness of the third metal layer 409 formed on the second metal layer 404 can be at least about 5 nanometers (nm).

[0055] In one or more embodiments, the third metal layer 409 acts as a seed layer to improve the formation of one or more layers placed on the third metal layer 409, for example, as a seed layer to improve the formation of the next metal layer or conductive material placed on the third metal layer 409.

[0056] Following the fourth operation 240 of method 200, in which a third metal layer 409 is deposited on top of the second metal layer 404, the fifth operation 250 of method 200, shown in Figure 4E, includes filling the opening 401 with a conductive material.

[0057] Figure 4E shows an opening 401 filled with a conductive material 406 formed on the third metal layer 409 by a fourth metal deposition process. In one or more embodiments, the conductive material used in the fourth metal deposition process may include a precursor containing tungsten hexafluoride (WF6). In yet another embodiment, the conductive material used in the fourth metal deposition process may include molybdenum (Mo).

[0058] In one or more embodiments that can be combined with other embodiments, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes selectively depositing a conductive material 406, such as a precursor containing WF6, by any preferred chemical deposition technique, including but not limited to CVD or ALD. In other embodiments that can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductive material.

[0059] In yet another embodiment, which can be combined with other embodiments, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes selectively depositing the conductive material 406 to fill the opening 401 using a metal-containing precursor gas and plasma. In yet another embodiment, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes selectively depositing the conductive material 406 to fill the opening 401 using PVD, PVD and pullback, or PVD and direct selective filling.

[0060] Following the fifth operation 250 of Method 200, the sixth operation 260 of Method 200, shown in Figure 4F, includes depositing a capping layer 408 onto the conductive material 406. Figure 4F shows the capping layer 408 deposited on the conductive material 406 that fills the opening 401 by the fifth metal deposition process. In one or more embodiments, the material used in the fourth metal deposition process may include tungsten (W). In other embodiments, the conductive material used in the second metal deposition process may include molybdenum (Mo).

[0061] In one or more embodiments that can be combined with other embodiments, a fifth metal deposition process, such as the sixth operation 260 of Method 200, includes selectively depositing a capping layer 408 on the conductive material 406 filling the opening 401 by any preferred chemical deposition technique, including but not limited to CVD or ALD. In other embodiments that can be combined with other embodiments, conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes are used to deposit the capping layer 408.

[0062] In yet another embodiment, which can be combined with other embodiments, a fifth metal deposition process, such as the sixth operation 260 of Method 200, includes utilizing a metal-containing precursor gas and plasma to deposit a capping layer 408 on a conductive material 406 that fills the opening 401.

[0063] In yet another embodiment, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes selectively depositing a conductive material 406 to fill the opening 401 using PVD, PVD and pullback, or PVD and direct selective filling.

[0064] First alternative filling process An alternative embodiment utilizing method 200 in Figure 2 is best understood by referring to Figures 4G to 4I. Figures 4G to 4I show cross-sectional views of a portion of the semiconductor structure 300 according to the embodiments described herein. The cross-sectional views in Figures 4G to 4I are views along the Y direction of a portion of the semiconductor structure 300 cut off at 4X-4X' in Figure 3.

[0065] Following the third operation 230 of method 200 previously described in relation to Figure 4C, the fourth operation 240 of method 200 shown in Figure 4G includes forming a third metal layer 409 on the second metal layer 404, and forming the third metal layer 409 on the first metal layer includes depositing the third metal layer 409 on the second metal layer 404 and the substrate 302 by using a physical vapor deposition (PVD) process.

[0066] In one or more embodiments, the metal used in the third metal deposition process may consist of a conductive material. The conductive material may include, but is not limited to, a variety of metal alloys, metals, or conductive ceramics, including aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and one or more combinations thereof.

[0067] In one or more embodiments that can be combined with other embodiments, a third metal deposition process, such as the fourth operation 240 of Method 200, includes selectively depositing the third metal layer 409 by any preferred deposition technique, including but not limited to PVD, CVD, or ALD. In one or more embodiments, the thickness of the third metal layer 409 formed on the second metal layer 404 can be at least about 5 nanometers (nm).

[0068] In Figure 4G, the third metal deposition process is used to deposit a metal layer on the second metal layer 404 and the substrate 302. In one or more embodiments, the metal used in the third metal deposition process may consist of a conductive material. The conductive material may include, but is not limited to, a variety of metal alloys, metals, or conductive ceramics, including aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and one or more combinations thereof.

[0069] A third metal deposition process, such as the fourth operation 240 of Method 200, includes depositing a third metal layer 409 by the use of a PVD deposition technique. In one or more embodiments that can be combined with other embodiments, a third metal deposition process, such as the fourth operation 240 of Method 200, includes forming a third metal layer 409 by sputtering material from a target containing a metal or metal alloy containing W, Mo, Co, Ti, Ru, Cu or other useful metals. In one example, the third metal layer 409 contains W or Mo. In some embodiments, the substrate is biased during the third metal deposition process to improve the bottom reach of the formed third metal layer 409 (i.e., the third metal layer 409 at the bottom of the opening 401 in Figure 4G). The process of biasing the substrate is carried out by RF, DC, or grounding of electrodes placed within a substrate support, and the substrate is positioned on the substrate support so that it is below the PVD target during the sputtering deposition process. The thickness of the second metal layer 404 and the third metal layer 409 formed on the substrate 302 can be at least about 5 nm.

[0070] Following the fourth operation 240 of method 200 shown in Figure 4G, in which a third metal layer 409 is deposited on top of the second metal layer 404, the fifth operation 250 of method 200 shown in Figure 4H includes filling the opening 401 with conductive material 406.

[0071] Figure 4H shows an opening 401 filled with a conductive material 406 formed on the third metal layer 409 by a fourth metal deposition process. In one or more embodiments, the conductive material 406 used in the fourth metal deposition process may include a precursor containing tungsten hexafluoride (WF6). In yet another embodiment, the conductive material used in the fourth metal deposition process may include molybdenum (Mo), which can be deposited by using, for example, a molybdenum pentachloride (MoCl5) or molybdenum hexafluoride (MoF6) precursor.

[0072] In one or more embodiments that can be combined with other embodiments, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes, but is not limited to, depositing a conductive material 406, such as a precursor containing WF6, by any preferred chemical deposition technique including CVD or ALD. In other embodiments that can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductive material.

[0073] In yet another embodiment, which can be combined with other embodiments, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes utilizing a metal-containing precursor gas and plasma to deposit a conductive material 406 to fill the opening 401. In yet another embodiment, a fourth metal deposition process, such as the fifth operation 250 of Method 200, includes using PVD, PVD and pullback, or PVD and direct selective filling to selectively deposit the conductive material 406 to fill the opening 401.

[0074] Following the fifth operation 250 of Method 200 shown in Figure 4H, the sixth operation 260 of Method 200 shown in Figure 4I includes depositing a capping layer 408 onto the conductive material 406. In one or more embodiments that can be combined with other embodiments, the fifth metal deposition process, such as the sixth operation 260 of Method 200, includes depositing a capping layer 408 onto the conductive material 406 filling the opening 401 by any preferred chemical deposition technique, including but not limited to CVD or ALD. In other embodiments that can be combined with other embodiments, conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes are used to deposit the capping layer 408.

[0075] In one embodiment, which can be combined with other embodiments, a fifth metal deposition process, such as the sixth operation 260 of method 200, includes using a metal-containing precursor gas and plasma to deposit a capping layer 408 on a conductive material 406 that fills the opening 401.

[0076] Second alternative filling process Another alternative embodiment utilizing method 200 in Figure 2 is best understood by referring to Figure 4J. Figure 4J shows a cross-sectional view of a portion of the semiconductor structure 300 according to the embodiment described herein. The cross-sectional view in Figure 4J is a view along the Y direction of a portion of the semiconductor structure 300 cut off at 4X-4X' in Figure 3.

[0077] Following the conclusion of the first operation 210 described above, the second operation 220 of method 200 shown in Figure 4J includes forming a metallic silicon compound layer on each exposed surface of the plurality of laminated contact structures 308 and on the surface of the substrate 302, wherein forming the metallic silicon compound layer on the exposed surface includes selectively depositing the first metal layer on the exposed surface. In addition, as shown in Figure 4J, the third operation 230 of method 200 includes forming a second metal layer on the metallic silicon compound layer 402, wherein forming the second metal layer on the first metal layer includes selectively depositing the second metal layer 404 on the metallic silicon compound layer 402.

[0078] Figure 4J shows the metallic silicon compound layer 402 formed on the contact structure 308 and the substrate 302 by the first metal deposition process. Forming the metallic silicon compound layer 402 on each exposed surface of the laminated contact structure and the substrate 302 involves selectively depositing the first metal layer on the exposed contact structure 308. In one or more embodiments, the first metal used in the first metal deposition process includes titanium (Ti). In other embodiments, where the substrate 302 can be silicon germanium (SiGe) or other p-type material, the first metal used in the first metal deposition process is a molybdenum silicon compound (MoSi x ) may be included. In other embodiments, Mo or W can be substituted, or a combination of both materials can be used.

[0079] In one or more embodiments that can be combined with other embodiments, the first metal deposition process, such as the second operation 220 of Method 200, includes selectively depositing a metallic silicon compound layer 402, such as titanium, by any preferred chemical deposition technique, including CVD or ALD, but is not limited thereto.

[0080] The first metal deposition process is selective for the contact structure 308 and substrate 302 compared to the dielectric material of the intermodule insulating layer 304, which can be formed from a silicon-containing dielectric material such as silicon oxide or silicon nitride. While not wishing to be constrained by theory, the selective metal-silicon compound deposition process is found in the range of approximately 1.5:1 to over 30:1, with silicon oxide (SiO2) and silicon nitride (Si x N y It is thought to have selectivity for silicon (Si) or silicon / germanium (SiGe) compared to [another material].

[0081] In one or more embodiments, the thickness of the metallic silicon compound layer 402 formed on the contact structure 308 and the substrate 302 can be in the range of about 1 to 30 nm (about 10 to 300 A), for example, in the range of about 3 to 20 nm (about 30 to 200 A), for example, in the range of about 4 to about 25 nm (about 40 to 260 A in method 200 A), for example, in the range of about 5 to about 20 nm (about 50 to 20 A), for example, in the range of about 10 nm (about 100 A). In one or more embodiments that can be combined with other embodiments, the thickness of the metallic silicon compound-containing material layer located on the silicon dioxide substrate can be in the range of about 0.1 to 3 nm (about 1 to 30 A). In one or more embodiments, the target thickness of the metallic silicon compound layer 402 formed on the contact structure 308 can be determined based on a desired corresponding Schottky barrier height. In one or more embodiments, the target thickness of the metallic silicon compound layer 402 formed on the contact structure 308 can be determined based on a desired corresponding gate structure contact resistance (R c It can be determined based on the following:

[0082] In one or more embodiments, the deposition time for a first metal deposition process, such as a second operation 220 of Method 200, which includes selectively depositing a metallic silicon compound layer 402, can be less than about 100 seconds.

[0083] The second metal layer 404 shown is formed on the metallic silicon compound layer 402 by a second metal deposition process. In one or more embodiments, the metal used in the second metal deposition process may include a precursor containing fluorine-free tungsten (FFW). In one or more embodiments, the FFW-containing precursor may include tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), or tungsten hexabromide (WBr6). In yet another embodiment, the metal precursor used in the second metal deposition process may include molybdenum (Mo), such as a precursor containing molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), or molybdenum tetrachloride oxide (MoOCl4). The second metal deposition process is selective for the metallic silicon compound layer 402, which can be formed from a titanium silicon compound (TiSi2). While not wishing to be constrained by theory, a selective second metal deposition process involves silicon oxide (SiO2) and silicon nitride (Si) in a ratio of approximately 1.5:1 to over 30:1. x N y It is considered to have selectivity for TiSi2 compared to ). In one or more embodiments, the thickness of the second metal layer 404 formed on the metallic silicon compound layer 402 can be at least about 3 nm.

[0084] In one or more embodiments that can be combined with other embodiments, a second metal deposition process, such as the third operation 230 of Method 200, includes selectively depositing a second metal layer 404, such as FFW, by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the chemical deposition technique may include halide-based CVD or ALD, such as WCl5 + diatomic hydrogen (H2). In one or more embodiments that can be combined with other embodiments, a second metal deposition process, such as the second operation 220 of Method 200, includes selectively depositing a second metal layer 404 using a metal-containing precursor gas and plasma. The plasma / carrier gas can then be introduced toward the surface of the semiconductor substrate.

[0085] Following the second operation 220 and the third operation 230 of method 200 in the second alternative filling process sequence discussed in relation to Figure 4J, the remaining operations, including the fourth operation 240, the fifth operation 250, and the sixth operation 260 of method 200, are performed as described above.

[0086] As those skilled in the art will understand, one or more configurations of the same semiconductor substrate and other parts of the same semiconductor substrate and its features, such as a semiconductor substrate or a contact bond, can benefit from the processes and methods described.

[0087] This specification includes details of many specific implementations, which should be interpreted not as limitations on the scope of the claims, but as descriptions of features specific to particular implementations. Certain features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may be implemented in multiple implementations, individually, or in any preferred partial combination. Furthermore, the aforementioned features may be described as acting in a particular combination, and may even be initially claimed as such, but one or more features from a claimed combination may, in some cases, be excluded from that combination, and the claimed combination may cover partial combinations or variations of partial combinations.

[0088] This document describes specific implementations of the subject matter. As will be apparent to those skilled in the art, other implementations, modifications, and rearrangements of the described implementations are also within the scope of the following claims. Although the drawings or claims show operations in a specific order, this should not be understood as requiring that such operations be performed in a specific order or sequence shown, or that all shown operations be performed, in order to achieve the desired result (some operations can be considered optional). In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and can be implemented where deemed appropriate. Although various steps in the methods or processes of the embodiments are presented and described sequentially, it will be understood to those skilled in the art that some or all of these steps can be performed in a different order, combined or omitted, and some or all of these steps can be performed in parallel. Such steps can be performed actively or passively. The methods or processes can be repeated or expanded to accommodate multiple components or multiple users in a field environment. Therefore, their scope should not be considered limited to the specific arrangement of steps shown in the flowcharts or figures. Furthermore, the relative dimensions, arrangement, shape, and orientation of the features shown in the figures are representative. Those skilled in the art will understand that in practice, each dimension, position, shape, and orientation may differ; for example, a rectangular feature may actually be diamond-shaped or circular. Therefore, the range should not be considered limited to the specific dimensions, arrangement, shape, and orientation shown in the figures.

[0089] Furthermore, the claimed implementation is also considered applicable to a computer system comprising at least a computer implementation, a non-temporary computer-readable medium for storing computer-readable instructions for implementing the computer implementation, and computer memory interoperably coupled to a hardware processor configured to implement the computer implementation or the instructions stored in the non-temporary computer-readable medium.

[0090] Unless otherwise defined, all technical and scientific terms used have the same meaning as those commonly understood by those skilled in the art to which these systems, apparatus, methods, processes, and compositions belong.

[0091] In this disclosure, terms such as “top,” “bottom,” “side,” “above,” “below,” “up,” “down,” “upward,” “downward,” “horizontal,” and “vertical” do not refer to absolute directions. Instead, these terms relate to directions relative to a nonspecific reference plane, which may be a vertical, horizontal, or other angular orientation.

[0092] Unless otherwise explicitly indicated by the context, the singular forms “a,” “an,” and “the” can refer to multiple objects. In the claims, a reference to a singular element is intended to mean “one or more,” not “only,” unless otherwise specifically stated. Unless otherwise specifically stated, the term “some” refers to one or more.

[0093] Embodiments of this disclosure may suitably “comprise,” “consist,” or “consist essentially of” the limited features disclosed, and may be implemented without the limited features not disclosed. As used herein and in the appended claims, the words “comprise,” “has,” and “include,” and all their grammatical variations, are intended to have an open and non-restrictive meaning that does not exclude additional elements or steps.

[0094] "Optional" and "optionally" mean that the following material, event, or situation may or may not be present or occur. This description includes instances in which the material, event, or situation occurs, and instances in which it does not.

[0095] When used, the term “determining” encompasses a wide range of actions. For example, “determining” can include calculating, computing, processing, deriving, investigating, referencing, such as referencing tables, databases, or other data structures, and verifying. It can also include receiving, such as receiving information, and accessing, such as accessing data in memory. Furthermore, it can include resolving, selecting, choosing, and establishing.

[0096] When the words "approximately" or "about" are used, the term can mean that there may be a variation of up to ±10%, up to 5%, up to 2%, up to 1%, up to 0.5%, up to 0.1%, or up to 0.01% in the value.

[0097] A range can generally encompass a range from one specific value to another specific value. When such a range is expressed, it should be understood that another embodiment is a range from one specific value to another specific value, along with all specific values ​​and combinations thereof within that range.

[0098] When used, terms such as “first” and “second” are assigned arbitrarily and are merely intended to distinguish two or more components of a system, apparatus, or composition. It should be understood that the words “first” and “second” serve no other purpose, are not part of the names or descriptions of the components, and do not necessarily define the relative location or position of the components. Furthermore, it should be understood that the mere use of the terms “first” and “second” does not require the existence of a “third” component, although such a possibility may be considered within the scope of the various embodiments described.

[0099] Although only a few exemplary embodiments have been described in detail, it will be readily apparent to those skilled in the art that many modifications are possible in these exemplary embodiments without materially departing from the scope of the disclosure described herein. Therefore, all such modifications are intended to fall within the scope of this disclosure as defined in the following claims. In the claims, the means-plus-function clause is intended to encompass structures described as performing the function described, and to encompass not only structural equivalents but also equivalent structures. It is the express intention of the applicant not to exercise Section 112(f) of the U.S. Patent Act for any limitation of any claim, except where the claim expressly uses the phrase “means for” in conjunction with the relevant function.

[0100] The following claims are not intended to be limited to the embodiments provided, but rather to give the full scope consistent with the language of the claims.

Claims

1. A method for forming a contact structure on a semiconductor substrate, This involves removing material from the surface of features formed within the surface of the substrate. The aforementioned feature includes a plurality of contact structures disposed within the feature formed within the substrate, The aforementioned contact structure includes a plurality of contacts, each containing silicon (Si) or silicon germanium (SiGe), Each of the plurality of contacts is separated in a first direction by a dielectric layer, The method for removing the material is Selectively forming reaction product material on the surface of each of the plurality of contacts, and The substrate is heated to a first temperature to remove the reaction product material from each of the surfaces of the plurality of contacts. Including removal, Selectively forming a first metal layer on each of the plurality of contacts, The method for forming a second metal layer is to form a second metal layer on the first metal layer, wherein forming the second metal layer on the first metal layer includes selectively depositing the second metal layer on the first metal layer, and selectively forming the second metal layer includes exposing the surface of the selectively formed first metal layer to a precursor containing a fluorine-free metal to form the second metal layer. The aforementioned features are filled with a conductive material, wherein the conductive material contains tungsten (W) or molybdenum (Mo). The capping layer is deposited on the aforementioned conductive material. Methods that include...

2. The method according to claim 1, wherein the reaction product material includes a material containing a silica salt.

3. The method according to claim 2, wherein the silica salt-containing material comprises ammonium hexafluorosilicate.

4. The method according to claim 3, wherein the first metal layer comprises a metallic silicon compound layer containing titanium.

5. The method according to claim 1, wherein the precursor containing the fluorine-free metal includes tungsten and a halogen-containing gas.

6. The aforementioned precursor containing a fluorine-free metal is tungsten pentachloride (WCl 5 ), tungsten hexachloride (WCl 6 ), tungsten pentabromide (WBr 5 ), and tungsten hexabromide (WBr 6 The method according to claim 5, selected from the group consisting of ).

7. The method according to claim 1, wherein the precursor containing the fluorine-free metal includes molybdenum and a halogen-containing gas.

8. The aforementioned metal-containing precursor that does not contain fluorine is molybdenum pentachloride (MoCl 5 ), molybdenum hexachloride (MoCl 6 ), and molybdenum tetrachloride (MoOCl) 4 The method according to claim 7, selected from the group consisting of ).

9. The method according to claim 8, wherein filling the features with the conductive material includes selectively forming the conductive material on the first metal layer, and selectively forming the conductive material on the first metal layer includes exposing the first metal layer to a fluorine-containing precursor.

10. The method according to claim 9, wherein selectively forming the conductive material includes exposing the second metal layer to a metal precursor containing molybdenum (Mo).

11. The selective formation of the conductive material is achieved by making the second metal layer tungsten hexafluoride (WF 6 The method according to claim 9, comprising exposing a metal precursor containing )

12. The method according to claim 1, wherein the first metal layer formed on the exposed surface has a thickness of about 3 nanometers or more.

13. The method according to claim 12, wherein the first metal layer on the exposed surface includes a first metal layer target thickness determined by a corresponding Schottky barrier height (SBH).

14. The method according to claim 1, wherein the selective deposition of the second metal layer on the outer surface of the first metal layer on the exposed surface includes a second metal layer thickness of about 3 nanometers or more.

15. The method according to claim 1, wherein selectively forming a first metal layer on the plurality of contacts includes introducing a hydrogen-containing reducing agent and a first metal-containing precursor onto the contact surface, thereby forming a first metal layer on the contact surface containing silicon or silicon germanium.

16. wherein the hydrogen-containing reducing agent is molecular hydrogen (H 2 ), the method according to claim 15.

17. The method according to claim 12, wherein the first metal layer on the exposed surface includes a first metal layer target thickness determined by a corresponding gate contact structure resistance (Rc).

18. The method according to claim 1, wherein the second metal layer provides an oxygen (O) barrier, a fluorine (F) barrier, or a barrier for both O and F.

19. The method according to claim 1, wherein the second metal layer acts as a seed layer for the conductive material.

20. The method according to claim 1, further comprising forming a third metal layer on the second metal layer, wherein forming the third metal layer on the second metal layer comprises selectively depositing the third metal layer on the second metal layer.

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