Efficient binary multiplier with reduced area and power consumption

Abstract

A signed or unsigned multiplier for binary multiplication comprises a combination of logic cells consisting of standard cells or circuits in any multiplication architecture, wherein the logic cells are modified, and the modified logic cells partially replace the CMOS circuitry in a mixed-matched implementation or completely replace the CMOS circuitry in a drop-in implementation in any architecture of the signed or unsigned multiplier.

Description

[Technical Field]

[0001] References US Patent Documents U.S. Patent No. 4638449 Multiplier Architecture U.S. Patent No. 5,150,322: Mixed Radix Series / Parallel Multiplier U.S. Patent No. 5,262,976: Multibit Reencoder Multiplier U.S. Patent No. 4752905: High-speed multiplier with carry-save adder circuit U.S. Patent No. 5008850: Circuit for multiplying binary numbers U.S. Patent No. 5,337,268: Partial multiplier selector for multiplication circuits U.S. Patent No. 6446104(B1): Double-precision floating-point multiplier with 32-bit Booth coded array multiplier U.S. Patent No. 5343417: High-Speed ​​Multiplier U.S. Patent No. 5586071: Advanced High-Speed ​​Multiplier U.S. Patent No. 5181185: Parallel Multiplier Using Skip Array and Modified Wallace Tree U.S. Patent No. 5504915: Modified Wallace Tree Adder, Structure, and Method for High-Speed ​​Binary Multiplier U.S. Patent No. 4901270: 4-to-2 Adder Cell for Parallel Multiplication U.S. Patent No. 5,347,482: Multiplier Tree Using a 9:3 Adder U.S. Patent No. 5,265,043: Wallace Tree Multiplier Array with Improved Layout Topology U.S. Patent No. 6029187: Fast Regular Multiplier Architecture

[0002] Other literature A Signed Binary Multiplication Technique, Booth, Andrew Donald, The Quarterly Journal of Mechanics and Applied Mathematics, vol. IV(2): pp 236-240 (1951).

[0003] A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. Kogge, Peter and Stone, Harold. IEEE Transactions on Computers. C-22(8):786-793 (1973).

[0004] The present invention relates to the field of static logic digital circuits. More specifically, the present invention relates to a power and area-efficient implementation of a binary multiplier by introducing a novel circuit design used as a drop-in or mixed-matching implementation of a CMOS binary multiplier. [Background technology]

[0005] Multipliers are fundamental blocks in many processors. A multiplier circuit or multiplier mainly consists of three parts: (1) a partial product generator implemented by multiple AND or NAND gates, each operating on a 1-bit multiplicand and a 1-bit multiplier (referring here to a different number being multiplied than the circuit); (2) a multiplier array (also called an adder array) consisting of a series of adders that reduce the partial products to a "sum" word and a "carry-out" word by addition; and (3) a multi-bit final adder that adds the sum and carry-out words to produce a single output word, i.e., the product. Multiplying two binary numbers, i.e., an M-bit multiplicand and an N-bit multiplier, usually produces M × N partial products. Generally, the resulting product has a binary bit length of M + N - 1. In most multiplier circuits, both the multiplicand and multiplier have the same bit length N, and therefore the resulting product is 2N - 1 bit long. Binary multiplication of any integer involves multiple additions of multi-bit numbers in a similar manner to decimal multiplication.

[0006] Multiplier circuits are often constructed with accumulators to form multiplicative accumulator (MAC) or fused multiplicative addition (FMA) processing elements. These processing elements serve as building blocks for circuits that implement vector dot products, matrix-vector multiplication, and matrix-matrix multiplication. High-speed processing is required in applications such as artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC), which rely on intensive multiplication and addition. Power loss is a critical metric for evaluating multiplier performance. Other important factors are area and layout regularity. Regular architectures of multipliers are easily routed, while irregular architectures increase wiring density and area. The choice of multiplier architecture involves trade-offs between power, area, and delay.

[0007] Multipliers are classified by their operating mode, i.e., series, parallel, or shift-add, as well as by their architecture, i.e., array architecture or tree architecture. Multipliers are also classified as unsigned or signed, depending on whether they multiply only positive numbers (i.e., unsigned numbers) or signed numbers (i.e., positive and negative numbers). Array architecture multipliers are common due to their relatively simple and regular structure. However, array multipliers have higher latency compared to other multiplier architectures. Array architectures have a delay of O(N) (where N is the word length in bits of the operands). Furthermore, the array architecture involves relatively high switching activity. High switching activity is the main cause of power loss in binary multipliers.

[0008] Tree architectures have an irregular structure, resulting in a propagation delay of O(log2N). Tree multipliers are faster than array multipliers, but require more complex wiring and a larger area.

[0009] Input recoding is one of the most common methods for achieving a compact multiplier.

[0010] A method of input recoding to reduce the number of partial products is described in "A Signed Binary Multiplication Technique" by Andrew Donald Booth in The Quarterly Journal of Mechanics and Applied Mathematics Vol. IV(2), pp. 236-240 (1951). This method multiplies two signed binary numbers in two's complement notation and a (modified) higher radix to reduce the number of partial products. Booth coding is commonly used for long operands (16 bits or more) to reduce the number of partial products. However, Booth multipliers increase circuit complexity in exchange for speed (i.e., adding further circuitry used to recode the input and generate partial products in the Booth coding scheme).

[0011] U.S. Patent No. 4,638,449 presents an array architecture that relies on a radix 4 boost encoder to reduce the depth of the multiplier and improve its speed. In U.S. Patent No. 5,150,322, Smith et al. present a mixed-radix 2 and 4 encoder array multiplier for area saving and increased speed. Also, re-encoding of two or more input bits to reduce the number of partial products is described in U.S. Patent No. 5,262,976. A multiplier array structure having an added step of a reduced number and using a combination of full adders and carry-save adders to reduce carry propagation time is described in U.S. Patent No. 4,752,905. U.S. Patent No. 5,008,850 describes a multiplier that includes dedicated circuitry for classifying the multiplicand and multiplier into consecutive groups of 1s and 0s. In addition to a general number of logic AND gates that generate partial products, the multiplier includes excess circuitry, such as multiplexers, and networks of multi-input AND and OR gates that increase the area and layout complexity of the multiplier. U.S. Patent No. 5,337,268 uses a Booth algorithm multiplier with internal registers used to store encoded inputs and retrieve them sequentially to reduce multiplier latency. U.S. Patent No. 6,446,104(B1) describes a double-precision floating-point multiplier for a 32-bit Booth encoded array multiplier using a partial product accumulator with a carry-save adder, a sum register, a carry-out counter, and an expander.

[0012] Regarding tree architectures, U.S. Patents 5,343,417 and 5,586,071 describe the Wallace tree architecture, in which full and half adders are used in a multiplier to reduce partial products to sum words and carry-out words through sequential addition. As a result, specific inputs added at each adder level are designed to increase the operating speed of the multiplier. U.S. Patents 5,181,185 by Han et al. and 5,504,915 by Rarick disclose a modified Wallace tree adder that sums partial products for the purpose of improving speed. U.S. Patent 4,901,270 by Galbi et al. presents the use of a 4:2 compressed adder in a tree multiplier to further improve the speed of the multiplier. In U.S. Patent No. 5,347,482, Williams disclosed the use of a 9:3 adder in a Wallace tree, which, while offering no speed improvement over a 3:2 compressed adder, simplifies the layout and routing of multipliers by using larger basic building blocks in the tree architecture. U.S. Patent No. 5,265,043 by Naini et al. discloses a Wallace tree multiplier architecture based on carry-save adders (CSAs) arranged in an L-folding floor plan, aimed at improving layout regularity and saving space. U.S. Patent No. 6,029,187 describes a multiplier architecture that provides increased operating speed while still achieving a smaller floor plan while maintaining the structural regularity of the multiplier architecture. The multiplier was modified by replacing the full adder circuit with a compressed circuit in a manner that maintains a balance of signal propagation delays.

[0013] As can be recognized, most patents attempt to improve the power, area, and performance of multipliers by modifying the multiplier architecture (e.g., tree architecture, high radix, etc.), and very little by introducing, replacing, or modifying standard multiplier cells (standard cells are pre-designed and pre-characterized building blocks used in microprocessor designs to implement different functions, i.e., adders, XOR / XNOR gates, etc.).

[0014] It is an object of the present invention to provide an implementation of a power- and area-efficient binary multiplier by replacing the standard cells of the multiplier with more efficient cells.

[0015] It is another object of the present invention to provide an implementation of a power- and area-efficient binary multiplier applicable to any type of multiplier architecture.

[0016] It is still another object of the present invention to provide an implementation of a power- and area-efficient arbitrary-bit-precision binary multiplier that performs unsigned or signed multiplication with or without input encoding.

[0017] Other objects and advantages of the present invention will become apparent as the description proceeds. Summary of the Invention Means for Solving the Problems

[0018] The present invention relates to static CMOS logic and describes a new circuit for binary multiplication.

[0019] A signed or unsigned multiplier for binary multiplication comprises a combination of logic cells configured with standard cells or circuits in any multiplication architecture, said logic cells being modified, and the modified logic cells partially replace CMOS circuits as a mixed-match implementation or completely replace CMOS circuits as a drop-in implementation in any architecture of a signed or unsigned multiplier.

[0020] The final adder of a signed or unsigned multiplier is implemented as a mixed-match or drop-in of modified standard cells or circuits in any adder architecture.

[0021] The mantissa (in floating-point format) is multiplied using an array architecture, tree architecture, or any other architecture of the multiplier, which is implemented by a combination of modified logical cells.

[0022] The exponent (in floating-point format) is added using a multi-bit adder implemented by a combination of modified logical cells.

[0023] The modified standard cells and circuits are as follows: -Exclusive NOR -exclusive OR - Selectable logic function gates -1-bit half-adder -1-bit full adder - Adder of predetermined bit size - High fan in AND gate - High fan in OR gate You may choose from the group.

[0024] A 1-bit half-adder may be dropped into an array multiplier (i.e., replacing a known standard CMOS cell), or mixed-matched (i.e., combined with a known standard CMOS cell or circuit), and the 1-bit half-adder is a) Connecting two 1-bit inputs to multiple transistors that perform binary addition, b) A sum is generated by a first block consisting of a first group of transistors, c) A second block consisting of a second group of transistors generates a carryout. It will be implemented by [the company / organization].

[0025] A 1-bit half-adder may be dropped into or mixed-matched with a tree multiplier, and the 1-bit half-adder is a) Connecting two 1-bit inputs to a number of transistors that perform binary addition, b) A sum is generated by a first block consisting of a first group of transistors, c) A second block consisting of a second group of transistors generates a carryout. It will be implemented by [the company / organization].

[0026] A 1-bit half-adder and / or a 1-bit full-adder, or a combination thereof, can be dropped into or mixed-matched with an N-bit adder of any architecture, where N is an arbitrary word length, and the 1-bit half-adder is... a) Connecting two 1-bit inputs to a number of transistors that perform binary addition, b) The sum is generated by the first block of a 1-bit half-adder composed of the first group of transistors. c) Generate carryout using a second block of a 1-bit half-adder composed of a second group of transistors. It will be implemented by [the company / organization].

[0027] A 1-bit half-adder and / or a 1-bit full-adder, or a combination thereof, may be dropped into or mixed-matched with an N×M multiplier of any architecture, where N and M are arbitrary bit lengths, and the 1-bit half-adder is a) Connecting two 1-bit inputs to a number of transistors that perform binary addition, b) generating an sum using the first block of a 1-bit half-adder composed of the first group of transistors, and c) Generate carryout using a second block of a 1-bit half-adder composed of a second group of transistors. It may be implemented by [this method].

[0028] A single-stage high-fan-in logic AND gate may be used to quickly check whether the 8-bit exponent of an IEEE-754 floating-point 32-bit format or any other integer or floating-point binary format is all 1 for infinity checks and NaN checks. a) A pull-up stack of n-type transistors that function as AND logic gates, supplying their output to a recovery buffer that outputs the result, or b) A double-stack CMOS topology of a pull-down n-type transistor network connected to an inverter or buffer stack to compensate for circuit delay. It will be implemented by [the company / organization].

[0029] A multi-bit adder is implemented using modified logical cells to add exponents.

[0030] A single-stage high-fan-in logic NOR gate is, a) For zero checking, it is implemented by a single-stage leak-proof NOR gate implemented in tandem with another leak-proof NOR gate or a standard CMOS NOR gate, the single-stage leak-proof NOR gate having a pull-up stack of p-type transistors whose output is fed into a restore buffer whose output is the gate output, optionally b) Any number of inputs may be implemented as a pull-up stack of leak-proof NOR gates, and the stack is divided into multiple sub-stacks of fewer inputs to be concatenated.

[0031] In one embodiment, a single-stage high-fan-in logic NOR gate is implemented by a CMOS topology consisting of a double stack of pull-up p-type transistor networks connected to a stack of inverters or buffers to compensate for circuit delay.

[0032] NOR gates of different bit lengths may be implemented for zero-checking of floating-point or integer binary forms of any bit length.

[0033] An n+1 input AND gate is used in a carry-skip adder that implements a carry-skip adder wider than 4 bits, and the n+1 input AND gate may comprise a stack of n-type transistors that function as AND logic gates, with outputs fed to a restore buffer that outputs the result. Alternatively, the n+1 input AND gate may comprise a CMOS topology double stack of a pull-down n-type transistor network connected to a stack of inverters or buffers to compensate for circuit delays.

[0034] Any combination of modified half-adders and full-adders may be drop-in or mixed-matched with known CMOS full-adders and half-adders.

[0035] Selectable logic gates that perform a pre-selected logical function are: a) A first inverter connected to the output of a logic gate whose output is selectable, b) A pair of parallel-connected complementary transistors having common source and drain ports and separate gate inputs, with the common drain and source ports being the outputs of selectable logic gates, c) Multiple inputs that constitute a logic gate that can be selected to perform a specific logic function, It is equipped with.

[0036] The selectable logic gates may be configured for pre-selected logic functions.

[0037] Unless otherwise specified, all technical and / or scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Methods and materials similar to or equivalent to those described herein may be used in carrying out or testing embodiments of the present invention, although exemplary methods and / or materials are described below. In case of any conflict, the patent specification, including definitions, shall prevail. In addition, materials, methods, and examples are merely illustrative and not necessarily intended to be limiting. [Brief explanation of the drawing]

[0038] The above and other features and advantages of the present invention will be better understood through the following non-limiting detailed description relating to preferred embodiments of the invention, with reference to the accompanying drawings. [Figure 1a] Figure 1a illustrates an implementation of the full-voltage swing two-input XOR gate of the present invention, comprising a pair of parallel-connected complementary transistors having common source and drain ports and separate gate inputs, the common drain and source ports being connected to an output inverter and two pull-up (p-type) and pull-down (n-type) transistors. [Figure 1b] Figure 1b illustrates another implementation of the full-voltage swing two-input XOR gate of the present invention. [Figure 2] Figure 2 illustrates the fully voltage-swinging, two-input selectable logic gate of the present invention, which performs a pre-selected logic function. [Figure 3] Figure 3 is a circuit diagram of the 1-bit half-adder of the present invention. [Figure 4a] Figure 4a (Conventional Technology) is a circuit diagram of a 1-bit full adder. [Figure 4b] Figure 4b (prior art) is a circuit diagram of a 1-bit full adder with an inverting output. [Figure 5a] Figure 5a shows the leak-tolerant single-stage high fan-in logic (10-input AND) gate of the present invention, which includes a pull-up stack of n-type transistors that function as AND logic gates, supplying their outputs to a restoration buffer that outputs the result. [Figure 5b] Figure 5b shows a single-stage implementation of the high fan-in logic (10-input AND) gate of the present invention, which includes a CMOS topology double stack of a pull-down n-type transistor network connected to an inverter or buffer stack to compensate for circuit delay. [Figure 6a] Figure 6a shows the leakage-tolerant single-stage 8-input NOR gate of the present invention, which comprises a stack of multiple p-type transistor pull-ups, each supplying an output to a restore buffer whose output is the gate output. [Figure 6b] Figure 6b shows a single-stage implementation of the high fan-in logic (8-input NOR) gate of the present invention, comprising a CMOS topology double stack of a pull-up p-type transistor network connected to an inverter or buffer stack for outputting the result. [Figure 7a] Figure 7a shows a conventional circuit diagram of a base 4 (also known as a modified Booth decoder). It includes the Booth decoder circuit (left) and the Booth encoder circuit (right). [Figure 7b] Figure 7b is a circuit diagram of the base 4 booth decoder of the present invention. [Figure 8] Figure 8 is a block diagram of a public domain n-bit carry-skip adder. [Figure 9] Figure 9 is a block diagram of a public domain 4-bit (also called a ripple carry) carry-ripple adder. [Figure 10] Figure 10 is a block diagram of a public domain 4-bit carry-save adder. [Figure 11] Figure 11 is a block diagram of a public domain implementation of a 4x4 unsigned A and B binary array multiplier with a partial product of pij = AiBj. [Figure 12] Figure 12 is a block diagram of a public domain implementation of a 4x4 unsigned A and B binary (Wallace) tree multiplier where the partial product Pij = AiBj. [Figure 13] Figure 13 is a block diagram of a prior art implementation of an 8-bit binary Kogge-Stone parallel prefix adder for A and B, where,

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[0039] The present invention relates to a power and area-efficient implementation of a binary multiplier by introducing a new circuit design. Embodiments of the present disclosure present a new static logic circuit that can be used as a drop-in implementation in a CMOS binary multiplier (where the CMOS circuit or standard cell is completely replaced by a modified logic cell that is power and area-efficient) or as a mixed-match implementation in a CMOS binary multiplier (where the CMOS circuit or standard cell is partially replaced by a modified logic cell that is power and area-efficient).

[0040] The methods and circuits described in this invention replace standard cells in a multiplier with more efficient cells (i.e., as drop-in or mixed-matched). The methods apply to any type of multiplier architecture, including but not limited to parallel and successive multipliers, pipelined systolic arrays of processing elements including multipliers, and circuits for computing elementary functions. The multiplier methods mentioned above apply to arbitrary bit-precision, unsigned, or signed multiplication, with or without input coding.

[0041] Figure 1a shows a full-voltage-swing two-input XOR gate circuit according to an embodiment of the present invention. The two-input XOR gate circuit comprises a transmission gate with a pair of parallel-connected complementary transistors having common source and drain ports and separate gate inputs, as well as a pMOS-nMOS transistor stack, in order to reduce power and area and improve performance compared to known CMOS XOR gate circuits.

[0042] Input A is supplied to one inverter, and input B is supplied to another inverter. Inverting input B is supplied to the transmission gate via pins 1 and pMOS-nMOS stack pins 5 and 6. Inverting input A and input A are supplied to control pins 3 and 2 of the transmission gate, respectively. Output pin 8 is used for exclusive OR operation.

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[0043] Alternatively, one of the inputs is inverted (i.e., by removing one of the input inverters, the input becomes...)

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[0044] Figure 1b shows another full-voltage swing 2-input XOR gate embodiment of the present invention that saves power. Output pin 9 is for exclusive OR operation.

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[0045] Alternatively, one of the inputs is inverted (i.e., by removing one of the input inverters).

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[0046] Figure 2 shows an embodiment of a standard cell of the full-voltage swing two-input selectable logic gate of the present invention. The circuit generates different logic functions at output Z depending on the configuration of inputs X1...X6. Inputs A and B or their complementary signals are used to implement different X to implement pre-selected logic functions. i It is supplied to the pin.

[0047] Table I shows several two-input configurations that implement different logical functions (e.g., XOR, AND, NOR, OR, NAND). [Table 1] Table I

[0048] Figure 3 shows a circuit diagram of an embodiment of the 1-bit half-adder of the present invention. Two 1-bit numbers A and B are supplied to terminals 10 and 11, respectively.

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[0049] In another embodiment, the half-adder is dropped into a multibit carry-skip adder, a carry-ripple adder, or a carry-save adder, or a multibit adder of any bit length and any architecture. In yet another embodiment of the present invention, the half-adder is used to perform partial product or element summation in any multiplier of any bit length and any architecture.

[0050] In another embodiment, the modified one-bit half-adder is implemented by connecting two one-bit inputs to a number of gates of a single-type transistor that computes binary addition, and by generating the sum with a first block consisting of a first group of transistors. The carry-out is then generated by a second block consisting of a second group of transistors. Finally, the modified one-bit half-adder is dropped into or mixed-matched with an array multiplier or a tree multiplier.

[0051] In another embodiment, a modified one-bit half-adder or a modified one-bit full-adder is implemented by connecting two one-bit inputs to a number of gates of a single-type transistor that computes binary addition, and by generating the sum by a first block consisting of a first group of transistors. The carry-out is then generated by a second block consisting of a second group of transistors. Finally, the modified one-bit half-adder and / or the modified one-bit full-adder, or a combination thereof, is dropped in or mixed-matched to an N-bit adder or an N×M multiplier of any architecture, where N and M are arbitrary values.

[0052] Figure 4a (prior art) is a circuit diagram of a known CMOS 1-bit full adder with 28 transistors. Two 1-bit numbers A(14) and B(15) are supplied together with the carry-in(16).

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[0053] Figure 4b (prior art) is a circuit diagram of the 1-bit full adder shown in Figure 4a, which has an inverting output. In other words, this adder performs an inverting sum

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[0054] In one embodiment of the present invention, any XOR / XNOR gate of the present invention is used to replace a known CMOS XOR / XNOR gate in a known CMOS full adder in order to save power and area of ​​the multiplier. In yet another embodiment of the present invention, two XOR or XNOR gates of the present invention are used as replacements for a known XOR gate in a known CMOS full adder in order to save power and area.

[0055] In yet another embodiment of the present invention, the modified CMOS 1-bit full adder according to the present invention is dropped into or mixed-matched with a multi-bit adder to save power and area. In yet another embodiment of the present invention, the modified CMOS 1-bit full adder (implemented using either the XOR or XNOR gate of the present invention) is dropped into or mixed-matched with a multiplier to save power and area.

[0056] Figure 5a shows a single-stage leak-tolerant high-fan-in logic AND gate of the present invention, comprising a pull-up stack of n-type transistors that function as AND logic gates, with outputs supplied to a restore buffer that outputs the result. In an embodiment of the present invention, ten data inputs A1 to A10 are supplied to a stack 21 of n-type transistors that function as AND logic gates, with outputs supplied to a restore buffer 22 that outputs the result to 23. Inverting the gate output results in a single-stage high-fan-in logic NAND gate. In an embodiment of the present invention, the high-fan-in gate is implemented as a replacement for a known CMOS gate tree to improve power consumption and save power.

[0057] The conditions for the IEEE-754 32-bit floating-point format for zero, infinity, and NaN numbers are given in Table II below. [Table 2] Table II

[0058] Zero, infinity, and Not a Number (NaN) checks are performed before any multiplication operation. In embodiments of the present invention, an 8-input single-stage leak-tolerant AND gate is used for fast checks where the 8-bit exponents in floating-point 32-bit format (FP32) are all 1 for infinity and NaN checks. In another embodiment of the leak-tolerant AND gate of the present invention, optimal leak-tolerance operation is achieved by placing the gate in a circuit where the logic output "1" is relatively rare (e.g., infinity or NaN value). Thus, for uniformly distributed inputs where N is the number of inputs, e.g., N=8, 10 or more.

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[0059] Referring to Figure 5b, a static CMOS high fan-in logic AND gate (i.e., 10 inputs) of the present invention is shown, compensating for the RC delay of the PDN stack with a double stack of pull-down networks (PDN, 24) used to overcome parasitic resistance and capacitance, and an inverter stack 25 at the output. In embodiments of the present invention, the high fan-in gate is implemented as a replacement for a known CMOS gate tree to reduce power consumption and conserve power. In another embodiment of the present invention, the high fan-in gate is used to implement infinity and NaN checks as previously described. In yet another embodiment of the present invention, multiple stacks of PDNs in different combinations (series, parallel, and series-parallel) are implemented to compensate for the RC delay. In yet another embodiment of the present invention, other stack combinations (series, parallel, and series-parallel) of inverters or buffers are used at the output 25 to compensate for the RC delay or to control the drive current of the gate.

[0060] Referring to Figure 6a, an implementation of a single-stage leak-tolerant 8-input NOR gate comprises a pull-up stack of multiple p-type transistors, the outputs of which are fed into a restore buffer whose output is the gate output, thereby overcoming the 4-input limitation or gate tree implementation with respect to a known standard CMOS cell to save power and area.

[0061] Data inputs A1 to A8 are supplied to a stack of p-type transistors 26, which function as NOR logic gates. The output of the stack is supplied to a restore buffer 27, whose output 28 is a gate output. Inverting output 28 results in an OR logic gate.

[0062] In one embodiment of a leak-tolerant NOR gate, a 23-input NOR gate comprising a stack of 23 p-type transistors is implemented in tandem with an 8-bit NOR gate implementation to save power and area for zero checking related to IEEE-754 32-bit floating-point format. Inverting the output of the gate yields an OR gate. In another embodiment of the invention, any number of inputs are implemented as a p-type transistor stack leak-tolerant OR gate or NOR gate, where the stack is divided into multiple sub-stacks of fewer inputs that are concatenated. In another embodiment of the gate, OR gates or NOR gates of different bit lengths are implemented for zero checking of floating-point or integer binary formats of any bit length. The use of high fan-in leak-tolerant NOR gates is limited to certain applications (e.g., sparse matrix multiplication).

[0063] Figure 6b shows a static CMOS circuit of the present invention's high fan-in NOR gate, which overcomes the known four-input limit of CMOS to save power and area. A double-stack pull-up network (PUN29) is implemented to reduce RC delay, and in addition, an inverter output stack 30 is implemented to improve speed and control the gate drive current. Output inversion results in a high fan-in OR gate. In embodiments of the present invention, the gate is used in the same manner as described for the high fan-in leak-tolerant NOR gate of the present invention.

[0064] The intertwined topology 29-30 of the double stack reduces the RC delay of the stack to provide a single-stage 8-input NOR gate instead of the tree topology used to implement the high fan-in gate in the known CMOS, and is used to implement a high input count (i.e., exceeding the 4 inputs of the known CMOS).

[0065] Fig. 7a is a prior art of a modified (radix-4) Booth encoder and decoder circuit. A radix-4 encoder circuit 31 that outputs signals Neg, X1, Z, and X2 for encoding a multiplier (into a radix-4 representation) is depicted. The encoded multiplier and multiplicand are a partial product (p ij ) supplied to a decoder 32 for generation. In embodiments of the present invention, the XOR and XNOR gates of the encoder are replaced by any of the XOR and XNOR gates of the present invention. In another embodiment of the present invention, any of the XNOR gates of the modified Booth decoder are replaced with the XNOR gates of the present invention.

[0066] Fig. 7b is a circuit diagram of a modified Booth encoder implementation 33 of the present invention that saves power and area. The encoded multiplier and multiplicand are a partial product (p ij ) supplied to a decoder for generation. In another embodiment of the present invention, the XOR gates of the decoder are replaced by any of the XOR gates of the present invention.

[0067] Fig. 8 (prior art) depicts a block diagram of an n-bit carry skip adder (CSkA). Two n-bit numbers An and Bn and a carry-in 34 are added. The result is a list of numbers S0 (LSB 35) to Sn (MSB 36) and a carry-out 38 at the output of the OR gate, where the squares designated as FA are 1-bit full adder cells. The carry skip subcircuit has n+1 partial products p i =A i B i comprising an AND gate 39 with n+1 inputs supplied by .

[0068] In one embodiment of the present invention, a known CMOS 1-bit full adder in CSkA is replaced by a modified single or multiple modified 1-bit full adder according to the present invention, thereby saving power and area as previously described. In another embodiment of the present invention, the n+1 input high fan-in AND gate of the present invention is used in place of a known CMOS AND gate in a carry-skip adder 39. In yet another embodiment of the present invention, a 9-input single-stage high fan-in AND gate, exceeding that of a known CMOS (a standard cell of any single-stage CMOS is limited to 4 inputs), is dropped in to implement an 8-bit single-block carry-skip adder (exceeding that of a known CMOS 4-bit wide carry-skip adder), thereby improving performance, power, and area. In yet another embodiment, any of the high fan-in AND gates of the present invention is used to implement a single-block carry-skip adder of any bit length. In another embodiment, any mixed-match combination relating to a known CMOS full adder implemented using the XOR or XNOR gates of the present invention is implemented to improve power consumption, save area, and increase the speed of any multibit adder.

[0069] Figure 9 shows a conventional 4-bit carry-ripple adder (CRA). Two 4-bit numbers A and B, along with a carry-in of 40, are added. The FA cell specifies a 1-bit full adder cell. Output 41 is the carry-out of the addition. The list of sums S0 (LSB) to S3 (MSB) is the result of the addition.

[0070] In embodiments of the present invention, a modified 1-bit full adder is implemented using the XOR or XNOR gates of the present invention or a combination thereof, and is dropped into a CRA in place of one or more known CMOS 1-bit full adders, or mixed-matched with a known CMOS 1-bit full adder, to save power and area. In embodiments where the least significant bit is implemented by a half adder (i.e., no carry-in), the half adder of the present invention is dropped in as a substitute for a known CMOS 1-bit half adder to save area and power. In another embodiment, any mixed-matching combination with respect to a prior art full adder is implemented using the XOR or XNOR gates and / or half adders of the present invention to improve power consumption, save area, and increase the speed of a CRA of any bit length.

[0071] Referring to Figure 10, the prior art of a multibit adder, a carry-save adder (CSA), is shown for the addition of two 4-bit binary numbers A and B and a carry-in (42). The list of numbers S0 (LSB) to S3 (MSB) and the carry-out (43) provide the result.

[0072] In embodiments of the present invention, any combination of the half adder of the present invention and a modified full adder having the XOR or XNOR gate of the present invention is dropped in or mixed-matched with known CMOS full and half adders in carry-save adders of arbitrary bit length to save power and area. In yet another embodiment, the XOR implementation of the present invention is dropped in instead of known CMOS XOR gates 44 to save power and area.

[0073] Figure 11 shows the architecture of a prior art unsigned array multiplier to demonstrate the multiplication of two 4-bit numbers A × B.

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[0074] In embodiments of the present invention, any combination of the half-adder of the present invention and the modified full-adder having the XOR or XNOR gate of the present invention can be dropped in or mixed-matched in any known CMOS adder to implement any array multiplier, in order to save power and area.

[0075] Referring to Figure 12, a prior art implementation of the (Wallace) tree multiplier is shown for the multiplication of two 4-bit numbers A × B.

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[0076] Tree multipliers are faster than array multipliers and are described in U.S. Patent No. 4,638,449, No. 5150,322, No. 5262,976, and others as N 2It is commonly used in conjunction with more advanced partial product generation schemes (i.e., Booth coding) that reduce the number of partial products to less than 1. According to the present invention, a combination of the half-adder of the present invention and a modified full-adder implemented using the XOR or XNOR gate of the present invention can be dropped in or mixed-matched to known CMOS adders to implement any tree multiplier to save power and area.

[0077] Figure 13 shows an example of a conventional parallel prefix adder based on the Kogge-Stone algorithm for adding two n-digit numbers A and B (8-bit numbers in Figure 13).

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[0078] Figure 14 shows a simplified public domain block diagram of one implementation of a multiplier for two 32-bit floating-point numbers. Each of the input numbers A and B is separated into a sign bit 51, an exponent bit 52, and a mantissa bit 53. Multiplication of the two numbers results in a number with a negative sign if one of the numbers has a negative value. An XOR gate (51) is used to determine the sign bit of the product. An unsigned adder is used for exponent addition. An unsigned multiplier is used for mantissa multiplication, with or without input coding.

[0079] In one embodiment of the present invention, the XOR circuit of the present invention is used for sign calculation to save power and area. In yet another embodiment of the present invention, an 8-bit length or arbitrarily concatenated single-type adder according to the present invention (e.g., a 3-bit adder concatenated with a 5-bit adder) or any combination of different bit lengths and different types of adders is implemented for exponential addition using the method described above. In another embodiment, an adder of arbitrary bit length is implemented for exponential addition using the drop-in or mixed-matching method described above. Without limiting the scope of the present invention, other prior art architectures relating to multibit adders, such as CarryLookAhead, Kogge-Stone, Brent-Kung, Ladner-Fischer, Han-Carlson, Beaumont-Smith, Jackson, Ling, Krapchenko, Sklansky, Knowles, and others, can be implemented in any multiplier architecture using the drop-in and mixed-matching methods of the present invention.

[0080] In another embodiment of the present invention, the mantissa (mantissa portion of a floating-point number) is multiplied by 53 using an array or tree of multipliers or any other architecture relating to the drop-in and mixed-matching methods of the present invention, as described for the multipliers.

[0081] In yet another embodiment of the present invention, whenever the last part of a signed or unsigned multiplier comprises a final adder that produces the final product, the drop-in and mixed-matching methods of the present invention described for multibit adders can be implemented for any multibit adder and any concatenated single or different types of adders (e.g., a k-bit length carry-skip adder concatenated with an l-bit carry-ripple adder concatenated with an m-bit carry-save adder, and so on) to create any any combination of adders and sub-adders of any bit length and arrangement order.

[0082] The methods and circuits described in this invention apply to any bit width and any type of multiplier architecture, including but not limited to parallel and successive multipliers, pipelined systolic arrays of processing elements including multipliers, and circuits for computing elementary functions.

[0083] Furthermore, it is understood that certain features of the Invention described in the context of separate embodiments for clarity may be provided in combination in a single embodiment. Conversely, various features of the Invention described in the context of a single embodiment for brevity may be provided separately, in any preferred combination of sub-features, or as preferred in any other descriptive embodiment of the Invention. Certain features described in the context of various embodiments should not be considered essential features of the embodiment unless the embodiment would be inoperable without that element.

[0084] Although the present invention has been described in relation to specific embodiments of the invention, it will be apparent that numerous alternatives, modifications, and variations will be evident to those skilled in the art. Accordingly, it is intended to include all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

Claims

1. A signed or unsigned multiplier for binary multiplication, comprising a combination of logic cells consisting of standard cells or circuits in any multiplication architecture, wherein the modified logic cells partially replace CMOS circuits as a mixed-matching implementation or completely replace CMOS circuits as a drop-in implementation in any architecture of the signed or unsigned multiplier.

2. The multiplier according to claim 1, wherein the final adder of the signed or unsigned multiplier is implemented in any adder architecture as a modified standard cell or circuit mixed-matched or as a drop-in.

3. The floating-point multiplier according to claim 1, wherein the mantissa is multiplied using an array architecture, tree architecture, or any other architecture of the multiplier implemented by the aforementioned combination of modified logical cells.

4. The exponent is a multiplier for floating-point numbers, which is added using a multibit adder implemented by a combination of modified logical cells.

5. The standard cell and circuit are as follows: - exclusive NOR, - exclusive OR, - Selectable logic function gates, -1 bit half adder, -1 bit full adder, - Adder with predetermined bit size, - High fan in AND gate, - High fan-in OR gate A multiplier according to any one of claims 1 to 4, selected from the group.

6. A one-bit half-adder is dropped into or mixed-matched with an array multiplier, and the one-bit half-adder is a) Connecting two 1-bit inputs to multiple gates of a single-type transistor used for binary addition, b) The sum is generated by the first block of the one-bit half-adder, which is composed of the first group of transistors. c) The carry-out is generated by the second block of the one-bit half-adder, which is composed of the second group of transistors. The multiplier according to claim 2, implemented by [the specified method].

7. A one-bit half-adder is dropped into or mixed-matched with a tree multiplier, and the one-bit half-adder is d) Connecting two 1-bit inputs to multiple gates of a single-type transistor used for binary addition. e) The sum is generated by the first block of the one-bit half-adder, which is composed of the first group of transistors. f) The second block of the one-bit half-adder, which is composed of the second group of transistors, generates the carry-out. The multiplier according to claim 2, implemented by [the specified method].

8. A modified one-bit half-adder and / or a modified one-bit full-adder, or a combination thereof, can be dropped into or mixed-matched with an N-bit adder of any architecture, where N is arbitrary, and the modified one-bit half-adder is a) Connecting two 1-bit inputs to multiple gates of a single-type transistor used for binary addition, b) The sum is generated by the first block of the one-bit half-adder, which is composed of the first group of transistors. c) The carry-out is generated by the second block of the one-bit half-adder, which is composed of the second group of transistors. The multiplier according to claim 2, implemented by [the specified method].

9. A modified one-bit half-adder and / or a modified one-bit full-adder, or a combination thereof, can be dropped into or mixed-matched with an N×M multiplier of any architecture, where N and M are arbitrary, and the modified one-bit half-adder is, a) Connecting two 1-bit inputs to multiple gates of a single-type transistor used for binary addition, b) The sum is generated by the first block of the one-bit half-adder, which is composed of the first group of transistors. c) The carry-out is generated by the second block of the one-bit half-adder, which is composed of the second group of transistors. A signed or unsigned multiplier according to claim 2, implemented by [the specified method].

10. A single-stage high-fan-in logic AND gate is used for fast checks where the 8-bit exponent of a floating-point 32-bit format or any other integer or floating-point binary format is all 1 for infinity checks and NaN checks, and the single-stage high-fan-in logic AND gate is used for fast checks where the 8-bit exponent is all 1 for infinity checks and NaN checks, a) A stack of n-type transistors that function as AND logic gates, with the output supplied to a restoration buffer that outputs the result, or b) CMOS dual-stacked pull-down n-type transistor network to compensate for output delay The multiplier according to claim 3, implemented by [the specified method].

11. The multiplier according to claim 3, wherein the multibit adder is implemented using the modified logic cell for adding exponents.

12. The multiplier according to claim 3, wherein the single-stage leak-tolerant NOR gate is implemented in tandem with another leak-tolerant NOR gate, or in a double-stack CMOS topology of a pull-up p-type transistor network connected to a stack of inverters or buffers, or in tandem with a standard CMOS NOR gate, and the single-stage leak-tolerant NOR gate comprises a stack of p-type transistors whose output is supplied to a restore buffer whose output is a gate output.

13. Any number of inputs are implemented as a p-type transistor stack of leak-proof NOR gates, and the stack is divided into multiple sub-stacks of fewer inputs that are linked together, or The multiplier according to claim 5, wherein the CMOS topology NOR gate comprises a double stack of a pull-up p-type transistor network connected to a stack of inverters or buffers to compensate for circuit delay.

14. The multiplier according to claim 12, wherein the NOR gates of different bit lengths are implemented for zero checking of floating-point or integer binary forms of any bit length.

15. The multiplier according to claim 2, wherein the n+1 input high fan-in AND gates are used in a carry-skip adder that implements a carry-skip adder wider than 4 bits, and the n+1 input high fan-in AND gates comprise a stack of n-type transistors that function as AND logic gates whose outputs are fed to a restore buffer that outputs the result, or the n+1 input high fan-in AND gates comprise a double stack of pull-down networks used to overcome parasitic components and compensate for output delay.

16. The multiplier according to any one of claims 1 to 4, wherein any combination of modified half-adders and full-adders can be dropped in or mixed-matched with known CMOS full-adders and half-adders.

17. A selectable logic gate that performs a logic function, a) A first inverter whose output is connected to the output of the selectable logic gate, b) A pair of parallel-connected complementary transistors having common source and drain ports and separate gate inputs, wherein the common drain and source ports are the outputs of the selectable logic gates, c) Multiple inputs that constitute the selectable logic gate to perform a specific logical function, A selectable logic gate equipped with the following features.

18. A selectable logic gate according to claim 16, configured as an XOR gate.

19. A selectable logic gate according to claim 16, used for sign checking.

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