System and method for hybrid sampling plan generation and accurate die loss prediction

Abstract

A system, method, apparatus, and non-temporary computer-readable medium for generating inspection tool sampling plans. The system, method, apparatus, and non-temporary computer-readable medium may include generating a static sampling plan for determining a baseline for inspection, generating a dynamic sampling plan for determining excursion events, applying the static sampling plan, and applying the dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to international application PCT / CN2023 / 113385 filed on 16 August 2023 and U.S. Patent Application No. 63 / 681,737 filed on 9 August 2024, the entirety of which is incorporated herein by reference.

[0002]

[0002] Embodiments provided herein relate to the generation of inspection tool sampling plans, and more specifically to a hybrid method for improving die loss prediction from inspection results or optimizing wafer area definition and sampling budget allocation to predict die loss with improved accuracy. [Background technology]

[0003]

[0003] In the manufacturing process of integrated circuits (ICs), unfinished or finished circuit components are manufactured according to the design and inspected to ensure they are free from defects. Inspection systems utilizing charged particle (e.g., electron) beam microscopes, such as optical microscopes or scanning electron microscopes (SEMs), can be employed. As the physical size of IC components continues to shrink, accuracy and yield in defect detection become increasingly important. Various metronome tools have been developed and are used to verify that ICs are manufactured correctly. To improve defect inspection performance, computer-guided inspection (CGI) machine learning models can be used to assist the tools by indicating the areas of the wafer to be inspected. [Overview of the initiative]

[0004]

[0004] Embodiments provided herein disclose methods for generating inspection tool sampling plans, more specifically, methods for improving die loss predictions from inspection results, or methods for optimizing wafer area definitions and sampling budget allocations to improve die loss predictions.

[0005]

[0005] Some embodiments provide systems, methods, apparatus, and non-temporary computer-readable media for generating inspection tool sampling plans. Embodiments may include generating a static sampling plan for determining a baseline for inspection, generating a dynamic sampling plan for determining excursion events, applying the static sampling plan, and applying the dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that has historically had a low defect probability.

[0006]

[0006] Some embodiments provide systems, methods, apparatus, and non-temporary computer-readable media for defect detection using computer-inducible inspection sampling plans. Embodiments may include generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabricated data and a computer-generated model; applying the baseline sampling plan to a sample; and applying the excursion event sampling plan to a sample if the predicted defect probability exceeds a threshold in an area of ​​the sample that has historically had a low defect probability.

[0007]

[0007] Some embodiments provide systems, methods, apparatus and non-temporary computer-readable media for generating inspection tool sampling plans. Embodiments may include providing wafer input data to a computer-calculated defect probability prediction model; determining the defect die probability of a first region of the wafer from the computer-calculated defect probability prediction model; and generating a wafer sampling plan based on the defect die probability determined for the first region of the wafer and on a predetermined second region of the wafer.

[0008]

[0008] Other advantages of the present disclosure will become apparent when reading the following description, in conjunction with the accompanying drawings, in which specific embodiments of the present disclosure are described as examples and examples.

[0009]

[0009] The above and other aspects of the present disclosure will become clearer when the description of the exemplary embodiments is read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1]

[0010] This is a schematic diagram showing an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure. [Figure 2A]

[0011] This is a schematic diagram showing an exemplary multibeam system, which is part of the exemplary charged particle beam inspection system shown in Figure 1, consistent with embodiments of the present disclosure. [Figure 2B]

[0012] This is a schematic diagram showing an exemplary single-beam system, which is part of the exemplary charged particle beam inspection system shown in Figure 1, consistent with embodiments of the present disclosure. [Figure 3]

[0013] This is a schematic block diagram showing the throughput for generating input data, consistent with the embodiments of this disclosure. [Figure 4]

[0014] This is an exemplary flowchart of a method for predicting die loss from inspection results using a sampling plan generated from input data that defines wafer regions and per-wafer sampling budget allocations, consistent with embodiments of the present disclosure. [Figure 5]

[0015] This is an illustrative diagram of the necessary inputs for an empirical sampling plan, consistent with embodiments of the present disclosure. [Figure 6]

[0016] This is an exemplary flowchart of a method for generating a dynamic sampling plan for a wafer and predicting die loss from inspection results according to a non-uniform defect density distribution within the wafer predicted by a computer calculation model, consistent with embodiments of the present disclosure. [Figure 7]

[0017] This is an exemplary flowchart of a method for generating a dynamic sampling plan for a wafer without predetermined wafer region sampling budget allocation, consistent with embodiments of the present disclosure. [Figure 8]

[0018] An exemplary sampling plan or estimated defect die probability map consistent with embodiments of the present disclosure. [Figure 9]

[0019] This is an exemplary flowchart of a method for generating a dynamic sampling plan for a wafer without defining a predetermined wafer region and allocating a sampling budget per wafer region, consistent with embodiments of the present disclosure. [Figure 10A]

[0020] This is an example of an estimated defect die probability map used to evaluate wafer region definitions, consistent with embodiments of the present disclosure. [Figure 10B]

[0020] An exemplary cumulative defective die probability plot consistent with embodiments of the present disclosure. [Figure 11]

[0021] This is an exemplary flowchart illustrating a method for directly optimizing wafer region definition and sampling budget allocation based on die loss prediction R2 correlation scores, consistent with embodiments of the present disclosure. [Figure 12]

[0022] An exemplary sampling plan for a wafer, consistent with embodiments of this disclosure, is shown. [Figure 13]

[0023] An exemplary metrologic sampling plan for a wafer, consistent with embodiments of this disclosure, is shown. [Figure 14]

[0024] An exemplary static sampling plan portion of a hybrid sampling plan, consistent with embodiments of this disclosure, is shown. [Figure 15]

[0025] A diagram of an exemplary static sampling plan portion of a hybrid sampling plan, consistent with embodiments of this disclosure, is shown. [Figure 16]

[0026] This is an exemplary flowchart of a method for generating a wafer hybrid sampling plan consistent with embodiments of the present disclosure. [Modes for carrying out the invention]

[0011]

[0027] Herein, exemplary embodiments are described in detail, examples of which are shown in the accompanying drawings. The following description refers to the accompanying drawings, and in the accompanying drawings, unless otherwise noted, the same numbers in different drawings represent the same or similar elements. The implementations described below in the description of exemplary embodiments do not represent all implementations. Rather, they are merely examples of apparatus and methods that correspond to aspects related to the disclosed embodiments as enumerated in the accompanying claims. For example, some embodiments are described in relation to the use of electron beams, but this disclosure is not so limited. Other types of charged particle beams (including, for example, protons, ions, muons, or any other charge-carrying particles) may be applied as well. Furthermore, other imaging systems such as optical imaging, photon detection, X-ray detection, and ion detection may be used.

[0012]

[0028] Electronic devices consist of circuits formed on a single piece of semiconductor material called a substrate. Semiconductor materials can include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits can be formed together on the same silicon piece, and these are called integrated circuits or ICs. The size of these circuits has been dramatically reduced so that more circuits can be mounted on the substrate. Improving the computing power of electronic devices while reducing the physical size of the device can be achieved by greatly increasing the mounting density of circuit components such as transistors, capacitors, and diodes on the IC chip. For example, a smartphone IC chip can be about the size of a thumbnail, yet contain more than 2 billion transistors, and the size of each transistor is less than 1 / 1000th the size of a human hair.

[0013]

[0029] ICs can be manufactured using lithography, a fabrication process that involves constructing complex circuit patterns drawn on a mask deposited on a substrate. Lithography can be performed using a lithography apparatus, which is a machine that applies a radiation source (e.g., light or X-rays) onto a target area of ​​the substrate to form a desired pattern. The target area of ​​the substrate may be covered with a pattern device (e.g., a mask) that can be removed or developed after exposure to the radiation source. This process of transferring the desired pattern onto the substrate is called the patterning process. The patterning process may include a patterning step of transferring the pattern from the pattern device (e.g., a mask) onto the substrate. There may also be one or more related patterning steps, such as mask development with a developing apparatus, baking of the substrate using a baking tool, etching of the pattern onto the substrate using an etching apparatus, or other chemical and physical processing steps involved in creating the pattern on the substrate. Variations in experimental parameters (e.g., stochastic variations, errors, or noise caused by inspection or pattern processing tools) can potentially limit lithography implementation or process yield for high-volume production (HVM) of ICs and may result in defects in the IC structure.

[0014]

[0030] In the manufacturing of ICs using lithography equipment, typically many lithographic patterning steps are performed, thereby forming functional features in continuous layers on a substrate. Therefore, a critical aspect of the lithography equipment's performance is its ability to correctly and accurately position the applied pattern relative to features placed in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure with a position that can later be measured, for example, using an electron beam inspection tool. Defects can occur if the applied pattern structure or pattern layer is not precisely positioned relative to the reference marks, or if the manufacturing conditions are not optimal. The reference marks or layout define the desired structure, the dimensions of the structure, and the distances between IC structures (gates, capacitors, etc.) or between interconnection lines. This ensures that IC devices or lines do not interact with each other in undesirable ways. The structural constraints imposed by the reference layout are typically called critical dimensions. The critical dimensions of a circuit can be defined as the minimum width of a line or hole, or the minimum distance between two lines or two holes. Therefore, critical dimensions determine the overall size and mounting density of the designed IC. The goal of IC fabrication is to faithfully reproduce the original IC design on the substrate. If errors occur during fabrication, where the constructed IC design pattern does not match the reference design, this can lead to defects in the IC structure and render the IC inoperable.

[0015]

[0031] The fabrication of these ICs, which have extremely small structures or components, is a complex, time-consuming, and costly process that often involves hundreds of individual steps. Even a single error in one step can have a significant impact on the functionality of the final product. Even a single "killer defect" can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, to achieve a 75% yield for a 50-step process, the yield of each individual step must be over 99.4%, while if the yield of each individual step is 95%, the overall process yield drops to 7%.

[0016]

[0032] In IC chip manufacturing facilities, high process yield is desirable, but maintaining high wafer throughput, defined as the number of wafers processed per hour, is also essential. In particular, if operator intervention is required to check for defects, the presence of defects can affect both high process yield and high wafer throughput. Therefore, high-throughput detection and identification of micro- and nano-sized defects are desirable. One factor that can improve process yield and wafer throughput is monitoring the IC fabrication process to ensure that the desired number of defect-free ICs are produced. One method of monitoring the fabrication process is to inspect the chip circuit structure at various stages of fabrication. In this regard, inspection using tools such as charged particle beam inspection tools may be used to maintain high process yield and high wafer throughput. In wafer inspection using electron beam inspection tools, images of the wafer can be generated to measure the dimensions of the IC structure. The measured dimensions can be compared to a defect-free reference structure to determine the presence of defects in the imaged structure. If a defect is found in the structure, the fabrication process can be adjusted to reduce the likelihood of the defect recurring. However, since wafers can contain up to 1 billion IC structures, inspecting ICs for defect detection is often a time-consuming process, and the wafer may not be inspected in the correct location to identify defects.

[0017]

[0033] To alleviate the limitations of IC inspection for detecting defects across the entire wafer, typical methods have been applied to estimate or predict the total number of defective dies on a wafer at the end of production using wafer inspection results during HVM. The total number of defective dies on a wafer is called die loss per wafer. To guide the inspection for each wafer inspected during HVM, typical methods rely on an empirical or static sampling plan (e.g., a purely static sampling plan generated from a stack probe probability map). The sampling plan is a two-dimensional map of the wafer showing where a particular defective die might be located. Typical methods generate the sampling plan using hierarchical inspection results that identify defective dies from previously inspected wafers (e.g., by focusing on areas of the wafer where the defect probability was high in the past, such as the wafer edge or center). The sampling plan is divided into wafer regions, each wafer region having a determined number of dies to inspect (e.g., a sampling budget). Wafer inspection may be performed inline with wafer fabrication, and each wafer inspected during wafer fabrication is inspected according to this sampling plan. After obtaining wafer inspection results using an empirical and fixed sampling plan, the die loss of the wafer at the end of production is predicted, assuming a uniform defect density or distribution within each wafer region. The predicted die loss can be used to ensure that a satisfactory wafer yield is maintained throughout the manufacturing process and to estimate the defect rate or actual die loss per wafer at the end of production. Wafer processing continues until the batch of wafers is completely manufactured, after which the actual die loss is measured by applying probe tests to the wafers manufactured in the batch. The final metric for evaluating the accuracy of this typical method is the R of the difference between the predicted die loss per wafer and the actual die loss per wafer. 2 It is possible to calculate the correlation score.

[0018]

[0034] However, in some cases, the typical methods described above may be undesirable because they can limit the accuracy of predicting die loss per wafer from inspection results. Guiding the inspection of all wafers inspected during HVM using a fixed sampling plan may not be sensitive to the inter-wafer variations that occur during wafer processing. Therefore, this method may not be optimal in terms of efficiently capturing defective dies within each inspected wafer. Typical methods for predicting die loss also assume a uniform defect density or distribution within each wafer, which may not accurately reflect the actual defect density or distribution within the wafer. For example, a typical static sampling plan alone may miss systematic defect signatures in wafer areas where defects are rarely observed. A static sampling plan alone does not adequately address undiscovered defect mechanisms and does not effectively capture future excursion wafers. Furthermore, a static sampling plan alone relies on chance, which lacks responsiveness to new defect patterns, thereby resulting in a low defect capture rate.

[0019]

[0035] Furthermore, the wafer area and the sampling budget allocated to each wafer area may not be optimal with a fixed sampling plan to ensure a high defect capture rate for each wafer being inspected. Therefore, typical methods that guide inspection using a fixed sampling plan and assume a uniform defect density or distribution may not accurately predict the defective dies of wafers in HVM.

[0020]

[0036] Other typical methods may include model-based methods that generate defect probability estimates based on incoming wafer metronome data to create a dynamic sampling plan. The dynamic sampling plan can be used to guide wafer inspection in HVM. Typical methods may use model-based scaling factors to provide a more accurate prediction of die loss without assuming a uniform defect density or distribution within the wafer. For example, these typical methods may use a pre-trained computational model to translate the probability estimates into a dynamic sampling plan for inline electron beam inspection, thereby improving inspection efficiency by inspecting only the areas of the wafer predicted by the model to have a high defect probability. The inspection results can also be used to predict die loss per wafer at end of production (e.g., wafer probe results). The final metric for these dynamic sampling plans is the correlation R between the predicted die loss and the actual die loss. 2 , and the capture rate of excursion fingerprints.

[0021]

[0037] However, dynamic sampling plans alone may have limitations. For example, a static or semi-static electronic scanning die-level sampling plan may be preferable for the purpose of monitoring device yield in wafer fabrication, so that any yield excursion events captured by the monitoring system can be confirmed to be actual yield fluctuations rather than the result of changes in the wafer-by-wafer sampling plan. A typical, purely dynamic sampling plan can be disadvantageous in that it forces users to change their line monitoring methods and creates a risk of baseline instability.

[0022]

[0038] In addition, a simple dynamic sampling plan is generated from model probability predictions based on inline metrology values. Due to throughput constraints, the data used by sampling plans based on inline metrology is typically far sparser compared to the probe data available for all dies on the wafer. Therefore, the resolution and accuracy of model prediction results from dynamic sampling plans alone can be limited. For example, dynamic sampling plans alone may lead to insufficient defect capture capability and the loss of defect fingerprints. Dynamic sampling plans alone do not adequately address unknown defect mechanisms and do not effectively capture future excursion wafers.

[0023]

[0039] Embodiments of this disclosure address the aforementioned constraints by generating a hybrid sampling plan that includes a static sampling plan portion and a dynamic sampling plan portion. For example, the static sampling plan portion can maintain a stable baseline by sampling the wafer at locations where wafer defects have previously been present. The dynamic sampling plan portion generates an excursion event sampling plan based on fabrication data and a computer simulation model, thereby taking into account non-uniform defect density or distribution within the wafer and improving the resolution and accuracy of the model.

[0024]

[0040] The relative dimensions of components in the drawings may be exaggerated for clarity. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only the differences relating to individual embodiments are described. Where used herein, unless otherwise specified, the term "or" encompasses all possible combinations unless impossible. For example, if it is stated that a component may include A or B, then unless otherwise specified or impossible, the component may include A or B or A and B. As a second example, if it is stated that a component may include A, B, or C, then unless otherwise specified or impossible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, and B, and C.

[0025]

[0041] Without limiting the scope of this disclosure, some embodiments may be described in connection with providing detectors and detection methods in systems utilizing electron beams. However, this disclosure is not limited in that way. Other types of charged particle beams may also be applied. Furthermore, the systems and methods for detection may also be used in other imaging systems such as optical imaging, photon detection, X-ray detection, and ion detection.

[0026]

[0042] Figure 1 shows an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. The EBI system 100 may be used for imaging. As shown in Figure 1, the EBI system 100 includes a main chamber 101, a loading / locking chamber 102, an electron beam tool 104, and an instrument front-end module (EFEM) 106. The electron beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional loading ports. The first loading port 106a and the second loading port 106b receive wafer front-opening integrated pods (FOUPs) containing wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples may be used interchangeably). A “lot” is a group of wafers that may be loaded for processing as a batch.

[0027]

[0043] One or more robotic arms (not shown) of the EFEM 106 may transport a wafer to the loading / locking chamber 102. The loading / locking chamber 102 is connected to a loading / locking vacuum pump system (not shown) that removes gas molecules from within the loading / locking chamber 102 to a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from the loading / locking chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules from within the main chamber 101 to a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by an electron beam tool 104. The electron beam tool 104 may be a single-beam system or a multi-beam system.

[0028]

[0044] The controller 109 is electronically connected to the electron beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. In Figure 1, the controller 109 is shown as being outside the structure, which includes the main chamber 101, the loading / locking chamber 102, and the EFEM 106, but it is understood that the controller 109 may also be part of the structure.

[0029]

[0045] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or dedicated electronic device capable of manipulating or processing information. For example, a processor may include any number or any combination of a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a composite programmable logic device (CPLD), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), and any type of circuitry capable of data processing. A processor may also be a virtual processor, comprising one or more processors distributed across multiple machines or devices connected via a network.

[0030]

[0046] In some embodiments, the controller 109 may further include one or more memories (not shown). The memories may be general-purpose or dedicated electronic devices capable of storing code and data accessible by the processor (e.g., via a bus). For example, the memories may include any number of random-access memories (RAM), read-only memories (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code may include an operating system (OS) and one or more application programs (or "apps") for a particular task. The memories may also be virtual memories, including one or more memories distributed across multiple machines or devices connected via a network.

[0031]

[0047] Embodiments of the present disclosure may provide a single-charged particle beam imaging system ("single-beam system"). Compared to a single-beam system, a multi-charged particle beam imaging system ("multi-beam system") may be designed to optimize throughput for different scanning modes. Embodiments of the present disclosure provide a multi-beam system with the ability to optimize throughput for different scanning modes by using beam arrays having different geometries and adapted to different throughput and resolution requirements.

[0032]

[0048] Referring here to Figure 2A, Figure 2A is a schematic diagram showing an exemplary electron beam tool 104, which includes a multibeam inspection tool that is part of the EBI system 100 of Figure 1, consistent with embodiments of the present disclosure. In some embodiments, the electron beam tool 104 may operate as a single-beam inspection tool that is part of the EBI system 100 of Figure 1. The multibeam electron beam tool 104 (also referred to herein as apparatus 104) includes an electron source 201, a Coulomb aperture plate (or "Gun aperture plate") 271, a focusing lens 210, a source conversion unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by the motorized stage 209 for holding a sample 208 to be inspected (e.g., a wafer or photomask). The multibeam electron beam tool 104 may further include a secondary projection system 250 and an electron detection device 240. The primary projection system 230 may include an objective lens 231. The electronic detection device 240 may include a plurality of detection elements 241, 242, and 243. The beam separator 233 and the deflection scanning unit 232 may be positioned inside the primary projection system 230.

[0033]

[0049] The electron source 201, Coulomb aperture plate 271, focusing lens 210, radiation source conversion unit 220, beam separator 233, deflection scanning unit 232, and primary projection system 230 can be aligned with the primary optical axis 204 of the device 104. The secondary projection system 250 and electron detection device 240 can be aligned with the secondary optical axis 251 of the device 104.

[0034]

[0050] The electron source 201 may include a cathode (not shown) and an extractor or anode (not shown). During operation, the electron source 201 is configured to emit primary electrons from the cathode, which are extracted or accelerated by the extractor and / or anode to form a primary electron beam 202 that forms a primary beam crossover (virtual or real) 203. The primary electron beam 202 can be visualized as being emitted from the primary beam crossover 203.

[0035]

[0051] The radiation source conversion unit 220 may include an image forming element array (not shown), an aberration compensator array (not shown), a beam limiting aperture array (not shown), and a pre-bending micro-deflector array (not shown). In some embodiments, the pre-bending micro-deflector array deflects multiple primary beamlets 211, 212, 213 of the primary electron beam 202 so that they are incident perpendicularly to the beam limiting aperture array, the image forming element array, and the aberration compensator array. In some embodiments, the device 104 may operate as a single-beam system so that a single primary beamlet is generated. In some embodiments, the focusing lens 210 is designed to focus the primary electron beam 202 so that it becomes a parallel beam and is incident perpendicularly to the radiation source conversion unit 220. The image forming element array may include one micro-deflector or microlens for each of the primary beamlets 211, 212, and 213 to influence a plurality of primary beamlets 211, 212, and 213 of the primary electron beam 202 and to form a plurality of parallel images (virtual or real images) of the primary beam crossover 203. In some embodiments, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include a plurality of microlenses to compensate for the field curvature aberration of the primary beamlets 211, 212, and 213. The astigmatism compensator array may include a plurality of micro-astigmatism correctors to compensate for the astigmatism of the primary beamlets 211, 212, and 213. The beam limiting aperture array may be configured to limit the diameter of the individual primary beamlets 211, 212, and 213. Figure 2A shows three primary beamlets 211, 212, and 213 as an example, and it is understood that the radiation source conversion unit 220 can be configured to form any number of primary beamlets. The controller 109 can be connected to various parts of the EBI system 100 in Figure 1, such as the radiation source conversion unit 220, the electron detection device 240, the primary projection system 230, or the motorized stage 209. In some embodiments, the controller 109 can perform various image and signal processing functions, as will be described in more detail below.The controller 109 can also generate various control signals to control the operation of the charged particle beam inspection system.

[0036]

[0052] The focusing lens 210 is configured to focus the primary electron beam 202. The focusing lens 210 may be further configured to adjust the currents of the primary beamlets 211, 212, and 213 downstream of the radiation source conversion unit 220 by changing the focusing force of the focusing lens 210. Alternatively, the currents may be changed by changing the radial size of the beam limiting apertures in the beam limiting aperture array corresponding to each primary beamlet. The currents may be changed by changing both the radial size of the beam limiting apertures and the focusing force of the focusing lens 210. The focusing lens 210 may be an adjustable focusing lens configured such that the position of the first principal plane is movable. The adjustable focusing lens may be configured to be magnetic, as a result, the off-axis beamlets 212 and 213 may irradiate the radiation source conversion unit 220 with a rotation angle. The rotation angle changes with the focusing force of the adjustable focusing lens or the position of the first principal plane. The focusing lens 210 may be a rotation-preventing focusing lens configured to maintain a constant rotation angle while the focusing force of the focusing lens 210 is changed. In some embodiments, the focusing lens 210 may be an adjustable rotation-preventing focusing lens in which the rotation angle does not change when the focusing force and the position of the first principal plane are changed.

[0037]

[0053] The objective lens 231 may be configured to focus beamlets 211, 212, and 213 onto the sample 208 for inspection, and in this embodiment, three probe spots 221, 222, and 223 may be formed on the surface of the sample 208. The Coulomb aperture plate 271 is configured to block peripheral electrons of the primary electron beam 202 during operation to reduce the Coulomb effect. The Coulomb effect can enlarge the size of each of the probe spots 221, 222, and 223 of the primary beamlets 211, 212, and 213, and thus degrade the inspection resolution.

[0038]

[0054] The beam separator 233 may be, for example, a Wien filter including an electrostatic deflector that generates an electrostatic dipole field and a magnetic dipole field (not shown in Figure 2A). When in operation, the beam separator 233 may be configured to exert an electrostatic force on the individual electrons of the primary beamlets 211, 212, and 213 by the electrostatic dipole field. This electrostatic force is equal in magnitude to the magnetic force exerted on the individual electrons by the magnetic dipole field of the beam separator 233, but in the opposite direction. Therefore, the primary beamlets 211, 212, and 213 can pass through the beam separator 233 at least substantially in a straight line with at least a substantially zero deflection angle.

[0039]

[0055] The deflection scanning unit 232 is configured to deflect the primary beamlets 211, 212, and 213 to scan probe spots 221, 222, and 223 across individual scanning areas in one section of the surface of sample 208 when in operation. In response to the primary beamlets 211, 212, and 213 or probe spots 221, 222, and 223 being incident on sample 208, electrons emerge from sample 208, generating three secondary electron beams 261, 262, and 263. Each of the secondary electron beams 261, 262, and 263 typically contains secondary electrons (with electron energy ≤ 50 eV) and backscattered electrons (with electron energy between 50 eV and the landing energies of the primary beamlets 211, 212, and 213). The beam separator 233 is configured to deflect the secondary electron beams 261, 262, and 263 toward the secondary projection system 250. Next, the secondary projection system 250 focuses the secondary electron beams 261, 262, and 263 onto the detection elements 241, 242, and 243 of the electron detection device 240. The detection elements 241, 242, and 243 are arranged to detect the corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals, which are transmitted to the controller 109 or a signal processing system (not shown) to construct, for example, an image of the corresponding scanning area of ​​the sample 208.

[0040]

[0056] In some embodiments, detection elements 241, 242, and 243 detect the corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109). In some embodiments, each detection element 241, 242, and 243 may include one or more pixels. The intensity signal output of a detection element may be the sum of the signals generated by all pixels within the detection element.

[0041]

[0057] In some embodiments, the controller 109 may include an image processing system including an image acquirer (not shown) and storage (not shown). The image acquirer may include one or more processors. For example, the image acquirer may include a computer, server, mainframe host, terminal, personal computer, any kind of mobile computing device and the like, or a combination thereof. The image acquirer may be communicably coupled to the electronic detection device 240 of the apparatus 104 through a medium such as a conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the internet, a wireless network, wireless communication, or a combination thereof. In some embodiments, the image acquirer may receive signals from the electronic detection device 240 and construct an image. Thus, the image acquirer may acquire an image of sample 208. The image acquirer may also perform various post-processing functions such as contour generation and overlaying indicators onto the acquired image. The image acquirer may be configured to perform adjustments such as brightness and contrast of the acquired image. In some embodiments, the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. Storage can be coupled to the image acquirer and used to store scanned raw image data as the original image and to store the processed image.

[0042]

[0058] In some embodiments, the image acquirer may acquire one or more images of a sample based on an imaging signal received from the electronic detection device 240. The imaging signal may correspond to a scanning operation for charged particle imaging. The acquired image may be a single image containing multiple imaging areas. The single image may be stored in storage. The single image may be a source image that can be divided into multiple regions. Each region may contain one imaging area containing features of the sample 208. The acquired image may contain multiple images of a single imaging area of ​​the sample 208, sampled multiple times in time series. The multiple images may be stored in storage. In some embodiments, the controller 109 may be configured to perform an image processing step using multiple images of the same location of the sample 208.

[0043]

[0059] In some embodiments, the controller 109 may include a measurement circuit (e.g., an analog-to-digital converter) to acquire the distribution of detected secondary electrons. The electron distribution data collected during the detection time window, in combination with the corresponding scanning path data of each primary beamlet 211, 212, and 213 incident on the wafer surface, can be used to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structure of sample 208, thereby revealing any defects that may be present in the wafer.

[0044]

[0060] In some embodiments, the controller 109 may control the motorized stage 209 to move the sample 208 during inspection. In some embodiments, the controller 109 may allow the motorized stage 209 to move the sample 208 continuously in a certain direction at a constant speed. In other embodiments, the controller 109 may allow the motorized stage 209 to change the speed at which the sample 208 moves over time in accordance with the steps of the scanning process.

[0045]

[0061] Figure 2A shows that the apparatus 104 uses three primary electron beams, but it is understood that the apparatus 104 may use one, two, or more primary electron beams. This disclosure does not limit the number of primary electron beams used in the apparatus 104. In some embodiments, the apparatus 104 may be a SEM used for lithography. In some embodiments, the electron beam tool 104 may be a single-beam system or a multi-beam system.

[0046]

[0062] For example, as shown in Figure 2B, the electron beam tool 100B (also referred to herein as apparatus 100B) may be a single-beam inspection tool used in an EBI system 10, consistent with embodiments of the present disclosure. Apparatus 100B includes a wafer holder 136 supported by an electric stage 134 to hold a wafer 150 to be inspected. The electron beam tool 100B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. The electron beam tool 100B further includes a beam limiting aperture 125, a focusing lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 may be a modified SORIL lens and includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. In the imaging process, the electron beam 161 emitted from the tip of the cathode 103 is accelerated by the anode 121 voltage, passes through the gun aperture 122, the beam limiting aperture 125, and the focusing lens 126, and is focused to a probe spot 170 by a modified SORIL lens, which can then collide with the surface of the wafer 150. The probe spot 170 can be scanned across the surface of the wafer 150 by a deflector such as the deflector 132c or other deflectors of the SORIL lens. Secondary particles or scattered primary particles, such as secondary electrons or scattered primary electrons emitted from the wafer surface, can be collected by the detector 144 to determine the beam intensity, thereby allowing an image of the target area on the wafer 150 to be reconstructed.

[0047]

[0063] An image processing system 199 including an image acquirer 120, storage 130, and a controller 109 may also be provided. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, server, mainframe host, terminal, personal computer, any kind of mobile computing device and the like, or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the electron beam tool 100B through a medium such as a conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the internet, wireless network, wireless communication, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and construct an image. Thus, the image acquirer 120 may acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions such as contour generation and overlaying indicators onto the acquired image. The image acquirer 120 may be configured to perform adjustments such as brightness and contrast of the acquired image. The storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, or other types of computer-readable memory. The storage 130 can be coupled with the image acquirer 120 and may be used to store scanned raw image data as the original image and to store the post-processed image. The image acquirer 120 and the storage 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated together as a single electronic control unit.

[0048]

[0064] In some embodiments, the image acquirer 120 may acquire one or more images of a sample based on imaging signals received from the detector 144. The imaging signals may correspond to scanning operations for charged particle imaging. The acquired image may be a single image containing multiple imaging areas that may contain various features of the wafer 150. The single image may be stored in the storage 130. Imaging may be performed based on imaging frames.

[0049]

[0065] The focusing and illumination optics of an electron beam tool may include or be complemented by electromagnetic quadrupole electron lenses. For example, as shown in Figure 2B, the electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, the first quadrupole lens 148 may be controlled to adjust the beam current, and the second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0050]

[0066] Figure 2B shows a charged particle beam apparatus in which the inspection system may use a single primary beam that can be configured to generate secondary electrons by interacting with the wafer 150. The detector 144 may be positioned along the optical axis 105, as in the embodiment shown in Figure 2B. The primary electron beam may be configured to move along the optical axis 105. Thus, the detector 144 may include a hole in its center so that the primary electron beam can pass through and reach the wafer 150.

[0051]

[0067] Referring here to Figure 3, which is an exemplary block diagram for generating input data consistent with embodiments of the present disclosure. The input data may be generated using two steps as shown in Figure 3. A lithography projection apparatus 301 may be used to fabricate a wafer under certain fabrication conditions (e.g., focus and dose of the radiation source). An inspection tool 302 (e.g., EBI system 100 in Figure 1, electron beam tool 104 in Figure 2A, electron beam tool 100B in Figure 2B) may be used to measure metronome information of structures formed on the wafer generated by the lithography projection apparatus 301. Metrology information may include, but is not limited to, necking, line pullback, thinning, critical dimensions, edge alignment, overlap (e.g., interlayer overlays of the wafer), resist top loss, resist undercut, missing defects, and bridge defects of the IC structure on the wafer. A processor 303 having memory (for example, controller 109 in Figure 1, controller 109 in Figure 2A, and controller 109 in Figure 2B) can be communicated to the inspection tool 302 and stored in the measured metronome information.

[0052]

[0068] Images generated by the inspection tool 302 can be used for wafer inspection. For example, a generated image capturing a test device region of a wafer can be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and may not contain known defects. If the difference between the generated image and the reference image exceeds an acceptable level, a potential defect may be identified. As another example, the inspection tool 302 may scan multiple regions of a wafer, each containing a test device region designed similarly, and generate multiple images capturing those test device regions during manufacturing. The multiple images can be compared with each other. If the differences between the multiple images exceed an acceptable level, a potential defect may be identified.

[0053]

[0069] In some embodiments, the processor 303 may be a general-purpose or dedicated electronic device capable of manipulating or processing information. For example, the processor 303 may include any number of central processing units (or "CPUs"), graphics processing units (or "GPUs"), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), composite programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), systems-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination of any type of circuitry capable of data processing. The processor 303 may also be a virtual processor comprising one or more processors distributed across multiple machines or devices connected via a network.

[0054]

[0070] In some embodiments, the processor 303 may further include one or more memories (not shown). The memories may be general-purpose or dedicated electronic devices capable of storing code and data accessible by the processor (e.g., via a bus). For example, the memories may include any number of random-access memories (RAM), read-only memories (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code and data may include an operating system (OS) and one or more application programs (or "apps") for a particular task. The memories may also be virtual memories, including one or more memories distributed across multiple machines or devices connected via a network.

[0055]

[0071] Current prediction methods for estimating the formation of defective dies during wafer processing and predicting die loss at the end of wafer processing rely on the use of empirical and static sampling plans for wafer inspection. A sampling plan can be generated by compiling hierarchical inspection results (e.g., probe data from one or more wafers) (e.g., hierarchical probe data containing die defect data from multiple wafers during inspection) that identify specific locations of wafer defects. In some embodiments, generating this sampling plan may involve generating a probability estimation map based on hierarchical probe data from multiple samples by averaging the hierarchical probe data (e.g., averaging a stacking map; the probability estimate from stacking / averaging may be the number of wafers with defects in the die divided by the total number of wafers), and generating a static sampling plan based on the generated probability estimation map. In some embodiments, applying this sampling plan involves inspecting samples within areas corresponding to historically high defect probabilities (e.g., the gray area of ​​wafer 1001 in Figure 10A, the sampling area in sampling plan 1210 in Figure 12).

[0056]

[0072] This sampling plan is also used for each wafer inspected during wafer processing and is therefore considered "fixed" or "static." Once the wafer inspection results are obtained via the static sampling plan, the predicted die loss can be calculated via the following formula.

number

[0057]

[0073] In equation 1,

number

number

number

number

number

[0058]

[0074] In addition to assuming a uniform defect density or distribution within the wafer region, the static method requires a predetermined wafer region definition and a wafer region-specific sampling budget allocation in the sampling plan. However, this may limit the accuracy of the predicted die loss (e.g., below optimal R). 2 (Correlation score). This is because defect density or distribution may not be uniform within a wafer region, and given wafer region definitions and per-wafer region sampling budget allocations can be highly empirical. Furthermore, static methods maintain the same wafer region definition and per-wafer region sampling budget allocation for all incoming wafers. This can limit the versatility of static methods for accurately predicting die loss across various wafers, because each wafer may have a different optimal wafer region definition or per-wafer region sampling budget. This can lead to the sampling plan inaccurately guiding inspection tools during wafer inspection in the HVM, resulting in missed defects and therefore inaccurate die loss predictions (e.g., below optimal R). 2(Correlation score). In other words, static methods can result in a sampling plan that guides the inspection tool to the same area for each sample without considering defects in other areas of the sample. Therefore, this reduces the yield and throughput of defect-free wafers during HVM.

[0059]

[0075] In some embodiments, the accuracy of the predicted die loss can be improved by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan and a dynamic sampling plan (e.g., method 600 in Figure 6, method 700 in Figure 7, method 900 in Figure 9 using wafer 801 in Figure 8, method 1001 in Figure 10A using the plot in Figure 10, and method 1100 in Figure 11) to sample the wafer at locations that have historically had wafer defects (e.g., sampling the wafer at locations that have historically tended to have defects or are known to have defects), while taking into account the density or distribution of non-uniform defects within the wafer. For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-generated model (e.g., based on a scanner recipe in a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0060]

[0076] Referring now to Figure 4, Figure 4 is an exemplary flowchart of a method 400 for predicting wafer die loss according to inspection results collected from an empirical and static (e.g., constant across wafers) sampling plan with fixed wafer region definitions and per-wafer region sampling budget allocation, consistent with embodiments of the present disclosure. The steps in Figure 4 may be performed by a computing device (e.g., processor 303 in Figure 3) and an inspection tool (e.g., inspection tool 302 in Figure 3).

[0061]

[0077] In step 401, an empirical sampling plan is generated. The sampling plan may be generated based on historical data from a previously inspected wafer or a batch of previously inspected wafers. The historical data may be inspection images containing identified defects on the wafer. Therefore, the generated sampling plan may include this historical defect signature. Furthermore, the sampling plan is generated according to a predetermined wafer region definition and a sampling budget per wafer region.

[0062]

[0078] In step 402, an empirical sampling plan is used to guide the inspection of wafers using inspection tools. For example, the sampling plan may be used to guide the inspection tools during wafer inspection. Wafer inspection is performed according to a predetermined sampling budget for each wafer area in the sampling plan. Wafer inspection is performed inline with respect to the HVM. The number of dies inspected in the first wafer area is equal to the sampling budget for the first wafer area, and the same applies to the second wafer area.

[0063]

[0079] In step 403, the obtained inspection results are used to predict the die loss of the wafer at the end of the wafer processing. For example, the die loss of the wafer may be predicted for the wafer after development, etching, etc. The die loss prediction may be performed as described above in Equations 1 and 2 (for example, assuming that the defect density or distribution within the wafer region is uniform).

[0064]

[0080] In step 404, the actual die loss is obtained by applying a probe test to the wafer at the end of the wafer processing. In some embodiments, the probe results may be applied to the wafer at various steps of the wafer processing (e.g., after development, after etching, etc.). The probe test determines whether each die on the wafer is defective or not. In step 405, from the actual die loss and the predicted die loss, R 2 The correlation score is evaluated. 2 It should be understood that the correlation score can be determined from a set of wafers. The first and second wafers may be inspected according to step 402, and two predicted die loss values ​​may be determined according to step 403. The first and second wafers at the end of wafer processing may be measured according to step 404 to obtain two actual die loss values. In some embodiments, the first layer of a wafer and the second layer of the same wafer may be inspected according to step 402, and two predicted die loss values ​​may be determined according to step 403. The wafer at the end of wafer processing may be measured according to step 404 to obtain an actual die loss value.

[0065]

[0081] In some embodiments, the accuracy of the predicted die loss can be improved by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both method 400 and a dynamic sampling plan (e.g., method 600 in Figure 6, method 700 in Figure 7, method 900 in Figure 9 using wafer 801 in Figure 8, method 1001 in Figure 10A using the plot in Figure 10, and method 1100 in Figure 11) to sample the wafer at locations that have historically had wafer defects (e.g., sampling the wafer at locations that have historically tended to have defects or are known to have defects), while taking into account the density or distribution of non-uniform defects within the wafer. For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-generated model (e.g., based on a scanner recipe in a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0066]

[0082] Referring now to Figure 5, which is an illustrative diagram of the necessary inputs for an empirical sampling plan consistent with embodiments of the present disclosure. Figure 5 shows a wafer 501 having a first wafer region 502, a second wafer region 503, and a third wafer region 504. Each wafer region has a corresponding sampling budget. Each wafer region definition and the corresponding per-wafer region sampling budget may not have to be adjusted according to conventional methods. Furthermore, each wafer region definition is kept constant for each wafer being inspected.

[0067]

[0083] Relying solely on static methods to generate empirical sampling plans with predetermined wafer area definitions and per-wafer sampling budget allocations can lead to inaccurate guidance of inspection tools during wafer inspection, potentially reducing inspection yield throughput. Furthermore, relying on a constant wafer area definition and per-wafer sampling budget allocation for all incoming wafers, and assuming a uniform defect density distribution within each wafer area, can make it difficult to accurately predict die loss for different wafers during HVM, and thus ensure the maintenance of the desired wafer yield.

[0068]

[0084] In some embodiments of this disclosure, these limitations from static methods alone can be improved by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan (e.g., method 600 in Figure 6, method 700 in Figure 7, using wafer 801 in Figure 8, method 900 in Figure 9, using wafer 1001 in Figure 10A, using plot in Figure 10, and method 1100 in Figure 11) to sample the wafer at locations that have historically had wafer defects (e.g., sampling the wafer at locations that have historically tended to have defects or are known to have defects), taking into account the density or distribution of non-uniform defects within the wafer. For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabricated data and a computer-generated model (for example, based on a scanner recipe in a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0069]

[0085] With regard to dynamic sampling plans, embodiments of the present disclosure may provide a model-based approach for predicting die loss during wafer processing. A computation guided inspection (CGI) process guides an inspection tool to locations on a wafer where the probability of defects is high. A machine learning-based CGI model receives inputs from a variety of data sources to train the model, including wafer characteristic data, which may include scanner data, metrology data, and fabrication process data, and data from inspection results. Because the CGI machine learning model can be constructed and used to output a sampling plan indicating locations on a wafer where defects are likely to have formed after a wafer processing step, the inspection tool moves to the sampling locations to perform inspection that is more efficient than inspecting wafer locations based on experience (e.g., a history of previous defects detected during scanning). In some embodiments, the machine learning-based CGI model can be trained using historical data (e.g., history of previous defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan. The CGI process is performed inline for wafer fabrication, increasing the efficiency of the inspection tool by increasing the accuracy of finding defects on the wafer with a higher defect capture rate than a baseline value. Inspection results can be used to confirm that satisfactory wafer yield is maintained throughout manufacturing, and to predict defect rate or die loss per wafer at the end of production. This predicted defect rate may be compared to the results of a wafer probe test, whereby the defect rate is determined for each die fabricated on the wafer. The final metric for a use case of a CGI model is the R between estimated die defects and measured die defects on the wafer 2 square correlation score.

[0070]

[0086] A CGI model can be applied to characteristic wafer data to estimate the defect probability of each die on the wafer. A sampling plan optimizer or sampling plan generator then converts the estimated defect die probability for each die on the wafer into a die-level sampling decision wafer map (also known as a sampling plan). In some embodiments, the sampling plan may be used to modify the processing parameters of the tools in the fabrication process (e.g., scanner parameters, etcher parameters, etc.) to provide feedback or feedforward in the fabrication process, thereby mitigating identified defects. The sampling plan may be generated according to input information defining a predetermined wafer region definition and a sampling budget per wafer region, as well as user-specified sampling options. The sampling plan may provide die-level binary sampling decisions (e.g., whether to inspect or not inspect a particular die on the wafer). The sampling plan can then be used to guide inspection tools (e.g., scanning electron microscopes, SEMs, or optical tools) to regions on the wafer that have a set number of dies to inspect (e.g., a sampling budget). The inspection results obtained through the sampling plan indicate the number of actual defective dies present, and these results can then be used to predict the estimated die loss of the wafer. In some embodiments, the CGI model can be trained using historical data (e.g., history of previous defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan. R for defective die prediction provided by the CGI model sampling plan 2The correlation score can be determined by collecting "ground truth" results for the wafer. "Ground truth" results indicate the actual defective die results of the wafer at the end of production and correspond to probe test results of a fully completed wafer. Therefore, the probe test results provide accurate identification of defects in each die on the wafer. The final metric for the CGI model and sampling plan optimizer is the correlation R between the predicted estimated die loss determined by the CGI model and the actual die loss determined by the probe test results. 2 It could be a score.

[0071]

[0087] The CGI model provides output of defective die probabilities at the inter-die level. This means that the CGI model estimates the defect probability of each die on the wafer, which can vary die-wise and wafer-wise. The estimated defective die probabilities can be collected to generate a wafer sampling plan. Since the sampling plan can be generated for each wafer based on a specific defective die probability for each die on the wafer, the sampling plan generated by the CGI model can be called a “dynamic” sampling plan. The dynamic sampling plan can be used to guide inspection tools during wafer inspection to predict the die loss of the wafer at the end of wafer processing.

[0072]

[0088] In some embodiments of this disclosure, the predicted die loss is determined without assuming a uniform defect density or distribution within the wafer region. As described above, the die loss may be predicted after inspection results are collected from an inspection tool guided by a CGI-generated dynamic sampling plan. The predicted die loss may be calculated via the following formula, consistent with embodiments of this disclosure.

number

[0073]

[0089] In formula 3, N dd This is the number of defective dies,

number

[0074]

[0090] In some embodiments, generating the dynamic sampling plan portion of a hybrid sampling plan may include determining the defective die probability of a first region of the wafer using a (e.g., trained) computer-generated defect probability prediction model, as described above. The first region of the wafer may exclude areas of the wafer already included in the static sampling plan portion of the hybrid sampling plan. In some embodiments, generating the dynamic sampling plan portion of a hybrid sampling plan may include converting estimated defective die probabilities of the first region that exceed a threshold into a die-level sampling determination wafer map. That is, the hybrid sampling plan may include areas of the wafer covered by the static sampling plan portion and areas of the wafer that have historically had low defective die probabilities (dynamic sampling plan portion). However, the dynamic sampling plan portion may only include dies that have defective die probabilities exceeding a certain threshold. Therefore, it is possible that none of the defective die probabilities in the first region of the wafer meet the threshold, and the hybrid sampling plan may include only the static sampling plan.

[0075]

[0091] In some embodiments, the die defect probability in a first region (e.g., the white region of wafer 1001 in Figure 10A, the dynamic sampling region in sampling plan 1230 in Figure 12) may be lower than the die defect probability in regions of the wafer covered by the static sampling plan (e.g., the gray region of wafer 1001 in Figure 10A, the sampling region in sampling plan 1210 in Figure 12). In some embodiments, the dynamic sampling plan portion of the hybrid sampling plan may be applied to a sample by triggering additional sampling (in addition to applying the static sampling plan) when the predicted defect probability exceeds a threshold in an area of ​​the sample that has historically had a low defect probability (e.g., the dynamic sampling plan may determine excursion events on the wafer).

[0076]

[0092] Referring now to Figure 6, Figure 6 is an exemplary flowchart of Method 600, which generates a dynamic sampling plan of a wafer and predicts die loss from inspection results assuming a non-uniform defect density or distribution within the wafer, consistent with embodiments of the present disclosure. The steps of Method 600 may be performed by a computing device, e.g., the processor 303 in Figure 3. It should be understood that Method 600 as illustrated may be modified to change the order of the steps and to include additional steps. In some embodiments (e.g., in a sampling plan generated using a hybrid method), the non-uniform defect density or distribution may be obtained from static stack probe defect probability estimates or from predictions of a computer-computed defect probability prediction model.

[0077]

[0093] In step 601, input data is acquired and provided to the CGI model. The input data may correspond to metronome information collected from one or more images of a first and second wafer acquired via wafer processing during HVM. In some embodiments, the input data may correspond to metronome information collected from one or more images of a first layer of the acquired wafer and a second layer of the same wafer. In some embodiments, the wafer may be manufactured under certain manufacturing conditions (e.g., lithography focus, dose conditions, etc.). The input data may include a predetermined wafer region definition and sampling budget allocation. The metronome information may include, but is not limited to, necking, line pullback, line thinning, limit dimensions, edge placement, overlap (e.g., interlayer overlays on the wafer), resist top loss, resist undercut, missing defects, and bridge defects on the wafer.

[0078]

[0094] In step 602, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and is affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0079]

[0095] In step 603, the estimated defective die probabilities for all dies on the first wafer are ranked. The estimated defective die probabilities are ranked for each wafer region as follows: Top N i The top N with the highest estimated defect die probability i Each die can be ranked by wafer region so as to be considered. As mentioned above, N i This is the sampling budget for each wafer area.

[0080]

[0096] In step 604, the sampling plan for the first wafer is determined by the wafer region definition and the top N of each wafer region determined in step 603. i It is generated based on individual dies.

[0081]

[0097] In step 605, the inspection tool is guided during the inspection of the first wafer using the sampling plan generated for the first wafer. The inspection tool collects inspection results of the first wafer according to one or more expected defect areas identified by the sampling plan. In step 606, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 605 and according to equations 3 and 4.

[0082]

[0098] In some embodiments, the generated sampling plan may be used to modify the processing parameters of the tools in the fabrication process (e.g., scanner parameters, etcher parameters, etc.) to provide feedback or feedforward in the fabrication process, thereby mitigating the identified defects.

[0083]

[0099] In step 607, the estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer. The calculation may be performed by one or more processors (e.g., processor 303 in Figure 3) capable of applying a CGI model to the second wafer. The input data for the second wafer is as described above in step 601 and may include the wafer region definition and sampling budget allocation for the second wafer. The estimated defective die probabilities for all dies on the second wafer may be ranked by wafer region, a sampling plan may be generated based on the ranked estimated defective die probabilities, and die losses may be predicted for the second wafer by repeating steps 603 to 606.

[0084]

[0100] In some embodiments, if it is known that a certain area of ​​the wafer is prone to defects, this sampling plan can be used to compensate for the defect-prone area by changing the processing parameters of the tools used in fabrication (e.g., scanner parameters such as focus dose and etcher parameters).

[0085]

[0101] In step 608, probe test results for the first and second wafers may be obtained when the wafer processing is complete at the end of the wafer processing. In some embodiments, probe test results for the first or second wafer may be obtained at various steps of the wafer processing (e.g., after development, after etching, etc.). In step 609, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0086]

[0102] It should be understood that Method 600 can provide a dynamic sampling plan that can guide an inspection tool to areas on the wafer that may contain a more dense concentration of dies expected to be defective, compared to conventional methods. Furthermore, Method 600 can provide a more robust method for predicting die loss at the end of the wafer processing stage. In some embodiments, Method 600 can provide a more robust method for predicting die loss after various stages of wafer processing (e.g., after development, after etching, etc.). Thus, the die loss predicted by Method 600 may better agree with the ground truth results, and the resulting R 2 The correlation score may be higher compared to that of conventional methods. In some embodiments, method 600 may compensate for and mitigate die loss by generating a sampling plan that can be used, for example, to change the processing parameters of the tool in the fabrication (e.g., scanner parameters such as focal dose and etcher parameters).

[0087]

[0103] In some embodiments of this disclosure, limitations of dynamic sampling plans alone, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, can be mitigated by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan as described above for method 600, thereby taking into account non-uniform defect density or distribution within the wafer, improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations where wafer defects have historically been present (e.g., sampling the wafer at locations that have historically been prone to or shown to be defective). For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-generated model (e.g., based on a scanner recipe of a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0088]

[0104] Referring now to Figure 7, which is an exemplary flowchart of a method 700 for generating a dynamic sampling plan for a wafer without a predetermined wafer-area sampling budget allocation, consistent with embodiments of the present disclosure. The steps of method 700 may be carried out by a computing device, for example, the processor 303 in Figure 3. It should be understood that the illustrated method 700 may be modified to change the order of the steps and to include additional steps.

[0089]

[0105] In step 701, input data is acquired and provided to the CGI model. The input data may correspond to metronome information collected from one or more images of a first wafer and a second wafer acquired via wafer processing during HVM. In some embodiments, the input data may correspond to metronome information collected from one or more images of a first layer of the acquired wafer and a second layer of the same wafer. In some embodiments, the wafer may be manufactured under certain manufacturing conditions (e.g., lithography focus, dose conditions, etc.). The input data may include a predetermined wafer region definition. The metronome information may include, but is not limited to, necking, line pullback, line thinning, limit dimensions, edge placement, overlap (e.g., interlayer overlays on the wafer), resist top loss, resist undercut, missing defects, and bridge defects on the wafer.

[0090]

[0106] In step 702, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and is affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0091]

[0107] In step 703, the sampling budget for each region on the first wafer is allocated according to the estimated defect die probability for each wafer region. The calculations performed in step 703 may be as follows:

number

[0092]

[0108] In formula 5, SB i,j represents the sampling budget for region i on the wafer, SB wThis represents the sampling budget for the entire wafer. Therefore, the sampling budget for a region on the wafer can be calculated by multiplying the sampling budget for the entire wafer by the ratio of the sum of the defect die probabilities within that wafer region to the sum of the defect die probabilities for the entire wafer. In Equation 6,

number

[0093]

[0109] In step 704, a sampling plan for the first wafer is generated based on the wafer region definition and the per-wafer region sampling budget calculated in step 703.

[0094]

[0110] In step 705, the inspection of the first wafer is guided using an inspection tool, based on the sampling plan generated for the first wafer. For example, the generated sampling plan may be used to guide the inspection tool during the inspection of the first wafer. The inspection tool collects inspection results of the first wafer according to one or more expected defect areas identified by the sampling plan. In step 706, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 705. Die loss prediction may be performed through equations 3 and 4.

[0095]

[0111] In step 707, the estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer. The calculation may be performed by a processor capable of applying a CGI model to the second wafer (e.g., processor 303 in Figure 3). The input data for the second wafer is as described above in step 701 and may include the wafer region definitions and total sampling budget for the second wafer. The sampling budget may be allocated to each wafer region, a sampling plan based on the estimated defective die probability may be generated, and die losses can be predicted by repeating steps 703-706 for the second wafer.

[0096]

[0112] In step 708, probe test results for the first and second wafers may be obtained when the wafer processing is complete at the end of the wafer processing. In some embodiments, probe test results for the first or second wafer may be obtained at various steps of the wafer processing (e.g., after development, after etching, etc.). In step 709, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0097]

[0113] Method 700 is understood to provide a sampling plan that, compared to conventional methods, can allocate a larger proportion of the total sampling budget to wafer regions identified as containing a more concentrated number of defective and expected dies. Thus, the estimated defective die probability map may better agree with the ground truth results, and the resulting R 2 The correlation score may be higher compared to that of conventional methods. In some embodiments, method 700 may compensate for and mitigate die loss by generating a sampling plan which can be used, for example, to change the processing parameters of the tool in the fabrication (e.g., scanner parameters such as focal dose and etcher parameters).

[0098]

[0114] In some embodiments of this disclosure, limitations of dynamic sampling plans alone, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, can be mitigated by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan as described above for method 700, thereby taking into account non-uniform defect density or distribution within the wafer, improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations where wafer defects have historically been present (e.g., sampling the wafer at locations that have historically been prone to or shown to be defective). For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-generated model (e.g., based on a scanner recipe of a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0099]

[0115] Referring now to Figure 8, Figure 8 is an exemplary sampling plan or estimated defective die probability map generated by Method 700, consistent with embodiments of the present disclosure. Figure 8 corresponds to wafer 801, which includes dies 802. Each die 802 is represented as a square on wafer 801 with a black outline. As stated above, Method 700 uses a predetermined wafer region definition, so the estimated defective die probability map in Figure 8 may contain, for example, the same definition and number of wafer regions as in Figure 5. Figure 8 is for illustrative purposes only, and it should be understood that the wafer regions may be of any shape or size, and the number of wafer regions may not be so limited. Figure 8 is presented as a gradient image, where darker colors indicate a higher defective die probability, and lighter colors indicate a lower defective die probability. Figure 8 shows three wafer regions, where dotted line 803 represents the boundary of the first wafer region between the first and second wafer regions, and dotted line 804 represents the boundary of the second wafer region between the second and third wafer regions. The second wafer region (e.g., the region between dotted lines 803 and 804) shows the darkest color and therefore indicates the wafer region with the highest defect die probability. The sampling plan generated according to Method 700 (Figure 7) allocates a larger proportion of the total sampling budget to the second region and therefore directs the inspection tool more toward the second wafer region compared to the other wafer regions. Since Method 700 can optimize the sampling budget allocation per wafer region while maintaining a given total sampling budget per wafer, the estimated defect die probability map in Figure 8 may show different defect die probabilities per wafer region compared to the estimated defect die probability map that could be generated for the one in Figure 5. Therefore, Figure 8 may show an improved sampling plan, or more accurate die loss prediction, generated according to Method 700 (in Figure 7), in order to optimize the per-wafer sampling budget allocation for wafer inspection while maintaining a predetermined wafer region definition and total per-wafer sampling budget.

[0100]

[0116] In some embodiments of this disclosure, limitations of dynamic sampling plans alone, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, can be mitigated by using a hybrid sampling plan. In some embodiments, a hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan as described above for wafer 801, thereby taking into account non-uniform defect density or distribution within the wafer, improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations where wafer defects have historically been present (e.g., sampling the wafer at locations that have historically been prone to or shown to be defective). For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-generated model (e.g., based on a scanner recipe of a computer-generated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0101]

[0117] Referring now to Figure 9, Figure 9 is an exemplary flowchart of Method 900 for generating a wafer sampling plan without predetermined wafer area definitions and per-wafer area sampling budget allocation, consistent with embodiments of the present disclosure. The steps of Method 900 may be carried out by a computing device, for example, the processor 303 in Figure 3. It should be understood that Method 900 as illustrated may be modified to change the order of the steps and to include additional steps.

[0102]

[0118] In step 901, input data is acquired and provided to the CGI model. The input data may correspond to metronome information collected from one or more images of a first wafer and a second wafer acquired via wafer processing during HVM. In some embodiments, the input data may correspond to metronome information collected from one or more images of a first layer and a second layer of the acquired wafer. The wafer processing and metronome information may be as described above. However, the input data does not require a predetermined wafer region definition and a per-wafer region sampling budget allocation.

[0103]

[0119] In step 902, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and is affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0104]

[0120] In step 903, an estimated defective die probability map is generated for the first wafer by editing the defective die probabilities as described above. In step 904, the boundaries of the wafer region are evaluated to improve the uniformity of the defective die probability density on the defective die probability map. The uniformity of the defective die probability density can be improved by grouping the first die on the wafer with a second die that exhibits a similar defective die probability. Step 904 may be carried out in two optional steps. Step 904_1 may be carried out by applying the sampling plan generated by the CGI from step 903 and performing an image segmentation technique, which may include, but is not limited to, graph cuts, Otsu's algorithm, edge-based segmentation, threshold-based segmentation, region-based segmentation, cluster-based segmentation, watershed segmentation, semantic segmentation, instance segmentation, panoptic segmentation, and other methods of dividing an image into multiple subgroups. The resulting image segmentation can define regions of dies on the wafer where the uniformity of the defective die probability density is improved. For example, the estimated defective die probability map or sampling plan shown in Figure 8 may correspond to the map or sampling plan generated in step 903. Instead of defining wafer region boundaries, optimizing the sampling budget allocation for each defined wafer region, and thus adjusting the resulting estimated defective die probability map, as described above, step 904_1 applies the wafer region boundaries to the estimated defective die probability map based on the radial distribution of defective die probabilities. Thus, dies on the wafer can be grouped more uniformly within wafer regions.

[0105]

[0121] Instead, in step 904_2, the wafer region boundary is determined by integrating the estimated defective die probability map with respect to radial distance to generate a cumulative defective die probability map. The wafer region boundary can be evaluated by regions with a uniform slope or by changes in cumulative defective die probability. Thus, the evaluated wafer region may contain dies on the wafer with similar defective die probabilities and improve the uniformity of the defective die probability density on the generated defective die probability map.

[0106]

[0122] In step 905, a sampling plan using the evaluated wafer region boundaries is used to guide the inspection of the first wafer using the inspection tools. For example, the sampling plan may be used to guide the inspection tools during the inspection of the first wafer. In step 906, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 905. The die loss prediction may be performed through equations 3 and 4.

[0107]

[0123] In step 907, the estimated defective die probability for each die on the second wafer is calculated based on the input data of the second wafer. By repeating steps 903 to 906 for the second wafer, a sampling plan based on the estimated defective die probability may be generated, wafer regions may be evaluated, and the die loss of the second wafer may be predicted. In step 908, probe test results may be obtained for the first and second wafers once they are fully processed at the end of the wafer processing. In some embodiments, probe test results for the first or second wafer may be obtained at various steps of the wafer processing (e.g., after development, after etching, etc.). In step 909, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0108]

[0124] It should be understood that Method 900 can provide a sampling plan that is more versatile for different wafers. The wafer regions evaluated by Method 900 can guide inspection tools toward areas with a larger defect die probability that may have been separated from the predetermined and constant wafer region definitions of conventional methods.

[0109]

[0125] In some embodiments of this disclosure, limitations of dynamic sampling plans alone, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, can be mitigated by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan as described above for method 900, thereby taking into account non-uniform defect density or distribution within the wafer, improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations where wafer defects have historically been present (e.g., sampling the wafer at locations that have historically been prone to or shown to be defective). For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-calculated model (e.g., based on a scanner recipe of a computer-calculated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0110]

[0126] Referring here to Figures 10A and 10B, these figures are exemplary estimated defective die probability maps and exemplary cumulative defective die probability plots used to evaluate wafer region definitions consistent with embodiments of the present disclosure. Figure 10A may illustrate step 903 of method 900 (see Figure 9). As shown in Figure 10A, the defective die probability map of wafer 1001 may include a first probability boundary 1002 and a second probability boundary 1003 exhibiting differences in defective die probabilities. For example, the first probability boundary 1002 shows separation from areas of wafer 1001 with higher defective die probabilities (e.g., shown as gray) and areas of wafer 1001 with lower defective die probabilities (e.g., shown as white). The same may be observed for the second probability boundary 1003. The radial distance 1004 is shown as starting from the center of wafer 1001, passing through the first probability boundary 1002, passing through the second probability boundary 1003, and ending at the edge of wafer 1001 (e.g., the radius of wafer 1001).

[0111]

[0127] Referring now to Figure 10B, Figure 10B is an exemplary figure consistent with embodiments of the present disclosure, in which the wafer region definition is evaluated by integrating the wafer defect die probability map with respect to the radial distance. Figure 10B may correspond to step 904_2 of Method 900 (see Figure 9). The plot shown in Figure 10B may be obtained by integrating the wafer defect die probability map of wafer 1001 in Figure 10A with respect to the radial distance 1004. Thus, Figure 10B represents the cumulative defect die probability 1005 as a function of the radial distance 1004 of wafer 1001. The multiple dotted lines in Figure 10B, starting from the origin and appearing from left to right, represent the first probability boundary 1002, then the second probability boundary 1003, and the edge of wafer 1001. Since the radial distance 1004 starts at the center of wafer 1001, the cumulative defect die probability 1005 starts at 0 and increases as the radial distance 1004 increases. The radial distance between the origin and the first probability boundary 1002 may correspond to the first wafer region 1006, which may correspond to the gray area enclosed by the first probability boundary 1002 in Figure 10A. The same can be observed for the second wafer region 1007 and the third wafer region 1008. Since the first wafer region 1006 has a higher concentration or density of defects according to Figure 10A, the first wafer region 1006 shows a steeper slope in the plotted cumulative defect die probability. The same can be observed for the third wafer region 1008. Since the second wafer region 1007 exhibited a lower density of defect die probability in Figure 10A, the slope in the corresponding region in Figure 10B is gentler. The difference in slopes in each region in Figure 10B can be used to evaluate the wafer region definition of wafer 1001. In some embodiments, a wafer region may be defined such that the defect die probability density is uniform within the wafer region. For example, as shown in Figure 10B, this may correspond to the slope of the cumulative defect die probability plotted across the entire wafer region remaining constant. The wafer region boundary can then be applied to the defect die probability map at the corresponding radial distance (e.g., wafer region boundary 803 and wafer region boundary 804 in Figure 8).

[0112]

[0128] Referring now to Figure 11, Figure 11 shows a die loss prediction R consistent with the embodiment of this disclosure. 2 This is an illustrative flowchart of Method 1100, which directly optimizes wafer area definition and sampling budget allocation based on correlation scores. Method 1100 uses parameterized wafer area definition variables and per-wafer area sampling budget variables as optimization variables to predict die loss R based on a training set of wafers. 2 The correlation score can be optimized. Method 1100 is used for wafers that have been inspected using an inspection tool according to a sampling plan generated by CGI and also inspected via probe testing to obtain ground truth results, 2 This may be performed after the correlation score has been obtained. 2 The correlation score is used to guide the optimization of parameterized wafer area definition variables and sampling budget allocation variables, so the wafer may be called a “training wafer.” Method 1100 can be performed without a predetermined wafer area definition and per-wafer area sampling budget allocation. The steps of Method 1100 can be performed by a computing device, for example, the processor 303 in Figure 3. It should be understood that Method 1100 as illustrated can be modified to change the order of the steps and to include additional steps.

[0113]

[0129] In step 1101, input data is provided to the CGI model. The input data may include probe test results and images of the training wafer obtained through wafer processing, including the metronome information described above.

[0114]

[0130] In step 1102, the wafer region definition and the sampling budget per wafer region are parameterized for the training wafer. For example, the wafer region definition may be parameterized if the wafer contains two wafer region variables. These parameterized variables may be r1 and r2, where r1 is the radial distance from the center of the wafer to the first wafer region boundary, and r2 is the radial distance from the center of the wafer to the second wafer region boundary. Given this definition, r1 is less than r2 and 0 <r1、r2<r max Constrained by, here r max r is the maximum radial distance from the center of the wafer to the edge of the wafer. max It can be 150 mm. The third wafer region is r2 and r max It should be understood that it is defined by the radial distance between them. It should also be understood that a wafer may contain fewer than three or more wafer regions. The sampling budget per wafer region may be parameterized to variables N1, N2, and N3, where N1 corresponds to the sampling budget for the first wafer region, N2 corresponds to the sampling budget for the second wafer region, and N3 corresponds to the sampling budget for the third wafer region. N1, N2, and N3 may be constrained so that the sampling budget for a wafer region does not exceed the total number of dies in the wafer region, where N1 + N2 + N3 = N budget And here N budget This is the predetermined total sampling budget for wafers to be tested.

[0115]

[0131] In step 1103, the parameterized wafer region variable and the parameterized wafer region sampling budget variable are used in R 2The optimization is optimized to maximize the correlation score. The optimization is an arbitrary constrained global optimization technique that uses a forward solver to parameterize wafer region variables or parameterized wafer region-specific sampling budget variables based on the training wafer and the defect die loss R 2 This can be carried out by constrained global optimization techniques that map to correlation scores. Constrained global optimization techniques may include, but are not limited to, Bayesian optimization, coordinate descent, adaptive coordinate descent, cuckoo search, beetle antenna search, online nonlinear extremum search of databases, evolutionary strategies, genetic algorithms, multilevel coordinate search algorithms, Nelder-Mead method, particle swarm optimization, pattern search, random search, simulated annealing, stochastic optimization, subgradient methods, or any other derivative-free optimization algorithm. Step 1103 is performed when the parameterized variables described above are at their maximum R 2 This process can be repeated until it is simultaneously optimized to produce a correlation score.

[0116]

[0132] In step 1104, a sampling plan is generated using concurrently optimized parameterized wafer region variables and wafer region sampling budget variables. In step 1105, the generated sampling plan is applied to the first and second wafers in the test set during inspection of the first and second wafers in the test set to guide the inspection tool. The updated sampling plan may show different wafer region definitions and wafer region sampling budget allocations compared to the sampling plan used to guide the inspection tool for the training wafer before method 1100 was implemented.

[0117]

[0133] In step 1106, the die loss of the first and second wafers in the test set is predicted using the test results collected for the first and second wafers in the test set. Die loss prediction can be performed through equations 3 and 4. In step 1107, after wafer processing is complete, probe test results for the first and second wafers in the test set are collected to obtain the actual die loss. In step 1108, verification R 2 The correlation score is evaluated. Validation R 2 The correlation score is calculated using the starting R of method 1100. 2 It is compared with the correlation score. Validation R 2 The correlation score is at the start of R 2 If the correlation score is higher, the concurrently optimized parameterized wafer region variables and wafer region-specific sampling budget allocation variables can be applied to the wafer for subsequent wafer processing.

[0118]

[0134] Method 1100 should be understood as providing an optimization-based approach that generates a more versatile, optimal, and fixed sampling plan setting (e.g., wafer region definition or sampling budget allocation) for predicting defective dies on different wafers with improved accuracy. It should also be understood that optimized, parameterized wafer region definitions and sampling budget definitions determined from Method 700 or Method 900 can be applied as initial inferences in Method 1100. This may reduce the time and computational costs associated with the optimization in Method 1100.

[0119]

[0135] Referring to Table 1, Table 1 shows the R values ​​determined by Methods 600 and 700 of this disclosure for three wafer datasets. 2This demonstrates an improvement in correlation scoring compared to conventional methods. Specifically, each dataset includes a batch of more than 100 wafers for which a sampling plan was generated to guide inspection tools according to Methods 600 and 700 of this disclosure. For a portion of the wafers in batch 1 of dataset 1, the predicted die loss was calculated and probe test results were obtained, while for each wafer in datasets 2 and 3, the predicted die loss was calculated and probe test results were obtained. It should be understood that the die loss was predicted using Equations 3 and 4 (assuming, for example, a non-uniform defect density or distribution) for both Methods 600 and 700. 2 The correlation score is determined as described above, and when either Method 600 or Method 700 is applied instead of the conventional method, R is applied to each dataset of wafers. 2 It was found that the correlation score improved. For all three datasets when Method 600 was applied, R was improved compared to the conventional method. 2 The improved correlation score indicates that assuming a heterogeneous defect density or distribution is beneficial in die loss prediction. 2 The correlation scores were shown to be further improved for datasets 2 and 3 when method 700 was applied compared to method 600. Therefore, R 2 The correlation score can be further improved by applying model-based sampling budget allocation, in addition to assuming a non-uniform defect density or distribution in die loss prediction.

[0120] [Table 1]

[0121]

[0137] The advantages provided by the embodiments of this disclosure are that, without the need for input variables, the R of the actual die loss is improved compared to the predicted die loss using a CGI model. 2 A correlation score may be obtained. In some embodiments, the disclosure predicts die loss without assuming that the defect density or distribution is uniform within the wafer region, and R2 This may provide a method to improve the correlation score. In some embodiments, R 2 To improve the correlation score, the wafer sampling budget allocation or wafer region definition may be optimized. In some embodiments, R 2 An optimization-based model is provided that can further improve correlation scores. Some embodiments of this disclosure may provide methods for improving the performance and versatility of CGI models for guiding wafer inspection. Some embodiments of this disclosure may provide methods for improving defect inspection accuracy and defect-free wafer yield across the entire HVM.

[0122]

[0138] In some embodiments of this disclosure, limitations of dynamic sampling plans alone, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, can be mitigated by using a hybrid sampling plan. In some embodiments, the hybrid sampling plan may use both a static sampling plan (e.g., method 400 in Figure 4, wafer 501 in Figure 5) and a dynamic sampling plan as described above for method 1100, thereby taking into account non-uniform defect density or distribution within the wafer, improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations where wafer defects have historically been present (e.g., sampling the wafer at locations that have historically been prone to or shown to be defective). For example, generating the static sampling plan portion of a hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, generating the dynamic sampling plan portion of a hybrid method may include generating an excursion event sampling plan based on fabrication data and a computer-calculated model (e.g., based on a scanner recipe of a computer-calculated lithography model, including scanner resolution enhancement techniques such as optical proximity correction).

[0123]

[0139] Referring now to Figure 12, Figure 12 shows exemplary sampling plans 1210, 1220, and 1230 for a wafer, consistent with embodiments of the present disclosure.

[0124]

[0140] In some embodiments, the sampling plan 1210 may represent a static sampling plan for wafers 1201, 1202, 1203, 1204, 1205, and 1206 (e.g., one generated using method 400 in Figure 4, corresponding to wafer 501 in Figure 5). As shown in the sampling plan 1210, wafers 1201, 1202, 1203, 1204, 1205, and 1206 include uniform sampling regions 1211 and 1212. In some embodiments, the sampling regions 1211 and 1212 may correspond to regions of wafers that have previously had wafer defects (e.g., regions of wafers that have previously been prone to defects or shown to have defects).

[0125]

[0141] In some embodiments, the sampling plan 1220 may show a dynamic sampling plan for wafers 1201, 1202, 1203, 1204, 1205, and 1206 (e.g., generated using method 600 in Figure 6, method 700 in Figure 7, corresponding to wafer 801 in Figure 8, method 900 in Figure 9, corresponding to wafer 1001 in Figure 10A, corresponding to the plot in Figure 10B, and method 1100 in Figure 11). As shown in the sampling plan 1220, wafers 1201, 1202, 1203, 1204, 1205, and 1206 include non-uniform sampling regions (e.g., sampling regions 1221 and 1222 of wafer 1201). In other words, the sampling areas of wafers 1201, 1202, 1203, 1204, 1205, and 1206 vary from wafer to wafer due to differences in the input data (e.g., manufacturing data for each wafer) supplied to the computer calculation model for generating the dynamic sampling plan.

[0126]

[0142] In some embodiments, some sampling areas of the dynamic sampling plan 1220 (e.g., sampling area 1223 of wafer 1203 and sampling area 1224 of wafer 1206) may correspond to areas of the wafer that have not had wafer defects in the past (e.g., areas of the wafer that have not been prone to defects or have not been shown to have defects in the past).

[0127]

[0143] In some embodiments, the sampling plan 1230 may represent a hybrid sampling plan generated based on a static sampling plan 1210 and a dynamic sampling plan 1220. As shown in the hybrid sampling plan 1230, the sampling regions 1211 and 1212 are included in wafers 1201, 1202, 1203, 1204, 1205, and 1206, respectively.

[0128]

[0144] In some embodiments, the dynamic sampling plan portion of the hybrid sampling plan 1230 may include only dies having a defective die probability above a certain threshold (e.g., sampling regions of the dynamic sampling plan 1220 that are outside the static sampling plan 1210 and above the threshold). For example, the hybrid sampling plan 1230 may include the static sampling plan 1210 and sampling regions 1223 and 1224 of the dynamic sampling plan 1220 (e.g., the defective die probabilities corresponding to sampling regions 1223 and 1224 may exceed the threshold).

[0129]

[0145] Referring now to Figure 13, Figure 13 shows exemplary metrology sampling plans 1310 and 1320 for a wafer, consistent with embodiments of the present disclosure.

[0130]

[0146] In some embodiments, the sampling plan 1310 may correspond to a typical metrologic sampling plan for acquiring input data (e.g., fabrication data) to generate a dynamic sampling plan (e.g., method 700 in Figure 7, corresponding to wafer 801 in Figure 8, method 900 in Figure 9, corresponding to wafer 1001 in Figure 10A, corresponding to plot in Figure 10B, method 1100 in Figure 11, dynamic sampling plan 1220 in Figure 12, generated using method 600 in Figure 6).

[0131]

[0147] In embodiments of this disclosure for generating a hybrid sampling plan, sampling plan 1310 may have an inefficient distribution of the sampling budget because a static sampling plan (e.g., static sampling plan 1210 in Figure 12) is applied. Therefore, in some embodiments, the sampling budget may be redistributed to improve the accuracy of the dynamic sampling plan portion of the hybrid sampling plan. For example, sampling plan 1320 may be generated. In some embodiments, sampling plan 1320 may be a modification of an existing metrologic sampling plan (e.g., a modification of sampling plan 1310). As shown in sampling plans 1310-1320, the sampling area (e.g., sampling area 1312) may be redistributed from the area corresponding to the static sampling plan portion to the area corresponding to the dynamic sampling plan portion to improve the accuracy of the dynamic sampling plan portion (e.g., redistributed to sampling area 1322, which is an area that has historically had a low defect probability).

[0132]

[0148] In some embodiments using a hybrid sampling plan (e.g., sampling plan 1230 in Figure 12), the wafer sampling budget ratio may be adjusted to allocate dies sampled using a static sampling plan and dies sampled using a dynamic sampling plan based on real-time needs and historical data (e.g., the number of dies sampled using static sampling and the number of dies sampled using wafer-per-wafer dynamic sampling may be adjusted). In some embodiments, the dynamic sampling plan of the hybrid sampling plan may use a fixed sampling budget per wafer or per zone (e.g., a region of the wafer, a quarter of the wafer, a concentric ring region of the wafer, etc.) based on dynamic sampling optimization.

[0133]

[0149] Figure 14 shows an exemplary static sampling plan portion 1400 of a hybrid sampling plan (e.g., sampling plan 1230 in Figure 12) consistent with embodiments of the present disclosure. In some embodiments, in addition to the CGI-generated dynamic sampling plan portion of the hybrid sampling plan, fixed die locations 1410 within the static sampling plan portion 1400 may be selected for inspection. Conveniently, this option allows for targeted sampling of areas known from experience (e.g., historical data) or areas suspected of having problems.

[0134]

[0150] Figure 15 shows Figure 1500, an exemplary static sampling plan portion of a hybrid sampling plan (e.g., sampling plan 1230 in Figure 12) consistent with embodiments of the present disclosure.

[0135]

[0151] In some embodiments, maps 1510, 1520, and 1530 may be generated from historical defect data across multiple wafers. For example, each of maps 1510, 1520, and 1530 may correspond to a different wafer. Maps 1510, 1520, and 1530 may represent the defect probability of each die on a wafer. For example, points 1512, 1522, and 1532 may represent dies on a wafer that are "failed" (e.g., likely to have defects), and points 1514, 1524, and 1534 may represent dies on a wafer that are "passed" (e.g., unlikely to have defects).

[0136]

[0152] The system can generate a map 1540 that may represent the stack probe wafer map using Equation 7. That is, map 1540 can be generated by averaging maps 1510, 1520, and 1530 using Equation 7.

number

[0137]

[0153] Map 1540 may be used to generate the static sampling portion of a hybrid sampling plan. In some embodiments, Map 1540 may be used to generate the static sampling portion of a hybrid sampling plan by determining fixed sampling locations on Map 1540 based on the highest defect probability. In some embodiments, the static sampling portion of a hybrid sampling plan may be generated by determining different zones of Map 1540 (e.g., a quadrant of Map 1540, a concentric ring of Map 1540, etc.) to ensure more strategic wafer coverage.

[0138]

[0154] Similar to Figure 15, in some embodiments, instead of using a stack probe map (e.g., map 1540) to generate the static sampling plan portion of the hybrid sampling plan, a wafer map may be used to generate the static sampling plan portion. For example, each die in the wafer map may correspond to historical sampling frequency data. In some embodiments, each die in the wafer map may correspond to the probability that the die at that location will be sampled.

[0139]

[0155] Based on the wafer map, a static sampling plan portion of a hybrid sampling plan can be generated. For example, the static sampling plan portion may target areas of the wafer that have not been sampled in the past or the areas that have been least sampled, based on a probability map of past sampling data. Advantageously, this method aims to explore and address areas of high uncertainty on the wafer.

[0140]

[0156] The system can generate a stacked wafer map using equation 8.

number

[0141]

[0157] In some embodiments, predicted die losses can be calculated based on hybrid sampling design methods. For example, based on Equation 9, static or fixed sampling probabilities can be combined with defect probabilities generated by CGI (based on dynamic sampling design) to produce a more accurate and comprehensive risk assessment. Hybrid sampling probability (x,y) =CGI model predicted probability (x,y) × Dynamic sampling ratio + Stack probe or sampling probability (x,y) × Fixed sampling ratio (Equation 9).

[0142]

[0158] The hybrid sampling probability of a die at coordinate (x,y) (e.g., the probability that the die at coordinate (x,y) will be rejected or defective in a hybrid sampling plan) can be determined based on the CGI model prediction probability (the probability that the die at coordinate (x,y) will be rejected or defective in the dynamic sampling portion) and the stack probe probability (e.g., Equation 7) or the stack sampling probability (e.g., Equation 8). The dynamic sampling ratio and the fixed sampling ratio may be the ratio of dies in the sampling budget (e.g., the ratio of dies during dynamic sampling and the ratio of dies during static sampling).

[0143]

[0159] The predicted die loss can be determined using equation 10.

number

[0144]

[0160] Embodiments of the present disclosure illustrating a hybrid sampling plan conveniently result in an increased defect detection rate. By combining strategic static sampling (e.g., Figures 14 and 15) with a dynamic, data-driven sampling plan, the hybrid sampling plan can more effectively target defects across the wafer and predict expected die loss with greater accuracy.

[0145]

[0161] Embodiments of the present disclosure describing a hybrid sampling plan conveniently result in improved adaptability and coverage. For example, embodiments of the present disclosure provide flexibility that enables a tailored inspection strategy to adapt to new and evolving defect patterns, thereby significantly improving coverage. Embodiments of the present disclosure increase throughput by focusing on areas of the wafer that are less likely to contain defects.

[0146]

[0162] Embodiments of the present disclosure describing hybrid sampling plans conveniently provide enhanced model robustness by incorporating broader datasets and multiple sampling strategies to enhance the overall predictive power and reliability of the model.

[0147]

[0163] Referring now to Figure 16, which is an exemplary flowchart of a method 1400 for generating a wafer hybrid sampling plan consistent with embodiments of the present disclosure.

[0148]

[0164] In step 1601, the system (e.g., processor 303 in Figure 3) may generate a static sampling plan (e.g., generate a baseline sampling plan based on historical inspection data) to determine the baseline for inspection. In some embodiments, the static sampling plan may include a predetermined area of ​​the wafer. For example, step 1601 may be carried out as described above with respect to the method 400 in Figure 4, the wafer 501 in Figure 5, the static sampling plan 1210 in Figure 12, the static sampling plan portion 1400 in Figure 14, Figure 1500 in Figure 15, and embodiments described with respect to the drawings above.

[0149]

[0165] In step 1602, the system may generate a dynamic sampling plan for determining excursion events (e.g., generating an excursion event sampling plan based on fabrication data and a computer calculation model). In some embodiments, generating a dynamic sampling plan may include providing wafer input data to a computer calculation defect probability prediction model and determining the defect die probability of a region of the wafer from the computer calculation defect probability prediction model. For example, step 1602 may be carried out as described above for method 600 in Figure 6, method 700 in Figure 7, wafer 801 in Figure 8, method 900 in Figure 9, wafer 1001 in Figure 10A, plot in Figure 10B, method 1100 in Figure 11, or dynamic sampling plan 1220 in Figure 12.

[0150]

[0166] In step 1603, the system may apply a static sampling plan. For example, step 1603 may be carried out as described above with respect to method 400 in Figure 4, wafer 501 in Figure 5, static sampling plan 1210 in Figure 12, static sampling plan portion 1400 in Figure 14, Figure 1500 in Figure 15, and embodiments described with respect to the drawings above.

[0151]

[0167] In step 1604, the system may apply a dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​a sample that previously had a lower defect probability. For example, step 1604 may be performed as described above for method 600 in Figure 6, method 700 in Figure 7, wafer 801 in Figure 8, method 900 in Figure 9, wafer 1001 in Figure 10A, plot in Figure 10B, method 1100 in Figure 11, or dynamic sampling plan 1220 in Figure 12.

[0152]

[0168] Non-temporary computer-readable media may be provided which store instructions for the processor of a controller (e.g., controller 109 in Figure 1, controller 109 in Figure 2A, controller 109 in Figure 2A) for, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, focusing lens adjustment, activated charged particle source, and beam deflection; instructions for the processor of a lithography projection apparatus (e.g., lithography projection apparatus 301 in Figure 3) and an inspection tool (e.g., inspection tool 302 in Figure 3) for, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, focusing lens adjustment, activation of charged particle source, and beam deflection; for, determining sample input data, performing method 600 in Figure 6, method 700 in Figure 7, method 900 in Figure 9, method 1100 in Figure 1100, method 1600 in Figure 1600; and performing other executable functions related to wafer area definition for inspection in HVM or modeling and optimization of per-wafer area sampling budget allocation. Common forms of non-temporary media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, compact disk read-only memory (CD-ROM), any other optical data storage media, any physical media having a pattern of holes, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), flash EPROM or any other flash memory, non-volatile random access memory (NVRAM), caches, registers, any other memory chips or cartridges, and networked versions of the aforementioned.

[0153]

[0169] Embodiments may be further described using the following clauses. Clause 1. A method for generating an inspection tool sampling plan, To provide wafer input data to a computer-based defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Determining the defect die probability for each wafer region from a computer-calculated defect probability prediction model, Using the determined defective die probability, select at least one die from each of the multiple wafer regions, A method comprising generating a wafer sampling plan based on a selected die. Clause 2. The method described in Clause 1, wherein the input data includes an image containing wafer metronome information. Clause 3. The method according to Clause 1 or 2, wherein the input data includes a definition of a predetermined wafer region and a sampling budget for each wafer region. Clause 4. Using the determined defective die probability, at least one die may be selected from each wafer region among multiple wafer regions. Ranking the defect die probability for each determined wafer region, The method according to Clause 3, further comprising selecting a number of dies for each wafer region of a plurality of wafer regions based on the determined ranking of defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each wafer region. Article 5. Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 1 to 4, further comprising evaluating the correlation score. Clause 6. The method according to Clause 5, wherein the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 7. The method according to any one of Clauses 1 to 6, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 8. The method described in any one of Clauses 1 to 7, wherein the computer-generated defect probability prediction model is a computer-generated inductive test model. Clause 9. A method for optimizing the inspection tool sampling plan, To provide wafer input data to a computer-based defect probability prediction model, This includes allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in the wafer, The expected number of defective die counts in that region is the sum of the expected defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the expected defective die probabilities for that wafer. A method for obtaining the predicted defect die probability of a region and the predicted defect die probability of a wafer from a computer-computed defect probability prediction model. Clause 10. The method described in Clause 9, wherein the input data includes an image containing wafer metronome information. Clause 11. The method according to Clause 9 or 10, wherein the input data includes a definition of a predetermined wafer area and a wafer sampling budget. Article 12. To generate a sampling plan to guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 9 to 11, further comprising evaluating the correlation score. Clause 13. The method described in any one of Clauses 9 to 12, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 14. The method described in any one of Clauses 9 to 13, wherein the computer-generated defect probability prediction model is a computer-generated inductive test model. Clause 15. A method for optimizing the inspection tool sampling plan, To provide wafer input data to a computer-based defect probability prediction model, Determining the defect probability of each die in the wafer using a computer-generated defect probability prediction model, Generating a sampling plan, Evaluating wafer regions from the defect die probability of each die on the wafer, For each of the evaluated wafer regions, the sampling budget allocation is evaluated, and A method comprising using a sampling plan, along with evaluated wafer areas and sampling budget allocation, to guide wafer inspection of a wafer. Clause 16. The method described in Clause 15, wherein the input data includes an image containing wafer metronome information. Clause 17. The method described in Clause 15 or 16, wherein the input data includes a predetermined sampling budget for the wafer. Clause 18. The method according to any one of Clauses 15 to 17, wherein the wafer area is evaluated by integrating the calculated defective die probability of each die on the wafer over the radial direction on the wafer. Clause 19. The method according to any one of Clauses 15 to 17, wherein the wafer area is evaluated by image segmentation of the defective die probability calculated for each die of the wafer. Article 20. Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 15 to 19, further comprising evaluating the correlation score. Clause 21. The method according to any one of Clauses 15 to 20, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 22. The method described in any one of Clauses 15 to 21, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 23. A method for optimizing the inspection tool sampling plan, Providing wafer input data to a computer-based computational defect probability prediction model, parameterizing a wafer region definition and a wafer region sampling budget, wherein the parameterized wafer region definition and the wafer region sampling budget have specific constraints, optimizing the parameterized wafer region definition and the parameterized wafer region sampling budget in accordance with the specific constraints to maximize a prediction value. A method comprising: Clause 24. The method of clause 23, wherein the input data comprises wafer probe test results. Clause 25. The input data comprises R 2 correlation scores. The method of any one of clauses 23 or 24, Clause 26. The method of any one of clauses 23 to 25, wherein the wafer region definition is parameterized using a first variable and a second variable. Clause 27. The method of clause 26, wherein the first variable is r1, the second variable is r2, r1 is a radial distance from a center of the wafer to a first wafer region boundary, and r2 is a radial distance from the center of the wafer to a second wafer region boundary. Clause 28. The constraints for the first variable and the second variable comprise 0 < r1, r2 < r max , wherein r max is a radius of the wafer. The method of clause 27, Clause 29. The method of clause 27 or 28, wherein the constraints for the first variable and the second variable comprise r1 < r2. Clause 30. The method of any one of clauses 23 to 29, wherein a sampling budget for a wafer region on the wafer is parameterized using a first variable, a second variable, and a third variable. Clause 31. The method of clause 30, wherein the first variable is N1, the second variable is N2, the third variable is N3, N1 is a sampling budget for a first wafer region, N2 is a sampling budget for a second wafer region, and N3 is a sampling budget for a third wafer region. Clause 32. The constraints on N1, N2, and N3 are N1+N2+N3=N budget Including N budget However, the method according to clause 31, which is the total sampling budget for the wafer. The method according to Clause 31 or 32, wherein N1, N2, and N3 are less than the total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. Clause 34. The method of any one of Clauses 23 to 33, wherein optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region involves using constrained global optimization techniques. Clause 35. The method according to Clause 34, wherein the constrained global optimization technique is a derivative-free optimization algorithm. Clause 36. The predicted values ​​are generated by optimizing the parameterized wafer region definition and the parameterized wafer region sampling budget. 2 The correlation score is determined by the method described in any one of clauses 23 to 35. Article 37. To generate a sampling plan to guide wafer inspection of the second wafer, Using the inspection results of the second wafer, calculate the predicted die loss, To obtain the probe test results for the second wafer, R 2 The method described in any one of clauses 23 to 36, further comprising evaluating the correlation score. Clause 38. The method described in any one of Clauses 23 to 37, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 39. The method described in any one of Clauses 23 to 38, wherein the computer-generated defect probability prediction model is a computer-generated inductive test model. Clause 40. Apparatus for generating inspection tool sampling plans, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To provide wafer input data to a computer-based defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Determining the defect die probability for each wafer region from a computer-calculated defect probability prediction model, Using the determined defective die probability, select at least one die from each of the multiple wafer regions, An apparatus including at least one processor that performs operations including generating a wafer sampling plan based on a selected die. Clause 41. The apparatus described in Clause 40, wherein the input data includes an image containing wafer metronome information. Clause 42. The apparatus described in Clause 40 or 41, wherein the input data includes a definition of a predetermined wafer region and a sampling budget for each wafer region. Clause 43. Using the determined defective die probability, at least one die may be selected from each wafer region among multiple wafer regions. The defect die probability determined for each die is ranked according to wafer region, The apparatus according to Clause 42, further comprising selecting the number of dies for each wafer region of a plurality of wafer regions based on the determined ranking of defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each wafer region. Clause 44. The operation is, Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 40 to 43, further comprising evaluating the correlation score. Clause 45. The apparatus described in Clause 44, wherein the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 46. An apparatus as described in any one of Clauses 40 to 45, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 47. An apparatus as described in any one of Clauses 40 to 46, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 48. Apparatus for optimizing the inspection tool sampling plan, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To provide wafer input data to a computer-based defect probability prediction model, The system includes at least one processor that performs an operation including allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in that wafer, The expected number of defective die counts in that region is the sum of the expected defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the expected defective die probabilities for that wafer. An apparatus in which the predicted defect die probability of a region and the predicted defect die probability of that wafer are obtained from a computer-calculated defect probability prediction model. Clause 49. The apparatus described in Clause 48, wherein the input data includes an image containing wafer metronome information. Clause 50. The apparatus described in Clause 48 or 49, wherein the input data includes a definition of a predetermined wafer region and a wafer sampling budget. Clause 51. The operation is, To generate a sampling plan to guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 48 to 50, further comprising evaluating the correlation score. Clause 52. An apparatus as described in any one of Clauses 48 to 51, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 53. An apparatus as described in any one of Clauses 48 to 52, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 54. Apparatus for optimizing the inspection tool sampling plan, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To provide wafer input data to a computer-based defect probability prediction model, Determining the defect probability of each die in the wafer using a computer-generated defect probability prediction model, Generating a sampling plan, Evaluating wafer regions from the defect die probability of each die on the wafer, For each of the evaluated wafer regions, the sampling budget allocation is evaluated, and An apparatus including at least one processor that causes the apparatus to perform operations including guiding wafer inspection of a wafer using a sampling plan together with evaluated wafer regions and sampling budget allocation. Clause 55. The apparatus described in Clause 54, wherein the input data includes an image containing wafer metronome information. Clause 56. The apparatus described in Clause 54 or 55, wherein the input data includes a predetermined sampling budget for a wafer. Clause 57. An apparatus as described in any one of Clauses 54 to 56, wherein the wafer area is evaluated by integrating the calculated defective die probability of each die on the wafer over the radial direction on the wafer. Clause 58. An apparatus according to any one of Clauses 54 to 56, wherein a wafer region is evaluated by image segmentation of the generated defect die probability map of the wafer. Clause 59. The operation is, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 54 to 58, further comprising evaluating the correlation score. Clause 60. An apparatus as described in any one of Clauses 54 to 59, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 61. An apparatus as described in any one of Clauses 54 to 60, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 62. Apparatus for optimizing the inspection tool sampling plan, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To provide wafer input data to a computer-based defect probability prediction model, The parameterization of the wafer region definition and the wafer region sampling budget, wherein the parameterized wafer region definition and wafer region sampling budget have specific constraints. An apparatus comprising at least one processor that performs an operation including optimizing the definition of a parameterized wafer region and the sampling budget of a parameterized wafer region in accordance with those specific constraints to maximize the predicted value. Clause 63. The apparatus described in Clause 62, in which input data includes wafer probe test results. Clause 64. Input data is R 2 The apparatus according to clause 62 or 63, including a correlation score. Clause 65. The apparatus according to any one of Clauses 62 to 64, wherein the definition of the wafer region is parameterized using a first variable and a second variable. Clause 66. The apparatus according to Clause 65, wherein the first variable is r1, the second variable is r2, r1 is a radial distance from a center of the wafer to a first wafer region boundary, and r2 is a radial distance from the center of the wafer to a second wafer region boundary. Clause 67. Constraints on the first variable and the second variable include 0<r1, r2<r max , and r max is a radius of the wafer, the apparatus according to Clause 66. Clause 68. The apparatus according to Clause 66 or 67, wherein the constraints on the first variable and the second variable include r1<r2. Clause 69. The apparatus according to any one of Clauses 62 to 68, wherein a sampling budget of a wafer region on the wafer is parameterized using a first variable, a second variable, and a third variable. Clause 70. The method according to Clause 69, wherein the first variable is N1, the second variable is N2, the third variable is N3, N1 is a sampling budget of a first wafer region, N2 is a sampling budget of a second wafer region, and N3 is a sampling budget of a third wafer region. Clause 71. Constraints on N1, N2, and N3 include N1+N2+N3=N budget , and N budget is a total sampling budget of the wafer, the apparatus according to Clause 70. Clause 72. The apparatus according to Clause 70 or 71, wherein N1, N2, and N3 are each less than a total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. Clause 73. The apparatus according to any one of Clauses 62 to 72, wherein optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region comprises using a constrained global optimization technique. Clause 74. The apparatus according to Clause 73, wherein the constrained global optimization technique is a derivative-free optimization algorithm. Clause 75. The predicted values ​​are generated by optimizing the parameterized wafer region definition and the parameterized wafer region sampling budget. 2 The apparatus described in any one of clauses 62 to 74, which is a correlation score. Clause 76. The operation is, To generate a sampling plan to guide wafer inspection of the second wafer, Using the inspection results of the second wafer, calculate the predicted die loss, To obtain the probe test results for the second wafer, R 2 The apparatus described in any one of clauses 62 to 75, further comprising evaluating the correlation score. Clause 77. An apparatus as described in any one of Clauses 62 to 76, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 78. An apparatus as described in any one of Clauses 62 to 77, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 79. A non-temporary computer-readable medium including a set of instructions executable by one or more processors of a computing device for causing the computing device to perform an action for generating an inspection tool sampling plan, wherein the action is: To provide wafer input data to a computer-based defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Determining the defect die probability for each wafer region from a computer-calculated defect probability prediction model, Using the determined defective die probability, select at least one die from each of the multiple wafer regions, A non-temporary computer-readable medium, including generating a wafer sampling plan based on a selected die. Clause 80. Non-temporary computer-readable media as described in Clause 79, including images containing wafer metronome information, where input data is included. Clause 81. A non-temporary computer-readable medium as described in Clause 79 or 80, in which the input data includes a definition of a given wafer area and a sampling budget for each wafer area. Clause 82. Using the determined defective die probability, at least one die may be selected from each wafer region among multiple wafer regions. The defect die probability determined for each die is ranked according to wafer region, A non-temporary computer-readable medium as described in Clause 81, further comprising selecting the number of dies for each wafer region of a plurality of wafer regions based on the determined ranking of defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each wafer region. Clause 83. The operation is, Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 79 to 82, further including the evaluation of correlation scores. Clause 84. A non-transient computer-readable medium as described in Clause 83, in which the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 85. A non-temporary computer-readable medium as described in any one of Clauses 79 to 82, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 86. A non-temporary computer-readable medium as described in any one of Clauses 79-85, in which the computer-calculated defect probability prediction model is a computer-calculated guided test model. Clause 87. A non-temporary computer-readable medium including a set of instructions executable by one or more processors of a computing device for causing the computing device to perform an action to optimize the inspection tool sampling plan, wherein the action is: To provide wafer input data to a computer-based defect probability prediction model, This includes allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in the wafer, The expected number of defective die counts in that region is the sum of the expected defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the expected defective die probabilities for that wafer. A non-temporary, computer-readable medium from which the predicted defect die probability of that region and the predicted defect die probability of that wafer are obtained from a computer-calculated defect probability prediction model. Clause 88. Non-temporary computer-readable media as described in Clause 87, including images containing wafer metronome information, where input data is included. Clause 89. A non-temporary computer-readable medium as described in Clause 87 or 88, in which the input data includes a definition of a predetermined wafer area and a wafer sampling budget. Clause 90. The operation is, To generate a sampling plan to guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 87 to 89, further including the evaluation of correlation scores. Clause 91. A non-temporary computer-readable medium as described in any one of Clauses 87-90, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 92. The non-transitory computer-readable medium according to any one of Clauses 87 to 91, wherein the computer-based defect probability prediction model is a computer computation-guided inspection model. Clause 93. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device for causing the computing device to perform operations for optimizing an inspection tool sampling plan, wherein the operations comprise: providing input data of a wafer to a computer-based defect probability prediction model; determining a defective die probability for each die of the wafer from the computer-based defect probability prediction model; generating a sampling plan; evaluating wafer regions from the defective die probability of each die of the wafer; evaluating a sampling budget allocation for each of the evaluated wafer regions; using the sampling plan together with the evaluated wafer regions and the evaluated sampling budget allocation to guide wafer inspection of the wafer; the non-transitory computer-readable medium comprising the foregoing. Clause 94. The non-transitory computer-readable medium according to Clause 93, wherein the input data comprises an image containing metrology information of the wafer. Clause 95. The non-transitory computer-readable medium according to Clause 93 or 94, wherein the input data comprises a predetermined sampling budget for the wafer. Clause 96. The non-transitory computer-readable medium according to any one of Clauses 93 to 95, wherein the wafer regions are evaluated by integrating the calculated defective die probability of each die of the wafer in a radial direction on the wafer. Clause 97. The non-transitory computer-readable medium according to any one of Clauses 93 to 95, wherein the wafer regions are evaluated by image segmentation of a generated defective die probability map of the wafer. Clause 98. The operations comprise: calculating an expected die loss using inspection results of the wafer; obtaining wafer probe test results, and evaluating an R 2 correlation score by comparing the probe test results with predicted die loss, the non-transitory computer-readable medium according to any one of Clauses 93 to 97, further comprising the step. Clause 99. The non-transitory computer-readable medium according to any one of Clauses 93 to 98, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 100. The non-transitory computer-readable medium according to any one of Clauses 93 to 99, wherein the computationally defect probability prediction model is a computationally guided inspection model. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device, for causing the computing device to perform operations for optimizing an inspection tool sampling plan, the operations comprising: providing wafer input data to a computationally defect probability prediction model; and parameterizing a wafer area definition and a wafer area sampling budget, wherein the parameterized wafer area definition and the parameterized wafer area sampling budget have specific constraints; and optimizing the parameterized wafer area definition and the parameterized wafer area sampling budget in accordance with the specific constraints to maximize a prediction value, the non-transitory computer-readable medium comprising the step. Clause 102. The non-transitory computer-readable medium according to Clause 101, wherein the input data comprises wafer probe test results. Clause 103. The input data comprises R 2 correlation score, the non-transitory computer-readable medium according to Clause 101 or 102. Clause 104. The non-transitory computer-readable medium according to any one of Clauses 101 to 103, wherein the wafer area definition is parameterized using a first variable and a second variable. Clause 105. The non-transitory computer-readable medium according to Clause 104, wherein the first variable is r1, the second variable is r2, r1 is a radial distance from a center of the wafer to a first wafer region boundary, and r2 is a radial distance from the center of the wafer to a second wafer region boundary. Clause 106. The constraint on the first variable and the second variable is 0<r1, r2<r max the non-transitory computer-readable medium according to Clause 105, wherein r max is a radius of the wafer. Clause 107. The non-transitory computer-readable medium according to Clause 105 or 106, wherein the constraint on the first variable and the second variable includes r1<r2. Clause 108. The non-transitory computer-readable medium according to any one of Clauses 101 to 107, wherein a sampling budget for a wafer region on the wafer is parameterized using the first variable, the second variable, and a third variable. Clause 109. The non-transitory computer-readable medium according to Clause 108, wherein the first variable is N1, the second variable is N2, the third variable is N3, N1 is a sampling budget for a first wafer region, N2 is a sampling budget for a second wafer region, and N3 is a sampling budget for a third wafer region. Clause 110. The constraint on N1, N2, and N3 is N1+N2+N3=N budget the non-transitory computer-readable medium according to Clause 109, wherein N budget is a total sampling budget of the wafer. Clause 111. The non-transitory computer-readable medium according to Clause 109 or 110, wherein N1, N2, and N3 are each less than a total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. Clause 112. The non-transitory computer-readable medium according to any one of Clauses 101 to 111, wherein optimizing the definition of the parameterized wafer region and the sampling budget of the parameterized wafer region comprises using a constrained global optimization technique. Clause 113. The non-transitory computer-readable medium according to Clause 112, wherein the constrained global optimization technique is a derivative-free optimization algorithm. Clause 114. The predicted value is R generated by optimizing the definition of the parameterized wafer region and the sampling budget of the parameterized wafer region 2 which is a correlation score, the non-transitory computer-readable medium according to any one of Clauses 101 to 113. Clause 115. The operation comprises: generating a sampling plan for guiding wafer inspection of a second wafer; and calculating an expected die loss using the inspection result of the second wafer; and obtaining a probe test result of the second wafer; and R 2 evaluating a correlation score, the non-transitory computer-readable medium according to any one of Clauses 101 to 114, further comprising. Clause 116. The non-transitory computer-readable medium according to any one of Clauses 101 to 115, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 117. The non-transitory computer-readable medium according to any one of Clauses 101 to 116, wherein the computer computed defect probability prediction model is a computer computation-guided inspection model. Clause 118. A system for generating an inspection tool sampling plan using a computational model, the system comprising: one or more processors configured to execute instructions, wherein the instructions cause the system to: provide wafer input data to a computer computed defect probability prediction model; and divide the wafer into a plurality of wafer regions having a plurality of dies; and determine a defective die probability for each wafer region from the computer computed defect probability prediction model; and select at least one die from each of the plurality of wafer regions using the determined defective die probability; and A system comprising one or more processors that generate a wafer sampling plan based on a selected die and perform the following actions. Clause 119. The method according to any one of Clauses 1 to 8, wherein the defect die probability of the selected die exceeds a threshold. Clause 120. The method described in any one of Clauses 1 to 8 or 119, wherein the selected die includes a die from a wafer that has been excluded from the wafer's static sampling plan. Clause 121. The method according to Clause 120, wherein the defect die probability of the selected die is less than the defect die probability of the dies included in the static sampling plan. Clause 122. The method described in any one of Clauses 120 to 121, wherein the static sampling plan of the wafer includes a predetermined area of ​​the wafer. Clause 123. The method according to Clause 122, wherein a predetermined area of ​​a wafer is based on past defective die data of one or more wafers. Clause 124. A method for generating an inspection tool sampling plan, To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying a static sampling plan, A method comprising applying a dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability. Clause 125. The method of Clause 124, wherein generating a static sampling plan is based on historical probe data of multiple samples. Clause 126. The method according to Clause 125, wherein the chronological probe data includes die defect data during inspection of multiple samples. Clause 127. Generating a static sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, The method according to any one of clauses 125 to 126, including generating a static sampling plan based on the generated probability estimation map. Clause 128. The method described in any one of Clauses 124-127, which involves applying a static sampling plan, including inspecting samples in areas corresponding to historically high defect probabilities. Clause 129. Generating a dynamic sampling plan based on a trained computer model, using the method described in any one of Clauses 124-128. Clause 130. The method according to Clause 129, wherein the trained computer computation model is a computer computationally inductive test model. Clause 131. Generating a dynamic sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, The method described in any one of clauses 129 to 130, including converting a probability estimate into a dynamic sampling design. Clause 132. The method according to Clause 131, wherein the preparation data includes metrometry data corresponding to the preparation of the sample. Clause 133. The method according to Clause 132, wherein the metrologic data includes one or more of the following in the integrated circuit structure on the sample: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects. Clause 134. The method of any one of Clauses 124 to 133, further comprising generating a metronome sampling plan or modifying an existing metronome sampling plan to obtain fabrication data from areas of samples that have historically had a low defect probability. Article 135. Using a sampling plan to guide the sample testing of samples, Using the sample test results, calculate the predicted die loss, Obtaining the probe test results of the sample, By comparing probe test results with the predicted die loss, R 2 further comprising evaluating a correlation score, the method according to any one of Clauses 124 to 134. Clause 136. The method according to any one of Clauses 124 to 135, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool. Clause 137. A method for defect detection using a computationally guided inspection sampling plan, comprising: generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabrication data and a computational model; applying the baseline sampling plan to a sample; applying the excursion event sampling plan to the sample if a predicted defect probability exceeds a threshold in an area of the sample that historically had a low defect probability. Clause 138. A method for generating an inspection tool sampling plan, comprising: providing input data of a wafer to a computational defect probability prediction model; determining a defective die probability for a first region of the wafer from the computational defect probability prediction model; generating a wafer sampling plan based on the defective die probability determined for the first region of the wafer and based on a predetermined second region of the wafer. Clause 139. The method of Clause 138, wherein the defective die probability of the first region of the wafer is smaller than the defective die probability of dies in the second region of the wafer. Clause 140. The method according to any one of Clauses 138 to 139, wherein the defective die probability of the first region of the wafer exceeds a threshold. Clause 141. The method according to any one of Clauses 138 to 140, wherein the second region of the wafer is determined based on historical defective die data of one or more wafers. Clause 142. The method described in any one of Clauses 138 to 141, wherein the input data includes an image containing wafer metronome information. Clause 143. The method according to any one of Clauses 138 to 142, wherein the input data includes a definition of a predetermined wafer region and a sampling budget for each wafer region of the wafer. Article 144. Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 138 to 143, further comprising evaluating the correlation score. Clause 145. The method according to Clause 144, wherein the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 146. The method of Clause 145, wherein a non-uniform defect density or distribution is obtained from static stack probe defect probability estimation or from a computer-computed defect probability prediction model. Clause 147. The method described in any one of Clauses 138 to 146, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 148. The method described in any one of Clauses 138 to 147, wherein the computer-generated defect probability prediction model is a computer-generated inductive test model. Clause 149. An apparatus described in any one of Clauses 40 to 47, wherein the defect die probability of the selected die exceeds a threshold. Clause 150. An apparatus as described in any one of Clauses 40-47 or 149, wherein the selected die includes a die from a wafer that has been excluded from the wafer's static sampling plan. Clause 151. The apparatus described in Clause 150, wherein the defect die probability of the selected die is less than the defect die probability of the dies included in the static sampling plan. Clause 152. An apparatus as described in any one of Clauses 150 to 151, wherein the static sampling plan of the wafer includes a predetermined area of ​​the wafer. Clause 153. The apparatus described in Clause 152, wherein a predetermined area of ​​a wafer is based on past defective die data of one or more wafers. Clause 154. A non-transient computer-readable medium as described in any one of Clauses 79-86, wherein the probability of a selected die being defective exceeds a threshold. Clause 155. A non-temporary computer-readable medium as described in any one of Clauses 79-86 or 154, including dies from wafers that have been excluded from the wafer static sampling plan. Clause 156. A non-temporary computer-readable medium as described in Clause 155, wherein the defect die probability of the selected die is less than the defect die probability of the dies included in the static sampling plan. Clause 157. A non-temporary computer-readable medium as described in any one of Clauses 155 to 156, in which a static sampling plan for a wafer includes a predetermined area of ​​the wafer. Clause 158. A non-transient computer-readable medium as described in Clause 157, on which a given area of ​​a wafer is based on past defective die data of one or more wafers. Clause 159. The method described in Clause 137, which generates a baseline sampling plan based on historical probe data of multiple samples. Clause 160. The method according to Clause 159, wherein the chronological probe data includes die defect data during inspection of multiple samples. Clause 161. Generating a baseline sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, The method according to any one of clauses 159 to 160, including generating a baseline sampling plan based on the generated probability estimation map. Clause 162. The method described in any one of Clauses 137 or 159-161, wherein the application of a baseline sampling plan includes inspecting samples in areas corresponding to historically high defect probabilities. Clause 163. Generating an excursion event sampling plan based on a trained computer model, using the method described in any one of Clauses 137 or 159-162. Clause 164. The method described in Clause 163, wherein the trained computer computation model is a computer computationally inductive test model. Clause 165. Generating an excursion event sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, The method described in any one of clauses 163 to 164, including converting a probability estimate into an excursion event sampling plan. Clause 166. The method according to Clause 165, wherein the preparation data includes metrometry data corresponding to the preparation of the sample. Clause 167. The method according to Clause 166, wherein the metrologic data includes one or more of the following in the integrated circuit structure on the sample: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects. Clause 168. The method of any one of Clauses 137 or 159-167, further comprising generating a metronome sampling plan or modifying an existing metronome sampling plan to obtain fabrication data from areas of samples that have historically had a low defect probability. Article 169. Using a sampling plan to guide the sample testing of samples, Using the sample test results, calculate the predicted die loss, Obtaining the probe test results of the sample, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 137 or 159-168, further comprising evaluating the correlation score. Clause 170. The method described in any one of Clauses 137 or 159-169, wherein the inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool. Clause 171. Apparatus for generating inspection tool sampling plans, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying a static sampling plan, An apparatus comprising at least one processor that performs an operation including applying a dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability. Clause 172. The apparatus described in Clause 171, which generates a static sampling plan based on historical probe data of multiple samples. Clause 173. The apparatus described in Clause 172, wherein the chronological probe data includes die defect data during inspection of multiple samples. Clause 174. Generating a static sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, An apparatus as described in any one of Clauses 172 to 173, including generating a static sampling plan based on a generated probability estimation map. Clause 175. Apparatus described in any one of Clauses 171 to 174, which includes applying a static sampling plan to inspect samples in areas corresponding to historically high defect probabilities. Clause 176. An apparatus described in any one of Clauses 171 to 175 that generates a dynamic sampling plan based on a trained computer model. Clause 177. The apparatus described in Clause 176, wherein the trained computer computation model is a computer computationally inductive test model. Clause 178. Generating a dynamic sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, Apparatus as described in any one of Clauses 176 to 177, including converting a probability estimate into a dynamic sampling plan. Clause 179. The apparatus described in Clause 178, wherein the preparation data includes metronome data corresponding to the preparation of the sample. Clause 180. The apparatus described in Clause 179, in which the metrologic data includes one or more of the following in an integrated circuit structure on a sample: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects. Clause 181. The apparatus described in any one of Clauses 171 to 180, further comprising generating a metronome sampling plan or modifying an existing metronome sampling plan to obtain fabrication data from areas of samples that have historically had a low defect probability. Article 182. Using a sampling plan to guide the sample testing of samples, Using the sample test results, calculate the predicted die loss, Obtaining the probe test results of the sample, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 171 to 181, further comprising evaluating the correlation score. Clause 183. The apparatus described in any one of Clauses 171 to 182, wherein the inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool. Clause 184. Apparatus for defect detection using a computationally inductive inspection sampling plan, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, Generating a baseline sampling plan based on historical test data, Based on the generated data and computer calculation model, an excursion event sampling plan is generated, Applying a baseline sampling plan to the samples, An apparatus comprising at least one processor, which causes the apparatus to perform an operation including applying an excursion event sampling plan to a sample if the predicted defect probability exceeds a threshold in an area of ​​the sample that has historically had a low defect probability. Clause 185. The apparatus described in Clause 184, which generates a baseline sampling plan based on historical probe data of multiple samples. Clause 186. The apparatus described in Clause 185, wherein the chronological probe data includes die defect data during inspection of multiple samples. Clause 187. Generating a baseline sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, The method described in any one of clauses 185 to 186, including generating a baseline sampling plan based on the generated probability estimation map. Clause 188. Apparatus described in any one of Clauses 184-187, which includes applying a baseline sampling plan to inspect samples in areas corresponding to historically high defect probabilities. Clause 189. An apparatus described in any one of Clauses 184-188, which generates an excursion event sampling plan based on a trained computer model. Clause 190. The apparatus described in Clause 189, wherein the trained computer computation model is a computer computationally inductive test model. Clause 191. Generating an excursion event sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, Apparatus as described in any one of Clauses 189 to 190, including converting probability estimates into excursion event sampling plans. Clause 192. The apparatus described in Clause 191, wherein the preparation data includes metronome data corresponding to the preparation of the sample. Clause 193. The apparatus described in Clause 192, in which the metrologic data includes one or more of the following in an integrated circuit structure on a sample: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects. Clause 194. The apparatus described in any one of Clauses 184 to 193, further comprising generating a metronome sampling plan or modifying an existing metronome sampling plan to obtain fabrication data from areas of samples that have historically had a low defect probability. Article 195. Using a sampling plan to guide the sample testing of samples, Using the sample inspection results, we calculate the predicted die loss. Obtaining the probe test results of the sample, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 184 to 194, further comprising evaluating the correlation score. Clause 196. The apparatus described in any one of Clauses 184 to 195, wherein the inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool. Clause 197. Apparatus for generating inspection tool sampling plans, Memory that stores a set of instructions, At least one processor configured to execute a set of instructions, wherein the set of instructions is provided to the device, To provide wafer input data to a computer-based defect probability prediction model, Determining the defect die probability of the first region of the wafer from a computer-calculated defect probability prediction model, An apparatus comprising at least one processor that performs an operation including generating a wafer sampling plan based on a defect die probability determined for a first region of the wafer and based on a predetermined second region of the wafer. Clause 198. The apparatus described in Clause 197, wherein the defect die probability of a first region of the wafer is less than the defect die probability of a second region of the wafer. Clause 199. An apparatus as described in any one of Clauses 197-198, wherein the defect die probability of a first region of the wafer exceeds a threshold. Clause 200. The apparatus described in any one of Clauses 197 to 199, wherein a second area of ​​a wafer is determined based on hysteretic defect die data of one or more wafers. Clause 201. An apparatus as described in any one of Clauses 197 to 200, wherein the input data includes an image containing wafer metronome information. Clause 202. An apparatus as described in any one of Clauses 197 to 201, wherein the input data includes a definition of a predetermined wafer region and a sampling budget for each wafer region of the wafer. Article 203. Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 197 to 202, further comprising evaluating the correlation score. Clause 204. The apparatus described in Clause 203, wherein the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 205. The apparatus described in Clause 204, wherein the non-uniform defect density or distribution is obtained from static stack probe defect probability estimation or from predictions of a computer-computed defect probability prediction model. Clause 206. An apparatus as described in any one of Clauses 197 to 205, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 207. An apparatus as described in any one of Clauses 197 to 206, wherein the computer-generated defect probability prediction model is a computer-generated inductive inspection model. Clause 208. A non-temporary computer-readable medium including a set of instructions executable by one or more processors of a computing device for causing the computing device to perform an action for generating an inspection tool sampling plan, wherein the action is: To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying a static sampling plan, A non-temporary computer-readable medium that includes applying a dynamic sampling plan by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability. Clause 209. Generating a static sampling plan based on historical probe data of multiple samples in non-temporary computer-readable media as described in Clause 208. Clause 210. A non-temporary computer-readable medium as described in Clause 209, in which historical probe data includes die defect data during inspection of multiple samples. Clause 211. Generating a static sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, A non-temporary computer-readable medium as described in any one of clauses 209 to 210, including generating a static sampling plan based on the generated probability estimation map. Clause 212. Non-temporary computer-readable media as described in Clauses 208-211, which include applying a static sampling plan to inspect samples in areas corresponding to historically high defect probabilities. Clause 213. Generating a dynamic sampling plan is based on a trained computer model and is a non-temporary computer-readable medium as described in any one of Clauses 208-212. Clause 214. A non-temporary computer-readable medium as described in Clause 213, where the trained computer computation model is a computer computation-inducing test model. Clause 215. Generating a dynamic sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, The method described in any one of clauses 213 to 214, including converting a probability estimate into a dynamic sampling plan. Clause 216. Non-temporary computer-readable media as described in Clause 215, in which the preparation data includes metrology data corresponding to the preparation of the sample. Clause 217. Non-transient computer-readable media as described in Clause 216, in which metrologic data includes one or more of the following: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of integrated circuit structures on a sample. Clause 218. A non-temporary computer-readable medium as described in any one of Clauses 208 to 217, wherein a set of instructions executable by one or more processors of the computing device causes the computing device to further perform tasks such as generating a metronome sampling plan or modifying an existing metronome sampling plan in order to obtain fabricated data from areas of samples that have historically had a low probability of defects. Clause 219. A set of instructions that can be executed by one or more processors of a computing device is provided to the computing device. Using a sampling plan to guide the sample testing of samples, Using the sample test results, calculate the predicted die loss, Obtaining the probe test results of the sample, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 208-218, which further enables the evaluation of correlation scores. Clause 220. The inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool, in a non-temporary computer-readable medium as described in any one of Clauses 208 to 219. Clause 221. A non-temporary computer-readable medium comprising a set of instructions executable by one or more processors of a computing device for causing the computing device to perform an operation for defect detection using a computer-inducible inspection sampling plan, wherein the operation is: Generating a baseline sampling plan based on historical test data, Based on the generated data and computer calculation model, an excursion event sampling plan is generated, Applying a baseline sampling plan to the samples, A non-temporary computer-readable medium, including applying an excursion event sampling plan to a sample if the predicted defect probability exceeds a threshold in an area of ​​the sample that has historically had a low defect probability. Clause 222. Generating a baseline sampling plan based on historical probe data of multiple samples in a non-temporary computer-readable medium as described in Clause 221. Clause 223. A non-temporary computer-readable medium as described in Clause 222, in which historical probe data includes die defect data during the inspection of multiple samples. Clause 224. Generating a baseline sampling plan, By averaging historical probe data from multiple samples, a probability estimation map is generated based on the historical probe data, The method according to any one of clauses 222 to 223, including generating a baseline sampling plan based on the generated probability estimation map. Clause 225. Non-temporary computer-readable media as described in any one of Clauses 221-224, where the application of a baseline sampling plan includes inspecting the sample in areas corresponding to historically high defect probabilities. Clause 226. The sampling plan for excursion events is generated on a non-temporary computer-readable medium as described in any one of Clauses 221 to 225, based on a trained computer model. Clause 227. A non-temporary computer-readable medium as described in Clause 226, where the trained computer computation model is a computer computation-inducing test model. Clause 228. Generating an excursion event sampling plan, The data from the creation of the samples is supplied to a trained computer model, To generate a probability estimate of the sample, A non-temporary computer-readable medium as described in any one of clauses 226 to 227, including converting probability estimates into excursion event sampling plans. Clause 229. Non-temporary computer-readable media as described in Clause 228, in which the preparation data includes metrology data corresponding to the preparation of the sample. Clause 230. Non-transient computer-readable media as described in Clause 229, in which metrologic data includes one or more of the following: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of integrated circuit structures on a sample. Clause 231. A non-temporary computer-readable medium as described in any one of Clauses 221 to 230, wherein a set of instructions executable by one or more processors of the computing device causes the computing device to further perform the task of generating a metrologic sampling plan or modifying an existing metrologic sampling plan in order to obtain fabricated data from areas of samples that have historically had a low probability of defects. Clause 232. A set of instructions that can be executed by one or more processors of a computing device is provided to the computing device. Using a sampling plan to guide the sample testing of samples, Using the sample test results, calculate the predicted die loss, Obtaining the probe test results of the sample, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 221 to 231, which further enables the evaluation of correlation scores. Clause 233. The inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool, a non-temporary computer-readable medium as described in any one of Clauses 221 to 232. Clause 234. A non-temporary computer-readable medium including a set of instructions executable by one or more processors of a computing device for causing the computing device to perform an action for generating an inspection tool sampling plan, wherein the action is: To provide wafer input data to a computer-based defect probability prediction model, Determining the defect die probability of the first region of the wafer from a computer-calculated defect probability prediction model, A non-temporary computer-readable medium comprising generating a wafer sampling plan based on a defect die probability determined for a first region of the wafer and based on a predetermined second region of the wafer. Clause 235. A non-transient computer-readable medium as described in Clause 234, wherein the defect die probability of a first area of ​​the wafer is less than the defect die probability of a second area of ​​the wafer. Clause 236. A non-transient computer-readable medium as described in any one of Clauses 234-235, wherein the defect die probability of a first region of the wafer exceeds a threshold. Clause 237. A non-temporary computer-readable medium as described in any one of Clauses 234 to 236, in which the second area of ​​the wafer is determined based on the hierarchical defect die data of one or more wafers. Clause 238. Non-temporary computer-readable media as described in any one of Clauses 234 to 237, including images containing wafer metronome information. Clause 239. A non-temporary computer-readable medium as described in any one of Clauses 234 to 238, in which the input data includes the definition of a given wafer area and the sampling budget for each wafer area of ​​the wafer. Clause 240. A set of instructions that can be executed by one or more processors of a computing device is provided to the computing device. Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 234-239, which further enables the evaluation of correlation scores. Clause 241. A non-transient computer-readable medium as described in Clause 240, in which the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. Clause 242. Non-transient computer-readable media as described in Clause 241, in which a non-uniform defect density or distribution is obtained from static stack probe defect probability estimation or from predictions of a computer-computed defect probability prediction model. Clause 243. A non-temporary computer-readable medium as described in any one of Clauses 234 to 242, wherein the inspection tool is a scanning charged particle microscope or an optical tool. Clause 244. A non-temporary computer-readable medium as described in any one of Clauses 234 to 243, in which the computer-calculated defect probability prediction model is a computer-calculated guided test model. Clause 245. The method of any one of Clauses 1-8 or 119-123, further comprising adjusting manufacturing process parameters based on a determined defect die probability in order to reduce areas of the wafer that are prone to defects. Clause 246. The method according to Clause 245, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 247. An apparatus as described in any one of Clauses 40-47 or 149-53, wherein a set of instructions executable by at least one processor causes the apparatus to further adjust manufacturing process parameters based on a determined defective die probability in order to reduce areas of the wafer that are prone to defects. Clause 248. The apparatus described in Clause 247, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 249. A non-temporary computer-readable medium as described in any one of Clauses 79-86 or 154-158, wherein a set of instructions executable by one or more processors of the computing device causes the computing device to further adjust manufacturing process parameters based on a determined defective die probability in order to reduce areas of the wafer that are prone to defects. Clause 250. A non-temporary computer-readable medium as described in Clause 249, wherein the manufacturing process parameters include one or more of the parameters of a scanner recipe or an etcher recipe. Clause 251. The method according to any one of Clauses 124 to 136, further comprising adjusting the fabrication process parameters based on the predicted defect probability in order to reduce areas of the sample that are prone to defects. Clause 252. The method according to Clause 251, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 253. The method of any one of Clauses 137, 159-170, further comprising adjusting the fabrication process parameters based on the predicted defect probability in order to reduce areas of the sample that are prone to defects. Clause 254. The method according to Clause 253, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 255. The method of any one of Clauses 138 to 148, further comprising adjusting manufacturing process parameters based on a determined defect die probability in order to reduce areas of the wafer that are prone to defects. Clause 256. The method according to Clause 253, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 257. Apparatus as described in any one of Clauses 171 to 183, further comprising adjusting fabrication process parameters based on predicted defect probabilities in order to reduce areas of the sample that are prone to defects. Clause 258. The apparatus described in Clause 257, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 259. Apparatus as described in any one of Clauses 184-196, further comprising adjusting the fabrication process parameters based on the predicted defect probability in order to reduce areas of the sample that are prone to defects. Clause 260. The apparatus described in Clause 259, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 261. Apparatus as described in any one of Clauses 197-207, further comprising adjusting manufacturing process parameters based on a determined defect die probability in order to reduce areas of the wafer that are prone to defects. Clause 262. The apparatus described in Clause 261, wherein the manufacturing process parameters include one or more of the parameters of the scanner recipe or the parameters of the etcher recipe. Clause 263. A non-temporary computer-readable medium as described in any one of Clauses 208-220, wherein a set of instructions executable by one or more processors of the computing device causes the computing device to further perform the adjustment of manufacturing process parameters based on predicted defect probabilities in order to reduce areas of a sample that are prone to defects. Clause 264. A non-temporary computer-readable medium as described in Clause 263, wherein the manufacturing process parameters include one or more of the parameters of a scanner recipe or an etcher recipe. Clause 265. A non-temporary computer-readable medium as described in any one of Clauses 221 to 233, wherein a set of instructions executable by one or more processors of the computing device causes the computing device to further adjust manufacturing process parameters based on predicted defect probabilities in order to reduce areas of the sample that are prone to defects. Clause 266. A non-temporary computer-readable medium as described in Clause 265, wherein the manufacturing process parameters include one or more of the parameters of a scanner recipe or an etcher recipe. Clause 267. A non-transient computer-readable medium as described in any one of Clauses 234-244, wherein a set of instructions executable by one or more processors of a computing device causes the computing device to further adjust manufacturing process parameters based on a determined defective die probability in order to reduce areas of the wafer that are prone to defects. Clause 268. A non-temporary computer-readable medium as described in Clause 267, wherein the manufacturing process parameters include one or more of the parameters of a scanner recipe or an etcher recipe. Clause 269. The method described in any one of Clauses 124-136, 251, or 252, wherein a static sampling plan is generated based on the sampling budget ratio of the wafer. Clause 270. The method according to Clause 269, wherein the wafer sampling budget ratio includes the allocation of dies to be sampled by a static sampling plan and the allocation of dies to be sampled by a dynamic sampling plan. Clause 271. The method of any one of Clauses 124-136, 251, 252, 269, or 270, which includes generating a static sampling plan, including selecting a fixed die location for the wafer to be inspected. Clause 272. The method described in any one of Clauses 124-136, 251, 252, or 269-271, which includes generating a static sampling plan, which includes generating a stack probe wafer map. Clause 273. The method according to Clause 272, wherein the stack probe wafer map includes multiple defect probability results corresponding to dies on the wafer. Clause 274. The method of Clause 273, wherein multiple defect probability results indicate the probability that the die contains a defect. Clause 275. The method of any one of Clauses 272 to 274, wherein generating a stack probe wafer map includes averaging hysteretic defect data of multiple wafers. Clause 276. The method described in any one of Clauses 124-136, 251, 252, or 269-271, which includes generating a static sampling plan, which includes generating a stack sampling wafer map. Clause 277. The method according to Clause 276, wherein the stacked sampling wafer map includes multiple sampling probability results corresponding to dies on the wafer. Clause 278. The method of Clause 277, wherein multiple sampling probability results indicate the probability of whether or not a die is sampled. Clause 279. The method of any one of Clauses 276 to 278, wherein generating a stacked sampling wafer map includes averaging chronological sampling data of multiple wafers. Clause 280. The method described in any one of Clauses 135-136, wherein the predicted die loss is calculated based on the predicted defect probability of the static sampling plan, the predicted defect probability of the dynamic sampling plan, the sampling ratio of the static sampling plan, and the sampling ratio of the dynamic sampling plan. Clause 281. The method described in any one of Clauses 137, 159-170, 253, or 254, wherein the baseline sampling plan is generated based on the wafer sampling budget ratio. Clause 282. The method according to Clause 281, wherein the wafer sampling budget ratio includes the allocation of dies to be sampled by the baseline sampling plan and the allocation of dies to be sampled by the excursion event sampling plan. Clause 283. The method of any one of Clauses 137, 159-170, 253, 254, 281, or 282, which includes generating a baseline sampling plan, including selecting a fixed die location for the wafer to be inspected. Clause 284. The method described in any one of Clauses 137, 159-170, 253, 254, or 281-283, which includes generating a baseline sampling plan, or generating a stack probe wafer map. Clause 285. The method according to Clause 284, wherein the stack probe wafer map includes multiple defect probability results corresponding to dies on the wafer. Clause 286. The method of Clause 285, wherein multiple defect probability results indicate the probability that the die contains a defect. Clause 287. The method of any one of Clauses 284 to 286, wherein generating a stack probe wafer map includes averaging hysteretic defect data of multiple wafers. Clause 288. The method described in any one of Clauses 137, 159-170, 253, 254, or 281-283, which includes generating a baseline sampling plan, or generating a stack sampling wafer map. Clause 289. The method according to Clause 288, wherein the stacked sampling wafer map includes multiple sampling probability results corresponding to dies on the wafer. Clause 290. The method according to Clause 289, wherein multiple sampling probability results indicate the probability of whether or not a die is sampled. Clause 291. The method described in any one of Clauses 288 to 290, wherein generating a stacked sampling wafer map includes averaging chronological sampling data from multiple wafers. Clause 292. The method according to any one of Clauses 169 to 170, wherein the predicted die loss is calculated based on the predicted defect probability of the baseline sampling plan, the predicted defect probability of the excursion event sampling plan, the sampling ratio of the baseline sampling plan, and the sampling ratio of the excursion event sampling plan. Clause 293. A system for generating inspection tool sampling plans, Memory that stores a set of instructions, A system comprising one or more processors configured to execute a set of instructions to cause the system to perform an operation in accordance with any one of the clauses 269 to 279. Article 294. A system for defect detection using a computer-guided inspection sampling plan, Memory that stores a set of instructions, A system comprising one or more processors configured to execute a set of instructions to cause the system to perform an operation in accordance with any one of the clauses 280 to 292. Clause 295. A non-temporary computer-readable medium for storing a set of instructions executable by at least one processor of a computing device for causing the computing device to perform a method for generating a test tool sampling plan as described in any one of Clauses 269 to 279. Clause 296. A non-temporary computer-readable medium for storing a set of instructions executable by at least one processor of a computing device for causing the computing device to implement a method for defect detection using a computer-inducible inspection sampling plan as described in any one of Clauses 280 to 292.

[0154]

[0170] The block diagrams in the figures may illustrate the architecture, functions, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic diagram may represent a specific arithmetic or logical operation that can be implemented using hardware such as electronic circuits. A block may also represent a module, segment, or part of code containing one or more executable instructions for performing a specified logical function. It should be understood that in some alternative implementations, the functions shown in a block may be performed in an order different from the order shown in the drawings. For example, two consecutively shown blocks may be executed or performed substantially simultaneously, or two blocks may be executed in reverse order depending on the functions they relate to. Some blocks may be omitted. It should be understood that each block and combination of blocks in the block diagram may also be performed by a dedicated hardware-based system or a combination of dedicated hardware and computer instructions that performs a specified function or operation.

[0155]

[0171] It will be understood that the embodiments of this disclosure are not limited to the structures described above and shown in the accompanying drawings, and that various modifications and alterations may be made without departing from the scope of this disclosure. While this disclosure has been described in relation to various embodiments, other embodiments will become apparent to those skilled in the art by examining the specifications and practices of the art disclosed herein. This specification and examples are to be considered merely illustrative, and the true scope and spirit of this disclosure are intended to be shown by the following claims.

Claims

1. A non-temporary computer-readable medium storing a set of instructions executable by at least one processor of a computing device for causing the computing device to perform an operation for generating an inspection tool sampling plan, wherein the operation is To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying the aforementioned static sampling plan, The dynamic sampling plan is applied by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability, Non-temporary computer-readable media, including [specific examples of such media].

2. The non-temporary computer-readable medium according to claim 1, wherein the static sampling plan is generated based on historical probe data of multiple samples.

3. The non-temporary computer-readable medium according to claim 2, wherein the hierarchical probe data includes die defect data during inspection of the plurality of samples.

4. To generate the aforementioned static sampling plan, By averaging the historical probe data of the multiple samples, a probability estimation map is generated based on the historical probe data. The process involves generating the static sampling plan based on the generated probability estimation map, A non-temporary computer-readable medium according to claim 2, including the following:

5. The non-temporary computer-readable medium according to claim 1, wherein applying the static sampling plan includes inspecting the sample in areas corresponding to historically high defect probabilities.

6. The non-temporary computer-readable medium according to claim 1, wherein the generation of the dynamic sampling plan is based on a trained computer computation model.

7. The non-temporary computer-readable medium according to claim 6, wherein the trained computer model is a computer-inducible test model.

8. The generation of the aforementioned dynamic sampling plan is The sample preparation data is supplied to the trained computer model, To generate a probability estimate of the aforementioned sample, Converting the aforementioned probability estimation into the aforementioned dynamic sampling plan, A non-temporary computer-readable medium according to claim 6, including the following:

9. The non-temporary computer-readable medium according to claim 8, wherein the production data includes metronome data corresponding to the production of the sample.

10. The non-transient computer-readable medium according to claim 9, wherein the metrologic data includes one or more of the following: necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on a sample.

11. The non-temporary computer-readable medium according to claim 1, further comprising generating a metronome sampling plan or modifying an existing metronome sampling plan in order to obtain fabrication data from areas of samples that have historically had a low defect probability.

12. The aforementioned operation, Using the aforementioned sampling plan, the sample testing of the samples will be guided, Using the inspection results of the aforementioned sample, the predicted die loss is calculated, Obtain the probe test results of the aforementioned sample, By comparing the probe test results with the predicted die loss, R ２ Evaluating the correlation score, A non-temporary computer-readable medium according to claim 1, further comprising:

13. The non-temporary computer-readable medium according to claim 1, wherein the inspection tool in the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

14. A system for generating inspection tool sampling plans, Memory that stores a set of instructions, One or more processors configured to execute the set of instructions, wherein the set of instructions is configured in the system To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying the aforementioned static sampling plan, The dynamic sampling plan is applied by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability, One or more processors that perform operations including, A system equipped with these features.

15. A method for generating a sampling plan for an inspection tool, To generate a static sampling plan to determine the baseline for testing, To generate a dynamic sampling plan for determining excursion events, Applying the aforementioned static sampling plan, The dynamic sampling plan is applied by triggering additional sampling when the predicted defect probability exceeds a threshold in an area of ​​samples that previously had a low defect probability, A method that includes this.

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