Integrated circuit with memory and shared write port

Abstract

A semiconductor package is provided that includes a memory wafer and an application wafer bonded together to create a system for data processing and memory storage. The memory wafer is a host for a group of modules, each having several modules, a shared write port, and an independent read port to enable simultaneous read operations. The application wafer, which communicates operably with the memory wafer, may include various processing elements such as FPGA cores, GPUs, CPUs, and neural network accelerators. Both wafers have a perimeter with the same extent and can support configurations such as rectangular, square, and circular shapes, providing substantial memory capacity. The package may use bump-less bonding technology to reduce thermal and electrical resistance and incorporate through-silicon vibrators (TSVs) for robust interconnects.

Description

Technical Field

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed on August 11, 2023, entitled "INTEGRATED CIRCUIT HAVING MEMORIES AND A SHARED WRITE PORT", which is identified by attorney docket number P23-133-US-PSP, the entire content of which is incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed on November 27, 2023, entitled "METHOD AND SYSTEM FOR KNOWN-GOOD-DIE TESTABILITY OF FACE-TO-FACE BONDED CHIPLETS", the entire content of which is incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed on November 27, 2023, entitled "SYSTEM AND METHOD FOR HAVING CORRECT-BY-CONSTRUCTION TIMING CLOSURE", the entire content of which is incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed on March 20, 2024, entitled "ASSEMBLY HAVING A FACE-TO-FACE BONDED CHIPLET", which is identified by attorney docket number P24-052-US-PSP, the entire content of which is incorporated herein by reference.

[0005] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed on 23 April 2024, identified by reference number P24-081-US-PSP, entitled “INTEGRATED CIRCUIT HAVING MICROVAULT MEMORIES,” the entire contents of which are incorporated herein by reference.

[0006] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed on 23 April 2024, identified by reference number P24-082-US-PSP, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS,” the entire contents of which are incorporated herein by reference.

[0007] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed on 23 July 2024, identified by reference number P24-135-US-PSP, entitled “SYSTEM, METHOD, AND APPARATUS FOR WAFER-SCALE MEMORY,” the entire contents of which are incorporated herein by reference.

[0008] Technical field This disclosure relates to an integrated circuit. More specifically, this disclosure relates to an integrated circuit having a plurality of modules having memory and a shared write port. [Background technology]

[0009] Description of related technologies A chiplet refers to a small chip designed to function as a single entity while utilizing advanced packaging technology. This miniaturized chip is created by dividing a larger chip into several smaller chips, each possessing a unique function or capability. The concept, stemming from the semiconductor industry, requires overcoming the physical limitations of traditional monolithic chip designs and achieving higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality. [Overview of the project] [Problems that the invention aims to solve]

[0010] Chiplets are derived from different architectures such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways according to the requirements of a specific application. One of the advantages of the chiplet approach is that different chiplets from different manufacturers can be mixed and matched to create custom solutions that meet specific computing requirements. Because chiplets can be upgraded or replaced without requiring a complete system redesign, this approach also enables shorter time to market, reduced development costs, and increased flexibility.

[0011] The effects of chiplets can be utilized in a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chiplets are expected to play a significant role in future computing and are thought to unlock new possibilities for creating more powerful and / or advanced electronic devices. [Means for solving the problem]

[0012] Summary of the Invention

[0013] Integrated circuits, which may be part of semiconductor devices, are disclosed herein. Methods for manufacturing or writing and reading data to and from the modules are disclosed herein and may be used in conjunction with all examples, embodiments, and aspects described herein.

[0014] In one schematic embodiment, the integrated circuit may include a group of modules having a plurality of modules, including a first module and a second module. The integrated circuit may also include a shared write port configured to write to the group of modules. The integrated circuit may further include a first read port configured to read from the first module. In addition, the integrated circuit may include a second read port configured to read from the second module.

[0015] The implementation may include one or more of the following features: The integrated circuit may have first and second read ports configured to be deactivated when a write operation is applied to a shared write port. The integrated circuit may include a shared write peripheral, which may be located on a first semiconductor device and configured to write to a group of modules via a shared write port, the shared write peripheral being located on the silicon substrate of the first semiconductor device; a first read peripheral being configured to read a first module via a first read port, the first read peripheral being located on the silicon substrate of the first semiconductor device; and a second read peripheral being configured to read a second module via a second read port, the second read peripheral being located on the silicon substrate of the first semiconductor device, with the first and second modules located on a second layer of the first semiconductor device.

[0016] The integrated circuit may be configured such that the first module is a three-dimensional column of memory bit cells disposed between a first surface of the first semiconductor device and a silicon substrate of the first semiconductor device. The integrated circuit may have a first read port configured to electrically communicate with a second semiconductor device, and / or the second semiconductor device is configured to be fixed to the first surface of the first semiconductor device.

[0017] One or more interposers may be located between the first surface of the first semiconductor device and the second semiconductor device. The first read port may include a read address bus that traverses the second layer of the first semiconductor device. The first read port may include a read data bus that traverses the second layer of the first semiconductor device. A shared write port may be configured to communicate electrically with the second semiconductor device. The second semiconductor device may be configured to be fixed to the first surface of the first semiconductor device. The integrated circuit may include an interposer of electrical connections located between the first surface of the first semiconductor device and the second semiconductor device. The shared write port may include a write address bus that traverses the second layer of the first semiconductor device. The shared write port may include a write data bus that traverses the second layer of the first semiconductor device.

[0018] The first and second read ports may be configured to process reads from each other simultaneously. A shared write port may be configured to write to the address space. The shared write port may be configured to write to the first module via a first portion of the address space and to the second module via a second portion of the address space. Each module in a group of modules may include an independent read port that reads simultaneously through any of the independent read ports of the group of modules, where the first read port is configured to read from the first module simultaneously with another read from the second module using the second read port. The group of modules may be configured to have a single write address space configured to write to the group of modules. The first read port may be configured to have a first read address space, and the second read port may be configured to have a second read address space. The first read address space may numerically overlap with the second read address space. The first read address space may have the same extent as the second read address space and / or be contiguous with respect to the second read address space.

[0019] The module group may be formed in a second layer of the integrated circuit device. The integrated circuit may be implemented as a chiplet configured to be face-to-face bonded. The chiplet may include a plurality of input / output (I / O) junctions, each of which is configured to provide a read port for each of the plurality of modules, and each of which is configured to interface with a complementary input / output (I / O) junction of a second device when bonded to the chiplet.

[0020] An integrated circuit may be part of a semiconductor device. The semiconductor device may be mounted as a die, wafer, or chiplet die, and may be bonded to a second semiconductor device which is one of the following: a GPU (graphics processing unit), a SoC (system on a chip), or a GPPU (general-purpose processing unit).

[0021] The second semiconductor device may be implemented as a chiplet die, a wafer, an ASIC (application-specific semiconductor chip), and an FPGA (field-programmable gate array). The semiconductor device may include a plurality of input / output (I / O) junctions, each of which is configured to provide a read port for each of the plurality of modules, and each of which is configured to be electrically connected to a complementary input / output (I / O) junction of the second semiconductor device.

[0022] The chiplet die has a first side and a second side, where the second side is configured to be face-to-face bonded to a second semiconductor device. The chiplet die and the second semiconductor device may be part of a multichip package. The semiconductor device may include an interposer of electrical connections positioned between the chiplet die and the second semiconductor device. A first read port may be located on the chip die. The chip die has a surface, and the first module may include a memory array having a plurality of memory unit cells arranged within the first module, and a read peripheral circuit configured to read data stored in the memory array via the first read port.

[0023] The footprint is the space that a device can project onto a surface (for example, how much xy space the device occupies, which may or may not extend into a third dimension (e.g., the z-axis). The footprint of the read peripheral circuitry on the surface may overlap with the footprint of the memory array on the surface. Multiple memory unit cells may be arranged in a three-dimensional configuration. The footprint of the first read port on the surface may overlap with the footprint of the memory array on the surface. The footprint of the read peripheral circuitry on the surface may have the same extent as the footprint of the memory array on the surface. The footprint of the first read port on the surface may have the same extent as the footprint of the memory array on the surface. The memory array, read peripheral circuitry, and first read port may be stacked vertically and configured to minimize the module footprint on the surface of the chiplet die.

[0024] In some embodiments, the write peripheral circuit may be connected to the shared write port on the surface of the chiplet die such that the write peripheral circuit defines a first footprint on the surface, where the first footprint does not overlap with the footprint of the memory array and does not overlap with the footprint of the first read port, and the shared write port defines a second footprint on the surface, where the second footprint does not overlap with the footprint of the memory array and does not overlap with the footprint of the first read port. In some embodiments, the first footprint may overlap with the second footprint.

[0025] The plurality of memory unit cells may be formed from at least one non-volatile memory unit cell. These memory unit cells may include various materials such as ferroelectric, magnetic, spin-orbit torque, spin transfer torque, phase change, and / or antiferroelectric materials. One implementation may include organizing a plurality of modules into separate sections each having dedicated read peripherals, wherein each dedicated read peripheral has an independent clock. Alternatively, each module may have its own dedicated read peripheral. During reset, the group of modules may be configured to process only write commands and disable read capability. Conversely, when the group of modules is not in a reset state, the write capability may be disabled. The group of modules may include at least two different non-volatile memory technologies.

[0026] One implementation may include an integrated circuit having a dynamic allocation circuit for allocating memory blocks to a plurality of modules based on use of the group of modules. Furthermore, the integrated circuit may include write peripherals connected to dedicated I / O pads that enable data transfer external to the integrated circuit. The integrated circuit may be formed on a silicon substrate via an additive manufacturing process, and may be electrically connected to a second semiconductor device including another integrated circuit.

[0027] The integrated circuit may include read peripherals for at least one of the plurality of modules disposed on the silicon substrate or the second semiconductor device. The second semiconductor device may be implemented as a system-on-chip, a chiplet die, a wafer, an ASIC, or an FPGA.

[0028] In one implementation configuration, the multiple modules are formed from non-volatile memory unit cells arranged in a three-dimensional connection fabric perpendicular to the silicon substrate and the second semiconductor device, and may utilize at least one of crosspoints, 3D NAND, 3D NOR, 3D AND, and stacked planar layers. The integrated circuit may include a single write peripheral with a dedicated clock, or multiple clocks supplied to each module at timings separated from other modules. Each of the multiple clocks is configured to clock the respective read ports of each of the multiple modules.

[0029] Another implementation may include a group of modules formed on a chiplet having a first side and a second side, the second side being configured to be bonded to a second semiconductor device. The integrated circuit may also include a decoder circuit, a driver circuit, and a register circuit on the silicon substrate of the chiplet. Alternatively, the group of modules may be formed on a second layer of the chiplet. The second semiconductor device may have a plurality of processing elements, each processing element including an interface for communicating with each of the multiple modules in the group of modules when the second semiconductor device is bonded to the chiplet. The chiplet may also have an interface to a shared write port on the second side, thereby interface-connecting to complementary interfaces in the second semiconductor device.

[0030] The second semiconductor device may have a network-on-chip configured to provide inter-element communication between multiple processing elements. The multiple processing elements may include at least one embedded FPGA, or one of a soft processor, a DSP block, an embedded processor, and a microcontroller.

[0031] In yet another implementation, write operations to a group of modules are performed through a priority arbitration circuit that facilitates access to the modules in a predetermined order. The integrated circuit may also include a power gating circuit that selectively cuts off power to some of the modules when they are not in use. Furthermore, a shared write port may be configured to write to a virtual address space mapped to a physical memory space.

[0032] The integrated circuit may also include a control circuit configured to conserve energy by enabling the shared write port during write operations and disabling it during read operations. Alternatively, the control circuit may conserve energy by disabling the first read port during write operations and enabling it during read operations. It may also include a power management module that selectively cuts off power to the shared write port during read operations to conserve energy. The write circuit may be configured to dynamically shift power allocation from write operations to read operations, or to enter sleep mode during read operations to cut off power to the shared write port to conserve energy.

[0033] The non-volatile memory used by multiple modules may be selected from the group comprising FeFET, FeRAM, ReRAM, SOT (Spin-Orbit Torque), and STT (Spin-Transition Torque). The writing peripheral for the module group may be mounted on the silicon substrate and located between the module group and the second side of the chiplet. The reading peripheral for the first module may be mounted on the silicon substrate and located between the module group and the first side of the chiplet, or alternatively, on the second layer. In some implementations, each module has its own dedicated writing peripheral that utilizes a shared clock. [Brief explanation of the drawing]

[0034] Brief explanation of the drawing

[0035] These and other embodiments will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the drawings.

[0036] [Figure 1] Figure 1 is a block diagram of an integrated circuit, which may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure.

[0037] [Figure 2] Figure 2 shows a perspective view of an assembly having the integrated circuit of Figure 1 mounted on a semiconductor device that is electrically connected to another device to form an assembly, according to an embodiment of the present disclosure.

[0038] [Figure 3] Figure 3 shows a block diagram illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure.

[0039] [Figure 4] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to an embodiment of the present disclosure.

[0040] [Figure 5] Figure 5 shows a diagram of an integrated circuit that may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure.

[0041] [Figure 6] Figure 6 shows a perspective view of an assembly having the integrated circuit of Figure 1 mounted on a semiconductor device electrically connected to a system-on-chip, according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0042] Modes for carrying out the invention

[0043] Figure 1 shows a block diagram of an integrated circuit 100 that can be packaged as a bondable chiplet (e.g., a bondable face-to-face chiplet) according to embodiments of the present disclosure. The integrated circuit (IC) 100 includes a group of modules 106, comprising modules 108, 110, 112, and 114. The IC 100 also features a shared write port 102 configured to write to the group of modules 106 using a write peripheral 104. Furthermore, the IC 100 includes read peripherals 116, 118, 120, and 122, as well as read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0044] The write port 102 may be configured to provide a single write address space for all of the module group 106, where each of modules 108, 110, 112, and 114 has its own dedicated read ports 124, 126, 128, and 130, respectively. The integrated circuit 100 may be packaged as part of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet or IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet may be electrically connected to another device by means of bonding, soldering, wafer-wafer bonding, face-face chiplet bonding, chiplet-wafer bonding, chiplet-interposer bonding, and / or together by an interposer or other interface connection technology. An interposer may not be used, one or more interposers may be used, or other interface connection technologies common to heterogeneous 3D system-in-package solutions may be used to electrically connect the chiplet to another device.

[0045] Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use a multicycle pipeline circuit. When bonded to another device (e.g., wafer, chiplet, chip, SOC, package, FPGA, etc.), the electrical contacts may be arranged in a manner that provides exclusive access to specific modules 108, 110, 112, 114. For example, a processing / computation element may have exclusive access to module 108 via read port 124, which may contain neural network weights in its register file. Similarly, different processing / computation elements may have exclusive read access to module 110 via read port 126, which may contain different register files. In this particular embodiment, this arrangement of electrical contacts ensures that each computing / processing element has the dedicated access it needs to efficiently perform its specific calculation, thereby providing a compact, modular, and expandable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to use the same resources in a row, which would slow down the overall processing speed. By providing dedicated access, the proposed chiplet ensures, in this particular embodiment, that each processing element can operate at its maximum capacity without interference from other computing elements.

[0046] The write peripheral 104 is a peripheral circuit responsible for processing and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts such that the chip is electrically connected (e.g., junctioned) to a chiplet of the integrated circuit, and as a result, the write port 102 is accessible via a shared write logic system that includes utilizing a shift register-based different voltage design, preferably a high-voltage design, having a shared write address and data component. This shared write logic system is designed to be accessed via a junction chip, another junction chiplet, and / or other circuitry in the same package as the integrated circuit 100. The shift register may allow the system to move data through a series of steps, each of which receives data from the previous step. By utilizing the shift register, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location where data is written to the chiplet.

[0047] In another embodiment, the interlock 132 may disable the read ports 124, 126, 128, and 130 while data is being written to the module group 106 via the write port 102. Similarly, the interlock 132 may disable the write port 102 when read operations are being performed on the read ports 124, 126, 128, and 130. The written data can then be simultaneously accessed by all processing elements that need to read the data via the respective read ports 124, 126, 128, and 130. This ensures that all processing elements have the most frequently used data available to them, regardless of other reads being performed simultaneously by other processing elements.

[0048] The circuitry of the writing peripheral 104 includes a write driver. This unit receives the data to be written and converts the data into a suitable signal that can change the state of the memory cell. Depending on the type of memory technology used, the signal may include a voltage level, a current pulse, or other type of energy. The shared write logic system may be high voltage due to the specific voltage requirements of the chiplet. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within parameters suitable to avoid causing damage or unnecessary wear.

[0049] Furthermore, the circuitry of the writing peripheral 104 may feature a data buffer or a write buffer. This component temporarily stores the data to be written, enabling the write operation to be performed at an optimal pace. By balancing the rate of incoming data with the rate at which the memory cell can be written, the write buffer helps prevent data loss and optimizes system performance.

[0050] Furthermore, in some embodiments, the writing peripheral device 104 may include a write control unit that coordinates a series of operations in the writing process. This write control unit generates control signals to activate the write driver at the appropriate time, controls the flow of data from the write buffer, and adjusts the timing of the write operation. By synchronizing these various operations, the write control unit ensures efficient and reliable writing operations.

[0051] Furthermore, the writing peripheral 104 may include a data encoding mechanism to improve reliability and data integrity. For example, before data is written to the memory cell, the mechanism encodes the data in a manner that allows potential errors to be detected and, in some cases, corrected when the data is read later. This may be useful in systems where data integrity is a higher priority, such as servers or scientific research devices.

[0052] Furthermore, the writing peripheral 104 may include a timing unit that functions as the heartbeat of the system, supplying a clock signal to synchronize the operation of various components of the system. In some systems, the timing unit may include components such as an oscillator, a clock generator, or a phase-locked loop. The timing unit may ensure that all operations occur at appropriate times relative to each other.

[0053] IC100 may be implemented as a face-to-face junction chiplet in which modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC100 may also feature dynamic allocation circuits for allocating memory blocks to the module group 106 based on the use of the module group 106 (for example, each module 108 may include dynamic allocation circuits that dynamically allocate a range of read locations for its respective processing elements).

[0054] IC100 features multiple clocks, each of which supplies a clock to a module of the multiple modules, providing each module with isolated timing relative to the other modules of the multiple modules. The module group 106 may be arranged in any topology known to those skilled in the art. The bit cell density can be up to 10 times denser than the embedded SRAM cells in the module group 106.

[0055] IC100 may be formed in a chiplet including a first side and a second side, the second side being configured to be bonded to a second semiconductor device. IC100 may include high-voltage writing logic adjacent to the first side of the chiplet. Decoder circuits, driver circuits, and register circuits may be formed in the silicon substrate portion of the chiplet, while the module group 106 is formed in the second layer portion of the chiplet. The second semiconductor device may comprise a plurality of processing elements. Each processing element includes an interface for communicating with each of the multiple modules in the module group 106 when the second semiconductor device is bonded to the chiplet.

[0056] Silicon substrates traditionally serve as the initial stage in IC manufacturing, focusing on the creation of active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to create the complex structures of transistors. These processes operate on a small scale. By applying photolithography, etching, and implantation techniques, it becomes possible to precisely define the transistor structure. The importance of silicon substrates lies in their ability to establish the basic building blocks necessary for signal processing, amplification, and control within the IC. This layer is sometimes referred to as the line front-end ("FEOL").

[0057] In the manufacturing process, a second layer may be added, which traditionally plays the role of interconnect manufacturing, facilitating electrical connections between various IC components. This stage has traditionally focused on creating passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The process for the second layer is typically different from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers, usually aluminum or copper, to construct a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are incorporated to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects that enable the routing and distribution of electrical signals throughout the IC. However, as described herein, circuits may also be utilized within this second layer (sometimes referred to as the back-end of the line ("BEOL")).

[0058] Alternative embodiments of IC100 may be implemented as a stacked die, monolithic design, TSV, or through-silicon electrode. In a stacked die design, several dies may be stacked on top of each other, with each die performing a different function such as memory and processing. The stacked dies may communicate through wire junctions, microbumps, or bumpless junctions. In a monolithic design, the various functions and modules of IC100 may be incorporated into a single die, forming a more compact and power-efficient design.

[0059] Furthermore, IC100 may include one or more interlocks 132 to prevent conflicts when reading or writing data. The module group 106 may be formed from various non-volatile or semi-volatile (e.g., very long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistors (FeFETs), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating-gate memory, and / or Schottky diodes.

[0060] The module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., a latch flip-flop) that ensures that stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, the module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0061] Module group 106 may utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein features a matrix of memory cells, each composed of a floating-gate transistor or a charge trap device. Module group 106 may also utilize wear-leveling techniques to extend the lifespan of the memory cells.

[0062] The module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. The FeRAM topology utilizes a ferroelectric material capable of maintaining a polarization state. In a particular embodiment, one such memory topology may utilize an FeFET to program the ferroelectric material by holding state information. The ferroelectric material may be used to function as a memory bit cell by holding state information.

[0063] The module group 106 may utilize a phase-change memory (PCM) topology, which is a non-volatile memory technology that utilizes a reversible phase change of material to store data. The PCM topology may include any phase-change material, for example, a chalcogenide alloy or chalcogenide glass housed within the memory cell.

[0064] The module group 106 may utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistive switching phenomenon. The ReRAM topology may utilize a thin film material that exhibits a reversible change in resistance when an electrical stimulus is applied.

[0065] Module group 106 may utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a type of non-volatile memory that utilizes spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology may incorporate a magnetic tunnel junction (MTJ) structure and leverage spin-orbit interaction effects to write and read data. The magnetic tunnel junction may have a dielectric layer between the magnetic fixed layer and the magnetic free layer. Writing may be performed by switching the magnetization of the free magnetic layer by applying an in-plane current in an adjacent SOT layer. Reading may be performed by applying current to the magnetic tunnel junction. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write energy consumption.

[0066] Module group 106 may utilize a spin-transfer torque (STT) magnetic random-access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology may use a magnetic tunnel junction (MTJ) structure in which the magnetization orientation determines the stored data. Furthermore, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be modified, for example, using a spin-polarization current.

[0067] IC100 may include a single write peripheral 104 having its own dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock (not shown in Figure 1). Furthermore, the module group 106 may be organized into separate compartments, each having its own dedicated read peripheral 116, 118, 120, 122 having an independent clock.

[0068] Another possible embodiment of IC100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the packaging of IC100. Furthermore, in additional specific embodiments, IC100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) that processes data within the IC.

[0069] Figure 2 shows a perspective view of assembly 200 of the integrated circuit 212 of Figure 1, mounted on a chiplet 230 bonded to a second device 226 according to an embodiment of the present disclosure. The integrated circuit 212 is the circuit within the chiplet 230. The second device 226 may be a chiplet, a semiconductor wafer, a semiconductor package, a encapsulation circuit, etc. For example, the second device 226 may be an AI accelerator such that each processing unit has read access to one module (or a predetermined set) of the module group 236. In yet another embodiment, the second device 226 may be a network controller, where offload circuitry exists to read data from each of the modules and process incoming / outgoing packets, etc. The assembly 200 includes a module group 236 having a plurality of modules, including a first module 232 and a second module 234. Figure 2 shows several modules, but for clarity only modules 232 and 234 have reference numbers. The integrated circuit 212 further includes a shared write port 222. The shared write port 222 is interfaced to the write peripheral device 202.

[0070] The second device 226 may write data to any module in the module group 236 using a shared write port 222 via an address and data bus along with a clock and enable signal, although other methods of writing data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc., may be used. Each module has a read port having a read address 218 (to send an address to module 234) and read data 214 (which is the read of data from module 232).

[0071] The module group 236 is formed in a chiplet 230 having two sides including a surface 228 that can be bonded to and complement the second device 226. The chiplet 230 may be formed by forming a circuit on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers may be in reverse order, and / or other layers may be added, removed, etc. The read address 218 and read data 220 are used to read the module 232.

[0072] The second device 226 may read data from module 232 using an address and data bus along with a clock and enable signal, but other methods for reading data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc. may be used.

[0073] All read ports (e.g., 218 and 222) are configured to be deactivated when a write operation is applied to the shared write port 222. The read ports may also be configured to handle reads simultaneously with each other. The shared write port 222 is configured to write to the address space, where it is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the multiple modules 236 includes an independent read port that reads simultaneously through its own independent read port relating to any of the multiple modules.

[0074] Each read port for each module may include contacts for a circuit found in the second device 226 for interface connection via metal contacts. Thus, there may be metal contacts on the upper layer 208 configured to interface with metal contacts on the surface 228 of the chiplet 230, and as a result, the metal contacts enable a read space having the same extent as the module read space of module 236. All of the read spaces of the module group 236 may have the same extent as one another (as described with reference to Figures 3 and 4).

[0075] In one embodiment, the read peripherals for the first module 232 are mounted on the silicon substrate 204 (sometimes referred to as the front end of the line). In the manufacturing process, a second layer 206 (sometimes referred to as the back end of the line) may then be built on top of the silicon substrate 204 (and any circuitry) and may include each memory bit cell. In an alternative embodiment, the read peripherals for the first module 232 are mounted on the second layer 206 and are located between the module group 236 and the surface 228 of the chiplet 230.

[0076] The module group 236 may be configured to process only write commands during reset. The write command may be a "slow write" command; that is, the module group 236 may have a write speed that is very low compared to the read speed of the module group 236. The write logic may be frozen (or disabled) when the module group 236 is used to read data. In some specific embodiments, the integrated circuit 212 provides the ability to allocate memory blocks to the module group 236 based on its use. In other embodiments, the memory address is fixed with the allocation. The integrated circuit 212 may be implemented as a face-to-face bonded chiplet 230. The face-to-face bond may be a bump-less wafer bond.

[0077] The module group 236 may have a single write peripheral 202. In other embodiments, each module of the module group 236 may have a dedicated write peripheral that utilizes a shared clock. In yet another embodiment, the module group 236 may also be organized into separate partitions, each having a partition with a dedicated read peripheral, where each dedicated read peripheral has an independent clock. The partitions may consist of one, two, or more modules of the module group 236.

[0078] The overall circuit architecture of the write peripheral 202 may include a set of different components, including a write driver, address decoder, sense amplifier, data input latch, data bus, and / or any combination thereof. The write driver or write buffer may be responsible for the task of transferring data to the memory cell. The write driver or write buffer may amplify the input signal to the memory cell to achieve an appropriate level. The address decoder may be used to interpret the memory address supplied as input to which data should be written. The address decoder may be used to select a target memory cell by activating specific rows and columns of the memory array linked to the address. The sense amplifier may be used to identify and amplify the signal from the memory cell during a read operation and to participate in refreshing the memory cell after data has been written during a write operation. The write operation is initiated by a write enable signal. When a write command is initiated, this signal causes the write driver and decoder to proceed with the write process. The data input latch may be used as a temporary storage unit to hold data that has been set to be written to memory until the write operation is implemented. A data bus with a transmit route may be used to facilitate the movement of data from the data input latch to the memory cell.

[0079] The write operation to the module group may be performed through a priority arbitration circuit that facilitates the access of modules in a predetermined order, and the shared write port 222 may be configured to write to a virtual address space mapped to a physical memory space. The integrated circuit 212 may include high-voltage write logic used in the write peripheral 202, and the second semiconductor device 226 may have multiple processing elements, each of which includes an interface for communicating with each module of the module group 236. Furthermore, the chiplet 230 may include an interface to the shared write port 222 on the second side, thereby interface-connecting to a complementary interface in the second semiconductor device 226.

[0080] Furthermore, the integrated circuit 212 may include a power gating circuit that selectively cuts off the power to the module 236 when it is not in use. In addition, the integrated circuit 212 may have a programming peripheral 202 for the module group 236 connected to dedicated I / O pads to enable data transfer outside the integrated circuit package.

[0081] The integrated circuit 212 may utilize multiple modules of a group of modules 234 that are grouped together. These modules may be synchronized with one another in certain embodiments. In some cases, all modules are synchronized, while in other examples, only specific modules are synchronized. For example, the circuitry in the second device 226 may need to be synchronized with a specific module when reading data from one of the modules in the group of modules 236.

[0082] To synchronize the modules, the integrated circuit 212 may use various timing techniques. In some cases, multiple clocks may be supplied to each module of the module group 236, thereby allowing each module to have isolated timing relative to the other modules in the group. This isolation ensures that any delay in one module does not affect the functionality of other modules. It should be noted that the clocks used may or may not need to be synchronized. In some cases, a common clock may be used to synchronize the modules. In yet another embodiment, the clock signal or signal(s) may be provided by a second device 226.

[0083] In alternative embodiments, other synchronization techniques, such as phase comparison of clock signals or synchronization methods of a phase-locked loop (PLL), may be used. Another embodiment for synchronizing modules in an IC may use synchronization of a delay-locked loop (DLL). In this method, a delay element is added to the clock signal path, and its output is compared with the input clock signal. A feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.

[0084] In another embodiment, the integrated circuit 212 may achieve synchronization between modules using a combination of different synchronization techniques. For example, some modules may use PLL synchronization, while others may use clock delay line or DLL synchronization depending on their specific requirements. Furthermore, the integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in case one method fails. For example, the integrated circuit 212 may use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the others can still maintain synchronization.

[0085] Figure 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0086] The write address space 316 consists of various units in which data, such as weights and / or instructions, can be stored. These units are referred to as memory addresses. The module group 302 includes several memory modules 304, 306, and 308. The write address space 316 can be distributed among the memory modules 304, 306, and 308 such that the write address space 316 extends from 0 to N*M-1. As shown in Figure 3, the module group 302 has N memory modules 304, 306, and 308, where N is a positive integer and each module has a memory size of M. The total number of unique write memory addresses in the write address space is N*M, which can be referred to by integers from 0 to N*M-1.

[0087] Starting at 0, the memory addresses in the write address space 316 are arranged sequentially up to N*M-1. In other words, the first address is 0, the last address is N*M-1, and there are a total of N*M addresses. This ordering can be linear (each address increasing by 1) or some other incidental designation pattern.

[0088] Write memory addressing can be implemented in various ways depending on the system architecture. One method used in a particular embodiment is to use a base register and a limit register. The base register holds the smallest valid physical write memory address, and the limit register specifies the size of the range. Thus, the base is added to the relative address to generate a logical address. In other embodiments, a memory addressing scheme may be used, where the base used is set to 0. Further write addressing techniques will be understood by those skilled in the art.

[0089] For any device writing to module group 302, each memory module may have a unique set of write memory addresses, and as a result, all memory addresses within module group 302 are unique with respect to data writing, for example, starting with 0 for the first module and ending with N*M-1 for the last module. In some embodiments, this allocation may depend on the memory management system of the devices writing data to modules 304, 306, and 308, which can range from a simple fixed partitioning scheme to a more complex dynamic partitioning model.

[0090] For example, in a simple linear model where each module (304, 306, or 308) has an address of the same size M, the first module 304 has write addresses 0 to M-1, the second module has write addresses M to 2M-1, the third module has write addresses 2M to 3*M-1, and so on. Therefore, the Nth module 308 has write addresses (N-1)*M to N*M-1.

[0091] Those skilled in the art may use other implementations of write memory addresses from 0 to N*M-1, which depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of programs executed in the system.

[0092] The module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 may have overlapping address spaces, contiguous address spaces, or address spaces with the same extent. The read address spaces 310, 312, and 314 may be independent of each other. The system includes three independent read address spaces labeled as read address spaces 310, 312, and 314. Each of these read address spaces is separate from the others, meaning that reads can be performed in each space without affecting the others.

[0093] The read address spaces 310, 312, and 314 may be defined as contiguous blocks of memory addresses, each having its own start and end addresses. In the module group 302, each read address space 310, 312, and 314 may have addresses in the range of 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0094] In one embodiment, simultaneous reads may be implemented as described herein, by enabling one processing unit to interface with each of the read address spaces 310, 312, and 314. The independence of the read address spaces 310, 312, and 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.

[0095] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to embodiments of the present disclosure. The signals used in Figure 4 may be used in any embodiment described herein. However, those skilled in the art will understand that different signaling schemes may be used.

[0096] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus containing the address of the data to be written, a write data bus containing the data, and a write clock that causes the write (e.g., on the leading or trailing edge of a clock signal). The write occurs only if the write enable signal indicates that the write should occur. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In some embodiments, the write peripheral 411 may be on a chiplet 230, and in other embodiments, the write peripheral 411 is on a second device 226.

[0097] Module group 402 has modules 404, 406, and 408, each having its own read peripheral 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for transmitting a read address, a read data bus for receiving data, a read clock which is a clock used to control the timing of the output of digital data, and an output enable which is a prerequisite for the output of data. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In further embodiments, multibit or analog data storage may be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the chiplet 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the second device 226.

[0098] Figure 5 shows a diagram of an integrated circuit 500, which may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure. The integrated circuit 500 may be arranged in a semiconductor device such as a chiplet, having a silicon substrate 506 and a second layer 508. Within the integrated circuit 500, there may be array sections forming a module 502, where the memory bit cells 522 of a three-dimensional column array have components necessary for memory storage in a non-volatile memory, semi-volatile memory, or memory format as described herein.

[0099] Even if only a single module 502 is shown, the integrated circuit 500 may include a group of modules having multiple modules, such as a first module and a second module. The memory bit cell 522 is written to by shared write ports 512, 516, which include both a write address bus line 512 and a write data bus 516. These buses extend through a second layer 508 and may be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement the electrical contacts on the surface 518, enabling the second device to be electrically connected to the write address and data buses. The memory bit cell 522 can be read out by read ports 524, 526, which include a read address bus line 524 and a read data bus 526. Both of these buses may also extend through the second layer 508 to a second semiconductor device connected to the surface 518, which also has complementary electrical contacts that enable the second semiconductor device to be electrically connected to the read address and data buses.

[0100] Various types of memory technologies, such as a vertically connected fabric structure formed from non-volatile memory unit cells arranged in a three-dimensional column array 522, may be used for the memory bit cell 522. The memory bit cell 522 may utilize one or more of the following: crosspoint, 3D-NAND, 3D-NOR, 3D AND, and / or stacked planar layers.

[0101] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device (not shown in Figure 5) comprising another integrated circuit, which may be a system-on-chip or a field-programmable gate array. In some embodiments, the memory bit cell 522 may be formed from various non-volatile memory types such as FeFET, FeRAM, ReRAM, SOT, or STT. Furthermore, alternatively or optionally, the memory bit cell may be formed from a non-volatile memory unit cell having a two-terminal, three-terminal, or four-terminal device.

[0102] For example, the memory unit bit cell 522 may be formed from a ferroelectric material such as a ferroelectric tunnel junction, diode, capacitor, single-gate transistor, or dual-gate transistor. Alternatively, the memory unit bit cell 522 may be formed from a memristor material, such as at least one ReRAM, or a magnetic material, such as at least one spin-orbit torque device or at least one spin-transition torque device. Furthermore, the non-volatile memory unit cell 522 may also be formed from a phase-change material or an antiferroelectric material.

[0103] In some alternative embodiments, the non-volatile memory unit cell 522 may be formed from other types of materials, such as phase-change materials, antiferroelectric materials, or multi-bit PCM materials. The non-volatile unit cell may be formed using different structures, such as resistive random-access memory (RRAM) technology, magnetic random-access memory (MRAM) technology, or ferroelectric random-access memory (FRAM) technology.

[0104] Furthermore, in some implementations, 3D NAND technology may be used to form the memory unit bit cell 522. For example, the memory unit bit cell 522 may be formed from stacked memory layers, where each layer contains multiple memory cells that can be accessed using a shared bit line. In such a case, read ports 524, 526 may be connected to bit lines, and write ports 512, 516 may be connected to word lines that control access to each layer.

[0105] In another embodiment, the 3D connected fabric structure may be constructed of stacked layers of NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates may be combined to optimize the functionality of the structure. In addition, the 3D connected fabric structure may be formed using through-silicon (TSV) technology, which enables vertical interconnection of different layers of the structure.

[0106] Furthermore, the non-volatile memory unit cell may include a two-terminal device, such as a capacitive or memristor device with or without an additional selector device such as a series diode; a three-terminal device, such as a floating-gate transistor or a transistor with an access gate; or a four-terminal device, such as a transistor with two access gates. The type and configuration of the non-volatile memory unit cell 522 may depend on the requirements of a particular application, including circuit speed, power consumption, and reliability. The memory unit cell may include, or may consist of, a single ferroelectric transistor or a 6T SRAM cell. The memory unit cell may also be a combination of many different devices, including, but not limited to, one or more of the following: transistors, memristors, capacitors, etc.

[0107] In some embodiments, ferroelectric materials may be used to form non-volatile memory unit cells 522. Ferroelectric materials may be implemented as thin-film devices, including, but not limited to, ferroelectric tunnel junctions, capacitors, single-gate transistors, or dual-gate transistors, or any other type of device.

[0108] In another embodiment, the non-volatile memory unit cell 522 may be formed from a memristor material, such as a metal oxide memristor (MOM), a conductive bridge RAM (CBRAM), or a valence-change memory (VCM), each offering different advantages in terms of power consumption, speed, durability, and so on.

[0109] Furthermore, in some embodiments, the non-volatile memory unit cell 522 may be formed from a magnetic material, such as a spin-orbit torque (SOT) device, a spin-transition torque (STT) device, or a perpendicular magnetic tunnel junction (p-MTJ).

[0110] In one embodiment, the module group may include a number of modules, each of which can be accessed through dedicated read ports 524, 526 having dedicated read peripherals 520, while sharing the same write ports 512, 516 and a shared write peripheral 510. The shared write ports 512, 516 may be configured to selectively write to one or more of the modules in the module group, including memory bit cells 522. Each module may have the same or different sizes, and different module sizes may be configured to optimize the use of the memory array in different operating scenarios, etc.

[0111] Furthermore, the integrated circuit 500 may be formed using different manufacturing processes and technologies, including but not limited to CMOS or bipolar CMOS-DMOS (BCD) processes, silicon on insulator (SOI) processes, FinFET processes, silicon germanium (SiGe) processes, and gallium arsenide (GaAs) processes.

[0112] Figure 6 shows a perspective view of assembly 600 having the integrated circuit of Figure 1 mounted on a semiconductor device such as a chiplet 230, which is electrically connected to a system-on-a-chip ("SOC") 610, according to an embodiment of the present disclosure. In this embodiment, the semiconductor device is a chiplet 230 that is electrically connected to a system-on-a-chip ("SOC") 610.

[0113] Referring to Figure 6, the SOC610 includes a silicon substrate 602 on which multiple processing elements are formed, including a processing element 606. The processing elements can communicate with each other through a network-on-chip ("NOC") 604, which is a communication fabric that directs data transfer between processing elements. The communication fabric can take various forms, including buses, switches, NOCs, etc. In the SOC610, the NOC 604 directs data traffic between various nodes (e.g., processing elements 606) and links that provide communication paths between nodes.

[0114] The processing elements, including processing element 606, may be any suitable type of processor capable of executing instructions, including a microprocessor, graphics processing unit (GPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC).

[0115] Furthermore, the SOC610 may comprise various modules, such as module 232, which are grouped together to provide memory functionality to assembly 600 as described herein. Modules in module group 236 may be connected to their respective processing elements to provide readable memory to each processing element. In some embodiments, the connection between modules (e.g., module 232) and processing elements (e.g., 606) may be achieved through interconnects in the silicon substrate 602.

[0116] After the circuit is formed on the silicon substrate 602, a second layer 608 may be placed on the substrate. The second layer 608 may be any suitable material, such as an insulating material, a metal, a dielectric, or an interconnect layer, and the second layer 608 may be bonded to the chiplet 230. Bonding may be performed using any suitable technique, including but not limited to adhesives, soldering, or welding.

[0117] In general, assembly 600 provides a means for integrating a chiplet 230, which may include the integrated circuit shown in Figure 1, into the SOC 610. The integration of the chiplet 230 offers various advantages, such as improved functionality, higher performance, and lower power consumption. Furthermore, the integration of the chiplet 230 into the SOC 610 can be achieved in various ways depending on the specific application and design objectives of the system.

[0118] Assembly 600 can incorporate various modifications and alterations to meet the specific requirements of the system. For example, the processing elements formed on the silicon substrate 602 can vary in number, type, and arrangement. Similarly, the modules in the module group 236 can vary in number, type, and function.

[0119] Furthermore, the second layer 608 may be modified to include additional functions. For example, the second layer 608 may include passive components such as resistors, capacitors, and inductors, or active components such as transistors or diodes. By incorporating these components into the second layer 608, the functionality and performance of the system can be further improved.

[0120] In another variation, assembly 600 may incorporate a heterogeneous integration technique, where the chiplet 230 is manufactured using a different technique than that used in SOC610. This technique allows for the optimal use of different manufacturing techniques for different parts of the system, resulting in improved performance and reduced power consumption.

[0121] Various alternatives and modifications can be conceived by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to include all such alternatives, modifications, and variations. Furthermore, while some embodiments of this disclosure are shown in the drawings and / or described herein, this disclosure is not intended to be limited thereto, as this disclosure is broad in the scope of what the art makes possible, and the specification is intended to be read similarly. Therefore, the above description should not be construed as a limitation, but merely as an example of a particular embodiment. Those skilled in the art will conceive of other modifications within the scope and spirit of the claims appended herein. Other elements, steps, methods, and techniques that differ slightly from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0122] The embodiments shown in the drawings are presented solely to demonstrate specific examples of the present disclosure. The drawings described are illustrative and non-limiting. In the drawings, for illustrative purposes only, the sizes of some elements may be exaggerated and not depicted to a particular scale. Furthermore, elements shown in the drawings with the same number may be identical or similar elements, depending on the context.

[0123] When the term “equipped with” is used herein and in the claims, the term does not exclude other elements or steps. When an indefinite or definite article is used with a single noun, for example, “a,” “an,” or “the,” this includes multiple such nouns unless specifically stated otherwise. Therefore, the term “equipped with” should not be interpreted as being limited to the items enumerated therein, and since the term does not exclude other elements or steps, the scope of the expression “a device comprising items A and B” should not be limited to a device consisting only of components A and B. This expression means to the present disclosure that A and B are merely related components of a device.

[0124] Furthermore, the terms “First,” “Second,” “Third,” and similar terms, whether used in the specification or in the claims, are provided to distinguish similar elements and are not necessarily provided to describe a sequential or chronological order. Terms used in this manner are interchangeable under appropriate circumstances (unless otherwise expressly disclosed), and it should be understood that embodiments of the disclosure described herein may operate in sequences and / or arrangements other than those described or shown herein.

[0125] Each of the characteristics and examples described herein, as well as any combination thereof, can be said to be included by this disclosure. Accordingly, this disclosure covers the following non-limiting numbered embodiments:

[0126] 1. An integrated circuit comprising: a group of modules having a plurality of modules including a first module and a second module; a shared write port configured to write to the group of modules; a first read port configured to read from the first module; and a second read port configured to read from the second module.

[0127] 2. The integrated circuit according to embodiment 1, wherein the first and second read ports are configured to be deactivated when a write operation is applied to the shared write port.

[0128] 3. The integrated circuit according to embodiment 1, wherein the first and second read ports are configured to process reads from each other simultaneously.

[0129] 4. The integrated circuit according to embodiment 1, wherein the shared write port is configured to write to the address space, and the shared write port is configured to write to the first module via a first portion of the address space and to write to the second module via a second portion of the address space.

[0130] 5. The integrated circuit according to Embodiment 1, wherein each of the plurality of modules includes an independent read port that reads simultaneously through the independent read port of any of the plurality of modules, so that the first read port is configured to read from the first module simultaneously with another read of the second module using the second read port.

[0131] 6. The integrated circuit according to embodiment 1, wherein the group of modules is configured to have a single write address space configured for writing to the plurality of modules.

[0132] 7. The integrated circuit according to embodiment 6, wherein the first read port is configured to have a first read address space, and the second read port is configured to have a second read address space.

[0133] 8. The integrated circuit according to embodiment 7, wherein the first read address space numerically overlaps with the second read address space.

[0134] 9. The integrated circuit according to embodiment 7, wherein the first read address space has the same extent as the second read address space.

[0135] 10. The integrated circuit according to embodiment 7, wherein the first read address space is contiguous with respect to the second read address space.

[0136] 11. The integrated circuit according to embodiment 1, wherein the group of modules is formed in the second layer of the integrated circuit device.

[0137] 12. The integrated circuit according to embodiment 1, wherein the integrated circuit is implemented as a chiplet configured to be face-to-face bonded.

[0138] 13. The integrated circuit according to embodiment 12, wherein the chiplet further comprises a plurality of input / output (I / O) junctions, each of the plurality of input / output (I / O) junctions configured to provide a respective read port for each of the plurality of modules, and each of the plurality of input / output (I / O) junctions configured to interface with a complementary input / output (I / O) junction of a second device when bonded to the chiplet.

[0139] 14. A semiconductor device comprising the integrated circuit described in Embodiment 1.

[0140] 15. The semiconductor device according to embodiment 14, wherein the semiconductor device is mounted as a die.

[0141] 16. The semiconductor device according to embodiment 14, wherein the semiconductor device is mounted as a wafer.

[0142] 17. The semiconductor device according to embodiment 14, wherein the semiconductor device is mounted as a chiplet die.

[0143] 18. The semiconductor device according to embodiment 17, wherein the chiplet die is bonded to a second semiconductor device.

[0144] 19. The semiconductor device according to embodiment 18, wherein the second semiconductor device is selected from the group consisting of a GPU ("graphics processing unit"), a SoC ("system on a chip"), and a GPPU ("general-purpose processing unit").

[0145] 20. The semiconductor device according to embodiment 18, wherein the second semiconductor device is mounted as a chiplet die.

[0146] 21. The semiconductor device according to embodiment 18, wherein the second semiconductor device is mounted as a wafer.

[0147] 22. The semiconductor device according to embodiment 18, wherein the second semiconductor device is an ASIC ("Application-Specific Semiconductor Chip").

[0148] 23. The semiconductor device according to embodiment 18, wherein the second semiconductor device is an FPGA ("Field Programmable Gate Array").

[0149] 24. The semiconductor device according to embodiment 18, further comprising a plurality of input / output (I / O) junctions, each of which is configured to provide a read port for each of the plurality of modules, and each of which is configured to be electrically connected to a complementary input / output (I / O) junction of the second semiconductor device.

[0150] 25. The semiconductor device according to embodiment 18, wherein the chiplet die has a first side and a second side, the second side being configured to be face-to-face bonded to the second semiconductor device.

[0151] 26. The semiconductor device according to embodiment 25, wherein the chiplet die and the second semiconductor device are part of a multi-chip package.

[0152] 27. The semiconductor device according to embodiment 18, further comprising an electrical connection interposer disposed between the chiplet die and the second semiconductor device.

[0153] 28. The semiconductor device according to embodiment 17, wherein the first read port is located on the chiplet die, the chiplet die has a surface, and the first module comprises a memory array having a plurality of memory unit cells located within the first module, and a read peripheral circuit configured to read data stored in the memory array via the first read port.

[0154] 29. The semiconductor device according to embodiment 28, wherein the footprint of the read peripheral circuit overlaps with the footprint of the memory array.

[0155] 30. The semiconductor device according to embodiment 28, wherein the footprint on the surface of the first read port overlaps with the footprint on the surface of the memory array.

[0156] 31. The semiconductor device according to embodiment 28, wherein the footprint of the read peripheral circuit is the same in extent as the footprint of the memory array.

[0157] 32. The semiconductor device according to embodiment 28, wherein the footprint on the surface of the first read port has the same extent as the footprint on the surface of the memory array.

[0158] 33. The semiconductor device according to embodiment 28, wherein the memory array, the read peripheral circuit, and the first read port are stacked vertically and configured to minimize the module footprint on the surface of the chiplet die.

[0159] 34. The semiconductor device according to embodiment 28, further comprising a write peripheral circuit connected to the shared write port on the surface of the chiplet die, wherein the write peripheral circuit defines a first footprint on the surface, the first footprint does not overlap with the footprint of the memory array, the first footprint does not overlap with the footprint of the first read port, the shared write port defines a second footprint on the surface, the second footprint does not overlap with the footprint of the memory array, and does not overlap with the footprint of the first read port.

[0160] 35. The semiconductor device according to embodiment 28, wherein the plurality of memory unit cells are formed from at least one non-volatile memory unit cell.

[0161] 36. The semiconductor device according to embodiment 34, wherein the first footprint overlaps with the second footprint.

[0162] 37. The semiconductor device according to embodiment 28, wherein the memory unit cell includes a ferroelectric material.

[0163] 38. The semiconductor device according to embodiment 28, wherein the memory unit cell includes at least one of a magnetic material, a spin-orbit torque material, a spin-transition torque material, a phase change material, and an antiferroelectric material.

[0164] 39. The semiconductor device according to any one of embodiments 28 to 38, wherein the plurality of memory unit cells are arranged in a three-dimensional configuration.

[0165] 40. The integrated circuit according to embodiment 1, wherein the plurality of modules are organized into separate compartments, each having its own dedicated read peripheral device.

[0166] 41. The integrated circuit according to embodiment 40, wherein each dedicated read peripheral has an independent clock.

[0167] 42. The integrated circuit according to embodiment 1, wherein each of the plurality of modules has a dedicated read peripheral device.

[0168] 43. The integrated circuit according to embodiment 1, wherein the module group is configured to process only write commands during a reset, thereby disabling read capability during the reset.

[0169] 44. The integrated circuit according to embodiment 43, wherein the group of modules is configured to disable the write capability when the group of modules is not in a reset state.

[0170] 45. The integrated circuit according to embodiment 1, wherein the group of modules includes at least two different non-volatile memory technologies.

[0171] 46. ​​The integrated circuit according to embodiment 1, further comprising a dynamic allocation circuit for allocating memory blocks to the plurality of modules based on the use of the group of modules.

[0172] 47. The integrated circuit according to embodiment 1, further comprising a programming peripheral for the group of modules connected to a dedicated I / O pad to enable data transfer outside the package of the integrated circuit.

[0173] 48. The integrated circuit according to embodiment 1, wherein the integrated circuit is formed on a silicon substrate via an additive manufacturing process.

[0174] 49. The integrated circuit according to embodiment 48, wherein the integrated circuit is electrically connected to a second semiconductor device comprising another integrated circuit.

[0175] 50. The integrated circuit according to embodiment 49, further comprising a read peripheral for at least one of the plurality of modules arranged on the silicon substrate.

[0176] 51. The integrated circuit according to embodiment 49, further comprising a read peripheral for at least one of the plurality of modules arranged in the second semiconductor device.

[0177] 52. The integrated circuit according to embodiment 1, wherein the integrated circuit is electrically connected to a second semiconductor device comprising another integrated circuit.

[0178] 53. The integrated circuit according to embodiment 52, wherein the second semiconductor device is a system-on-a-chip.

[0179] 54. The integrated circuit according to embodiment 52, wherein the second semiconductor device is mounted as a chiplet die.

[0180] 55. The semiconductor device described in the preceding 2 is an integrated circuit according to embodiment 52, which is mounted as a wafer.

[0181] 56. The integrated circuit according to embodiment 52, wherein the second semiconductor device is an ASIC ("application-specific semiconductor chip").

[0182] 57. The integrated circuit according to embodiment 52, wherein the second semiconductor device is an FPGA ("Field-Programmable Gate Array").

[0183] 58. The integrated circuit according to embodiment 52, wherein the plurality of modules are formed from non-volatile memory unit cells arranged in a three-dimensional connection fabric perpendicular to a silicon substrate and the second semiconductor device.

[0184] 59. The integrated circuit according to embodiment 52, wherein the plurality of modules are formed using at least one of a crosspoint, 3D NAND, 3D NOR, 3D AND, and stacked planar layers.

[0185] 60. The integrated circuit according to embodiment 1, wherein the plurality of modules have a single writing peripheral device.

[0186] 61. The integrated circuit according to embodiment 60, wherein the single writing peripheral has a dedicated clock.

[0187] 62. The integrated circuit according to embodiment 1, further comprising a plurality of clocks, each of which provides a clock to each of the plurality of modules, so that each module has a timing separated from the other modules of the plurality of modules, and each of the plurality of clocks is configured to clock each of the respective read ports of each of the plurality of modules.

[0188] 63. The module group is formed in a chiplet having a first side and a second side, the second side being configured to be bonded to a second semiconductor device. The integrated circuit according to Embodiment 1.

[0189] 64. The integrated circuit according to embodiment 63, further comprising a decoder circuit, a driver circuit, and a register circuit on the silicon substrate of the chiplet.

[0190] 65. The integrated circuit according to embodiment 64, wherein the group of modules is formed on the second layer of the chiplet.

[0191] 66. The integrated circuit according to embodiment 63, wherein the second semiconductor device comprises a plurality of processing elements, each processing element comprising an interface for communicating with each of the plurality of modules in the module group when the second semiconductor device is bonded to the chiplet.

[0192] 67. The integrated circuit according to embodiment 63, wherein the chiplet interfaces with a complementary interface in the second semiconductor device by providing an interface to the shared write port on the second side.

[0193] 68. The integrated circuit according to embodiment 63, wherein the second semiconductor device comprises a network-on-chip.

[0194] 69. The integrated circuit according to embodiment 68, wherein the second semiconductor device comprises a plurality of processing elements, and the network on chip is configured to provide inter-element communication with respect to the plurality of processing elements.

[0195] 70. The integrated circuit according to embodiment 69, wherein the plurality of processing elements include at least one embedded FPGA.

[0196] 71. The integrated circuit according to embodiment 69, wherein the plurality of processing elements include at least one of a soft processor, a DSP block, an embedded processor, and a microcontroller.

[0197] 72. The integrated circuit according to embodiment 1, wherein the write operation to the group of modules is performed through a priority arbitration circuit that facilitates the access of the modules in a predetermined order.

[0198] 73. The integrated circuit according to embodiment 1, further comprising a power gating circuit that selectively turns off the power to one of the plurality of modules when not in use.

[0199] 74. The integrated circuit according to embodiment 1, wherein the shared write port is configured to write to a virtual address space mapped to a physical memory space.

[0200] 75. The integrated circuit according to embodiment 1, further comprising a control circuit configured to conserve energy by enabling the shared write port during a write operation and deactivating the shared write port during a read operation.

[0201] 76. The integrated circuit according to embodiment 1, further comprising a control circuit configured to conserve energy by disabling the first read port during a write operation and enabling the first read port during a read operation.

[0202] 77. The integrated circuit according to embodiment 1, further comprising a power management module configured to conserve energy by selectively turning off power to the shared write port during a read operation.

[0203] 78. The integrated circuit according to embodiment 1, further comprising a writing circuit configured to conserve energy by dynamically shifting power allocation from a write operation to a read operation.

[0204] 79. The integrated circuit according to embodiment 1, further comprising a writing circuit configured to enter sleep mode during a read operation and turn off power to the shared writing port to conserve energy.

[0205] 80. The integrated circuit according to embodiment 1, wherein the plurality of modules are formed from non-volatile memories selected from the group comprising FeFET, FeRAM, ReRAM, SOT (spin-orbit torque), and STT (spin-transition torque).

[0206] 81. The programming peripheral for the module group is the integrated circuit described in Embodiment 1, which is mounted on a silicon substrate.

[0207] 82. The integrated circuit according to embodiment 81, wherein the integrated circuit is formed in a chiplet having a first side and a second side, the second side being configured to be bonded to another integrated circuit located in a package, and the writing peripheral is located between the group of modules and the second side of the chiplet.

[0208] 83. The read peripheral for the first module is an integrated circuit according to embodiment 1, mounted on a silicon substrate.

[0209] 84. The integrated circuit according to embodiment 83, wherein the integrated circuit is formed in a chiplet having a first side and a second side, the second side being configured to be bonded to another integrated circuit located in a package, and the read peripheral is located between the module group and the first side of the chiplet.

[0210] 85. The read peripheral for the first module is an integrated circuit according to Embodiment 1, which is mounted on the second layer.

[0211] 86. The integrated circuit according to embodiment 85, wherein the integrated circuit is formed in a chiplet having a first side and a second side, the second side being configured to be bonded to another integrated circuit located in a package, and the read peripheral is located between the group of modules and the first side of the chiplet.

[0212] 87. The integrated circuit according to embodiment 1, wherein each module has its own dedicated writing peripheral device.

[0213] 88. The integrated circuit according to embodiment 87, wherein each dedicated writing peripheral is configured to utilize a shared clock.

[0214] 89. The integrated circuit according to embodiments 1 to 27, 30, 32, 35 to 40, 43 to 46, 48 to 49, 52 to 60, 62 to 80, or 87 to 88, further comprising: an integrated circuit disposed on a first semiconductor device; a shared write peripheral configured to write to the group of modules via the shared write port, the shared write peripheral being disposed on the silicon substrate of the first semiconductor device; and a first read peripheral configured to read the first module via the first read port, the first read peripheral being disposed on the silicon substrate of the first semiconductor device; and a second read peripheral configured to read the second module via the second read port, the second read peripheral being disposed on the silicon substrate of the first semiconductor device, the first module and the second module being disposed on the second layer of the first semiconductor device.

[0215] 90. The integrated circuit according to embodiment 89, wherein the first module is a three-dimensional column of memory bit cells disposed between the first surface of the first semiconductor device and the silicon substrate of the first semiconductor device.

[0216] 91. The integrated circuit according to embodiment 89, wherein the first read port is configured to communicate electrically with a second semiconductor device, and the second semiconductor device is configured to be fixed to a first surface of the first semiconductor device.

[0217] 92. The integrated circuit according to embodiment 91, further comprising an interposer disposed between the first surface of the first semiconductor device and the second semiconductor device.

[0218] 93. The integrated circuit according to embodiment 89, wherein the first read port includes a read address bus traversing the second layer of the first semiconductor device.

[0219] 94. The integrated circuit according to embodiment 89, wherein the first read port includes a read data bus traversing the second layer of the first semiconductor device.

[0220] 95. The integrated circuit according to embodiment 89, wherein the shared write port is configured to communicate electrically with a second semiconductor device, and the second semiconductor device is configured to be fixed to a first surface of the first semiconductor device.

[0221] 96. The integrated circuit according to embodiment 95, further comprising an interposer for electrical connections disposed between the first surface of the first semiconductor device and the second semiconductor device.

[0222] 97. The integrated circuit according to embodiment 89, wherein the shared write port includes a write address bus that traverses the second layer of the first semiconductor device.

[0223] 98. The integrated circuit according to embodiment 89, wherein the shared write port includes a write data bus that traverses the second layer of the first semiconductor device.

[0224] 99. A method comprising forming an integrated circuit according to any one of embodiments 1 to 98.

[0225] 100. A method using an integrated circuit described in any one of embodiments 1 to 98, the method comprising writing to the group of modules and reading from the group of modules.

Claims

1. It is an integrated circuit, A group of modules having multiple modules, including a first module and a second module, A shared write port configured to write to the aforementioned group of modules, A first read port configured to read from the first module, A second read port configured to read from the second module, An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, wherein the first and second read ports are configured to be deactivated when a write operation is applied to the shared write port.

3. The integrated circuit according to claim 1, wherein the first and second read ports are configured to process reads from each other simultaneously.

4. The integrated circuit according to claim 1, wherein the shared write port is configured to write to the address space, and the shared write port is configured to write to the first module via a first portion of the address space and to write to the second module via a second portion of the address space.

5. The integrated circuit according to claim 1, wherein each of the plurality of modules includes an independent read port that reads simultaneously through the independent read port of any of the plurality of modules, so that the first read port is configured to read from the first module simultaneously with another read of the second module using the second read port.

6. The integrated circuit according to claim 1, wherein the group of modules is configured to have a single write address space configured to write to the plurality of modules.

7. The integrated circuit according to claim 6, wherein the first read port is configured to have a first read address space, and the second read port is configured to have a second read address space.

8. The integrated circuit according to claim 7, wherein the first read address space numerically overlaps with the second read address space.

9. The integrated circuit according to claim 7, wherein the first read address space has the same extent as the second read address space.

10. The integrated circuit according to claim 7, wherein the first read address space is contiguous with respect to the second read address space.

11. The integrated circuit according to claim 1, wherein the group of modules is formed in the second layer of the integrated circuit device.

12. The integrated circuit according to claim 1, wherein the integrated circuit is mounted as a chiplet configured to be face-to-face bonded.

13. The integrated circuit according to claim 12, wherein the chiplet further comprises a plurality of input / output (I / O) junctions, each of the plurality of input / output (I / O) junctions configured to provide a read port for each of the plurality of modules, and each of the plurality of input / output (I / O) junctions configured to interface with a complementary input / output (I / O) junction of a second device when bonded to the chiplet.

14. A method for forming an integrated circuit, wherein the method is To form a group of modules having multiple modules, including a first module and a second module, To form a shared write port configured to write to the aforementioned group of modules, To form a first read port configured to read from the first module, To form a second read port configured to read from the second module, Methods that include...

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