Devices including a substrate in which passive electronic components are embedded.

Abstract

The device includes a core, the core comprising an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer in contact with the upper and lower core dielectric layers, and passive electronic components embedded within the central core dielectric layer. The device includes an upper stacked stack coupled to the upper core dielectric layer. The upper stacked stack comprises an upper metal layer and contact pads configured to electrically connect the die to the passive electronic components via conductive paths defined by the set of upper metal layers. The device includes a lower stacked stack coupled to the bottom surface of the lower core dielectric layer. The lower stacked stack comprises a lower metal layer and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

Description

Technical Field

[0001] Cross-Reference to Related Applications

[0001] This application claims the benefit of priority from U.S. Non-Provisional Patent Application No. 18 / 455,439, filed on August 24, 2023, which is commonly owned by the applicant, the entire content of which is expressly incorporated herein by reference.

[0002]

[0002] Various features relate to integrated devices. Background

[0003]

[0003] Electrical connections exist at each level of the system hierarchy. This system hierarchy includes everything from the interconnection of active devices at the lowest system level to system-level interconnections at the highest level. For example, an interconnection layer can connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnection layers are used to provide electrical connections between devices. More recently, the number of interconnection levels for circuits has increased substantially in modern electronic devices, due to the large number of devices that are now interconnected. Increasing the number of interconnection levels to support the increase in the number of devices involves more complex processes.

[0004]

[0004] State-of-the-art mobile application devices require small form factors, low cost, tight power budgets, and high electrical performance. Mobile package design has evolved to meet these diverse goals to enable mobile applications supporting multimedia extensions. However, when multiple dies are configured within a small form factor, these mobile applications are susceptible to power and signal routing issues. Designing and manufacturing devices for use in mobile applications is challenging due to conflicts between various design goals. For example, smaller form factor devices are generally more expensive to design and manufacture, and the smaller size can exacerbate other issues such as thermal management.

[0005]

[0005] As another example, the power distribution network (PDN) performance of a device can be improved by electrically connecting the PDN to a suitable passive component (e.g., a capacitor). However, adding such passive components tends to increase the package size or limit the area available for other components. In some cases, passive components can be embedded within the package substrate to alleviate size and area concerns (and to address other issues). However, embedding passive components within the package substrate presents further challenges, which may limit routing options and / or require the use of more layers within the package substrate. [Overview of the project]

[0006]

[0006] Various features relate to integrated devices.

[0007]

[0007] One example provides a device comprising a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer in direct contact with the bottom surface of the upper core dielectric layer and in direct contact with the top surface of the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device also includes an upper stacked stack coupled to the top surface of the upper core dielectric layer. The upper stacked stack includes a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic component via a conductive path defined by the set of upper metal layers. The device also includes a lower stacked stack coupled to the bottom surface of the lower core dielectric layer. The lower stacked stack includes a set of lower metal layers, including a first lower metal layer in direct contact with the bottom surface of the lower core dielectric layer. The lower stacked stack also includes a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

[0008]

[0008] Another example provides a device comprising a core containing a passive electronic component embedded inside. The device also comprises an upper stacked stack coupled to the core. The upper stacked stack comprises a set of contact pads configured to electrically connect the die to the passive electronic component via a conductive path defined by one or more upper metal layers of the upper stacked stack. The device also comprises a lower stacked stack coupled to the core. The lower stacked stack comprises a set of lower metal layers. The metal layer closest to the core in the set of lower metal layers comprises one or more traces that pass through the shadow of the passive electronic component.

[0009]

[0009] In another example, a method for manufacturing a device is provided. The method includes providing a core. The core includes a central core dielectric layer in which passive electronic components are embedded, an upper core dielectric layer on the upper surface of the central core dielectric layer, and a lower core dielectric layer on the bottom surface of the central core dielectric layer. The method includes forming an upper stacked stack on the upper surface of the upper core dielectric layer. The upper stacked stack includes a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic components via a conductive path defined by the set of upper metal layers. The method includes forming a lower stacked stack on the bottom surface of the lower core dielectric layer. The lower stacked stack includes a set of lower metal layers, including a first lower metal layer in direct contact with the bottom surface of the lower core dielectric layer.

[0010]

[0010] In another example, a method for manufacturing a device is provided. The method includes providing a core containing a passive electronic component embedded therein. The method also includes forming an upper stacked stack coupled to the core. The upper stacked stack includes a set of contact pads configured to electrically connect a die to the passive electronic component via a conductive path defined by one or more upper metal layers of the upper stacked stack. The method also includes forming a lower stacked stack coupled to the core. The lower stacked stack includes a set of lower metal layers. The metal layer closest to the core in the set of lower metal layers includes one or more traces that pass through the shadow of the passive electronic component. [Brief explanation of the drawing]

[0011]

[0011] By reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, various features, essences, and advantages can be made clear. In the drawings, the same reference numerals throughout indicate corresponding parts. [Figure 1]

[0012] A schematic cross-sectional profile diagram of an example device including a substrate containing embedded passive electronic components is shown. [Figure 2]

[0013] Figure 2 shows a schematic cross-sectional profile of another example of a device including a substrate with embedded passive electronic components. [Figure 3]

[0014] Figure 3 shows a schematic cross-sectional profile of another example of a device including a substrate with embedded passive electronic components. [Figure 4A]

[0015] In addition, an exemplary sequence for manufacturing a device including a substrate containing embedded passive electronic components is shown. [Figure 4B] In addition, an exemplary sequence for manufacturing a device including a substrate containing embedded passive electronic components is shown. [Figure 5]

[0016] This flowchart illustrates an exemplary method for manufacturing a device including a substrate containing embedded passive electronic components. [Figure 6]

[0017] This flowchart shows another exemplary method for manufacturing a device including a substrate containing embedded passive electronic components. [Figure 7]

[0018] This specification describes various electronic devices that can integrate dies, electronic circuits, integrated devices, substrates, packages, and / or device packages. [Modes for carrying out the invention]

[0012]

[0019] The following description includes specific details to provide a complete understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of this disclosure. As another example, various devices and structures disclosed herein are shown schematicly. Such schematics are not to scale and are generally intentionally simplified. For example, an integrated device may have tens or hundreds of contacts and corresponding interconnections. However, in this specification, only a very small number of such contacts and interconnections are shown to highlight the important features of this disclosure without overcomplicating the drawings.

[0013]

[0020] Specific aspects of this disclosure are described below with reference to the drawings. In this description, common features are indicated by common reference numbers. Where used herein, various terms are used solely for the purpose of describing specific implementations and are not intended to limit the implementations. For example, the singular forms "a," "an," and "the" are intended to include the plural form unless the context otherwise explicitly indicates. Furthermore, some features described herein are singular in some implementations and plural in others. For ease of reference in this specification, such features are generally introduced as "one or more" features, and therefore refer to the singular or any optional plural form (such as indicated by "(singular or plural)") unless an aspect relating to the plural of a feature is described.

[0014]

[0021] In some drawings, multiple examples of a particular type of feature are shown. In some situations, fewer than all of such features may be identified using reference numbers. For example, a single reference number may be given and associated with a representative example of the feature, so as not to obscure other aspects of the drawing.

[0015]

[0022] As used herein, the terms “comprise,” “comprises,” and “comprising” may be used interchangeably with “include,” “includes,” or “including.” As used herein, “exemplary” refers to an example, an implementation, and / or an aspect, and should not be construed as limiting or indicating a preferred or desirable implementation. As used herein, order-determining terms used to modify elements such as structure, components, and behavior (e.g., “first,” “second,” “third,” etc.) do not in themselves indicate any priority or order of that element over another element, but rather merely distinguish that element from another element that has the same name (apart from the use of order-determining terms). As used herein, the term “set” refers to one or more of a particular element, and the term “plurality” refers to multiple (e.g., two or more) particular elements.

[0016]

[0023] As used herein, the term “layer” includes films and, unless otherwise stated, shall not be construed as indicating vertical or horizontal thickness. As used herein, the term “chiplet” may refer to an integrated circuit block, a functional circuit block, or any other similar circuit block specifically designed to work with one or more other chiplets to form a larger and more complex chiplet architecture.

[0017]

[0024] Improvements in manufacturing technology and the demand for lower-cost, higher-performance electronic devices are increasing the complexity of integrated circuits (ICs). Often, more complex ICs have more complex interconnection schemes to enable interaction between ICs in a device. In state-of-the-art mobile application devices, the number of interconnection levels for circuits has substantially increased due to the sheer number of interconnected devices that are now present.

[0018]

[0025] These interconnections include back-end-of-line (BEOL) interconnect layers, which may refer to conductive interconnect layers for electrically coupling to the front-end-of-line (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at the corresponding BEOL interconnect levels, where lower BEOL interconnect levels generally use thinner metal layers compared to higher BEOL interconnect levels. The BEOL interconnect layers may be electrically coupled to middle-of-line (MOL) interconnect layers that interconnect to the FEOL active devices of the IC.

[0019]

[0026] State-of-the-art mobile application devices require small form factors, low cost, strict power budgets, and high electrical performance. Mobile package design has evolved to meet these diverse goals to enable mobile applications supporting multimedia extensions. One approach to reducing package size is to integrate multiple dies within a single package. One example of a multi-die package is a two-dimensional (2D) package architecture, in which two or more dies are bonded side-by-side to each other on a package substrate. Dies in this configuration can interact with each other (e.g., via die-to-die connections) and with devices external to the package (e.g., via off-package connections). A challenge with such a configuration is that die-to-die connections and off-package connections have different design criteria. For example, off-package connections are generally larger (e.g., in terms of line width, line spacing, etc.) than required for die-to-die connections. Various workarounds have been used to address this size difference. For example, an additional device (e.g., an interposer device or a bridge die) can be added to the package to route die-to-die connections using finer lines. As another example, additional layers or a separate laminated substrate can be added to the package substrate to provide redistribution routing for connecting to die-to-die connections and off-package connections.

[0020]

[0027] Another approach to reducing package size is a 2.5D architecture, in which two or more devices are placed side-by-side on a package substrate, and one or more additional devices are stacked on at least one of the side-by-side devices. By way of illustration, a stacked die arrangement can be bonded to a package substrate side-by-side with another die, a passive device, another die stack, or the like. Stacked die schemes and chiplet architectures are becoming more common as significant improvements in power performance area (PPA) and yield have been demonstrated in stacked die and chiplet architecture product lines.

[0021]

[0028] Passive devices such as integrated capacitor devices can be embedded in the core of a package substrate to improve power distribution network performance. However, embedding passive devices in the core of a substrate can introduce other challenges. For example, a typical core used in an integrated device package includes a dielectric layer having a metal layer (e.g., copper foil) on each side. A portion of the dielectric layer and a portion of each of the metal layers are removed to form an opening in which the passive device is embedded. Before or after embedding the passive device in the core, the metal layers are patterned to form traces and pads of the substrate. As a result of these operations, the nearest metal layer above the core does not include metal directly above the embedded passive device, and the nearest metal layer below the core does not include metal directly below the embedded passive device. The absence of metal in these locations means that traces cannot be routed directly above or below the embedded passive device in these layers, which limits routing options and may in some cases require the use of more metal layers in the substrate to meet routing requirements, which increases the overall thickness of the substrate and the integrated device associated with the substrate.

[0022]

[0029] Furthermore, the absence of metal in these locations means that conductive paths between the embedded passive device and the power distribution network of a die coupled to the package cannot be routed through the metal layers closest to the core. Consequently, conductive paths between the embedded passive device and the power distribution network are routed through other metal layers, which may require the use of longer conductive paths. Longer conductive paths are associated with increased inductance and resistance, each of which degrades PDN performance.

[0023]

[0030] Embodiments disclosed herein address each of the above challenges by adding a relatively thin dielectric build-up layer to the core. In particular, passive electronic components can be embedded within a central core layer, and upper and lower build-up layers can be arranged on top of the central core layer and the passive electronic components embedded therein. The nearest metal layer above the core is bonded to the upper build-up layer, and the nearest metal layer below the core is bonded to the lower build-up layer. As a result of this arrangement configuration, the first metal layer above the core can be patterned to include a conductor (e.g., traces and / or pads) directly above the embedded passive electronic components. Similarly, the first metal layer below the core can be patterned to include a conductor (e.g., traces and / or pads) directly below the embedded passive electronic components. A technical advantage of this arrangement configuration is improved routing flexibility. A further technical advantage of this arrangement configuration is that the conductive path from the embedded passive electronic components to the PDN can be shortened, thereby reducing the inductance and resistance of the conductive path and improving PDN performance.

[0024]

[0031] The aforementioned limitations in trace routing can be addressed by adding more layers to the substrate. For example, if routing requirements cannot be met due to the inability to route traces or the inability to place pads directly above or below passive electronic components in the first metal layer from the core, additional routing options can be provided by adding more metal layers (and dielectric layers between them). However, the implementation configuration disclosed herein solves these problems without adding more layers, and as a result, can provide a more compact substrate. Furthermore, in contrast to the disclosed implementation configuration, adding more layers may not solve, but rather exacerbate, the problems associated with interconnecting embedded passive electronic components to the PDN.

[0025] Exemplary device including a substrate in which passive electronic components are embedded.

[0032] Figure 1 shows a schematic cross-sectional profile of an example of a device 100 including a substrate 102 in which a passive electronic component 130 is embedded. One or more dies (e.g., die 104) are electrically connected to conductors of the substrate 102. In particular, die 104 is electrically connected to the passive electronic component 130 and the out-of-package contacts 166 (e.g., contacts of a ball grid array (BGA)) via conductors of the substrate 102. As will be described in more detail below, the passive electronic component 130 is embedded within a core 106 of the substrate 102, and one or both of the metal layers closest to the core 106 (e.g., metal layer 146, metal layer 142, or both) include conductors (e.g., traces and / or pads) that are within or pass through a region corresponding to the shadow 172 of the passive electronic component 130.

[0026]

[0033] The die 104 includes circuits such as a plurality of transistors 160 and / or other circuit elements arranged and interconnected to form a power distribution network (PDN) 162. The transistors 160 can be arranged to form logic cells, memory cells, amplifiers, other active circuit elements, or combinations thereof. The components of the circuits can be formed in and / or on the semiconductor substrate of the die 104. Different implementations can use different types of transistors 160, such as field-effect transistors (FETs), planar FETs, fin FETs, gate-all-around FETs, or a mixture of transistor types. In some implementations, a front-end (FEOL) process may be used to form the die 104, and the circuits may be manufactured in and / or on the semiconductor substrate.

[0027]

[0034] The circuitry of die 104 is electrically connected to a set of contacts 186 on die 104. The contacts 186 are configured to be electrically connected via conductors on substrate 102 to one or more other dies (as described with reference to, for example, Figure 2 or Figure 3), out-of-package devices via out-of-package contacts 166, passive electronic components 130, or a combination thereof. As an example, the passive electronic component 130 may include an integrated capacitor device (such as a deep trench capacitor device or a multilayer ceramic capacitor device) coupled to the PDN 162 of die 104 to improve the performance of the PDN 162.

[0028]

[0035] The substrate 102 includes a core 106, an upper stacked stack 108, and a lower stacked stack 110. The core 106 includes an upper core dielectric layer 112, a lower core dielectric layer 114, and a central core dielectric layer 116 that is in direct contact with the bottom surface 118 of the upper core dielectric layer 112 and the top surface 120 of the lower core dielectric layer 114. The upper core dielectric layer 112 and the lower core dielectric layer 114 are thinner than the central core dielectric layer 116. For example, the central core dielectric layer 116 has a thickness in the range of 40 to 210 micrometers, and each of the upper core dielectric layer 112 and the lower core dielectric layer 114 has a thickness of less than 20 micrometers, for example, 8 to 12 micrometers. In a particular mounting configuration, the upper core dielectric layer 112 and the lower core dielectric layer 114 are formed at predetermined locations on the central core dielectric layer 116 to form the core 106. For example, each of the upper core dielectric layer 112 and the lower core dielectric layer 114 may include, or correspond to, a resin layer or resin embedding layer (e.g., a prepreg layer) that is applied to the central core dielectric layer 116 and cured to form the core 106 layer. In this example, the upper core dielectric layer 112 and the lower core dielectric layer 114 may be called build-up layers.

[0029]

[0036] The passive electronic component 130 is embedded within the central core dielectric layer 116. For example, the central core dielectric layer 116 may include an opening in which the passive electronic component 130 is disposed. A resin 196 can be disposed in the opening of the central core dielectric layer 116 to hold the passive electronic component 130. The upper core dielectric layer 112 covers the upper surface of the central core dielectric layer 116, which includes covering the opening in which the passive electronic component 130 is disposed. The lower core dielectric layer 114 covers the bottom surface of the central core dielectric layer 116, which includes covering the opening in which the passive electronic component 130 is disposed. The contacts 178 of the passive electronic component 130 are electrically connected to conductors of the metal layer 146 by conductive vias 176 that extend through the upper core dielectric layer 112.

[0030]

[0037] The upper stacked stack 108 is coupled to the upper surface 132 of the upper core dielectric layer 112. The upper stacked stack 108 includes a set of upper metal layers (e.g., metal layer 146 and metal layer 148) separated by an upper dielectric layer (one or more) (e.g., dielectric layer 150). In the example shown in Figure 1, metal layer 146 is in direct contact with the upper surface 132 of the upper core dielectric layer 112. The upper stacked stack 108 also includes interconnects (e.g., conductive vias 182) between the metal layers that penetrate the dielectric layer (one or more). Figure 1 shows the upper stacked stack 108 as including two metal layers and one dielectric layer between them, but in some implementations, the set of upper metal layers may include three or more metal layers and dielectric layers between them.

[0031]

[0038] The upper stacked stack 108 also includes a set of contact pads (e.g., contact pad 138 in the metal layer 148) configured to electrically connect the die 104 to the passive electronic component 130 via conductive paths defined by the set of upper metal layers. For example, in Figure 1, the contact pad 138 is electrically connected to the contact 186 of the die 104 via a bump pad 184 extending through the solder resist layer 190 of the upper stacked stack 108, and by solder bumps of a set of microbumps 188 of the die 104. The contact pad 138 is also connected to a pad or trace (e.g., trace 152) of the metal layer 146 by a conductive via 182. The pad or trace of the metal layer 146 is electrically connected to one of the contacts 178 of the passive electronic component 130 by one of the conductive vias 176 extending through the upper core dielectric layer 112.

[0032]

[0039] The lower stacked stack 110 is coupled to the bottom surface 134 of the lower core dielectric layer 114. The lower stacked stack 110 includes a set of lower metal layers (e.g., metal layer 142 and metal layer 144) separated by a dielectric layer (e.g., dielectric layer 140). In the example shown in Figure 1, metal layer 142 is in direct contact with the bottom surface 134 of the lower core dielectric layer 114. The lower stacked stack 110 also includes interconnects (e.g., conductive vias 174) between the metal layers and through the dielectric layer(s). Figure 1 shows the lower stacked stack 110 as including two metal layers and one dielectric layer between them, but in some implementations, the set of lower metal layers may include three or more metal layers and dielectric layers between them.

[0033]

[0040] The lower stacked stack 110 also includes a set of contact pads (e.g., contact pads 194 in the metal layer 144) configured to electrically connect the substrate 102 and / or components coupled thereto (e.g., dies 104) to one or more out-of-package devices via out-of-package contacts 166. For example, in Figure 1, the contact pad 194 is electrically connected to the ball grid array contacts 170 of the out-of-package contacts 166 that extend through the solder resist layer 192 of the lower stacked stack 110. The contact pad 194 is also connected to a pad or trace (e.g., trace 180) in the metal layer 142 by one of the conductive vias 174. The metal layer 142 is patterned to form a trace that is coupled to the metal layer 146 by conductive vias 164 that penetrate the core 106, and the metal layer 146 is patterned to form a trace that is electrically connected to the contacts 178 of the passive electronic component 130, to the contacts 186 of the die 104, or both, via conductors of the upper stacked stack 108.

[0034]

[0041] Since the nearest metal layer above core 106 (e.g., metal layer 146) is on the surface covering the passive electronic component 130 (e.g., the upper surface 132 of the upper core dielectric layer 112), the nearest metal layer above core 106 can be patterned to form traces and / or pads in the region directly above the passive electronic component 130. For example, in Figure 1, trace 152 is in the metal layer closest to core 106 and extends through the region corresponding to the shadow 172 of passive electronic component 130. Thus, the upper stacked stack 108 offers greater routing flexibility than would be available if the metal layer closest to core 106 did not include traces and / or contacts in the region corresponding to the shadow 172 of passive electronic component 130, as is the case with conventional embedded cores.

[0035]

[0042] Similarly, in Figure 1, the nearest metal layer beneath the core 106 (e.g., metal layer 142) is on the surface covering the passive electronic component 130 (e.g., the bottom surface 134 of the lower core dielectric layer 114). As a result, the nearest metal layer beneath the core 106 can be patterned to form traces and / or pads in the region directly beneath the passive electronic component 130. For example, in Figure 1, the trace 180 is in the nearest metal layer beneath the core 106 and extends through the shadow 172 of the passive electronic component 130. Thus, the lower stacked stack 110 offers greater routing flexibility than would be available if the nearest metal layer beneath the core 106 did not contain traces and / or contacts within the shadow 172 of the passive electronic component 130, as is the case with conventional embedded cores.

[0036]

[0043] Figure 2 shows a schematic cross-sectional profile of another example of device 200 including the substrate 102 of Figure 1. Device 200 in Figure 2 includes a die 104 coupled to the substrate 102. The die 104 and the substrate 102 have the same features as described above with reference to Figure 1, although for clarity certain features are not reproduced in Figure 2. Furthermore, device 200 includes one or more additional devices coupled to the substrate 102. For example, device 200 includes a die 202 coupled to the substrate 102 via one or more interconnectors 208 and a redistribution structure 206. The redistribution structure 206 may include a second substrate or a set of redistribution layers. In either case, the redistribution structure 206 includes a plurality of metal layers patterned and interconnected to form conductive paths through a set of dielectric layers. The substrate 102 may include one or more contacts 210 electrically connected to one or more interconnection portions 208 to provide conductive paths between die 104 and die 202, between die 202 and passive electronic components 130, between die 202 and package-external contacts 166, or combinations thereof.

[0037]

[0044] Figure 3 shows a schematic cross-sectional profile of another example of device 300 including the substrate 102 of Figure 1. The device 300 in Figure 3 includes a die 104 coupled to the substrate 102. The die 104 and the substrate 102 have the same features as described above with reference to Figure 1, although for clarity certain features are not reproduced in Figure 2. Furthermore, device 300 includes one or more additional devices coupled to the substrate 102. For example, device 300 includes a die 302 coupled to a contact 304 of the substrate 102 alongside the die 104. In this example, the conductors of the substrate 102 can define a conductive path between the die 104 and the die 302. Additionally, or alternatively, the conductors of the substrate 102 can define a conductive path between the die 302 and the passive electronic component 130, between the die 302 and the out-of-package contact 166, or both.

[0038]

[0045] Figures 1 to 3 show individual dies coupled to the substrate 102, but in some mounting configurations, one or more of the dies include, or correspond to, chiplets that are interconnected via the substrate 102 or stacked and coupled to the substrate 102 as a stack. In a stacked chiplet configuration, one chiplet is stacked on top of another chiplet and electrically connected to that other chiplet. Using chiplets arranged and interconnected as a 3D stack can offer various advantages compared to providing the same functional circuitry within a single monolithic chip. For example, each chiplet is smaller than a monolithic die containing all of the same functional circuitry blocks. Yield loss in IC manufacturing tends to increase with increasing die size, so using smaller dies can reduce yield loss in the IC manufacturing process (i.e., increase yield). Another advantage is that chiplets can be manufactured in different locations and / or by different manufacturers, and possibly using different manufacturing technologies (e.g., different manufacturing technology nodes). For example, one chiplet in an integrated device may contain a component with a first minimum size (e.g., an interconnect, a transistor, etc.), and another chiplet in the integrated device may contain a component with a second minimum size (e.g., an interconnect, a transistor, etc.), where the second minimum size is larger than the first minimum size. In contrast, all circuits in a monolithic die are manufactured using the same manufacturing techniques and equipment. As a result, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex component of the monolithic die. In contrast, when using chiplets, different chiplets can be manufactured using different manufacturing techniques (e.g., different manufacturing technique nodes), and only one or more chiplets containing the most complex component are subject to the most stringent manufacturing constraints.In this configuration, chiplets manufactured using less expensive and / or higher yield manufacturing techniques can be integrated with chiplets manufactured using more expensive and / or lower yield manufacturing techniques to form an integrated device, resulting in overall savings. Furthermore, in some cases, as technology improves, the design of one or both chiplets can be modified so that the new chiplet design integrates with the older chiplet design, which improves manufacturing flexibility and reduces design costs.

[0039]

[0046] In various implementations, any of devices 100, 200, or 300 may include components such as power management integrated circuits (PMICs), application processors (including one or more processor cores), modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory (including multiple memory cells), power management processors, and / or combinations thereof. In such implementations, dies 104, 202, and 302 can operate as any of these components (or combinations thereof), including active circuits.

[0040] Exemplary sequence for manufacturing a device including a substrate with embedded passive electronic components

[0047] In some implementations, manufacturing a device including a substrate containing internally embedded passive electronic components involves several processes. Figures 4A and 4B show exemplary sequences for providing or manufacturing a device including a substrate containing internally embedded passive electronic components, as described with reference to any of Figures 1 to 3. In some implementations, the sequences in Figures 4A and 4B may be used to provide (for example, during their manufacture) device 100 in Figure 1, device 200 in Figure 2, or device 300 in Figure 3.

[0041]

[0048] It should be noted that the sequences in Figures 4A and 4B may be combinations of one or more steps to simplify and / or clarify the sequence for providing or manufacturing an integrated device. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. In the following description, various exemplary steps of the sequence numbered (using circled numbers) in Figures 4A and 4B will be referenced.

[0042]

[0049] Step 1 in Figure 4A shows the state after the opening 404 has been formed in the core 402. In the example shown in Figure 4A, a support layer 406 is applied to the core 402 either before or after the formation of the opening 404. For example, the support layer 406 corresponds to or includes a tape layer applied to one of the surfaces of the core 402. In certain implementation configurations, the core 402 corresponds to or includes the central core dielectric layer 116 in Figure 1. The opening 404 can be formed using one or more cutting operations, such as laser cutting.

[0043]

[0050] Stage 2 shows the state after the passive electronic component 410 has been placed within the opening 404. The passive electronic component 410 corresponds to or includes the passive electronic component 130 in Figure 1. For example, the passive electronic component 410 may include an integrated capacitor device. In the example shown in Figure 4A, the passive electronic component 410 is shown as being placed "downward" (for example, with the contacts facing the support layer 406). However, in other configurations, the passive electronic component 410 can be placed "upward" (for example, with the contacts facing away from the support layer 406). The support layer 406 supports and holds the passive electronic component 410 within the opening 404.

[0044]

[0051] Step 3 shows the state after forming or applying a first build-up layer 412 on the core 402 and coating the resin 411 into the portion of the opening 404 that is not filled by the passive electronic components 410. The first build-up layer 412 corresponds to or includes the upper core dielectric layer 112 or the lower core dielectric layer 114, and the resin 411 corresponds to or includes the resin 196 in Figure 1.

[0045]

[0052] In some implementations, the first build-up layer 412 and the resin 411 are coated simultaneously. In some examples, the resin can be coated onto the core 402 such that the resin at least partially encapsulates the passive electronic components 410 and forms the resin 411 and the first build-up layer 412. In some such examples, the resin coated to simultaneously form the first build-up layer 412 and the resin 411 includes a liquid or gel coated via a fluid coating process (e.g., using one or more spray, rolling, dipping, or spin-on operations). In other such examples, the resin is incorporated into a prepreg material comprising the resin and a carrier medium such as a fiber mat or tape material, and the prepreg material may be coated using a composite layup operation.

[0046]

[0053] Step 4 shows the state after the removal of the support layer 406, the formation of the second build-up layer 414, the formation of the opening 416 that penetrates the first build-up layer 412, the core 402, and the second build-up layer 414, and the formation of the opening 418 that penetrates the second build-up layer 414. The second build-up layer 414 can be formed in the same manner as described above with respect to the formation of the first build-up layer 412 in Step 3. The second build-up layer 414 corresponds to or includes the upper core dielectric layer 112 or the lower core dielectric layer 114 in Figure 1. For example, if the first build-up layer 412 corresponds to the upper core dielectric layer 112, then the second build-up layer 414 corresponds to the lower core dielectric layer 114. Alternatively, if the first build-up layer 412 corresponds to the lower core dielectric layer 114, then the second build-up layer 414 corresponds to the upper core dielectric layer 112.

[0047]

[0054] The openings 416 and 418 can be formed after the build-up layers 412 and 414 have cured. The openings 416 and 418 can be formed using one or more material removal operations such as etching, mechanical drilling, or laser drilling. The opening 416 is a through-opening extending from one side to the other of the workpiece 415, which corresponds to or includes the core 106 in Figure 1. The opening 418 extends through the second build-up layer 414, exposing the contacts of the passive electronic component 410.

[0048]

[0055] Step 5 shows the state after the formation of conductive vias 420, 422 and the formation and patterning of metal layers 424, 426. Conductive via 420 is formed within opening 416 and corresponds to or includes conductive via 164 in Figure 1. Conductive via 422 is formed within opening 418 and corresponds to or includes conductive via 176 in Figure 1. Metal layer 424 is formed on the first build-up layer 412 (e.g., in direct contact with its surface) and corresponds to or includes metal layer 142 in Figure 1. Metal layer 426 is formed on the second build-up layer 414 (e.g., in direct contact with its surface) and corresponds to or includes metal layer 146 in Figure 1. The metal layer 424 is patterned to include conductive feature portions 432 (e.g., traces or pads), and the conductive feature portions 432 may include traces or pads in the region directly above the passive electronic component 410 (in the orientation shown in Figure 4A). For example, the conductive feature portions 432 may include traces or pads in the shadow of the passive electronic component 410. Similarly, the metal layer 426 is patterned to include conductive feature portions 430 (e.g., traces or pads), and the conductive feature portions 430 may include traces or pads in the region directly below the passive electronic component 410 (in the orientation shown in Figure 4A). For example, the conductive feature portions 426 may include traces or pads in the shadow of the passive electronic component 410.

[0049]

[0056] In some configurations, the metal layers 424, 426 are formed and patterned simultaneously with the formation of the conductive vias 420, 422. For example, a patterned film can be applied to the first and second build-up layers 412, 414 to define the feature portions 432, 430 of the metal layers 424, 426 and the openings for the conductive vias 420, 422. In this example, the metal layers 424, 426 and the conductive vias 420, 422 can be formed using a plating or deposition process induced by the patterned film. In other configurations, the conductive vias 420, 422 and the metal layers 424, 426 are formed in separate operations.

[0050]

[0057] Step 6 in Figure 4B (reversed relative to the orientation shown in Step 5 of Figure 4A) shows the formation and interconnection of additional metal layers. In Figure 4B, the formation and interconnection of additional metal layers includes the formation of a dielectric layer 440 on metal layer 424, the formation of a metal layer 442 on dielectric layer 440, and the formation of one or more conductive vias 450 to electrically connect metal layer 424 and metal layer 442. Furthermore, in Figure 4B, the formation and interconnection of additional metal layers includes the formation of a dielectric layer 444 on metal layer 426, the formation of a metal layer 446 on dielectric layer 444, and the formation of one or more conductive vias 454 to electrically connect metal layer 426 and metal layer 446. Metal layers 442 and 446 are patterned to include conductive features 452 and 456 (e.g., traces or pads). In some implementations, metal layer 442 corresponds to or includes metal layer 148 in Figure 1, and metal layer 446 corresponds to or includes metal layer 144 in Figure 1.

[0051]

[0058] In some implementations, the metal layers 442 and 446 are formed and patterned simultaneously with the formation of the conductive vias 450 and 454, as described above with respect to step 5. In other implementations, the conductive vias 450 and 454 and the metal layers 424 and 426 are formed in separate operations. Figure 4B shows only two metal layers on each side of the core 402, but in other implementations, three or more metal layers can be formed on each side of the core 402 by repeating the operations described with reference to step 6.

[0052]

[0059] Step 7 shows the state after the formation and patterning of the solder resist layer 462 on the upper metal layer (e.g., the metal layer 442 shown in Step 6) and the formation and patterning of the solder resist layer 466 on the lower metal layer (e.g., the metal layer 446 shown in Step 6). The solder resist layer 462 is patterned to form openings 464 for exposing contacts (e.g., one or more of the conductive features) of the upper metal layer, and the solder resist layer 466 is patterned to form openings 468 for exposing contacts (e.g., one or more of the conductive features) of the lower metal layer. The formation of the substrate 460 with the passive electronic components 410 embedded is completed in Step 7. The substrate 460 includes a core portion 470 corresponding to or containing the core 106 in Figure 1, an upper portion 472 corresponding to or containing the upper stacked stack 108 in Figure 1, and a lower portion 474 corresponding to or containing the lower stacked stack 110 in Figure 1.

[0053]

[0060] Step 8 shows the state after one or more dies (including die 480) have been mounted on the substrate 460 to form device 490. For example, contact 486 of die 480 may be electrically connected to the corresponding contact 488 of substrate 460 via solder bump 482 and bump pad 484. Device 490 may include solder ball 492 electrically connected to the corresponding contact 494 of substrate 460, enabling connection of device 490 to other devices. For example, solder bump 482 of die 480 may be positioned on bump pad 484 and heated to reflow the solder bump 482 to form a physical and electrical connection between contact 486 and contact 488.

[0054] Exemplary flowchart of a method for manufacturing a device including a substrate with embedded passive electronic components.

[0061] In some implementations, manufacturing a device including a substrate containing internally embedded passive electronic components involves several processes. Figure 5 shows an exemplary flow chart of a method 500 for providing or manufacturing a device including a substrate containing internally embedded passive electronic components. In some implementations, the method 500 in Figure 5 may be used to provide or manufacture any of the devices 100 in Figure 1, 200 in Figure 2, 300 in Figure 3, or 490 in Figure 4B. It should be noted that the method 500 in Figure 5 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified.

[0055]

[0062] Method 500 includes providing a core in block 502 that includes a central core dielectric layer in which passive electronic components are embedded, an upper core dielectric layer on the upper surface of the central core dielectric layer, and a lower core dielectric layer on the bottom surface of the central core dielectric layer. For example, the core may include or correspond to the core 106 in Figure 1, which includes an upper core dielectric layer 112, a lower core dielectric layer 114, and a central core dielectric layer 116 in which passive electronic components 130 are embedded. As another example, the core may correspond to or include the core portion 470 in Figure 4B, which includes a first build-up layer 412, a second build-up layer 414, and a core 402 in which passive electronic components 410 are embedded. Steps 1 to 5 in Figure 4A show examples of operations that can be used to provide (e.g., manufacture) a core.

[0056]

[0063] Method 500 includes forming an upper stacked stack on the upper surface of the upper core dielectric layer in block 504. The upper stacked stack includes a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic components via conductive paths defined by the set of upper metal layers. For example, the upper stacked stack may include or correspond to the upper stacked stack 108 in Figure 1. In this example, the upper stacked stack 108 includes metal layers 146, 148 and a dielectric layer 150 between them. The metal layers 146, 148 define traces and pads interconnected by vias 182 to form conductive paths between the contact 178 of the passive electronic component 130 and the contact pad 138 which is electrically connected to the contact 186 of the die 104 in Figure 1. In another example, the upper stacked stack may correspond to or include the upper portion 472 in Figure 4B. In this example, the upper portion 472 includes metal layers 424, 442 and a dielectric layer 440 between them. The metal layers 424 and 442 define conductive feature portions 432 and 452 interconnected by vias 450 to form a conductive path between the contacts of the passive electronic component 130 and contact 488 configured to be electrically connected to contact 486 of the die 480. Steps 5–7 in Figures 4A and 4B show an example of operation that can be used to form an upper stacked stack on the upper surface of the upper core dielectric layer.

[0057]

[0064] Method 500 includes forming a lower stacked stack on the bottom surface of a lower core dielectric layer in block 506. The lower stacked stack includes a set of lower metal layers, including a first lower metal layer that is in direct contact with the bottom surface of the lower core dielectric layer. For example, the lower stacked stack includes or corresponds to the lower stacked stack 110 in Figure 1. In this example, the lower stacked stack 110 includes metal layers 142, 144 and a dielectric layer 140 between them. In this example, metal layer 142 is in direct contact with the bottom surface 134 of the lower core dielectric layer 114. As another example, the lower stacked stack corresponds to or includes the lower portion 474 in Figure 4B. In this example, the lower portion 474 includes metal layers 426, 446 and a dielectric layer 444 between them. In this example, metal layer 426 is in direct contact with the bottom surface of the second build-up layer 414. Steps 5-7 in Figures 4A and 4B illustrate an example of an operation that can be used to form a lower stacked stack on the bottom surface of the lower core dielectric layer (for example, on the second build-up layer 414).

[0058]

[0065] In some implementation configurations, before forming the upper stacked stack, Method 500 includes forming a first opening extending through the upper core dielectric layer, the central core dielectric layer, and the lower core dielectric layer; forming a second opening extending through the upper core dielectric layer to expose contacts of passive electronic components; forming a first conductive via within the first opening and a second conductive via within the second opening, wherein one or more first traces of the upper metal layer set are electrically connected to the first conductive via and one or more second traces of the upper metal layer set are electrically connected to the second conductive via. For example, as described with reference to steps 4 and 5 of Figure 4A, an opening 416 can be formed to extend through the first build-up layer 412, the second build-up layer 414, and the core 402, and an opening 418 can be formed to extend through the second build-up layer 414. In this example, the first build-up layer 412 corresponds to the lower core dielectric layer, the second build-up layer 414 corresponds to the upper core dielectric layer, and the core 402 corresponds to the central core dielectric layer.

[0059]

[0066] In a particular implementation configuration, method 500 includes electrically connecting the PDN of a die to a set of contact pads in order to provide a conductive path between the PDN and the passive electronic component. For example, the PDN 162 of die 104 is electrically connected to the contact 178 of the passive electronic component 130 via conductors and vias 176 of the upper stacked stack 108.

[0060]

[0067] In some implementations, method 500 further includes forming a set of BGA contacts electrically connected to a set of lower metal layers on the bottom surface of the lower stacked stack. In some such implementations, at least one of the BGA contacts in the set of BGA contacts is at least partially located within the shadow of a passive electronic component. For example, device 100 in Figure 1 includes an out-of-package contact 166 containing solder balls arranged in a ball grid array and electrically connected to metal layers 144, 142 of the lower stacked stack 110. In this example, the BGA contact 170 is at least partially located within the shadow 172 of the passive electronic component 130.

[0061]

[0068] In some implementations, providing a core includes forming an opening in a central core dielectric layer, positioning a passive electronic component within the opening and supporting it with a support layer, applying a resin to at least partially encapsulate the passive electronic component within the opening, applying a resin to form a first build-up layer on the central core dielectric layer, and bonding a second build-up layer to the central core dielectric layer. In such implementations, the first build-up layer corresponds to either a lower core dielectric layer or an upper core dielectric layer, and the second build-up layer corresponds to the other of the lower core dielectric layer or the upper core dielectric layer. In some such implementations, providing a core also includes removing the support layer after applying the resin to at least partially encapsulate the passive electronic component and before bonding the second build-up layer to the central core dielectric layer. In some such implementations, bonding the second build-up layer to the central core dielectric layer includes applying a resin to the upper surface of the central core dielectric layer and curing the resin to form the second build-up layer. Examples of operations that can be used to provide the core in such an implementation are illustrated with reference to steps 1-4 in Figure 4A.

[0062]

[0069] Figure 6 shows an exemplary flow diagram of another method 600 for providing or manufacturing a device including a substrate containing internally embedded passive electronic components. In some implementations, method 600 of Figure 6 may be used to provide or manufacture any of the devices 100 in Figure 1, 200 in Figure 2, 300 in Figure 3, or 490 in Figure 4B. It should be noted that method 600 of Figure 6 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified.

[0063]

[0070] Method 600 includes providing a core in block 602 that includes a passive electronic component embedded therein. For example, the core may include or correspond to the core 106 in Figure 1 in which the passive electronic component 130 is embedded. As another example, the core may correspond to or include the core portion 470 in Figure 4B in which the passive electronic component 410 is embedded. Steps 1-4 in Figure 4A show examples of operations that can be used to provide (e.g., manufacture) the core.

[0064]

[0071] Method 600 includes forming an upper stacked stack coupled to a core in block 604. The upper stacked stack includes a set of contact pads configured to electrically connect the die to a passive electronic component via conductive paths defined by one or more upper metal layers of the upper stacked stack. For example, the upper stacked stack may include or correspond to the upper stacked stack 108 in Figure 1. In this example, the upper stacked stack 108 includes metal layers 146, 148 and a dielectric layer 150 between them. The metal layers 146, 148 are interconnected by vias 182 to define traces and pads that form conductive paths between a contact 178 of the passive electronic component 130 and a contact pad 138 that is electrically connected to a contact 186 of the die 104 in Figure 1. In another example, the upper stacked stack may correspond to or include the upper portion 472 in Figure 4B. In this example, the upper portion 472 includes metal layers 424, 442 and a dielectric layer 440 between them. The metal layers 424 and 442 are interconnected by vias 450 to define conductive feature portions 432 and 452, which form conductive paths between the contacts of the passive electronic component 130 and contact 488 configured to be electrically connected to contact 486 of the die 480. Steps 5–7 in Figures 4A and 4B show examples of operations that can be used to form an upper stacked stack on the upper surface of the upper core dielectric layer (for example, on the second build-up layer 414).

[0065]

[0072] Method 600 includes forming a lower stacked stack coupled to a core in block 606. The lower stacked stack includes a set of lower metal layers, the metal layer closest to the core among the set of lower metal layers, which includes one or more traces that pass through the shadow of the passive electronic component. For example, the lower stacked stack includes or can correspond to the lower stacked stack 110 in Figure 1. In this example, the lower stacked stack 110 includes metal layers 142, 144 and a dielectric layer 140 between them. In this example, metal layer 142 is closest to the core 106 among the metal layers 142, 144 of the lower stacked stack 110, and metal layer 142 includes a trace 180 that extends into the shadow 172 of the passive electronic component 130. Steps 5-7 in Figures 4A and 4B show examples of operations that can be used to form the lower stacked stack on the bottom surface of the lower core dielectric layer (e.g., on the first build-up layer 412).

[0066]

[0073] In some implementation configurations, before forming the upper stacked stack, Method 600 includes forming a first opening extending through the upper core dielectric layer, the central core dielectric layer, and the lower core dielectric layer; forming a second opening extending through the upper core dielectric layer to expose contacts of passive electronic components; forming a first conductive via within the first opening and a second conductive via within the second opening, wherein one or more first traces of the upper metal layer set are electrically connected to the first conductive via and one or more second traces of the upper metal layer set are electrically connected to the second conductive via. For example, as described with reference to steps 4 and 5 of Figure 4A, an opening 416 can be formed to extend through the first build-up layer 412, the second build-up layer 414, and the core 402, and an opening 418 can be formed to extend through the second build-up layer 414. In this example, the first build-up layer 412 corresponds to the lower core dielectric layer, the second build-up layer 414 corresponds to the upper core dielectric layer, and the core 402 corresponds to the central core dielectric layer.

[0067]

[0074] In a particular implementation, method 600 includes electrically connecting the PDN of a die to a set of contact pads in order to provide a conductive path between the PDN and the passive electronic component. For example, the PDN 162 of die 104 is electrically connected to the contact 178 of the passive electronic component 130 via conductors and vias 176 of the upper stacked stack 108.

[0068]

[0075] In some implementations, method 600 further includes forming a set of BGA contacts electrically connected to a set of lower metal layers on the bottom surface of the lower stacked stack. In some such implementations, at least one of the BGA contacts in the set of BGA contacts is at least partially located within the shadow of a passive electronic component. For example, device 100 in Figure 1 includes an out-of-package contact 166 containing solder balls arranged in a ball grid array and electrically connected to metal layers 144, 142 of the lower stacked stack 110. In this example, the BGA contact 170 is at least partially located within the shadow 172 of the passive electronic component 130.

[0069]

[0076] In some implementations, providing a core includes forming an opening in a central core dielectric layer, positioning a passive electronic component within the opening and supporting it with a support layer, applying a resin to at least partially encapsulate the passive electronic component within the opening, applying a resin to form a first build-up layer on the central core dielectric layer, and bonding a second build-up layer to the central core dielectric layer. In such implementations, the first build-up layer corresponds to either a lower core dielectric layer or an upper core dielectric layer, and the second build-up layer corresponds to the other of the lower core dielectric layer or the upper core dielectric layer. In some such implementations, providing a core also includes removing the support layer after applying the resin to at least partially encapsulate the passive electronic component and before bonding the second build-up layer to the central core dielectric layer. In some such implementations, bonding the second build-up layer to the central core dielectric layer includes applying a resin to the upper surface of the central core dielectric layer and curing the resin to form the second build-up layer. Examples of operations that can be used to provide the core in such an implementation are illustrated with reference to steps 1-4 in Figure 4A.

[0070] Exemplary electronic devices

[0077] Figure 7 shows various electronic devices that include, or can be integrated with, device 100 in Figure 1, device 200 in Figure 2, device 300 in Figure 3, substrate 460 in Figure 4B, or device 490 in Figure 4B. For example, a mobile phone device 702, a laptop computer device 704, a stationary terminal device 706, a wearable device 708, or a vehicle 710 (e.g., an automobile or an aerial device) may include device 700. Device 700 may include, for example, device 100 in Figure 1, device 200 in Figure 2, device 300 in Figure 3, substrate 460 in Figure 4B, device 490 in Figure 4B, or other devices described herein. Devices 702, 704, 706, and 708 shown in Figure 7, and vehicle 710 are merely examples. Device 700 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, and other stationary data units, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0071]

[0078] One or more of the components, processes, features, and / or functions shown in Figures 1 to 7 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. Note that Figures 1 to 7 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1 to 7 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, heat dissipation devices, and / or interposers.

[0072]

[0079] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures are schematic and may not be to exact scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various components and / or elements in the figures may be optional.

[0073]

[0080] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two electrically coupled objects may or may not transmit an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or fourth or higher) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The terms “encapsulate,” “encapsulating,” and / or any derived terms mean that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa.As described in this disclosure, a first component located "over" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) a first surface of the second component, and the third component may be located above (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being located above another, the term "on" as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of a component or embedded within a component). Therefore, for example, a first component above a second component may mean (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located "in" a second component may be partially located within the second component or completely located within the second component. A value of about X to XX refers to a value between X and XX, including X and XX. The value(s) between X and XX may be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10 percent of "value X". For example, a value of "about 1" or "approximately 1" means a value in the range of 0.9 to 1.1. The term "multiple" components may include all possible components, or only some of all possible components. For example, if a device contains 10 components, the term "multiple components" may refer to all 10 components, or only some of the 10 components.

[0074]

[0081] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0075]

[0082] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0076]

[0083] Further embodiments are described below to facilitate understanding of this disclosure.

[0077]

[0084] According to Example 1, the device includes a core, the core having an upper core dielectric layer, The device includes a lower core dielectric layer, a central core dielectric layer in direct contact with the bottom surface of the upper core dielectric layer and in direct contact with the top surface of the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device also includes an upper stacked stack coupled to the top surface of the upper core dielectric layer. The upper stacked stack includes a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic component via a conductive path defined by the set of upper metal layers. The device also includes a lower stacked stack coupled to the bottom surface of the lower core dielectric layer. The lower stacked stack includes a set of lower metal layers, including a first lower metal layer in direct contact with the bottom surface of the lower core dielectric layer, and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

[0078]

[0085] Example 2 includes the device of Example 1, wherein the upper stacked stack further includes a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers.

[0079]

[0086] Example 3 includes the device of Example 1 or Example 2, and includes a set of upper metal layers, the first upper metal layer in direct contact with the upper surface of the upper core dielectric layer.

[0080]

[0087] Example 4 includes any of the devices from Examples 1 to 3, and comprises a set of lower metal layers, the first lower metal layer in direct contact with the bottom surface of the lower core dielectric layer.

[0081]

[0088] Example 5 includes any of the devices from Examples 1 to 4, wherein the metal layer closest to the core in the set of lower metal layers includes one or more traces that pass through the shadow of the passive electronic component.

[0082]

[0089] Example 6 includes any of the devices from Examples 1 to 5, wherein the passive electronic component includes an integrated capacitor device.

[0083]

[0090] Example 7 comprises any device from Examples 1 to 6, further comprising a die, the power distribution network of the die being coupled to a passive electronic component via a set of contact pads and conductive paths defined by a set of upper metal layers.

[0084]

[0091] Example 8 includes the device of Example 7, wherein the die includes a plurality of transistors.

[0085]

[0092] Example 9 includes the device of Example 7 or Example 8, and further includes one or more additional components electrically connected to the die via a conductive path defined by a set of upper metal layers.

[0086]

[0093] Example 10 comprises any device from Examples 1 to 9 and further includes a plurality of conductive vias that extend through the core and electrically interconnect a set of upper metal layers and a set of lower metal layers.

[0087]

[0094] Example 11 includes any device from Examples 1 to 10 and further includes a set of BGA contacts located on the bottom surface of the lower stacked stack and configured to electrically connect the device to another device or substrate.

[0088]

[0095] Example 12 includes the device of Example 11, wherein at least one of the set of BGA contacts is at least partially positioned within the shadow of the passive electronic component.

[0089]

[0096] According to Example 13, the device includes a core containing a passive electronic component embedded therein. The device also includes an upper stacked stack coupled to the core, which includes a set of contact pads configured to electrically connect the die to the passive electronic component via a conductive path defined by one or more upper metal layers of the upper stacked stack. The device further includes a lower stacked stack coupled to the core, which includes a set of lower metal layers. The metal layer closest to the core in the set of lower metal layers includes one or more traces that pass through the shadow of the passive electronic component.

[0090]

[0097] Example 14 includes the device of Example 13, wherein the upper stacked stack further includes a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers.

[0091]

[0098] Example 15 includes the device of Example 13 or Example 14, and the set of upper metal layers includes a first upper metal layer that is in direct contact with the upper surface of the upper core dielectric layer of the core.

[0092]

[0099] Example 16 includes any of the devices from Examples 13 to 15, wherein the metal layer closest to the core in the set of lower metal layers is in contact with the bottom surface of the lower core dielectric layer of the core.

[0093]

[0100] Example 17 includes any device from Examples 13 to 16, wherein the passive electronic component includes a capacitor device.

[0094]

[0101] Example 18 comprises any device from Examples 13 to 17, further comprising a die, the power distribution network of the die being coupled to passive electronic components via a set of contact pads and conductive paths defined by a set of upper metal layers.

[0095]

[0102] Example 19 includes a device from any of Examples 13 to 18, wherein the die includes a plurality of transistors.

[0096]

[0103] Example 20 includes any device from Examples 13 to 19 and further includes one or more additional components electrically connected to the die via a conductive path defined by a set of upper metal layers.

[0097]

[0104] Example 21 comprises any device from Examples 13 to 20 and further includes a plurality of conductive vias extending through the core and interconnecting a set of upper metal layers and a set of lower metal layers.

[0098]

[0105] Example 22 includes any of the devices from Examples 13 to 21, and further includes a set of BGA contacts located on the bottom surface of a lower stacked structure, configured to electrically connect the device to another device or substrate.

[0099]

[0106] Example 23 includes the device of Example 22, wherein at least one of the set of BGA contacts is at least partially positioned within the shadow of the passive electronic component.

[0100]

[0107] According to Example 24, the method includes providing a core comprising a central core dielectric layer in which passive electronic components are embedded, an upper core dielectric layer on the upper surface of the central core dielectric layer, and a lower core dielectric layer on the bottom surface of the central core dielectric layer. The method also includes forming an upper stacked stack on the upper surface of the upper core dielectric layer, wherein the upper stacked stack comprises a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic components via a conductive path defined by the set of upper metal layers. The method also includes forming a lower stacked stack on the bottom surface of the lower core dielectric layer, wherein the lower stacked stack comprises a set of lower metal layers, including a first lower metal layer in direct contact with the bottom surface of the lower core dielectric layer.

[0101]

[0108] Example 25 comprises the method of Example 24, further comprising: forming a first opening extending through the upper core dielectric layer, the central core dielectric layer, and the lower core dielectric layer before forming the upper stacked stack; forming a second opening extending through the upper core dielectric layer to expose contacts of passive electronic components; forming a first conductive via within the first opening and a second conductive via within the second opening, wherein one or more first traces of the upper metal layer set are electrically connected to the first conductive via and one or more second traces of the upper metal layer set are electrically connected to the second conductive via.

[0102]

[0109] Example 26 comprises the method of Example 24 or Example 25, wherein one or more first traces of a set of lower metal layers are electrically connected to a first conductive via.

[0103]

[0110] Example 27 comprises the method of Example 26, wherein one or more first traces of the set of lower metal layers include at least one trace that passes through the shadow of the passive electronic component.

[0104]

[0111] Example 28 comprises any method of Examples 24 to 27, further comprising electrically connecting the PDN of the die to a set of contact pads to provide a conductive path between the PDN and the passive electronic components.

[0105]

[0112] Example 29 comprises any method of Examples 24 to 28, further comprising forming a set of BGA contacts electrically connected to a set of lower metal layers on the bottom surface of a lower stacked stack, wherein at least one of the BGA contacts is at least partially positioned in the shadow of a passive electronic component.

[0106]

[0113] Example 30 comprises any method of Examples 24 to 29, wherein providing a core includes forming an opening in a central core dielectric layer; positioning a passive electronic component within the opening so as to be supported by a support layer; applying a resin to at least partially encapsulate the passive electronic component within the opening; applying a resin to form a first build-up layer on the central core dielectric layer; and bonding a second build-up layer to the central core dielectric layer, wherein the first build-up layer corresponds to a lower core dielectric layer or an upper core dielectric layer, and the second build-up layer corresponds to the other of the lower core dielectric layer or the upper core dielectric layer.

[0107]

[0114] Example 31 comprises the method of Example 30, further comprising removing the support layer after applying a resin to at least partially encapsulate the passive electronic components and before bonding the second build-up layer to the central core dielectric layer.

[0108]

[0115] Example 32 comprises the method of Example 30 or Example 31, wherein a resin for at least partially encapsulating the passive electronic components and a resin for forming the first build-up layer are applied simultaneously.

[0109]

[0116] Example 33 comprises any of the methods of Examples 30 to 32, wherein bonding the second build-up layer to the central core dielectric layer includes applying a resin to the surface of the central core dielectric layer and curing the resin to form the second build-up layer.

[0110]

[0117] According to Example 34, the method includes providing a core containing a passive electronic component embedded therein; forming an upper stacked stack coupled to the core, wherein the upper stacked stack includes a set of contact pads configured to electrically connect a die to the passive electronic component via a conductive path defined by one or more upper metal layers of the upper stacked stack; and forming a lower stacked stack coupled to the core, wherein the lower stacked stack includes a set of lower metal layers, the metal layer closest to the core among the set of lower metal layers including one or more traces that pass through the shadow of the passive electronic component.

[0111]

[0118] Example 35 comprises the method of Example 34, further comprising electrically connecting the PDN of the die to a set of contact pads to provide a conductive path between the PDN and the passive electronic components.

[0112]

[0119] Example 36 comprises the method of Example 34 or Example 35, further comprising forming a set of BGA contacts electrically connected to a set of lower metal layers on the bottom surface of the lower stacked stack, wherein at least one of the BGA contacts is at least partially positioned in the shadow of the passive electronic components.

[0113]

[0120] Example 37 comprises any method of Examples 34 to 36, wherein providing a core includes forming an opening in a central core dielectric layer, positioning a passive electronic component within the opening so as to be supported by a support layer, applying a resin to at least partially encapsulate the passive electronic component within the opening, applying a resin to form a first build-up layer on the central core dielectric layer, and bonding a second build-up layer to the central core dielectric layer, wherein the first build-up layer corresponds to a lower core dielectric layer or an upper core dielectric layer, and the second build-up layer corresponds to the other of the lower core dielectric layer or the upper core dielectric layer.

[0114]

[0121] Example 38 comprises the method of Example 37, further comprising removing the support layer after applying a resin to at least partially encapsulate the passive electronic components and before bonding the second build-up layer to the central core dielectric layer, in order to provide the core.

[0115]

[0122] Example 39 comprises any of the methods of Examples 37 to 38, wherein a resin for at least partially encapsulating the passive electronic components and a resin for forming a first build-up layer are applied simultaneously.

[0116]

[0123] Example 40 comprises any of the methods of Examples 37 to 39, wherein bonding the second build-up layer to the central core dielectric layer includes applying a resin to the surface of the central core dielectric layer and curing the resin to form the second build-up layer.

[0117]

[0124] Example 41 comprises any method of Examples 37 to 40, further comprising: forming a first opening extending through an upper core dielectric layer, a central core dielectric layer, and a lower core dielectric layer before forming an upper stacked stack; forming a second opening through the upper core dielectric layer to expose contacts of passive electronic components; forming a first conductive via within the first opening and a second conductive via within the second opening, wherein one or more first traces of the upper metal layer set are electrically connected to the first conductive via and one or more second traces of the upper metal layer set are electrically connected to the second conductive via.

[0118]

[0125] Example 42 comprises the method of Example 41, wherein one or more traces passing through the shadow of the passive electronic component are electrically connected to the first conductive via.

[0119]

[0126] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the claims. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. It is the core, The upper core dielectric layer, Lower core dielectric layer, A central core dielectric layer that is in direct contact with the bottom surface of the upper core dielectric layer and in direct contact with the top surface of the lower core dielectric layer, A passive electronic component embedded in the central core dielectric layer, Including the core, An upper stacked stack bonded to the upper surface of the upper core dielectric layer, The set of upper metal layers, A set of contact pads configured to electrically connect the die to the passive electronic components via a conductive path defined by the set of upper metal layers, A top stacking stack including, A lower stacked stack coupled to the bottom surface of the lower core dielectric layer, A set of lower metal layers including a first lower metal layer that is in direct contact with the bottom surface of the lower core dielectric layer, A set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers, A lower stacked stack including, A device equipped with the following features.

2. The device according to claim 1, wherein the upper stacked stack further comprises a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers.

3. The device according to claim 1, wherein the set of upper metal layers includes a first upper metal layer that is in direct contact with the upper surface of the upper core dielectric layer.

4. The device according to claim 1, wherein the set of lower metal layers includes a first lower metal layer that is in direct contact with the bottom surface of the lower core dielectric layer.

5. The device according to claim 1, wherein the metal layer closest to the core among the set of lower metal layers includes one or more traces that pass through the shadow of the passive electronic component.

6. The device according to claim 1, wherein the passive electronic component includes an integrated capacitor device.

7. The device according to claim 1, further comprising the die, wherein the power distribution network of the die is coupled to the passive electronic component via the set of contact pads and the conductive path defined by the set of upper metal layers.

8. The device according to claim 7, further comprising one or more additional components electrically connected to the die via the conductive path defined by the set of upper metal layers.

9. The device according to claim 1, further comprising a plurality of conductive vias extending through the core and electrically interconnecting the set of upper metal layers and the set of lower metal layers.

10. The device according to claim 1, further comprising a set of ball grid array (BGA) contacts located on the bottom surface of the lower stacked stack and configured to electrically connect the device to another device or substrate, wherein at least one of the BGA contacts is at least partially positioned in the shadow of the passive electronic component.

11. A core containing passive electronic components embedded inside, An upper stacked stack comprising a set of contact pads bonded to the core and configured to electrically connect the die to the passive electronic components via conductive paths defined by one or more upper metal layers of the upper stacked stack, A lower stacked stack bonded to the core, comprising a set of lower metal layers, wherein the metal layer closest to the core in the set of lower metal layers comprises one or more traces passing through the shadow of the passive electronic component, A device equipped with the following features.

12. The device according to claim 11, wherein the upper stacked stack further comprises a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers.

13. The device according to claim 11, wherein the set of upper metal layers includes a first upper metal layer that is in direct contact with the upper surface of the upper core dielectric layer of the core.

14. The device according to claim 11, wherein the metal layer closest to the core among the set of lower metal layers is in contact with the bottom surface of the lower core dielectric layer of the core.

15. The device according to claim 11, wherein the passive electronic component includes a capacitor device.

16. The device according to claim 11, further comprising the die, wherein the power distribution network of the die is coupled to the passive electronic component via the set of contact pads and the conductive path defined by the set of upper metal layers.

17. The device according to claim 11, further comprising one or more additional components electrically connected to the die via the conductive path defined by the set of upper metal layers.

18. The device according to claim 11, further comprising a plurality of conductive vias extending through the core and interconnecting the set of upper metal layers and the set of lower metal layers.

19. The device according to claim 11, further comprising a set of ball grid array (BGA) contacts located on the bottom surface of the lower stacked stack and configured to electrically connect the device to another device or substrate, wherein at least one of the BGA contacts is at least partially located within the shadow of the passive electronic component.

20. To provide a core comprising a central core dielectric layer in which passive electronic components are embedded, an upper core dielectric layer on the upper surface of the central core dielectric layer, and a lower core dielectric layer on the bottom surface of the central core dielectric layer, Forming an upper stacked stack on the upper surface of the upper core dielectric layer, wherein the upper stacked stack includes a set of upper metal layers and a set of contact pads configured to electrically connect the die to the passive electronic components via a conductive path defined by the set of upper metal layers. The lower stacked stack is formed on the bottom surface of the lower core dielectric layer, wherein the lower stacked stack includes a set of lower metal layers, each including a first lower metal layer that is in direct contact with the bottom surface of the lower core dielectric layer. Methods that include...

21. Before forming the upper stacked stack, To form a first opening that extends through the upper core dielectric layer, the central core dielectric layer, and the lower core dielectric layer, To form a second opening that extends through the upper core dielectric layer and exposes the contacts of the passive electronic components, A first conductive via is formed in the first opening, and a second conductive via is formed in the second opening, wherein one or more first traces of the set of upper metal layers are electrically connected to the first conductive via, and one or more second traces of the set of upper metal layers are electrically connected to the second conductive via. The method according to claim 20, further comprising:

22. The method according to claim 21, wherein one or more first traces of the set of lower metal layers are electrically connected to the first conductive via.

23. The method according to claim 22, wherein the one or more first traces of the set of lower metal layers include at least one trace that passes through the shadow of the passive electronic component.

24. The method according to claim 20, further comprising electrically connecting the power distribution network (PDN) of the die to the set of contact pads to provide a conductive path between the PDN and the passive electronic components.

25. The method according to claim 20, further comprising forming a set of ball grid array (BGA) contacts electrically connected to the set of lower metal layers on the bottom surface of the lower stacked stack, wherein at least one of the BGA contacts is at least partially located in the shadow of the passive electronic components.

26. To provide the aforementioned core, To form an opening in the central core dielectric layer, Position the passive electronic component within the opening so that it is supported by the support layer, The process involves applying a resin to at least partially encapsulate the passive electronic components within the opening, and applying a resin to form a first build-up layer on the central core dielectric layer. A second build-up layer is bonded to the central core dielectric layer, wherein the first build-up layer corresponds to the lower core dielectric layer or the upper core dielectric layer, and the second build-up layer corresponds to the other of the lower core dielectric layer or the upper core dielectric layer. The method according to claim 20, including the method described in claim 20.

27. The method according to claim 26, further comprising providing the core by removing the support layer after applying the resin to at least partially encapsulate the passive electronic components and before bonding the second build-up layer to the central core dielectric layer.

28. The method according to claim 26, wherein the resin for at least partially encapsulating the passive electronic components and the resin for forming the first build-up layer are applied simultaneously.

29. Bonding the second build-up layer to the central core dielectric layer is The resin is applied to the surface of the central core dielectric layer, The resin is cured to form the second build-up layer, The method according to claim 26, including the method described in claim 26.

30. To provide a core that includes passive electronic components embedded inside, Forming an upper stack bonded to the core, wherein the upper stack includes a set of contact pads configured to electrically connect the die to the passive electronic component via conductive paths defined by one or more upper metal layers of the upper stack. Forming a lower stacked stack bonded to the core, wherein the lower stacked stack includes a set of lower metal layers, and the metal layer closest to the core in the set of lower metal layers includes one or more traces that pass through the shadow of the passive electronic component. Methods that include...

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