Etching selectivity adjustment by fluorocarbon treatment

Abstract

A method for fabricating a field-effect transistor (FET) on a substrate, comprising growing a p-type doped semiconductor from silicon nanosheets on the substrate, wherein the substrate comprises a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack comprising a trench exposing the sidewall of the layer stack, the p-type doped semiconductor and the sacrificial layer being separated by an inner dielectric spacer, the dummy gate being removed, and the sacrificial layer being selectively etched with respect to the p-type doped semiconductor, wherein the etching comprises exposing the substrate to a process gas comprising a fluorocarbon and a fluorine-containing etching gas in the absence of plasma.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority and the benefit of the filing date of U.S. Nonprovisional Patent Application No. 18 / 453,843, filed on 22 August 2023, which is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to a method for processing a substrate, and in specific embodiments, to the adjustment of etching selectivity by fluorocarbon treatment. [Background technology]

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are fabricated by sequentially depositing layers of dielectric, conductive, and semiconductor materials onto a substrate, and then patterning them to form a network of integrated electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal wires, contacts, and vias) in a monolithic structure. Many of the processing steps used to form the constituent structures of semiconductor devices are carried out using various deposition and etching techniques, such as plasma processes.

[0004] The semiconductor industry has repeatedly reduced the minimum feature size of semiconductor devices to a few nanometers in order to increase the integration density of components. Accordingly, the semiconductor industry is increasingly demanding processing technologies that provide processes for patterning features at dimensions often at the atomic scale, with accuracy, precision, and profile control. These requirements are particularly stringent for three-dimensional (3D) structures, such as fin field-effect transistors (FinFETs), gate-all-around FETs (GAAFETs), and multilayer FETs. Meeting this challenge, along with the uniformity and reproducibility required for mass production of ICs, necessitates further innovation in material processing technologies. [Overview of the Initiative] [Means for solving the problem]

[0005] According to one embodiment of the present invention, a method for fabricating a field-effect transistor (FET) on a substrate, comprising growing a p-type doped semiconductor from silicon nanosheets on the substrate, wherein the substrate comprises a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack comprising a trench exposing the sidewall of the layer stack, the p-type doped semiconductor and the sacrificial layer being separated by an inner dielectric spacer, the dummy gate being removed, and the sacrificial layer being selectively etched with respect to the p-type doped semiconductor, wherein the etching comprises exposing the substrate to a process gas comprising a fluorocarbon and a fluorine-containing etching gas in the absence of plasma.

[0006] According to one embodiment of the present invention, a method for fabricating a field-effect transistor (FET) on a substrate, comprising growing a p-type doped semiconductor from silicon nanosheets on the substrate, wherein the substrate comprises a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack comprises a trench exposing the sidewall of the layer stack, the p-type doped semiconductor and the sacrificial layer are separated by an inner spacer, the sacrificial layer comprises a surface oxide, the dummy gate is removed, the surface oxide is removed, the substrate is exposed to a pretreatment gas containing fluorocarbons in the absence of plasma to passivate the p-type doped semiconductor, a portion of the pretreatment gas penetrating the inner spacer, and the substrate is exposed to an etching gas containing fluorine in the absence of plasma to selectively etch the sacrificial layer with respect to the p-type doped semiconductor.

[0007] According to one embodiment of the present invention, a method for processing a substrate, the method comprising selectively etching undoped silicon germanium (SiGe) of the substrate with respect to doped SiGe of the substrate in the absence of plasma, wherein the etching method comprises exposing the substrate to a pretreatment gas containing C2F6 or C4F8, and exposing the substrate to an etching gas containing HF and F2.

[0008] To better understand the present invention and its advantages, please refer to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1A-1B] Figure 1A shows an exemplary cross-sectional view of a substrate for a p-channel field-effect transistor (pFET) that has suffered source and drain damage due to a conventional channel release process. Figure 1B shows the substrate before the conventional channel release process. [Figure 2A-2F] Figure 2A shows an exemplary cross-sectional view of a substrate during an exemplary process of pFET fabrication, including a plasmaless etching process at various stages according to various embodiments. Figure 2A shows an input substrate with two dummy gate structures having a nanosheet and sacrificial layer understack; Figure 2B shows another cross-sectional view perpendicular to Figure 2A; Figure 2C shows the substrate after source and drain (S / D) formation; Figure 2D shows the substrate after dummy gate removal; Figure 2E shows the substrate after a plasmaless etching process for channel release; and Figure 2F shows the substrate after high-k metal gate (HKMG) formation. [Figure 3A-3B] Figure 3B shows a cross-sectional view of another exemplary substrate during the exemplary fabrication process of a complementary FET (CFET) having a stack structure of n-channel FETs (nFETs) and pFETs according to an alternative embodiment. Figure 3A shows an input substrate having a stack structure with two types of FETs, and Figure 3B shows the substrate after a plasmaless etching process for channel release. [Figure 4] This embodiment demonstrates the effect of fluorocarbon pretreatment on the etching rates of undoped silicon germanium (SiGe) and boron-doped SiGe during plasmaless etching. [Figures 5A-5C] Process flowcharts of plasmaless etching methods according to various embodiments are shown. Figure 5A shows the process flow of one embodiment, Figure 5B shows the process flow of an alternative embodiment, and Figure 5C shows the process flow of another alternative embodiment. [Modes for carrying out the invention]

[0010] This application relates to a method for processing a substrate, and more specifically, to adjusting etching selectivity by fluorocarbon treatment. Generally, in order to fabricate complex structures for advanced semiconductor devices, such as gate-all-around field-effect transistors (GAAFETs) and multilayer FETs, it may be necessary to remove material laterally to selectively expose a portion of the underlying structure. However, due to the small size of the fabricated features and the complexity of the design, it may be difficult to achieve sufficient etching selectivity with certain processes.

[0011] One example of such a challenging etching process is the channel release process of nanosheet / nanowire p-channel FETs (pFETs), where insufficient etching selectivity can cause serious damage to the source / drain (S / D) region. Generally, as shown in Figure 1A, a layer stack of silicon (Si) nanosheets 110 and a sacrificial layer 120 can be formed to provide multiple Si nanosheet / nanowire channels, from which S / D material 130 can be epitaxially grown from the tip of the Si nanosheet / nanowire. Typically, the S / D material 130 may contain boron-doped silicon germanium (B-doped SiGe), and the sacrificial layer 120 may contain undoped SiGe. During the channel release process, the sacrificial layer 120 needs to be removed by dry etching. To protect the S / D material 130 during the channel release process, an inner spacer 140 can be used to separate the sacrificial layer 120 from the S / D material 130. However, as indicated by the arrows in Figure 1B, etching gases used in conventional channel release processes can penetrate the inner spacer 140 and reach and damage the S / D material 130. While the inner spacer 140 may have chemical resistance to etching gases and, in principle, could provide etching selectivity, to minimize parasitic capacitance caused by the inner spacer 140, it is usually miniaturized to a thin thickness and made porous to lower its dielectric constant, so penetration by etching gases may be unavoidable. Therefore, a new etching method that enables etching selectivity between undoped semiconductors (e.g., SiGe) and doped semiconductors (e.g., B-doped SiGe) may be desirable.

[0012] This disclosure proposes a plasmaless etching method enhanced with fluorocarbon pretreatment to enable such etching selectivity. In various embodiments, undoped SiGe can be selectively etched against B-doped SiGe in the absence of plasma. The inventors of this application propose that etching selectivity is enhanced with fluorocarbons (e.g., C2F6, C4F8, or C2F6). x F yIt has been demonstrated that this can be made possible by processing in ). Plasmaless etching of undoped semiconductors can be performed using fluorine-containing etching gases such as HF, F2, ClF3, or mixtures thereof. Fluorocarbon treatment may be performed as a pretreatment before the etching step, or it may be integrated as a single etching process step. Plasmaless etching methods can be applied, for example, as a channel release process in pFET fabrication, which can favorably mitigate the source / drain (S / D) damage problem despite penetrating the inner spacer, thereby improving device yield. The etching process may be part of the fabrication process for emerging multilayer FETs such as gate-all-around field-effect transistors (GAAFETs) or complementary FETs (CFETs).

[0013] The following describes steps for pFET fabrication, including plasmaless etching using fluorocarbon treatment, according to various embodiments, with reference to Figures 2A to 2F. As an example, the fabrication of a pFET for a nanosheet / nanowire gate all-around FET (GAAFET) device is shown in Figures 2A to 2F. Another example is also described according to another embodiment of a multilayer FET structure, with reference to Figures 3A to 3B. Exemplary etching rates of undoped SiGe and B-doped SiGe during plasmaless etching according to one embodiment are plotted in Figure 4. Exemplary process flow diagrams are shown in Figures 5A to 5C. All figures in this disclosure are for illustrative purposes only and are not to scale, including the aspect ratio of features. While this disclosure primarily describes embodiments of a channel release process that selectively removes SiGe from the source / drain (S / D) region of B-doped SiGe in GAAFET and multilayer FET applications, the plasmaless etching method using fluorocarbon treatment can also be applied to various other applications where fluorocarbon treatment can induce etching selectivity between undoped and doped semiconductors.

[0014] 2A to 2F are cross-sectional views of an exemplary substrate during an exemplary process for fabricating a pFET that includes a plasmaless etching process at various stages in accordance with various embodiments.

[0015] Figure 2A is a cross-sectional view of an input substrate 200 provided with two dummy gate structures having a lower stack of nanosheets and sacrificial layers, and Figure 2B is another cross-sectional view perpendicular to that shown in Figure 2A.

[0016] In Figure 2A, the semiconductor structure may have undergone several processing steps, for example, following conventional processes. For example, the semiconductor structure may comprise a substrate 200 on which various device regions are formed. At this stage, the substrate 200 may include isolation regions such as shallow trench isolation (STI) regions and other regions formed therein.

[0017] The substrate 200 may comprise a semiconductor substrate in various embodiments. In one or more embodiments, the substrate 200 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 200 may comprise a germanium wafer, a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate 200 comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well as a silicon layer on a silicon or SOI substrate.

[0018] In various embodiments, the substrate 200 shown in Figures 2A to 2B may be in an intermediate stage of fabricating a pFET device. For example, fabrication processes that may have been already performed include, but are not limited to, nanosheet layer stack formation, dummy gate formation, one or more spacer formations, source / drain fin etch-back, lateral recess etching, inner spacer formation, and another etch-back.

[0019] As further shown in Figure 2A, the substrate 200 may comprise a plurality of nanosheet layers or nanosheets 210 formed therein. Specifically, the nanosheets 210 are embedded in different materials. The nanosheets 210 may be separated from each other by one of a plurality of sacrificial layers or sacrificial layers 220. Thus, the substrate 200 comprises alternating layers of sacrificial layers 220 and nanosheets 210. Although three layers of nanosheets 210 are depicted in Figure 2A, the number of layers is not limited. In various embodiments, the nanosheets 210 can form a transistor channel at the end of fabrication, while the sacrificial layers 220 are removed in a later step of fabrication (e.g., channel release in Figure 2E) to release void space for the formation of a gate dielectric (e.g., a high-k dielectric material) and gate terminal. As mentioned above, removing the sacrificial layers 220 by conventional methods can result in damage to the source / drain (S / D) region, which can be advantageously overcome by various embodiments of the plasmaless etching process.

[0020] In various embodiments, the nanosheet 210 has a thickness of several nanometers to tens of nanometers, for example, about 1 nm to about 20 nm in one embodiment. In another embodiment, the nanosheet 210 has a thickness of about 1 nm to about 10 nm in one embodiment.

[0021] In various embodiments, the sacrificial layer 220 contains silicon germanium (SiGe), and the nanosheet 210 contains silicon (Si). In certain embodiments, the stacks of nanosheet 210 and sacrificial layer 220 may be formed by a deposition process, for example, epitaxially by chemical vapor deposition (CVD). In one or more embodiments, the SiGe for the sacrificial layer 220 may have a Ge concentration between 5% and 30%. In various embodiments, each layer of the sacrificial layer 220 and nanosheet 210 may have a thickness of 2, 3 nanometers to several nanometers. In one embodiment, each layer of the sacrificial layer 220 may have a thickness of 5 nm to 20 nm, and each layer of the nanosheet 210 may have a thickness of 1 nm to 10 nm.

[0022] As further shown in Figure 2A, the substrate 200 may comprise a dielectric blocking layer 245 on top of an alternating layer stack of nanosheets 210 and a sacrificial layer 220. In one embodiment, the dielectric blocking layer 245 may be an oxide layer. The dielectric blocking layer 245 may be formed by a deposition process, for example, by CVD. The dielectric blocking layer 245 may be used as an etch stop layer, or this may be optional.

[0023] The substrate 200 may further comprise a dummy gate 250 on top of a stack of nanosheets 210 and a sacrificial layer 220. Figure 2A shows, as an example, the features of two fins for the dummy gate 250. The dummy gate 250 may include, for example, polysilicon or amorphous silicon. The layer forming the dummy gate 250 can be deposited using deposition techniques such as chemical vapor deposition (CVD), vapor deposition including physical vapor deposition (PVD), and other plasma processes such as plasma-enhanced CVD (PECVD), sputtering, and other processes. The layer can then be patterned using photolithography and etching processes to form the dummy gate 250. The dummy gate 250 may have a thickness of about 50 nm to about 500 nm in various embodiments.

[0024] Continuing to refer to Figure 2A, there may be a hard mask 260 used to pattern the dummy gate 250. In one embodiment, the hard mask 260 may contain silicon oxide. In various embodiments, the hard mask 260 may contain silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). In an alternative embodiment, the hard mask 260 may contain titanium nitride. Furthermore, although not specifically shown, the first hard mask 260 may be a laminated hard mask comprising, for example, two or more layers using two different materials. The first hard mask of the hard mask 260 may contain a metallic layer such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds, and the second hard mask material of the hard mask 260 may contain a dielectric layer such as SiO2, silicon nitride, SiCN, SiOC, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon. The hard mask 260 can be deposited using deposition techniques such as chemical vapor deposition (CVD), vapor deposition including physical vapor deposition (PVD), and other plasma processes such as plasma-enhanced CVD (PECVD), sputtering, and other processes. In various embodiments, the hard mask 260 may have a thickness of about 5 nm to about 50 nm.

[0025] Furthermore, in Figure 2A, the outer spacer 270 may be formed to cover the sidewalls of the dummy gate 250. In various embodiments, the outer spacer 270 may include a dielectric material containing oxides or nitrides. In certain embodiments, the outer spacer 270 may include silicon-containing dielectric materials such as silicon oxide, silicon oxynitride (SiON), silicon oxycarbonite (SiOCN), and silicon boron carbonite (SiBCN). The outer spacer 270 can be deposited on the dummy gate 250 before fin etch-back using deposition techniques such as chemical vapor deposition (CVD), vapor deposition including physical vapor deposition (PVD), and other plasma processes such as plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), sputtering, and other processes. In various embodiments, the outer spacer 270 may have a thickness of about 1 nm to about 10 nm. In certain embodiments, the outer spacer 270 may be a laminated layer comprising, for example, two or more layers using two different materials.

[0026] In one or more embodiments, the fin height may be between 200 nm and 250 nm, and the distance between two fins may be between 6 nm and 12 nm. This high aspect ratio makes it difficult to fully etch the target material from the trench while preventing any damage to other materials.

[0027] In various embodiments, an inner spacer 240 is formed to cover the recessed sidewalls of the sacrificial layer 220. The inner spacer 240 ensures electrical insulation between the gate region and the source / drain (S / D) region, which will be formed in later steps in the fabrication process. The inner spacer 240 may be formed by first selectively etching the sacrificial layer 220 laterally against the nanosheet 210 to deposit a layer of inner spacer material, and then etching back so that only the tips of the nanosheet 210 are exposed, with the remaining portion of the inner spacer material covering the sacrificial layer 220 between the tips, as shown in Figure 2A.

[0028] In certain embodiments, the inner spacer 240 may include silicon-containing dielectric materials such as silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiBCN). In one embodiment, the inner spacer 240 may include a low-k dielectric material. The deposition of the inner spacer material can be carried out by deposition from the gas phase using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other deposition processes. In the plasma deposition process, precursor gas mixtures including but not limited to silanes, hydrocarbons, fluorocarbons, or nitrogen-containing compounds can be used in combination with one or more diluent gases (e.g., argon, nitrogen, etc.) under various pressure, power, flow rate, and temperature conditions.

[0029] In various embodiments, the material for the inner spacer 270 may be selected to provide etching selectivity for the S / D material formed in a subsequent step (e.g., Figure 2C). On the other hand, to minimize parasitic capacitance, the inner spacer 240 can be thin and porous. In one embodiment, the inner spacer 240 may have a thickness of 3 nm to 10 nm.

[0030] Figure 2B is a cross-sectional view along the cross-section represented by the dotted line 2b in Figure 2A. Conversely, Figure 2A shows a cross-sectional view along the cross-section 2a in Figure 2B. In Figure 2B, isolation regions such as the shallow trench isolation (STI) region 295 are visible, which are not visible in Figure 2A and the following Figures 2C to 2F, which share the same cross-section as Figure 2A. The STI region 295 serves to electrically isolate adjacent electronic components.

[0031] Furthermore, in Figure 2B, the tips of the nanosheet 210, dielectric blocking layer 245, and inner spacer 240 are exposed and visible in the source / drain (S / D) region, but the sacrificial layer 220 is masked by the inner spacer 240 and is not visible. The dummy gate 250 is also visible only in Figure 2A and is masked by the outer spacer 270.

[0032] Figure 2C shows a cross-sectional view of the substrate 200 after source and drain (S / D) formation.

[0033] In various embodiments, the source / drain (S / D) region may be formed of S / D material 230. The S / D material 230 fills the lateral recesses and portion of the fin features on the exposed tip of the nanosheet 210. The formation of the S / D region can be carried out, for example, by epitaxial growth. In certain embodiments, the S / D region formed by the epitaxial growth process may include a faceted outer surface. In various embodiments, the pFET can be fabricated using the substrate 200, and therefore the S / D material 230 may include a p-type semiconductor, such as boron-doped silicon germanium (B-doped SiGe). In certain embodiments, the dopant concentration in the S / D material 230 is 1 to 5 × 10⁻¹⁶. 20 / cm 3 This is possible. In one or more embodiments, the B-doped SiGe for the S / D material 230 may have a Ge concentration between 30% and 70%. In various embodiments, the Ge concentration in the S / D material 230 may be higher than the Ge concentration in the sacrificial layer 220.

[0034] In certain embodiments, although not specifically shown, the substrate 200 may further comprise one or more nFET structures adjacent to the pFET structures shown in Figures 2A to 2F. In the case of nFET structures, the substrate 200 may also comprise similar fin and dummy gate structures, where n semiconductors (e.g., phosphorus-doped silicon) can be epitaxially grown from the tips of nanosheets.

[0035] Figure 2D shows a cross-sectional view of substrate 200 after the dummy gate has been removed.

[0036] After S / D formation, the dummy gate 250 can be removed along with the rest of the hard mask 260. In certain embodiments, dummy gate pulling can be performed using a plasma etching process such as reactive ion etching (RIE) or other etching processes.

[0037] In certain embodiments, an oxide removal process may be optionally performed after the dummy gate pull (Figure 2D) and before subsequent steps in the plasmaless etching process (Figure 2E) to remove any surface oxide layers that may be present on the sacrificial layer 220. For example, the oxide removal process may be a plasmaless process that includes exposing the substrate 200 to a process gas containing HF in the absence of plasma. In one embodiment, the process gas may contain 30% HF and 30% NH3 in a carrier gas (e.g., Ar), and the process temperature may be 35°C to 80°C. After the oxide removal process, a heat treatment may be performed, which includes heating the substrate 200 to a temperature of 100°C to 200°C under an inert gas flow.

[0038] Figure 2E shows a cross-sectional view of the substrate 200 after a plasmaless etching process for channel release.

[0039] In various embodiments, a plasmaless etching process for channel release may be a two-step process comprising a fluorocarbon pretreatment step and an etching step. Both steps may be advantageously performed in the absence of plasma. The fluorocarbon pretreatment may include exposing the substrate 200 to a pretreatment gas containing fluorocarbons to passivate the S / D material 230 (e.g., B-doped SiGe), and the etching step may include exposing the substrate 200 to an etching gas containing fluorine to selectively etch the sacrificial layer 220 without damaging the S / D material 230.

[0040] In certain specific embodiments, the fluorocarbon for the pretreatment gas is C2F6, C4F8, or a compound of the general chemical formula C x F y . In another embodiment, the fluorocarbon may further comprise hydrogen (that is, hydrofluorocarbon of the general chemical formula C x H y F z ). In one or more embodiments, the process conditions for the fluorocarbon pretreatment step may be as follows: chamber pressure: 750~2000 mT, substrate temperature: 0~50°C, and process gas: 5~25% C x F y in Ar. In one embodiment, the process time may be 30 seconds to 10 minutes. Without wishing to be bound by any theory, it is expected that a portion of the pretreatment gas will penetrate the inner spacer 240, passivate the interface between the inner spacer and the S / D material 230, and prevent etching during the etching step. Furthermore, in some cases, there may be some defects in the inner spacer 240 resulting from a preceding process step (e.g., reactive ion etching), which may allow the pretreatment gas to reach the exposed portion of the S / D material 230 without penetrating the inner spacer 240.

[0041] In the etching step, the etching gas may comprise HF, F2, ClF3, or a combination thereof. In one or more embodiments, the process conditions for the etching step may be as follows: chamber pressure: 50~800 mT, substrate temperature: 35~80°C, and process gas: 40% HF / 30% F2 / 5% ClF3 in Ar. In one embodiment, the process time may be 10 seconds to 120 seconds. In one embodiment, the etching step may be performed without exposing the substrate 200 to the pretreatment fluorocarbon or any other fluorocarbon. In another embodiment, the etching gas may further comprise a fluorocarbon.

[0042] In various embodiments, post-etching heat treatment may be performed after the etching step by heating the substrate 200 to a temperature of 100°C to 200°C under a flow of inert gas.

[0043] In other embodiments, the fluorocarbon treatment may be integrated into the etching step, or the plasmaless etching process may be performed as a single continuous process. In these embodiments, the process gas for the plasmaless etching process is a fluorocarbon (e.g., C x F y The process may include both a fluorine-containing etching gas (e.g., HF, F2, and ClF3). In one or more embodiments, the process conditions may be as follows: Chamber pressure: 250-800 mT, Substrate temperature: 35-50°C, and Process gas: 25% C x F y , 40%HF, 30%F2, and 5%ClF3. In one embodiment, the process time may be 30 seconds to 10 minutes. By combining the two steps of the preceding embodiment, a single continuous process may advantageously have a shorter total process time to achieve the same etching performance. On the other hand, the two-step embodiment may be more flexible in fine-tuning process conditions and can ensure passivation of the protected surface.

[0044] Furthermore, in alternative embodiments, the passivation fluorocarbon can be flowed intermittently rather than at a constant flow rate during a single continuous plasmaless etching process. For example, a gas pulsed scheme may be applied. In one embodiment, the etching step can be started and progressed in the initial stage of removing the sacrificial layer 220, and as the etching nears the end of the process with the inner spacer 240 exposed, fluorocarbon can be flowed as an additional process gas component.

[0045] As shown by the dotted circle in Figure 2E, the sacrificial layer 220 (e.g., undoped SiGe) can be removed by a plasmaless etching process without damaging the S / D material 230 (e.g., B-doped SiGe), thus overcoming the aforementioned problem (see Figure 1B).

[0046] Figure 2F shows a cross-sectional view of the substrate 200 after the formation of a high-k metal gate (HKMG).

[0047] Channel release by a plasmaless etching process (Figure 2E) can free the space occupied by the sacrificial layer 220, and this generated void space can be filled with a gate dielectric (e.g., a high-k dielectric material) and gate terminal through HKMG formation. First, a high-k dielectric (HK) layer 285 can be deposited. In various embodiments, the HK layer 285 is HfO2 or Hf x Si y O z N w The HK layer 285 can be deposited using appropriate deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and other plasma processes such as plasma-enhanced CVD (PECVD), sputtering, and other processes. In certain embodiments, an optional insulating layer, such as a silicon oxide layer, may be formed beneath the HK layer 285.

[0048] HKMG formation can be completed by depositing a replacement metal gate (RMG) material 290 on top of the HK layer 285 to fill the remaining void spaces. In various embodiments, the RMG material 290 may include a combination of multiple layers containing a work function metal and metal fillers. The work function metal of the RMG material may include titanium nitride, tantalum nitride, or metal alloys, such as AlC, TiAl, and TiAlC. Metal deposition continues until the remaining voids are filled with excess metal filler material. In some embodiments, the metal filler material may include low-resistance metals, such as tungsten (W), copper (Cu), cobalt (Co), or aluminum (Al). In some embodiments, the RMG material 290 can be deposited using a highly conformal process such as atomic layer deposition (ALD). After the deposition step, excess metal can be removed by a planarization process such as chemical mechanical planarization (CMP). Subsequently, a middle-of-line (MOL) / back-end-of-line (BEOL) process can be performed.

[0049] Figures 3A and 3B show cross-sectional views of another exemplary substrate during the exemplary fabrication process of a complementary FET (CFET) having a stacked structure of n-channel FETs (nFETs) and pFETs according to an alternative embodiment. Figure 3A shows a cross-sectional view of an input substrate 300 having a stacked structure with two types of FETs. Some details of the layer stack structure on substrate 300 may be identical to those described above with reference to Figures 2A to 2F, and therefore will not be repeated.

[0050] In various embodiments, the CFET design allows one FET structure (e.g., pFET) to be stacked on top of another FET structure (e.g., nFET). Similar to the substrate 200 in Figure 2A, the substrate 300 may have already undergone nanosheet layer stacking (e.g., nanosheet 310 and sacrificial layer 320), dummy gate formation, one or more spacer formation, source / drain (S / D) fin etch-back, lateral recess etching, inner spacer formation (e.g., inner spacer 340), another etch-back, and S / D formation. In various embodiments, the nanosheet 310 may contain silicon (Si), the sacrificial layer 320 may contain undoped silicon germanium (undoped SiGe), and the inner spacer 340 may contain silicon-containing dielectric material.

[0051] In Figure 3A, S / D formation can be performed to epitaxially grow a first S / D material 330 and a second S / D material 332 from the tip of a nanosheet 310. In certain embodiments, the first S / D material 330 may contain phosphorus-doped silicon (P-doped Si) for an nFET device, and the second S / D material 332 may contain boron-doped silicon germanium (B-doped SiGe) for a pFET device. Channel release can then be performed (Figure 3B) to remove the sacrificial layer 320 and release void space for both FET device structures.

[0052] Figure 3B shows a cross-sectional view of the substrate 300 after the plasmaless etching process for channel release.

[0053] The plasmaless etching process method of this disclosure can be applied in CFET fabrication as a channel release process, as shown in Figure 3B. Details of the process in various embodiments have been described in the preceding embodiments with reference to Figures 2D to 2E and will not be repeated. As shown by the dotted circle in Figure 3B for the pFET device structure, the sacrificial layer 320 (e.g., undoped SiGe) can be removed by the plasmaless etching process without damaging the second S / D material 332 (e.g., B-doped SiGe). Damage to the first S / D material 330 (e.g., P-doped Si) is not usually caused because the first S / D material 330 may have distinctly different material properties, thanks to the inherent etching selectivity of the plasmaless etching process.

[0054] As described above with reference to Figures 2A-2F and 3A-3B, a plasmaless etching process can be used to selectively remove SiGe in GAAFET and multilayer FET applications. In various embodiments, this method can overcome the penetration problem where etching gas penetrates the inner spacer and damages the source / drain (S / D) region of B-doped SiGe. However, this method does not require the inner spacer or dopant blocking the B-doped SiGe to be specifically boron and can be applied to other applications. For example, this method can be applied even when the surface of the B-doped SiGe is exposed and not covered by an inner spacer or any layer. Furthermore, a plasmaless fluorocarbon treatment can also be applied to generally induce etching selectivity between undoped and doped semiconductors.

[0055] Figure 4 shows the effect of fluorocarbon pretreatment on the etching rates of undoped silicon germanium (SiGe) and boron-doped SiGe (B-doped SiGe) during plasmaless etching according to one embodiment.

[0056] The inventors of this application have demonstrated through experiments that fluorocarbon pretreatment can enable etching selectivity between undoped and doped semiconductors. A plasmaless etching process was tested on two substrates, undoped SiGe and B-doped SiGe, with and without fluorocarbon pretreatment with C2F6. The etching process was performed by exposing the substrates to an etching gas containing HF, F2, and ClF3 in Ar in the absence of plasma. Three different Ge concentrations in the SiGe substrates were investigated. As shown in Figure 4, without fluorocarbon pretreatment, SiGe (solid line) and B-doped SiGe (dotted line) exhibit equivalent etching rates at both Ge concentrations. At higher Ge concentrations, the etching rate of B-doped SiGe is slightly higher. Equivalent or higher etching rates for B-doped SiGe are undesirable, as described above (e.g., Figures 1A-1B). On the other hand, in fluorocarbon pretreatment, the etching rate of undoped SiGe (solid line) remained at almost the same level, while the etching rate of B-doped SiGe (dotted line) decreased significantly by about 30-40%. This trend was consistent for different Ge concentrations. Note that the Ge concentration can usually be higher in doped SiGe for S / D material than in undoped SiGe for sacrificial layers. The trend in Figure 4 demonstrates that a clear difference in etching rates can be achieved even between doped SiGe with higher Ge concentrations and undoped SiGe with lower Ge concentrations. The results demonstrate selective suppression of etching of B-doped SiGe, which allows for advantageous etching selectivity in plasmaless etching processes applicable to pFET fabrication.

[0057] Figures 5A to 5C show process flowcharts of plasmaless etching methods according to various embodiments. The process flow can be followed using the diagrams discussed above (for example, Figures 2C to 2E and Figures 3A to 3B), so it will not be explained again.

[0058] In Figure 5A, process flow 50 begins with growing a p-type doped semiconductor from silicon nanosheets on a substrate comprising a layer stack of alternating silicon nanosheets and a sacrificial layer, and also comprising a dummy gate formed on the layer stack, wherein the layer stack comprises trenches exposing the sidewalls of the layer stack, and the p-type doped semiconductor and the sacrificial layer are separated by dielectric inner spacers (block 510, Figure 2C). Subsequently, the dummy gate can be removed (block 520, Figure 2D), and then the sacrificial layer can be selectively etched with respect to the p-type doped semiconductor (block 530, Figure 2E). In various embodiments, etching is a plasmaless process comprising exposing the substrate to a process gas containing fluorocarbon and fluorine-containing etching gases in the absence of plasma.

[0059] In Figure 5B, another process flow 52 begins with growing a p-type doped semiconductor from silicon nanosheets on a substrate comprising a layer stack of alternating silicon nanosheets and a sacrificial layer, and also comprising a dummy gate formed on the layer stack, wherein the layer stack comprises trenches exposing the sidewalls of the layer stack, and the p-type doped semiconductor and the sacrificial layer are separated by an inner spacer, the sacrificial layer containing a surface oxide (block 512, Figure 2C). Subsequently, the dummy gate can be removed (block 520, Figure 2D), followed by the removal of the surface oxide (block 525). Next, the substrate can be exposed to a pretreatment gas containing fluorocarbons in the absence of plasma to passivate the p-type doped semiconductor, with some of the pretreatment gas penetrating the inner spacer (block 532), followed by the substrate being exposed to an etching gas containing fluorine in the absence of plasma to selectively etch the sacrificial layer relative to the p-type doped semiconductor (block 533, Figure 2E).

[0060] In Figure 5C, yet another process flow 54 is for selectively etching an undoped silicon germanium alloy (SiGe) substrate relative to a doped SiGe substrate in the absence of plasma (block 534). The etching process may include exposing the substrate to a pretreatment gas containing C2F6 or C4F8 (block 536) and exposing the substrate to an etching gas containing HF and F2 (block 537).

[0061] Exemplary embodiments of the present invention are described below. Other embodiments can be understood from the entirety of this specification and the claims filed herein. [Examples]

[0062] Example 1. A method for fabricating a field-effect transistor (FET) on a substrate, comprising growing a p-type doped semiconductor from silicon nanosheets on the substrate, wherein the substrate comprises a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack comprising a trench exposing the sidewall of the layer stack, the p-type doped semiconductor and the sacrificial layer being separated by an inner dielectric spacer, the dummy gate being removed, and the sacrificial layer being selectively etched with respect to the p-type doped semiconductor, wherein the etching comprises exposing the substrate to a process gas containing fluorocarbon and fluorine-containing etching gas in the absence of plasma.

[0063] Example 2. The method according to Example 1, further comprising performing an oxide removal process to remove surface oxides from the sacrificial layer before etching.

[0064] Example 3. The oxide removal process is the method according to Example 1 or 2, comprising exposing the substrate to a process gas containing HF in the absence of plasma and heating the substrate to a temperature of 100°C to 200°C under an inert gas flow.

[0065] Example 4. The method according to any one of Examples 1 to 3, further comprising heating the substrate to a temperature of 100°C to 200°C under a flow of inert gas after etching.

[0066] Example 5. The method according to any one of Examples 1 to 4, wherein the fluorocarbon is C2F6, C4F8, or hydrofluorocarbon.

[0067] Example 6. The fluorine-containing etching gas is the method according to any one of Examples 1 to 5, comprising HF, F2, or ClF3.

[0068] Example 7. The p-type doped semiconductor is a method according to any one of Examples 1 to 6, comprising a boron-doped silicon germanium alloy (B-doped SiGe).

[0069] Example 8. The sacrificial layer is a silicon germanium alloy (SiGe) as described in any one of Examples 1 to 7.

[0070] Example 9. The dielectric inner spacer is made of SiN, SiCN, SiOCN, or SiOC, as described in any one of Examples 1 to 8.

[0071] Example 10. The method according to any one of Examples 1 to 9, wherein the substrate further comprises another layer stack, the other layer stack comprises another silicon nanosheet and another sacrificial layer, the substrate further comprises an n-type semiconductor grown from the other silicon nanosheet, and etching also etches the other sacrificial layer.

[0072] Example 11. A method for fabricating a field-effect transistor (FET) on a substrate, comprising growing a p-type doped semiconductor from silicon nanosheets on the substrate, wherein the substrate comprises a layer stack of alternating silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack comprises a trench exposing the sidewall of the layer stack, the p-type doped semiconductor and the sacrificial layer are separated by an inner spacer, the sacrificial layer comprises a surface oxide, the dummy gate is removed, the surface oxide is removed, the substrate is exposed to a pretreatment gas containing fluorocarbons in the absence of plasma to passivate the p-type doped semiconductor, a portion of the pretreatment gas penetrating the inner spacer, and the substrate is exposed to an etching gas containing fluorine in the absence of plasma to selectively etch the sacrificial layer with respect to the p-type doped semiconductor.

[0073] Example 12. The method according to Example 11, further comprising heating the substrate to a temperature of 100°C to 200°C under an inert gas flow after exposure to an etching gas.

[0074] Example 13. The method according to Example 11 or 12, wherein exposure to the pretreatment gas is performed at a temperature of 0°C to 50°C, and exposure to the etching gas is performed at a temperature of 35°C to 80°C.

[0075] Example 14. The method according to any one of Examples 11-13, wherein exposure to etching gas is performed without exposing the substrate to fluorocarbon.

[0076] Example 15. The method according to any one of Examples 11 to 14, wherein the fluorocarbon is C2F6, C4F8, or hydrofluorocarbon, and the etching gas comprises HF, F2, or ClF3.

[0077] Example 16. The method according to any one of Examples 11 to 15, wherein the p-type doped semiconductor comprises a boron-doped silicon germanium alloy (B-doped SiGe), and the sacrificial layer comprises a silicon germanium alloy (SiGe).

[0078] Example 17. A method for processing a substrate, comprising selectively etching undoped silicon germanium (SiGe) of the substrate relative to doped SiGe of the substrate in the absence of plasma, wherein the etching comprises exposing the substrate to a pretreatment gas containing C2F6 or C4F8, and exposing the substrate to an etching gas containing HF and F2.

[0079] Example 18. The method of Example 17, further comprising fabricating a p-channel field-effect transistor (FET) using substrate-doped SiGe for the channel of the p-channel FET after etching.

[0080] Example 19. The method according to Example 17 or 18, further comprising, after etching, fabricating a stack of p-channel field-effect transistors (FETs) and n-channel FETs using substrate-doped SiGe for the channels of the p-channel FETs, wherein the etching includes channel release of the p-channel FETs and n-channel FETs.

[0081] Example 20. The etching gas further comprises ClF3, according to any one of Examples 17 to 19.

[0082] Example 21. The method according to any one of Examples 17-20, wherein the doped SiGe is boron-doped SiGe.

[0083] Example 22. The method according to any one of Examples 11-16, wherein the removal of surface oxides comprises exposing the substrate to another etching gas containing HF and NH3 in the absence of plasma.

[0084] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art through reference to this specification. Therefore, the appended claims are intended to encompass all such modifications or embodiments.

Claims

1. A method for manufacturing a field-effect transistor (FET) on a substrate, wherein the method is A step of growing a doped p-type semiconductor from silicon nanosheets on the substrate, wherein the substrate has a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack has trenches that expose the side walls of the layer stack, and the doped p-type semiconductor and the sacrificial layer are separated by dielectric inner spacers, The steps include removing the dummy gate, A step of selectively etching the sacrificial layer on the doped p-type semiconductor, comprising the step of exposing the substrate to a process gas containing fluorocarbon and fluorine-containing etching gas in the absence of plasma, A method having

2. The method according to claim 1, further comprising the step of performing an oxide removal process to remove surface oxides from the sacrificial layer before the etching step.

3. The oxide removal process described above is: The steps include: exposing the substrate to a process gas containing HF in the absence of plasma; The steps include heating the substrate to a temperature between 100°C and 200°C under an inert gas flow, The method according to claim 2, having the following characteristics.

4. The method according to claim 1, further comprising the step of heating the substrate to a temperature between 100°C and 200°C under an inert gas flow after the etching step.

5. The aforementioned fluorocarbon is C ２ F ６ , C ４ F ８ The method according to claim 1, wherein the material is a hydrofluorocarbon.

6. The fluorine-containing etching gas is HF, F ２ , or CLF ３ The method according to claim 1, including the method described in claim 1.

7. The method according to claim 1, wherein the doped p-type semiconductor includes a boron-doped silicon germanium alloy (B-doped SiGe).

8. The method according to claim 1, wherein the sacrificial layer comprises a silicon germanium alloy (SiGe).

9. The method according to claim 1, wherein the dielectric inner spacer includes SiN, SiCN, SiOCN, or SiOC.

10. The aforementioned substrate further has another layer stack, The aforementioned other layer stack has another silicon nanosheet and another sacrificial layer, The substrate further comprises an n-type semiconductor grown from the other silicon nanosheet. The method according to claim 1, wherein the etching step also etches the other sacrificial layer.

11. A method for manufacturing a field-effect transistor (FET) on a substrate, wherein the method is A step of growing a doped p-type semiconductor from silicon nanosheets on the substrate, wherein the substrate has a layer stack of alternating layers of silicon nanosheets and a sacrificial layer, and a dummy gate formed on the layer stack, the layer stack has trenches that expose the side walls of the layer stack, the doped p-type semiconductor and the sacrificial layer are separated by an inner spacer, and the sacrificial layer includes a surface oxide, The steps include removing the dummy gate, The step of removing the surface oxide, A step of exposing the substrate to a pretreatment gas containing fluorocarbons in the absence of plasma to passivate the doped p-type semiconductor, wherein a portion of the pretreatment gas penetrates the inner spacer. The steps include: exposing the substrate to a fluorine-containing etching gas in the absence of plasma to selectively etch the sacrificial layer from the doped p-type semiconductor; A method having

12. The method according to claim 11, further comprising the step of heating the substrate to a temperature between 100°C and 200°C under an inert gas flow after the step of exposure to the etching gas.

13. The step of exposure to the aforementioned pretreatment gas is carried out at a temperature between 0°C and 50°C. The method according to claim 11, wherein the step of exposure to the etching gas is carried out at a temperature between 35°C and 80°C.

14. The method according to claim 11, wherein the step of exposing the substrate to the etching gas is carried out without exposing the substrate to fluorocarbons.

15. The fluorocarbon is C ２ F ６ , C ４ F ８ or hydrofluorocarbon, and the etching gas comprises HF, F ２ or ClF ３ The method according to claim 11.

16. The method according to claim 11, wherein the doped p-type semiconductor comprises a boron-doped silicon germanium alloy (B-doped SiGe), and the sacrificial layer comprises a silicon germanium alloy (SiGe).

17. A method for processing a substrate, the method is The process includes a step of selectively etching the undoped silicon germanium (SiGe) of the substrate with respect to the doped SiGe of the substrate in the absence of plasma. The etching step described above is C ２ F ６ or C ４ F ８ The steps include: exposing the substrate to a pretreatment gas containing, HF and F ２ The steps include: exposing the substrate to an etching gas containing, A method having

18. The method according to claim 17, further comprising the step of manufacturing the p-channel field-effect transistor (FET) using the doped SiGe of the substrate for the channel of the p-channel field-effect transistor (FET) after the etching step.

19. Furthermore, after the etching step, the process includes a step of manufacturing a stack of p-channel field-effect transistors (FETs) and n-channel FETs using the doped SiGe of the substrate for the channels of the p-channel FETs. The method according to claim 17, wherein the etching step includes channel release of the p-channel FET and the n-channel FET.

20. The etching gas further contains ClF ３ The method according to claim 17, including the method described in claim 17.

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