Molded core substrate for embedding components

Abstract

Active and passive electronic components are placed on a substrate and sealed with molding material to create a molded core substrate for manufacturing hybrid integrated circuit (IC) devices. A carrier has a release film laminated on its surface. A copper seed layer is added on the release film, and a reference is plated onto the copper seed layer to position the component using alignment marks on the reference. The molding material is applied to the sealing layer and around and on top of the component. The molding material is ground coplanar with the top of the component. The carrier and release film are removed, exposing the copper seed layer, which is etched into a pattern. Holes are formed in the molding material and its surface is copper plated. A multilayer dielectric film is laminated on top of the copper plating. Vias are formed in the multilayer dielectric film for connection to the component.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit packaging of active and passive electronic components, and in particular to embedding components in a molded core substrate of an integrated circuit package. Background Art

[0002] A hybrid integrated circuit (Integrated Circuit, IC) device package can incorporate both active components such as transistors, oscillators, counters, resistors, memories, and integrated voltage regulators (Integrated Voltage Regulator, IVR), and passive components such as magnetic core inductors, deep trench capacitors, and other passive components into a single IC device package. The IC device package is composed of a substrate, wherein a central region of the substrate corresponds to component placement, and is a fiber-reinforced (FR4) core molded by various methods to provide electrical interconnection between the components embedded therein and external connections thereto. After the components are placed and connected, the FR4 core with the components connected therein can be encapsulated to manufacture a hybrid IC device package.

[0003] Electrical interconnection between components can be achieved through metal layers and traces, plated through holes (Plated Through Hole, PTH), and conductive vias. External connections may use contact pads exposed on an outer surface of the encapsulated substrate hybrid IC device package. Summary of Invention Means for Solving the Problems

[0004] In one example of the present disclosure, an integrated circuit (IC) molded core substrate includes a plurality of components having circuit connections on a first side and / or a second side thereof. A molding material surrounds the plurality of components, and a first surface and a second surface of the molding material are coplanar with the circuit connections. A copper pattern interconnects the circuit connections.

[0005] In one example of this disclosure, an integrated circuit (IC) includes a molded core substrate having a plurality of components having circuit connections on a first side and / or a second side. A molding material surrounds the plurality of components, and the first and second surfaces of the molding material are coplanar with the circuit connections. Copper patterns interconnect the circuit connections. An IC package includes an IC molded core substrate. External connections on the IC package are coupled to connections of the plurality of components within the molded core substrate.

[0006] In one example of this disclosure, a method for manufacturing an integrated circuit (IC) molded core substrate includes using a carrier panel. A release film is laminated onto one side of the carrier panel. A first copper seed layer is applied onto the release film. Electronic components are placed on the first copper seed layer. Molding material is applied around and on the electronic components. The molding material is cured. The molding material is ground coplanar with the top of the electronic components. The release film is removed from the first copper seed layer together with the carrier panel. The first copper seed layer is etched. Holes are formed in the cured molding material. A second copper seed layer is applied on the surface of the cured molding material and the formed holes. A copper blanket is applied on the second copper seed layer and in the formed holes. The formed holes are sealed to create plated through holes (PTHs). A portion of the copper blanket is removed, but the rest is left for the PTHs and component connection pads. A multilayer dielectric film is laminated on the PTHs and component connection pads. Vias are formed through the laminated multilayer dielectric film to the PTHs and component connection pads.

[0007] To allow for a more detailed understanding of the features of the present invention enumerated above, a more specific description of the invention, which has been concisely summarized above, can be made by reference to examples, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the invention and should therefore not be considered limiting its scope, as other equally effective embodiments of the invention may also be permitted. [Brief explanation of the drawing]

[0008] [Figure 1] This is a typical schematic elevation view of an prior art hybrid integrated circuit (IC) device using a fiber-reinforced (FR4) substrate core with embedded components. [Figure 2] This is a typical schematic elevation cross-sectional view of a molded core substrate having a mold material for encapsulating active and passive components used in a hybrid integrated circuit (IC) device, as an example. [Figure 3A] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 3B] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 3C] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 3D] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 4A] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 4B] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 5A] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 5B] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 5C] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 6A]This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 6B] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 6C] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 7A] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 7B] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 7C] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 8] This is a schematic elevation cross-sectional view illustrating the process steps for forming the molded core substrate of the IC device shown in Figure 2, as an example. [Figure 9] This is a schematic elevation cross-sectional view showing an example of stacked molded core substrates. [Figure 10] This is a schematic elevation cross-sectional view representing the IC device shown in Figure 2 in an integrated circuit package, as an example. [Modes for carrying out the invention]

[0009] For ease of understanding, where possible, the same reference numerals are used to indicate identical elements common to the drawings, and lowercase letters are added when elements are substantially the same. Elements of one embodiment are intended to be usefully incorporated into other embodiments.

[0010] Referring to Figure 1, a typical schematic elevation section of a prior art hybrid integrated circuit (IC) device using a fiber-reinforced (FR4) substrate core with embedded components is shown. The integrated circuit (IC) device, denoted 100 as a whole, is typically manufactured using a fiber-reinforced epoxy (FR4) core 102, which requires the formation of cavities 104 for embedding (placing) multiple components 106. These cavities 104 are then filled with a dielectric 108 having a high coefficient of thermal expansion (CTE). Having multiple components 106 within a single cavity 104 is difficult due to placement accuracy requirements and component displacement during the manufacturing process.

[0011] Forming cavities in FR4 core material requires laser drilling (which is expensive), and the number of cavities drilled increases or decreases as a function of the number of devices and components to be embedded within them. Generally, cavities are filled using multilayer dielectric films. In one example, the multilayer dielectric film includes an organic build-up film. In another example, the multilayer dielectric film includes an adhesive-coated polyester (PET) film. Adhesive-coated polyester (PET) films may have a CTE of less than approximately 40 ppm / K at 150°C. In one example, the multilayer dielectric film is an ABF film. ABF - "Ajinomoto Build-up Film" is a registered trademark of Ajinomoto Co., Inc. When cavities are filled using multilayer dielectric films (i.e., laminations), the multilayer dielectric film introduces undulations or variations in thickness that result in non-uniformity in the dielectric thickness over the devices and components within the cavities. FR4 material derives its rigidity from the presence of glass fiber bundles. When these fibers are cut or removed to form cavities, the overall rigidity of the core is weakened.

[0012] According to the teachings of the present disclosure, in an IC device for installation in an IC package (Fig. 10), a molded core substrate is used instead of an FR4 core. In contrast to the prior art, the use of an FR4 core requires drilling (subtractive method) to form cavities for arranging electronic components therein, and then filling these cavities containing the components. The molded core substrate has active and passive electronic components arranged on the substrate, and these components are then encapsulated with a molding material (additive method). The use of a molding process allows a large number of components, typically 50 to 100 components, to be embedded in the molded core substrate. By using the molding process, the need for an FR4 core is eliminated, and the costly and technically difficult steps of forming cavities in an FR4 substrate and filling the cavities, which are required by conventional IC device packaging, are avoided. The use of a molded core substrate instead of a conventional FR4 core enables large-scale integration of voltage regulators, inductors, deep trench capacitors, and other active and passive electronic components into easily manufactured and cost-effective IC products. A plurality of molded core substrates each having active and passive electronic components can be manufactured as a panel, encapsulated with a molding material, cured, and then singulated into individual molded core substrates ready for incorporation into IC packages.

[0013] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of the features of the embodiments. They are not intended as an exhaustive description of the embodiments below, or as a limitation to the claims. In addition, the embodiments shown do not necessarily have all the aspects or advantages shown. Aspects or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not shown or explicitly described as such. Referring here to the drawings, the details of the embodiments are schematic and representative layouts. Similar elements in the drawings are represented by the same reference numerals, and similar elements are represented by similar reference numerals with different lowercase suffixes.

[0014] Referring to Figure 2, a typical schematic elevation section of a molded core substrate having a molding material for encapsulating electronic components used in a hybrid integrated circuit (IC) device is shown as an example. The molded core substrate is generally represented by reference numeral 200 and may comprise a plurality of electronic components 206 encapsulated within the molding material 210. The molded core substrate 200 may be used to manufacture a hybrid IC device package.

[0015] The benefits and advantages of using a molding material to replace a FR4 core are as follows. When a molded core substrate is used, the molding material can be adjusted to achieve the desired rigidity and coefficient of thermal expansion (CTE). There is substantially no difference in CTE of the molding material across the entire device, as is experienced with the combination of prior art FR4 and cavity filling materials. No expensive drilling of unnecessary FR4 cores is performed to form cavities. Instead of drilling cavities in a FR4 core and filling them with a dielectric material (e.g., a multilayer dielectric film such as ABF), a molding process is used to embed components. The use of a mold grinding process to expose conductive pads or bumps on components allows standard bumped wafer components to be utilized without the need to customize surface finish / pad shapes for embedding. By placing components on a carrier and relying on the mold grinding process for uniform flat surface uniformity, thickness tolerance control is better.

[0016] The advantages of using a molded core substrate are as follows: Compared to manufacturing processes using FR4 cores, where the use of multilayer dielectric films for cavity filling increases the CTE of the composite core, it has a lower CTE (less than approximately 10 ppm / °C) and higher rigidity. The use of expensive laser cavity drilling and laminators is avoided, resulting in a lower manufacturing process cost. The material cost is lower compared to using multilayer dielectric films for cavity filling in FR4 drilled cores. It avoids the difficulties of cavity filling with multilayer dielectric films or prepregs, which can lead to a risk of voids during the lamination process. There is a larger margin for die shift during part encapsulation. The better uniformity of via and multilayer dielectric film thickness in the above-mentioned parts, mold, and grinding processes provides uniform core thickness and flatness. While the number of parts is limited in the conventional art due to the use of FR4 cavity drilling and filling capacity, more parts can be used. The mold material can be designed to achieve a low CTE and high molded core substrate rigidity. Instead of being forced to use the approximately 200-micrometer increments available in FR4 core material, it offers flexibility in its ability to have custom core thicknesses.

[0017] Figures 3A-3D, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, and 8 show schematic elevation and cross-sectional views illustrating process steps for forming a molded core substrate for the IC device of Figure 2, according to an example. According to the teachings of this disclosure, a process for manufacturing a molded core substrate 200 for use in a hybrid IC device can begin with a carrier panel 312 (Figure 3A). The carrier panel 312 may be, but is not limited to, a glass, ceramic, or metal substrate. Stainless steel / metal with a release film can also be used. The release film 314 may be laminated on the surface of the carrier panel 312 (Figure 3B). The release film 314 may be used in a subsequent manufacturing step (Figure 5B) to peel the carrier panel 312 from the molded core substrate 200.

[0018] A copper seed layer 316 and a reference 318 are added to the surface of the release film 314 (Figure 3C). The reference 318 is used to facilitate the accuracy of part placement on the copper seed layer 316. Optionally, a sealing layer 320 can be added on top of the copper seed layer 316 and made flat with the reference 318 (Figure 3D). The part 422 can be precisely positioned, for example, using the reference 318 and, for example, using alignment marks on the copper seed layer 316 (Figure 4A). After the part 422 is attached to the copper seed layer 316, the part 422 can be sealed using a mold material 424 (Figure 4B). For example, the mold material 424, such as an epoxy / filler composite, may have a low coefficient of thermal expansion (CTE) and a high modulus of elasticity to replicate a conventional core. The mold material may be formed in a compression mold.

[0019] Once cured, the mold material 424 can be ground to expose the top surface of the part 422 (Figure 5A). The mold grinding may be coplanar with the top of the part 422. The carrier panel 312 can then be removed by peeling the release film 314 from the copper seed layer 316 using, for example, but not limited to, a laser, thermal peeling, and photo-induced ultraviolet curing (Figure 5B). The copper seed layer 316 may be etched, and then the sealing layer 320 may be removed by solvent washing to expose the bottom of the part 422 (connection 522) and the reference 318 (Figure 5C).

[0020] To form vias, holes 626 may be formed in the cured mold material 424 (Figure 6A). The holes 626 may be formed by drilling, laser cutting, or other suitable techniques. A copper seed layer 628 may be formed on the top and bottom of the mold material 424 and inside the holes 626 to form plated through-holes (PTHs) (Figure 6B). A copper blanket 630 may be electroplated on the copper seed layer 628 and inside the holes 626 (Figure 6C), assisting in the further step of polishing the plug 732 to be flat with the copper blanket 630. The plug 732 may be formed inside the holes 626 using organic resin, paste printing, or liquid dispensing, and the copper blanket 630 may be connected to a PTH pad 734 formed after subtractive etching of the copper blanket 630. The reference 318 used for part placement accuracy may be removed during subtractive etching as it is no longer required (Figure 7B). The multilayer dielectric film 736 may be laminated on the upper and lower surfaces of the mold material 424 (Figure 7C). Subsequently, vias 840 may be formed within the multilayer dielectric film 736 for external connection of the mold material 424 to the component 422 during the substrate manufacturing process (Figure 8).

[0021] Referring to Figure 9, a schematic elevation section is shown illustrating an example of a stacked molded core substrate. The stacked molded core substrate, collectively represented by reference numeral 900, may include at least two molded core substrates 200 (two are shown), each containing multiple electronic components 206 sealed within a molded material 210. Since more components can be accommodated on a smaller horizontal footprint, the stacked molded core substrates 900 can be used to fabricate higher-density hybrid IC device packages. The component connection pads 922 of each of the at least two molded core substrates 200 are interconnected with connection points 940, for example, in a standard metallization and lithography process, and external connection points 1042 (Figure 10) may be formed via vias 840. The molded core substrates 200 and / or 900 can be packaged into a hybrid IC device product using further standard manufacturing processes.

[0022] Referring to Figure 10, a schematic elevation cross-sectional view is shown illustrating an example of an IC device in an integrated circuit package as shown in Figure 2. An IC molded core substrate 200, having components 206 inside, is manufactured within an IC package 1044. The IC package 1044 has external connection parts 1042, which are, for example, ball grid arrays, land grid arrays, or pin grid arrays, coupled to the component connection parts of the IC molded core substrate 200.

[0023] As will be understood by those skilled in the art who benefit from this disclosure, the embodiments disclosed herein may be embodied as systems, methods, apparatus, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, which may all be collectively referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0024] The technology disclosed above can be illustrated in the following non-limiting examples.

[0025] Example 1. An integrated circuit (IC) molded core substrate comprising: a plurality of components having circuit connection portions on a first side and / or a second side; a mold material surrounding the plurality of components, wherein the first surface and the second surface of the mold material are coplanar with the circuit connection portions; and a copper pattern that interconnects the circuit connection portions.

[0026] Example 2. The mold material is the IC molding core substrate of Example 1, having a low coefficient of thermal expansion (CTE).

[0027] Example 3. The mold material is the IC molded core substrate of Example 1, formed in a compression mold.

[0028] Example 4. An IC molded core substrate of Example 1, wherein the multiple components are selected from the group consisting of integrated voltage regulators, inductors, and deep trench capacitors.

[0029] Example 5. The IC molded core substrate of Example 1, further comprising plated through-holes within the mold material from the first surface to the second surface of the mold material.

[0030] Example 6. The IC molding core substrate of Example 1, further comprising a multilayer dielectric film including adhesive-coated polyester layers laminated on the first and second surfaces of the molding material.

[0031] Example 7. The IC molding core substrate of Example 6, further comprising vias in a multilayer dielectric film laminated on a first surface and / or a second surface of the molding material.

[0032] Example 8. An IC molded core substrate of Example 7, in which connections to multiple components within the molded core substrate are made via vias.

[0033] Example 9. An integrated circuit (IC) comprising: a plurality of components having circuit connection portions on a first side and / or a second side; a molded core substrate having a molded material surrounding the plurality of components, wherein the first surface and the second surface of the molded material are coplanar with the circuit connection portions; a copper pattern interconnecting the circuit connection portions; an IC package including the IC molded core substrate; and external connection portions on the IC package coupled to the circuit connection portions of the plurality of components in the molded core substrate.

[0034] Example 10. The IC package is the IC of Example 9, comprising at least two molded core substrates.

[0035] Example 11. The IC of Example 9, wherein the external connection portion on the IC package is selected from the group consisting of a ball grid array, a land grid array, and a pin grid array.

[0036] Example 12. A method for manufacturing an integrated circuit (IC) molded core substrate, comprising: laminating a release film onto one surface of a carrier panel; applying a first copper seed layer on the release film; arranging an electronic component on the first copper seed layer; applying a molding material around and on the electronic component; curing the molding material; grinding the molding material in the same plane as the top of the electronic component; removing the release film together with the carrier panel from the first copper seed layer; etching the first copper seed layer; forming holes in the molding material; applying a second copper seed layer on the surface of the cured molding material and the formed holes; applying a copper blanket on the second copper seed layer and in the formed holes; sealing the formed holes to create plated through-holes (PTH); removing a portion of the copper blanket, but leaving the other portion for the PTH and component connection pads; laminating a multilayer dielectric film on the PTH and component connection pads; and forming vias that penetrate the multilayer dielectric film to the PTH and component connection pads.

[0037] Example 13. The manufacturing method of Example 12, wherein the carrier panel is selected from the group consisting of a glass substrate, a ceramic substrate, and a metal substrate.

[0038] Example 14. The manufacturing method of Example 12, wherein the step of removing the carrier panel from the molded core substrate includes peeling off a release film from the first copper seed layer.

[0039] Example 15. The manufacturing method of Example 14, wherein the release film is peeled off from the first copper seed layer using a laser.

[0040] Example 16. The manufacturing method of Example 14, wherein the release film is peeled from the first copper seed layer by thermal peeling.

[0041] Example 17. The manufacturing method of Example 14, wherein the release film is peeled from the first copper seed layer by photo-induced ultraviolet curing.

[0042] Example 18. The manufacturing method of Example 12, wherein the copper blanket is applied to the second copper seed layer and into the holes formed by electroplating.

[0043] Example 19. The manufacturing method of Example 12, further comprising the step of plating a reference having alignment marks onto a first copper seed layer for positioning electronic components using the alignment marks of the reference.

[0044] Example 20. The manufacturing method of Example 19, further comprising the step of removing a reference by subtractive etching after the placement of the electronic components.

[0045] The above describes embodiments of the present invention, but other embodiments and further embodiments of the present invention can be devised without departing from the basic scope of the present invention, and the scope of the present invention is determined by the following "Claims".

Claims

1. A plurality of components having circuit connection portions on the first side and / or the second side, A molding material surrounding the plurality of parts, wherein the first surface and the second surface of the molding material are on the same plane as the circuit connection portion, The circuit comprises a copper pattern that interconnects the aforementioned circuit connection portion, Integrated circuit (IC) molded core substrate.

2. The mold material has a low coefficient of thermal expansion (CTE). IC molded core substrate according to claim 1.

3. The mold material is formed by a compression mold. IC molded core substrate according to claim 1.

4. The aforementioned plurality of components are selected from the group consisting of an integrated voltage regulator, an inductor, and a deep trench capacitor. IC molded core substrate according to claim 1.

5. The mold material is provided with a plating through-hole that penetrates from the first surface to the second surface. IC molded core substrate according to claim 1.

6. The mold material comprises a multilayer dielectric film including an adhesive-coated polyester layer laminated on the first and second surfaces, IC molded core substrate according to claim 1.

7. The mold material is provided with vias in the multilayer dielectric film laminated on the first and / or second surface of the mold material. IC molded core substrate according to claim 6.

8. The connection of the plurality of components within the molded core substrate is made via the vias. IC molded core substrate according to claim 7.

9. A plurality of components having circuit connection portions on the first side and / or the second side, A molding material surrounding the plurality of parts, wherein the first surface and the second surface of the molding material are on the same plane as the circuit connection portion, A molded core substrate having copper patterns that interconnect the circuit connection portions, An IC package including the aforementioned molded core substrate, The IC package comprises an external connection portion on the IC package that is coupled to the circuit connection portion of the plurality of components in the molded core substrate, Integrated circuit (IC).

10. The IC package includes at least two molded core substrates, The IC according to claim 9.

11. The external connection portion on the IC package is selected from the group consisting of a ball grid array, a land grid array, and a pin grid array. The IC according to claim 9.

12. Laminating a release film onto the surface of the carrier panel, Applying a first copper seed layer onto the release film, Placing electronic components on the first copper seed layer, Applying molding material around and on the aforementioned electronic component, The process involves curing the aforementioned mold material, The molding material is ground so that it is flush with the top of the electronic component, Removing the release film from the first copper seed layer together with the carrier panel, Etching the first copper seed layer, Forming holes in the aforementioned mold material, Applying a second copper seed layer to the hardened mold material and the surface of the formed hole, Applying a copper blanket to the second copper seed layer and the formed holes, The formed holes are sealed to create plated through-holes (PTHs), A portion of the copper blanket is removed, but the rest of the copper blanket is left in place for the PTH and component connection pads. The PTH and component connection pads are laminated with multilayer dielectric films, This includes forming vias that penetrate the multilayer dielectric film and reach the PTH and the component connection pad, A method for manufacturing an integrated circuit (IC) molded core substrate.

13. The carrier panel is selected from the group consisting of a glass substrate, a ceramic substrate, and a metal substrate. The method for manufacturing claim 12.

14. Removing the carrier panel from the molded core substrate includes peeling the release film from the first copper seed layer. The method for manufacturing claim 12.

15. This includes plating a reference having alignment marks onto the first copper seed layer, and positioning electronic components using the alignment marks on the reference. The method for manufacturing claim 12.

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