A method for forming a low-dielectric-constant dielectric material with reduced dielectric constant and increased density.

Abstract

An exemplary semiconductor processing method may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a precursor containing silicon, oxygen, and carbon. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of material containing silicon, oxygen, and carbon on the substrate. The layer of material containing silicon, oxygen, and carbon may be characterized by a dielectric constant of about 4.5 or less. The layer of material containing silicon, oxygen, and carbon may have a dielectric constant of about 2.0 g / cm³. 3 The above densities may be characteristic.

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims the benefits and priority of U.S. Patent Application No. 18 / 233,984, filed on 15 August 2023, entitled “METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND INCREASED DENSITY,” which is incorporated herein by reference in its entirety.

[0002] Technical field

[0002] This technology relates to deposition processes and chambers. More specifically, this technology relates to a method for manufacturing low dielectric constant materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by the process of manufacturing intricately patterned material layers on a substrate surface. Manufacturing patterned material on a substrate requires a controlled method for forming and removing the material. The properties of the material can affect the operation of the device and can also affect how the material is removed from one another. Plasma-enhanced deposition can manufacture materials with specific properties, which can affect the performance of the device. The properties of the material can be tuned or enhanced by changing the deposition conditions, such as the chemicals of the precursor provided during deposition and / or the processing conditions during deposition.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high-quality devices and structures. This technology addresses this need and other needs. [Overview of the project]

[0005]

[0005] An exemplary semiconductor processing method may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a precursor containing silicon, oxygen, and carbon. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of material containing silicon, oxygen, and carbon on the substrate. The layer of material containing silicon, oxygen, and carbon may be characterized by a dielectric constant of about 4.5 or less. The layer of material containing silicon, oxygen, and carbon may have a dielectric constant of about 2.0 g / cm³ 3 The above densities may be characteristic.

[0006]

[0006] In some embodiments, the silicon, oxygen, and carbon-containing precursor may be or include dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, methoxy(dimethyl)silylmethane, or vinylmethyldimethoxysilane. The deposition precursor further comprises a nitrogen-containing precursor. The nitrogen-containing precursor may be or include ammonia (NH3). The flow rate ratio of the silicon, oxygen, and carbon-containing precursor to the nitrogen-containing precursor may be about 10:1 or less. The method may include providing helium together with the deposition precursor. The flow rate ratio of the silicon, oxygen, and carbon-containing precursor to helium may be about 1:1 or less. Plasma emissions may be formed with a plasma output of about 1,500 W or less. The temperature in the semiconductor processing chamber may be maintained at about 250°C or higher. The pressure in the semiconductor processing chamber may be maintained at about 15 Torr or less. The layer of the silicon, oxygen, and carbon-containing material may be characterized by an oxygen content of about 20.0 at.% or more. A layer of material containing silicon, oxygen, and carbon may be characterized by a nitrogen content of approximately 20.0 at.% or less.

[0007]

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may be or include a silicon-, oxygen-, and carbon-containing precursor and a nitrogen-containing precursor. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of silicon-, oxygen-, and carbon-containing material on the substrate. The layer of silicon-, oxygen-, and carbon-containing material may be characterized by an oxygen content of about 25.0 at.% or more. The layer of silicon-, oxygen-, and carbon-containing material may be characterized by a dielectric constant of about 4.2 or less.

[0008]

[0008] In some embodiments, the precursor containing silicon, oxygen, and carbon may be or contain dimethyldimethoxysilane. The flow rate ratio of the silicon, oxygen, and carbon precursor to the nitrogen-containing precursor may be about 10:1 or less. The plasma emission can be formed with a plasma output of about 1,000 W or less. The layer of the silicon, oxygen, and carbon material is 0.001 A / cm 2 It may be characterized by a dielectric breakdown voltage of approximately 6.5 MV / cm or higher. The temperature within the processing area can be maintained at approximately 500°C or lower.

[0009]

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may be or include a precursor containing silicon, oxygen, and carbon. A substrate may be placed within the processing area. The silicon, oxygen, and carbon-containing precursor may be or include dimethyldimethoxysilane. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of a material containing silicon, oxygen, and carbon on a substrate. The layer of the material containing silicon, oxygen, and carbon may be characterized by an oxygen content of about 25.0 at.% or more. The layer of the material containing silicon, oxygen, and carbon may be characterized by a dielectric constant of about 4.2 or less. The layer of the material containing silicon, oxygen, and carbon may be characterized by a density of about 2.0 or more.

[0010]

[0010] In some embodiments, the deposition rate of the layer of material containing silicon, oxygen, and carbon may be about 500 Å / min or more. The layer of material containing silicon, oxygen, and carbon has a leakage current of about 2E-08 A / cm at 2 MV / cm. 2 It may be characterized by the following:

[0011]

[0011] Such techniques may offer numerous advantages over conventional processing methods. For example, by utilizing a silicon-containing precursor containing oxygen, carbon, and / or hydrogen during deposition, the atomic structure of the material may be modified, increasing the oxygen content in the deposited material. In addition, an increase in the oxygen content in the deposited material may lead to a decrease in dielectric constant and an increase in density. Along with these numerous advantages and features, the above embodiments and other embodiments will be described in further detail in conjunction with the description in the following specification and the accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] An exemplary top view of a processing system according to several embodiments of the present technology is shown. [Figure 2]

[0014] A schematic cross-sectional view of an exemplary plasma system according to several embodiments of this technology is shown. [Figure 3]

[0015] The steps of an exemplary method for semiconductor processing according to several embodiments of this technology are shown. [Modes for carrying out the invention]

[0014]

[0016] Some of the accompanying drawings are provided as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered as actual scale unless the scale is explicitly specified. In addition, as schematic diagrams, the figures are provided to facilitate understanding, may not include all aspects or information compared with actual depictions, and may include materials emphasized for illustrative purposes.

[0015]

[0017] In the accompanying drawings, similar components and / or features may have the same reference signs. Furthermore, various components of the same type may be distinguished according to the reference sign by a character that differentiates between similar components. Where only the first reference sign is used herein, the description is applicable to any similar component having the same first reference sign regardless of the character described above.

[0016]

[0018] During back-end-of-line semiconductor processing, structures may be manufactured to facilitate metallization such as dual damascene structures. These structures may be manufactured in several processing steps using a masking film and a low-dielectric-constant film, which may be processed and removed. The removal may be performed by chemical mechanical processing which includes a certain amount of physical wear of the material for removal. Low-dielectric-constant films may be characterized by relatively low hardness and tensile modulus, and high shear stress during polishing may cause cracks in the low-dielectric-constant film and lead to device failure, thus the effectiveness during polishing may be limited. To improve hardness while maintaining a lower k value, many prior art methods are forced to include additional processing steps such as UV curing to improve the hardness and / or density of the film. These additional processes may significantly reduce throughput and often require additional processing chambers on the tool. In addition, these additional processes may not improve mechanical properties to meet desired specifications.

[0017]

[0019] This technology can overcome these problems by providing a low dielectric constant film that, upon deposition, may be characterized by a decrease in dielectric constant as density increases. By performing deposition using a specific precursor, such as a precursor containing silicon, oxygen, and carbon, additional oxygen can be incorporated into the deposited material. As the amount of oxygen in the deposited material increases, the silicon-oxygen (Si-O) bonding in the film increases, while the ratio of carbon moieties necessary to maintain the reduced dielectric constant may be maintained. This overcomes the natural tendency for dielectric constant to increase with density and can also reduce the number of steps required during processing. In particular, this technology may not require subsequent post-deposition processing, including UV exposure, plasma treatment, or other processing steps to post-treat the film to improve density. However, subsequent post-deposition processing may still be performed to further reduce the dielectric constant and / or increase density.

[0018]

[0020] The remaining disclosures, as is customary, identify specific deposition processes that utilize the disclosed technology. However, it will be readily apparent that the systems and methods are equally applicable to other deposition chambers, not just those that may occur in the described chambers. Therefore, the technology should not be considered limited to use with these specific deposition processes or chambers alone. Before describing additional details of embodiments of the technology, this disclosure will consider one possible system and chamber that may be used to carry out a deposition process according to an embodiment of the technology.

[0019]

[0021] Figure 1 shows a top view of one embodiment of a processing system 100 comprising a deposition chamber, etching chamber, baking chamber, and UV processing chamber. In the figure, a pair of forward-opening unified pods 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a to 108f positioned in tandem sections 109a to 109c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to and from the substrate processing chambers 108a to 108f. Each substrate processing chamber 108a to 108f may be equipped to perform a number of substrate processing steps, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, UV processing, pre-cleaning, degassing, orientation, and other substrate processing such as annealing and ashing.

[0020]

[0022] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, UV-treating, and / or etching dielectric films or other materials on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) may be used to deposit dielectric material on the substrate, and a third pair of processing chambers (e.g., 108a-108b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit alternating laminates of dielectric material on the substrate. One or more of the described processes may be performed in a chamber separated from the manufacturing system as shown in various embodiments. Additional configurations of deposition chambers, etching chambers, annealing chambers, and UV-treating chambers for dielectric materials will be understood as being intended by system 100.

[0021]

[0023] Figure 2 shows a schematic cross-sectional view of an exemplary plasma system 200 according to several embodiments of the present technology. The plasma system 200 may exemplify a pair of processing chambers 108 that can be attached to one or more of the tandem sections 109 described above. This pair of processing chambers 108 may include a lid stack component according to embodiments of the present technology, which will be described further below. The plasma system 200 may generally include a chamber body 202. This chamber body 202 has side walls 212, a bottom wall 216, and an internal side wall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A and 220B may be similarly configured and include the same components.

[0022]

[0024] For example, the processing area 220B (whose components may also be included in the processing area 220A) may include a pedestal 228 positioned within the processing area through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, which can heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may be heated by a remote heating element, such as a lamp assembly, or by other heating devices.

[0023]

[0025] The body of the pedestal 228 may be connected to the stem 226 by a flange 233. The stem 226 may electrically connect the pedestal 228 to a power outlet or power box 203. The power box 203 may include a driver system that controls the raising and moving of the pedestal 228 within the processing area 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include interfaces for power indicators and temperature indicators, such as thermocouple interfaces. The stem 226 may include a base assembly 238 adapted to be detachably connected to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stopper or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0024]

[0026] Rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing area 220B and may be used to position substrate lift pins 261 positioned through the body of the pedestal 228. The substrate lift pins 261 may be used to move the substrate 229 into the processing area 220B through a substrate transfer port 260 and to transfer the substrate 229 from the processing area 220B, thereby facilitating the replacement of the substrate 229 by a robot.

[0025]

[0027] A chamber lid 204 may be connected to the uppermost portion of the chamber body 202. The lid 204 may house one or more precursor distribution systems 208 connected thereto. The precursor distribution system 208 may include a precursor inlet passage 240. This precursor inlet passage 240 can deliver reactants and washing precursors into the processing area 220B through a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 positioned in the middle of a faceplate 246. A radio frequency (RF) source 265 may be coupled to the dual-channel showerhead 218. This RF source 265 can power the dual-channel showerhead 218 to facilitate the generation of a plasma region between the faceplate 246 and the pedestal 228 of the dual-channel showerhead 218. The dual-channel showerhead 218 and / or faceplate 246 may include one or more openings that allow the flow of precursor from the precursor distribution system 208 to the processing areas 220A and / or 220B. In some embodiments, the openings may include at least one of a linear opening and a conical opening. In some embodiments, the RF source may be connected to another part of the chamber body 202 (such as a pedestal 228) to facilitate plasma generation. A dielectric isolator 258 may be placed between the lid 204 and the dual-channel showerhead 218 to prevent the conduction of RF power to the lid 204. A shadow ring 206 that engages with the pedestal 228 may be placed on the outer periphery of the pedestal 228.

[0026]

[0028] To cool the annular base plate 248 during operation, optional cooling channels 247 may be formed within the annular base plate 248 of the precursor distribution system 208. A heat transfer fluid, such as water, ethylene glycol, or gas, may be circulated through the cooling channels 247 so that the base plate 248 can be maintained at a predetermined temperature. To prevent the side walls 201, 212 from being exposed to the processing environment within the processing area 220B, a liner assembly 227 may be positioned within the processing area 220B, close to the side walls 201, 212 of the chamber body 202. The liner assembly 227 may include a circumferential pumping cavity 225, which can be connected to a pumping system 264 configured to exhaust gases and by-products from the processing area 220B and to control the pressure within the processing area 220B. Multiple exhaust ports 231 may be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas to flow from the processing area 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200.

[0027]

[0029] Figure 3 shows the steps of an exemplary method 300 for semiconductor processing according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the system 200 described above, and in any other chamber in which plasma deposition may be performed. Method 300 may include a number of optional steps, some of which may or may not be particularly relevant to some embodiments of the method according to the present technology.

[0028]

[0030] Method 300 may include a plasma-enhanced chemical vapor deposition (PECVD) process for forming a deposited low dielectric constant material. Method 300 may include optional steps before starting Method 300, or Method 300 may include additional steps after the deposition of the low dielectric constant material. In embodiments, Method 300 may include, as shown in Figure 3, providing a deposition precursor into the processing area of ​​a semiconductor processing chamber in step 305. A substrate may be housed in the processing area of ​​the semiconductor processing chamber when the deposition precursor is provided into the chamber. In step 310, plasma emissions of the deposition precursor may be formed. In step 315, a layer of material containing silicon, oxygen, and carbon may be deposited on the substrate. In embodiments, the layer of material containing silicon, oxygen, and carbon may be exposed to ultraviolet (UV) light in an optional step 320.

[0029]

[0031] In some embodiments, the deposition precursor may include a precursor containing silicon, oxygen, and carbon. The silicon, oxygen, and carbon precursors that may be used are, but are not limited to, dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, methoxy(dimethyl)silylmethane, or vinylmethyldimethoxysilane. By utilizing a silicon-containing precursor that also contains oxygen, an increased amount of oxygen may be present in the plasma emissions incorporated into the deposited material. Therefore, an increased amount of oxygen may be present in the deposited layer of the silicon, oxygen, and carbon material. An increase in the amount of oxygen and Si-O bonds may decrease the dielectric constant of the material, while also increasing the density of the material.

[0030]

[0032] The deposition precursor may further contain a nitrogen-containing precursor. Possible nitrogen-containing precursors include, but are not limited to, ammonia (NH3), hydrazine (N2H4), and any other nitrogen-containing precursors that can be used to form silicon-containing materials. In embodiments, the flow rate of the nitrogen-containing precursor relative to the flow rate of the silicon-, oxygen-, and carbon-containing precursor may be maintained and / or adjusted to a flow rate ratio that is useful for forming low dielectric constant materials having both low dielectric constant (κ value) and high oxygen uptake. The deposition precursor may also contain one or more carrier gases, such as helium, argon, and nitrogen (N2). One or more carrier gases may be delivered together with other deposition precursors, but the carrier gases may be considered inert gases that do not react and form part of the deposited material. One or more carrier gases may be delivered together with other deposition precursors to act as diluents.

[0031]

[0033] By utilizing silicon-containing precursors that also contain oxygen (e.g., the specific precursors listed earlier), an increased amount of oxygen can be incorporated into the deposited material. As mentioned above, an increase in oxygen content may decrease the dielectric constant of the deposited material. In addition, an increase in oxygen content can lead to a higher density of the deposited material. In conventional techniques, such as those where the deposited precursor does not contain precursors containing silicon, oxygen, and carbon, a trade-off may exist between dielectric constant and density.

[0032]

[0034] The flow rate of the precursor containing silicon, oxygen, and carbon may be approximately 50 sccm or more, approximately 60 sccm or more, approximately 70 sccm or more, approximately 80 sccm or more, approximately 90 sccm or more, approximately 100 sccm or more, approximately 125 sccm or more, approximately 150 sccm or more, approximately 175 sccm or more, approximately 200 sccm or more, approximately 250 sccm or more, approximately 300 sccm or more, approximately 350 sccm or more, approximately 500 sccm or more, approximately 750 sccm or more, approximately 1,000 sccm or more, approximately 1,250 sccm or more, approximately 1,500 sccm or more, or more.

[0033]

[0035] The flow rate of the nitrogen-containing precursor may be approximately 50 sccm or more, approximately 60 sccm or more, approximately 70 sccm or more, approximately 80 sccm or more, approximately 90 sccm or more, approximately 100 sccm or more, approximately 125 sccm or more, approximately 150 sccm or more, approximately 175 sccm or more, approximately 200 sccm or more, approximately 225 sccm or more, approximately 250 sccm or more, approximately 275 sccm or more, approximately 300 sccm or more, approximately 400 sccm or more, approximately 500 sccm or more, approximately 750 sccm or more, approximately 1,000 sccm or more, approximately 1,250 sccm or more, approximately 1,500 sccm or more, or more. The flow rate of the nitrogen-containing precursor may also be approximately 2,500 sccm or less, approximately 2,250 sccm or less, approximately 2,000 sccm or less, approximately 1,750 sccm or less, approximately 1,250 sccm or less, approximately 1,000 sccm or less, or less.

[0034]

[0036] The flow rate of one or more carrier gases may be approximately 200 sccm or more, approximately 300 sccm or more, approximately 400 sccm or more, approximately 500 sccm or more, approximately 750 sccm or more, approximately 1,000 sccm or more, approximately 2,000 sccm or more, approximately 3,000 sccm or more, approximately 4,000 sccm or more, approximately 5,000 sccm or more, or more.

[0035]

[0037] In the embodiment, the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to the nitrogen-containing precursor may be about 10:1 or less. For example, the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to the nitrogen-containing precursor may be about 9:1 or less, about 8:1 or less, about 7:1 or less, about 6:1 or less, or less. As the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to the nitrogen-containing precursor increases, the density may begin to decrease. Conversely, as the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to the nitrogen-containing precursor decreases, more nitrogen may be incorporated into the deposited material, and since the atomic weight of nitrogen is greater than that of carbon, the density of the deposited material may increase. Similarly, the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to a carrier gas such as helium may be about 1:1 or less. For example, the flow rate ratio of the silicon-, oxygen-, and carbon-containing precursor to a carrier gas may be about 1:2 or less, about 1:3 or less, about 1:4 or less, about 1:5 or less, or less. Furthermore, as the flow rate ratio of the silicon, oxygen, and carbon-containing precursor to the carrier gas increases, the density may begin to decrease. As the flow rate ratio of the silicon, oxygen, and carbon-containing precursor to the carrier gas decreases, the silicon, oxygen, and carbon-containing precursor becomes more diluted, which can slow down the deposition rate of the material and increase the density of the already deposited material.

[0036]

[0038] Embodiments of Method 300 may include forming plasma emitters from a deposited precursor in step 310. Plasma emitters can be formed from a deposited precursor in a processing area, for example, by supplying RF power to a faceplate to generate plasma within the processing area of ​​a semiconductor processing chamber. In embodiments, plasma emitters can be formed at a plasma output of about 2,000 W or less. Increasing the plasma output above 2,000 W may result in increased decomposition of the silicon, oxygen, and carbon-containing precursor, which may be extracted from the deposited material. Conversely, at plasma outputs of about 2,000 W or less, decomposition is less likely to occur, and Si-O bonds may be preserved within the deposited material. Therefore, plasma emissions can be formed with plasma power outputs of approximately 1,750W or less, approximately 1,500W or less, approximately 1,400W or less, approximately 1,300W or less, approximately 1,200W or less, approximately 1,100W or less, approximately 1,000W or less, approximately 900W or less, approximately 800W or less, approximately 700W or less, approximately 600W or less, approximately 500W or less, approximately 400W or less, approximately 300W or less, approximately 200W or less, or lower.

[0037]

[0039] The deposition rate of the layer of material containing silicon, oxygen, and carbon may be about 500 Å / min or more, about 525 Å / min or more, about 550 Å / min or more, about 575 Å / min or more, about 600 Å / min or more, about 625 Å / min or more, about 650 Å / min or more, about 675 Å / min or more, about 700 Å / min or more, about 725 Å / min or more, about 750 Å / min or more, about 775 Å / min or more, about 700 Å / min or more, or higher.

[0038]

[0040] Embodiments of Method 300 may include depositing a material containing silicon, oxygen, and carbon onto a substrate in step 315. As previously stated, the substrate may be located within a processing area of ​​a semiconductor processing chamber, and the material containing silicon, oxygen, and carbon may be formed from plasma emissions generated by the deposition plasma also present within the processing area. The processing area, and therefore the substrate, may be characterized during deposition at temperatures of about 600°C or less, about 580°C or less, about 560°C or less, about 540°C or less, about 520°C or less, about 500°C or less, about 480°C or less, about 460°C or less, about 440°C or less, about 420°C or less, about 400°C or less, about 380°C or less, about 360°C or less, about 340°C or less, about 320°C or less, about 300°C or less, about 280°C or less, about 260°C or less, or below. In addition, the processing area, and therefore the substrate, may be characterized by temperatures of approximately 250°C or higher, approximately 275°C or higher, approximately 300°C or higher, approximately 325°C or higher, approximately 350°C or higher, approximately 375°C or higher, approximately 400°C or higher, approximately 425°C or higher, approximately 450°C or higher, approximately 475°C or higher, approximately 500°C or higher, or above during deposition. At high temperatures such as approximately 250°C or higher, the density of materials containing silicon, oxygen, and carbon may increase. As the temperature rises, absorbed molecules in the material may diffuse over greater distances to bind to already formed nuclei rather than forming new nuclei. Therefore, as the temperature rises, absorbed molecules can obtain more thermal energy to align within the material, and a denser material may be formed.

[0039]

[0041] During method 300, the pressure in the semiconductor processing chamber during deposition may be approximately 1 Torr or more, approximately 2 Torr or more, approximately 3 Torr or more, approximately 4 Torr or more, approximately 5 Torr or more, approximately 6 Torr or more, approximately 7 Torr or more, approximately 8 Torr or more, approximately 9 Torr or more, approximately 10 Torr or more, approximately 15 Torr or more, approximately 20 Torr or more, or higher. As the pressure increases, the residence time of the deposition precursor may increase, thus lengthening the reaction time and potentially allowing for increased oxygen uptake into the deposited material. Furthermore, the pressure in the semiconductor processing chamber during deposition may be approximately 15 Torr or less, approximately 14 Torr or less, approximately 13 Torr or less, approximately 12 Torr or less, approximately 11 Torr or less, approximately 10 Torr or less, approximately 9 Torr or less, approximately 8 Torr or less, approximately 7 Torr or less, approximately 6 Torr or less, approximately 5 Torr or less, approximately 4 Torr or less, approximately 3 Torr or less, approximately 2 Torr or less, approximately 1 Torr or less, or lower.

[0040]

[0042] The oxygen content in the material can be controlled depending on the flow rate of the deposition precursor and / or the processing conditions. For example, the oxygen content in the material may be about 20.0 at.% or more, about 21.0 at.% or more, about 22.0 at.% or more, about 23.0 at.% or more, about 24.0 at.% or more, about 25.0 at.% or more, about 26.0 at.% or more, about 27.0 at.% or more, about 28.0 at.% or more, about 29.0 at.% or more, about 30.0 at.% or more, about 31.0 at.% or more, about 32.0 at.% or more, about 33.0 at.% or more, about 34.0 at.% or more, about 35.0 at.% or more, or more. As the oxygen content increases, the amount of Si-O bonds increases, and therefore the density may increase.

[0041]

[0043] In addition, the nitrogen content in the material may be about 20.0 at.% or less, and may be about 19.0 at.% or less, about 18.0 at.% or less, about 17.0 at.% or less, about 16.0 at.% or less, about 15.0 at.% or less, about 14.0 at.% or less, about 13.0 at.% or less, about 12.0 at.% or less, about 11.0 at.% or less, about 10.0 at.% or less, or even lower than this. When the nitrogen content decreases, the amount of Si-N bonds decreases and the amount of Si-O bonds increases, which can increase the density.

[0042]

[0044] In an embodiment, the layer of material containing silicon, oxygen and carbon has a leakage current of about 2E-08 A / cm at 2 MV / cm 2 or less. When the oxygen content in the material increases, the presence of Si-O bonds increases, so the leakage current of the material can decrease. In an embodiment, the leakage current at 2 MV / cm is about 1.9E-08 A / cm 2 or less, about 1.8E-08 A / cm 2 or less, about 1.7E-08 A / cm 2 or less, about 1.6E-08 A / cm 2 or less, about 1.5E-08 A / cm 2 or less, about 1.4E-08 A / cm 2 or less, about 1.3E-08 A / cm 2 or less, about 1.2E-08 A / cm 2 or less, about 1.1E-08 A / cm 2 or less, about 1E-08 A / cm 2 or less, or even lower than this.

[0043]

[0045] The layer of material containing silicon, oxygen and carbon has a breakdown voltage of 0.001 A / cm 2 of about 6.5 MV / cm or more. When the oxygen content in the material increases, the presence of Si-O bonds increases, so the leakage current of the material can decrease. In an embodiment, at 0.001 A / cm 2The breakdown voltage may be approximately 6.6 MV / cm or higher, approximately 6.7 MV / cm or higher, approximately 6.8 MV / cm or higher, approximately 6.9 MV / cm or higher, approximately 7.0 MV / cm or higher, approximately 7.1 MV / cm or higher, approximately 7.2 MV / cm or higher, approximately 7.3 MV / cm or higher, or greater than these.

[0044]

[0046] As described above, the methods of the present technology include embodiments that utilize deposition precursors and processing conditions for forming a low dielectric constant material having a low dielectric constant. In embodiments of Method 300, the deposited low dielectric constant material may be formed as a material containing silicon, oxygen, and carbon having a dielectric constant of about 5.0 or less, about 4.8 or less, about 4.6 or less, about 4.4 or less, about 4.2 or less, about 4.0 or less, about 3.9 or less, about 3.8 or less, about 3.7 or less, about 3.6 or less, about 3.5 or less, or lower.

[0045]

[0047] The present technology includes embodiments that utilize deposition precursors and processing conditions capable of forming low dielectric constant materials with increased density. In embodiments of Method 300, the deposited low dielectric constant material is approximately 2.0 g / cm³. 3 More than about 2.05g / cm 3 Approximately 2.1g / cm 3 Approximately 2.15g / cm 3 Above, about 2.2g / cm 3 More than about 2.25g / cm 3 Approximately 2.3g / cm 3 Above, about 2.35g / cm 3 Above, about 2.4g / cm 3 More than about 2.45g / cm 3 More than about 2.5g / cm 3 It can be formed as a material containing silicon, oxygen, and carbon having a density equal to or greater than that.

[0046]

[0048] Embodiments of Method 300 may further include exposing the silicon-oxygen-carbon material deposited in step 320 to ultraviolet (UV) treatment. In embodiments, the UV treatment may be carried out in a semiconductor processing chamber used for depositing the low dielectric constant material. However, it is also conceivable that the substrate having the deposited low dielectric constant material may be transferred to a separate semiconductor processing chamber in which the UV treatment step is carried out. In embodiments, the optional UV treatment in step 320 may expose a layer of silicon-oxygen-carbon material to ultraviolet light to provide a cured layer of the silicon-oxygen-carbon material. The treatment may produce a cured low dielectric constant material characterized by higher porosity and / or lower dielectric constant (κ value) than the deposited material.

[0047]

[0049] In some embodiments, the deposited silicon, oxygen, and carbon-containing material may be deposited to a thickness of about 750 Å or more, about 800 Å or more, about 850 Å or more, about 900 Å or more, about 950 Å or more, about 1,000 Å or more, about 1,100 Å or more, about 1,200 Å or more, about 1,300 Å or more, or greater. The deposited silicon, oxygen, and carbon-containing material may be deposited in two or more deposition and UV treatment cycles to construct the final UV-treated low dielectric constant material. For example, the number of deposition and treatment cycles may be about 3 or more cycles, about 5 or more cycles, about 10 or more cycles, about 15 or more cycles, about 20 or more cycles, about 30 or more cycles, about 40 or more cycles, about 50 or more cycles, or more.

[0048]

[0050] The preceding description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0049]

[0051] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art.

[0050]

[0052] Where a range of values ​​is provided, unless otherwise explicitly stated in the context, it is understood that each intermediary value between the upper and lower limits of that range is specifically disclosed down to the smallest unit of the lower limit. Any narrower range between any listed or unlisted intermediary values ​​within the stated range, and any other listed or intermediary values ​​within that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which one, neither, or both of the limit values ​​are included is also included in this technology, although there may be limit values ​​specifically excluded within the stated range. Where a stated range includes one or both of the limit values, ranges that exclude one or both of these included limit values ​​are also included.

[0051]

[0053] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless otherwise explicitly stated in the context. Thus, for example, “a layer” refers to multiple such layers, and “the precursor” refers to one or more precursors and their equivalents that are well known to those skilled in the art, and so on.

[0052]

[0054] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or processes, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, To provide a deposition precursor for a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a precursor containing silicon, oxygen, and carbon, and the substrate is disposed within the processing area. Forming plasma ejecta of the aforementioned deposition precursor, The method involves depositing a layer of material containing silicon, oxygen, and carbon on the substrate, wherein the layer of material containing silicon, oxygen, and carbon is characterized by a dielectric constant of about 4.5 or less, and the dielectric constant of the layer of material containing silicon, oxygen, and carbon is about 2.0 g / cm³. ３ The process involves depositing layers of a material containing silicon, oxygen, and carbon, characterized by the above densities. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the precursor containing silicon, oxygen, and carbon comprises dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, methoxy(dimethyl)silylmethane, or vinylmethyldimethoxysilane.

3. The semiconductor processing method according to claim 1, wherein the deposition precursor further comprises a nitrogen-containing precursor.

4. The nitrogen-containing precursor is ammonia (NH ３ The semiconductor processing method according to claim 3, including ).

5. The semiconductor processing method according to claim 3, wherein the flow rate ratio of the precursor containing silicon, oxygen, and carbon to the nitrogen-containing precursor is about 10:1 or less.

6. The semiconductor processing method according to claim 1, further comprising providing helium together with the deposition precursor, wherein the flow rate ratio of the silicon, oxygen, and carbon-containing precursor to the helium is about 1:1 or less.

7. The semiconductor processing method according to claim 1, wherein the plasma emission material is formed with a plasma output of approximately 1,500 W or less.

8. The semiconductor processing method according to claim 5, wherein the temperature inside the semiconductor processing chamber is maintained at approximately 250°C or higher.

9. The semiconductor processing method according to claim 1, wherein the pressure inside the semiconductor processing chamber is maintained at approximately 15 Torr or less.

10. The semiconductor processing method according to claim 1, wherein the layer of the material containing silicon, oxygen, and carbon is characterized by an oxygen content of about 20.0 at.% or more.

11. The semiconductor processing method according to claim 1, wherein the layer of the material containing silicon, oxygen, and carbon has a nitrogen content of about 20.0 at.% or less.

12. A semiconductor processing method, To provide a deposition precursor for a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a precursor containing silicon, oxygen, and carbon, and a nitrogen-containing precursor, and the substrate is disposed within the processing area. Forming plasma ejecta of the aforementioned deposition precursor, The method involves depositing a layer of a material containing silicon, oxygen, and carbon on the substrate, wherein the layer of the material containing silicon, oxygen, and carbon is characterized by an oxygen content of approximately 25.0 at.% or more, and the layer of the material containing silicon, oxygen, and carbon is characterized by a dielectric constant of approximately 4.2 or less. A semiconductor processing method, including the following.

13. The semiconductor processing method according to claim 12, wherein the precursor containing silicon, oxygen, and carbon includes dimethyldimethoxysilane.

14. The semiconductor processing method according to claim 12, wherein the flow rate ratio of the precursor containing silicon, oxygen, and carbon to the nitrogen-containing precursor is about 10:1 or less.

15. The semiconductor processing method according to claim 14, wherein the plasma emission material is formed with a plasma output of approximately 1,000 W or less.

16. The layer of the material containing silicon, oxygen, and carbon has a density of 0.001 A / cm². ２ The semiconductor processing method according to claim 12, characterized by a breakdown voltage of approximately 6.5 MV / cm or more.

17. The semiconductor processing method according to claim 12, wherein the temperature within the processing area is maintained at approximately 500°C or lower.

18. A semiconductor processing method, To provide a deposition precursor for a semiconductor processing chamber, wherein the deposition precursor comprises a precursor containing silicon, oxygen, and carbon, a substrate is disposed within the processing chamber, and the precursor containing silicon, oxygen, and carbon comprises dimethyldimethoxysilane. Forming plasma ejecta of the aforementioned deposition precursor, The method involves depositing a layer of a material containing silicon, oxygen, and carbon on the substrate, wherein the layer of the material containing silicon, oxygen, and carbon is characterized by an oxygen content of about 25.0 at.% or more, a dielectric constant of about 4.2 or less, and a density of about 2.0 or more. A semiconductor processing method, including the following.

19. The semiconductor processing method according to claim 18, wherein the deposition rate of the layer of the material containing silicon, oxygen, and carbon is 500 Å / min or more.

20. The layer of the material containing silicon, oxygen, and carbon has a density of approximately 2 E-0.8 A / cm at 2 MV / cm. ２ The semiconductor processing method according to claim 18, characterized by the following leakage current.

Images