Wide bandgap trench gate semiconductor device with embedded gate

Abstract

A wide-bandgap trench-gate semiconductor device is provided. In one example, the semiconductor device comprises a wide-bandgap semiconductor structure. The wide-bandgap semiconductor structure comprises a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device comprises a gate trench within the wide-bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device comprises an embedded gate structure within the gate trench. The embedded gate structure comprises a gate polysilicon layer and a gate silicide layer.

Description

Detailed description of the invention

[0001] [Claiming priority] This application is based on U.S. Patent Application No. 18 / 449,458, filed on 14 August 2023, and claims priority to said U.S. Patent Application. This application claims priority and benefits to the entirety of the cited application, which is incorporated herein by reference. [Field] This disclosure generally relates to semiconductor devices. [background] Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art, including, for example, power metal-oxide-semiconductor field-effect transistors ("MOSFETs"), bipolar junction transistors ("BJTs"), insulated-gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS-controlled thyristors, and various other devices. These power semiconductor devices can be fabricated from wide-bandgap semiconductor materials such as silicon carbide ("SiC") and / or gallium nitride ("GaN") based semiconductor materials. [overview] Aspects and advantages of the embodiments of this disclosure will be partially described in the following description, may be learned from the description, or may be learned through the implementation of the embodiments.

[0002] One exemplary embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a wide-bandgap semiconductor structure. The wide-bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench within the wide-bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes an embedded gate structure within the gate trench. The embedded gate structure includes a gate polysilicon layer and a gate silicide layer.

[0003] Another exemplary embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a wide-bandgap semiconductor structure. The wide-bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench within the wide-bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a gate structure within the gate trench. The semiconductor device includes a dielectric layer on the gate structure within the gate trench. The semiconductor device includes a spacer layer between the dielectric layer and the sidewall of the gate trench within the gate trench. The semiconductor device includes a gate dielectric layer between the gate structure and the drift region within the gate trench.

[0004] Another exemplary embodiment of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a gate trench within a wide-bandgap semiconductor structure. The method includes forming an embedded gate structure within the gate trench. The embedded gate structure includes a gate polysilicon layer and a gate silicide layer. The method includes forming a dielectric layer on the embedded gate structure within the gate trench.

[0005] These and other features, aspects of various embodiments, and advantages will be better understood by referring to the following description and the appended claims. The appended drawings incorporated into and constituting parts thereof illustrate embodiments of the present disclosure and, together with the description, illustrate the relevant principles. [Brief explanation of the drawing]

[0006] A detailed discussion of embodiments intended for those skilled in the art is provided in the specification, which refers to the attached drawings. [Figure 1] This diagram depicts a cross-sectional view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 2] This diagram depicts a cross-sectional view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 3] It depicts a cross-sectional view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 4] It depicts a cross-sectional view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 5] It depicts a cross-sectional view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 6] It depicts a flowchart of an exemplary method according to an exemplary embodiment of the present disclosure. [Figure 7] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 8] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 9] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 10] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 11] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 12] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 13] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 14] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 15] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 16] It depicts an exemplary manufacturing aspect of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF EMBODIMENTS FOR CARRYING OUT THE INVENTION

[0007] [Detailed explanation] One or more examples of embodiments are illustrated in the drawings with detailed reference thereto. Each example is provided for the description of the embodiments and is not a limitation of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the disclosure. For example, features illustrated or described as part of one embodiment can be used, together with another embodiment, to produce yet another embodiment. Thus, aspects of the disclosure are intended to cover such modifications and variations.

[0008] A power semiconductor device may have a semiconductor substrate having a first conductivity type (e.g., an n-type substrate), such as a silicon carbide substrate, on which an epitaxial layer structure (e.g., n-type) having the first conductivity type (e.g., n-type) is formed. (This epitaxial layer structure may include one or more distinct layers.) A portion of this epitaxial layer structure functions as a drift region of the power semiconductor device. The device typically includes an "active region" containing one or more power semiconductor devices having a junction, such as a pn junction. The active region may be formed on and / or within the drift region. The active region functions as a primary junction for blocking voltage in the reverse bias direction and allowing current to flow in the forward bias direction. The power semiconductor device may have a unit cell structure containing a plurality of separate "unit cell" devices, where the active regions of each power semiconductor device are electrically connected in parallel and together function as a single power semiconductor device.

[0009] Power semiconductor devices are often fabricated from wide-bandgap semiconductor materials such as silicon carbide or Group III nitride-based semiconductor materials (e.g., gallium nitride). In this specification, a wide-bandgap semiconductor material refers to a semiconductor material having a bandgap greater than 1.40 eV. The aspects of this disclosure are discussed with reference to silicon carbide-based semiconductor structures as wide-bandgap semiconductor structures. Those skilled in the art will understand, by using the disclosures provided herein, that power semiconductor devices according to exemplary embodiments of this disclosure may be used with any semiconductor material, including other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Exemplary wide-bandgap semiconductor materials include silicon carbide (e.g., alpha-silicon carbide with a bandgap of 2.996 eV at room temperature) and Group III nitrides (e.g., gallium nitride with a bandgap of 3.36 eV at room temperature).

[0010] Power semiconductor devices may have a lateral or vertical structure. In a device with a lateral structure, the device terminals (e.g., drain terminal, gate terminal, and source terminal of a power MOSFET device) are located on the same main surface of the semiconductor structure (e.g., top or bottom surface). In contrast, in a power semiconductor device with a vertical structure, at least one terminal is provided on each main surface of the semiconductor structure. For example, in a vertical MOSFET device, the source may be on the top surface of the semiconductor structure, and the drain may be on the bottom surface of the semiconductor structure. In this specification, the term “semiconductor structure” refers to a structure comprising a semiconductor substrate and / or one or more semiconductor layers, such as a semiconductor epitaxial layer.

[0011] Vertical power semiconductor devices, including MOSFET or IGBT transistors, may have a standard gate electrode design where the transistor's gate electrode is formed on top of the semiconductor structure. Alternatively, the power semiconductor device may have the gate electrode within a gate trench within the semiconductor structure. Power semiconductor devices with trench gate electrodes are typically referred to as trench-gate devices (e.g., trench-gate MOSFETs or trench-gate IGBTs). In a standard gate electrode design, the channel region of each unit cell transistor is positioned horizontally below the gate electrode. In contrast, in a trench-gate design, the channel is positioned vertically. Trench-gate devices can offer improved performance but may require more complex manufacturing processes.

[0012] Silicon carbide-based trench-gate vertical power devices can be attractive due to their inherently low on-resistivity, which can result in more efficient operation for power switching operations requiring low to moderate reverse blocking voltage levels (e.g., around 650–1200V). Trench-gate vertical power devices can exhibit lower resistivity during on-state operation because the channel is formed in the sidewall of the gate trench, and the trench design reduces the overall pitch of the device, allowing for increased integration. Furthermore, it has been found that the carrier mobility in the sidewall channels of trench-gate power semiconductor devices (e.g., trench-gate MOSFETs) is 2–4 times higher than the corresponding carrier mobility in the channels of planar (e.g., lateral structure) devices. This increased carrier mobility also increases current density.

[0013] Scaling trench gate devices to smaller geometries may be desirable to increase cell density, power density, and / or reduce the on-resistance of trench gate semiconductor devices. However, the complexity inherent in the geometries of trench gate semiconductor devices can present challenges in scaling. For example, using contact holes or metallized vias to connect source contacts to well tie-in regions adjacent to gate trenches can increase the unit cell pitch (e.g., lateral distance). In addition, having trench gate electrodes exposed through the trench surface may require contact masking and contact etching geometry, which can further increase the unit cell pitch.

[0014] Exemplary aspects of this disclosure relate to trench-gate semiconductor devices (e.g., trench-gate MOSFETs, trench-gate IGBTs) having embedded gate contacts within a gate trench of the semiconductor device. The gate trench may be within a wide-bandgap semiconductor structure (e.g., a silicon carbide semiconductor structure). In some examples, the gate structure for the semiconductor device may be a multilayer gate structure comprising a first gate layer (e.g., a gate polysilicon layer) and a second gate layer (e.g., a gate silicide layer) on the first gate layer. According to examples of this disclosure, the multilayer gate structure is completely embedded within the gate trench such that no portion of the gate structure is located above or outside the gate trench. For example, the gate structure may be covered within the gate trench (e.g., by one or more dielectric layers).

[0015] In some examples, a semiconductor device has a metallization layer on a semiconductor structure. The metallization layer may be, for example, a source metallization layer for the semiconductor device. The semiconductor device may also have a dielectric layer (e.g., a silicate glass layer) on a gate structure in a gate trench (e.g., covering the gate structure). In some examples, the dielectric layer may have a surface that is coplanar with the top surface of the semiconductor structure. The metallization layer may have a flat surface that is in contact with the semiconductor structure and the dielectric layer. In some examples, the dielectric layer electrically insulates the gate structure embedded in the gate trench from the metallization layer.

[0016] In some examples, the gate structure includes a gate silicide layer. The gate silicide layer may be made of a different material from the silicide layer on the well-tie-in region of the semiconductor device adjacent to the gate structure (for example, to provide ohmic contacts). In some examples, the silicide layer of the gate structure is made of the same material as the silicide layer on the well-tie-in region of the semiconductor device.

[0017] In some cases, the gate silicide layer is tantalum silicide Ta y S ix or tungsten silicide W y Si x This includes, where x is in the range of approximately 2.0 to approximately 3.0. In these examples, the gate silicide layer may be stable at the high temperatures required to planarize the dielectric layer in the gate trench and / or to subsequently form the silicide layer on the well tie-in region of the semiconductor structure. In some examples, the silicide layer on the well tie-in region of the semiconductor device includes nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, aluminum titanium silicide, nickel titanium aluminum silicide, or titanium tungsten silicide.

[0018] In some examples, semiconductor devices may include an electric field shielding region below the gate trench. For example, the semiconductor region below the gate dielectric layer at the bottom of the gate trench may be doped in the opposite direction (p in the case of nMOSFETs or nIGBTs). + By using this, electric field shielding of the gate dielectric layer at the bottom of the gate trench can be provided. The shielded region reduces the electric field experienced by the gate dielectric layer, and consequently can prevent dielectric breakdown and / or premature dielectric wear.

[0019] Aspects of this disclosure offer technical effects and advantages. For example, aspects of this disclosure may enable better scaling of wide-bandgap semiconductor device cells (e.g., trench-gate MOSFET cells and trench-gate IGBT cells) by embedding and metallizing gate electrodes in trenches to reduce the need for contact masking and contact etching shapes that contribute to the pitch within each cell. In addition, the gate bus structure that consumes active area can be reduced due to the metallized gate structure (e.g., a multilayer gate structure with a gate silicide layer). Because the gate structure is embedded, the surface area is flat, and the source metallization contacts the source and well-tie regions without penetrating the contacts or using metallized plugs in contact holes when connecting to the source and well-tie regions. The cell structure is fully self-aligned because there is no need for contact photography / etching steps to form contact openings. The self-aligning nature of cells with embedded gate metallization is a significant advantage for scaling cells to smaller shapes, enabling increased cell density and power density, and reduced relative on-resistance. In addition, by reducing the cell pitch and implementing a thick bottom dielectric with bottom field shielding underneath, at least one separate field reduction p + The need for doping columns is reduced.

[0020] While terms such as "first," "second," etc., may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. Where used herein, the term "and / or" includes any and all combinations of one or more of the items listed relating to the subject.

[0021] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. It will be further understood that the terms “equipped,” “equipped,” “contains,” and / or “contains” as used herein identify the presence of a described feature, integer, process, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, processes, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Terms used herein should be construed to have meanings consistent with their meanings in the context of this specification and the related art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless expressly defined herein.

[0023] When an element such as a layer, region, or substrate is said to be “on top of” or “extending upward” another element, it will be understood that it may be directly on top of or directly extending upward from the other element, or there may be an intervening element. In contrast, when an element is said to be “directly on top of” or “extending directly upward” another element, there is no intervening element. Similarly, when an element is said to be “connected” or “joined” to another element, it will be understood that it may be directly connected or joined to the other element, or there may be an intervening element. In contrast, when an element is said to be “directly connected” or “directly joined” to another element, there is no intervening element. Relative terms such as “below,” “up,” “top,” “bottom,” “horizontal,” “lateral,” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region, as illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device, in addition to the orientation depicted in the drawing.

[0024] Embodiments of the present disclosure are described herein with reference to cross-sectional drawings, which are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. Thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, variations from the illustrated shapes are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to specific shapes of regions illustrated herein, and should include, for example, deviations of shape resulting from manufacturing. Similarly, it will be understood that dimensional variations are to be expected based on the standard deviation in the manufacturing procedure. As used herein, “approximately” or “about” includes values ​​within 10% of the nominal value.

[0025] Throughout, similar numbers refer to similar elements. Therefore, the same or similar numbers may be explained by reference to other drawings, even if they are not mentioned or explained in the corresponding drawings. Similarly, elements not indicated by reference numbers may be explained by reference to other drawings.

[0026] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, an N-type material has a majority equilibrium concentration of negatively charged electrons, while a P-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with "+" or "-" (such as N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region. However, such notation does not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0027] Aspects of this disclosure are discussed with reference to silicon carbide-based transistor devices for illustrative and illustrative purposes. Those skilled in the art will understand, by using the disclosures provided herein, that certain aspects of this disclosure may be applicable to other transistor devices without departing from the scope of this disclosure.

[0028] Typical embodiments are disclosed in the drawings and specification, and certain terms are used, but these are used only in a general and descriptive sense and are not intended to limit the scope of the claims below.

[0029] Figure 1 depicts a cross-sectional view of an exemplary unit cell of an exemplary trench-gate power semiconductor device 100 according to an exemplary embodiment of the present disclosure. The power semiconductor device 100 in Figure 1 is a silicon carbide-based trench-gate MOSFET. Figure 1 is intended to represent a structure for identification and illustrative purposes and is not intended to represent a structure on a physical scale.

[0030] The power semiconductor device 100 comprises a highly doped (n+) n-type silicon carbide substrate 102. The power semiconductor device 100 comprises a wide bandgap semiconductor structure 104 (e.g., silicon carbide) on the silicon carbide substrate 102. The wide bandgap semiconductor structure 104 may be epitaxially formed on the substrate 102.

[0031] The wide bandgap semiconductor structure 104 may comprise a lightly doped (n-) silicon carbide drift region 106 on the substrate 102. The lightly doped silicon carbide drift region 106 may be formed on the substrate 102 by, for example, epitaxial growth.

[0032] A moderately doped p-type silicon carbide well region 108 is disposed on the drift region 106. The moderately doped p-type well region 108 may provide a p-well for the power semiconductor device 100. The moderately doped p-type well region 108 may be formed by, for example, epitaxial growth.

[0033] A highly doped (n+) n-type silicon carbide layer 110 is disposed on the well region 108. The highly doped n-type silicon carbide layer 110 may form a well tie-in region for the semiconductor device 100. The highly doped n-type silicon carbide layer 110 may be formed at least partially using ion implantation, for example.

[0034] The semiconductor device comprises a gate trench 120 within the wide bandgap semiconductor structure 104. The gate trench 120 extends through the highly doped n-type silicon carbide layer 110 and the well region 108 into the drift region 106. A gate dielectric layer 122 may be disposed along the bottom surface and sidewalls of the gate trench 120. The gate dielectric layer 122 may be, for example, an oxide film layer. In some examples, the gate dielectric layer 122 is made of SiO2, SiN, Al2O3, MgO x , MgN x , ZnO, SiN x , SiO xIt includes one or more of the following. In the example of Figure 1, the gate dielectric layer 122 may have a thickness T1. The thickness T1 may be in the range of, for example, about 150 angstroms to about 550 angstroms, for example, about 250 angstroms to about 550 angstroms, for example, about 300 angstroms to about 400 angstroms. The vertical channel region is provided to the well region 108 adjacent to the gate dielectric layer 122.

[0035] The power semiconductor device 100 may include an electric field shielding region 125 below the gate trench 120. The electric field shielding region 125 may be, for example, highly doped (p+) silicon carbide formed on the upper surface of the drift region 106 by ion implantation. The shielding region 125 may be effective in protecting the corners of the gate dielectric layer 122 from high electric fields during reverse blocking operation. The shielding region 125 may provide shielding for the gate dielectric layer 122 and may provide desired device performance resulting from utilizing the two sidewall surfaces for current conduction.

[0036] According to exemplary aspects of this disclosure, the gate structure 130 may be embedded within the gate trench 120. More specifically, the gate structure 130 may be entirely within the gate trench 120, with no portion of the gate structure 130 extending outside the gate trench 120. In some examples, the upper surface of the gate structure 130 may be at least about 1000 angstroms to about 4000 angstroms below the top of the gate trench 120, for example, about 1500 angstroms to about 3500 angstroms below the top of the gate trench 120, for example, about 2000 angstroms to about 3000 angstroms below the top of the gate trench 120.

[0037] The gate structure 130 may be a multilayer gate structure and may include a first gate layer 132 and a second gate layer 134. The first gate layer 132 may be, for example, a polysilicon layer and may be referred to as a gate polysilicon layer. The second gate layer 134 may be, for example, a silicide layer and may be referred to as a gate silicide layer.

[0038] In some examples, as shown in Figure 1, the first gate layer 132 (e.g., a gate polysilicon layer) may have a width W1. The second gate layer 134 (e.g., a gate silicide layer) may have a width W2 at the interface between the first gate layer 132 and the second gate layer 134. The width W2 may be smaller than the width W1. In some examples, the second gate layer 134 (e.g., a gate silicide layer) may have a variable width. The second gate layer 134 (e.g., a gate silicide layer) may have curved or arched sidewalls. The second gate layer 134 may have other suitable shapes without departing from the scope of this disclosure.

[0039] In some examples, the second gate layer 134 (e.g., the gate silicide layer) is made of tantalum silicide (Ta y Si x ) and / or tungsten silicide (W y Si x ) includes. In some embodiments, x may be in the range of about 2.0 to about 3.0.

[0040] In some examples, the interface between the first gate layer 132 and the second gate layer 134 may be located at a depth within the gate trench 120 that is close to the depth of the interface between the well region 108 and the highly doped silicon carbide layer 110 (which forms the well tie-in region). For example, the interface between the first gate layer 132 and the second gate layer 134 may be located above the interface between the well region 108 and the highly doped silicon carbide layer 110, at a distance in the range of approximately 0 nm to approximately 500 nm, for example, approximately 0 nm to approximately 250 nm, or for example, approximately 50 nm to approximately 100 nm.

[0041] The semiconductor device 100 may include a spacer layer 124 within the gate trench 120. As will be described in detail below, the spacer layer 124 can facilitate the formation of a second gate layer 134 (e.g., a gate silicide layer) of the gate structure 130 within the gate trench 120. The spacer layer 124 may be at least partially on the gate dielectric layer 122 and the first gate layer 132 (e.g., a gate polysilicon layer) of the gate structure 130. The spacer layer 124 may be between at least a portion of the gate structure 130 and the sidewall of the gate trench 120. For example, the spacer layer 124 may be between the second gate layer 134 (e.g., a gate silicide layer) and the sidewall of the gate trench 120. In some examples, the spacer layer 124 may be a dielectric material. In some examples, the spacer layer 124 is an oxide. In some examples, the spacer layer 124 is silicon dioxide or silicon nitride. Without departing from the scope of this disclosure, other suitable dielectric materials may be used as the spacer layer 124. For example, in some examples, the spacer layer 124 may be, for example, SiO2, Si3N4, Al2O3, MgO x MgN x ZnO, SiN x SiO x It may include one or more of the following.

[0042] The semiconductor device 100 may further include a dielectric layer 126 within a gate trench 120. The dielectric layer 126 may be on top of a second gate layer 134 (e.g., a gate silicide layer) of the gate structure 130. The dielectric layer 126 may cover the gate structure 130 within the gate trench 120. The dielectric layer 126 may be within an opening defined within a spacer layer 124. The dielectric layer 126 may have a surface that is coplanar with the surface (e.g., the top surface) of the wide-bandgap semiconductor structure 104. In some examples, the dielectric layer 126 is silicate glass. For example, the dielectric layer 126 may include borosilicate glass and / or borophosphosilicate glass (BPSG). Without departing from the scope of this disclosure, other suitable dielectric materials may be used as the dielectric layer 126. The dielectric layer 126 can electrically insulate the metallization layer 142 (e.g., the source metallization layer) from the gate structure 130 embedded in the gate trench 120.

[0043] More specifically, the semiconductor device 100 may be a vertical semiconductor device having a metallization layer 142 (e.g., a source metallization layer) on the upper surface of a wide-bandgap semiconductor structure 104. The semiconductor device 100 may include a metallization layer 144 (e.g., a drain metallization layer) on the lower surface of a substrate 102. The metallization layers 142 and 144 may be a single material or may include a multilayer structure using different materials. The metallization layers 142 and / or 144 may include a metal suitable for forming ohmic contact with the wide-bandgap semiconductor structure 104. For example, the metallization layer 142 and / or metallization layer 144 may be titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), nickel silide (NiSi). x ), Titanium Silicide (TiSi xIt may contain one or more of the following: titanium nitride (TiN), tungsten silicon nitride (WSiN), platinum (Pt), etc.

[0044] According to exemplary aspects of this disclosure, the metallization layer 142 may be a flat metallization layer 142. The metallization layer 142 may be in direct contact with the dielectric layer 126. In some examples, the metallization layer 142 may be in direct contact with the spacer layer 124.

[0045] The metallization layer 142 may come into contact with the wide-bandgap semiconductor structure 104. For example, the metallization layer 142 may come into contact with the wide-bandgap semiconductor structure 104 via a well-tie in silicide layer 112 on the upper surface of the wide-bandgap semiconductor structure 104. The well-tie in silicide layer 112 may facilitate the formation of ohmic contact between the metallization layer 142 and the wide-bandgap semiconductor structure 104.

[0046] In some examples, the well-tie in silicide layer 112 is made of the same material as the second gate layer 134 (e.g., the gate silicide layer) of the gate structure 130. In some examples, the well-tie in silicide layer 112 is made of a different material than the second gate layer 134 (e.g., the gate silicide layer) of the gate structure. In some examples, the well-tie in silicide layer 112 is one or more of nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, titanium aluminum aluminum silicide, nickel titanium silicide, or titanium tungsten silicide.

[0047] The metallization layer 142 can contact the well tie-in region of the wide bandgap semiconductor structure 104 without penetrating into contact holes or using metallized plugs. This can facilitate a reduction in the unit cell pitch of the power semiconductor device 100, thereby increasing scalability.

[0048] For example, Figure 2 depicts two exemplary unit cells adjacent to each other in a semiconductor device 100 according to an exemplary embodiment of the present disclosure. The power semiconductor device 100 in Figure 2 is a silicon carbide-based trench-gate MOSFET. Figure 2 is intended to represent structures for identification and illustrative purposes and not to represent structures to a physical scale. Because the gate structure 130 is embedded in the gate trench 120 and the metallization layer 142 and dielectric layer 126 are planar, the width W3 of the wide bandgap semiconductor structure 104 between the gate trenches can be reduced. In some examples, the width W3 may be in the range of about 25 nm to about 2000 nm, e.g., about 100 nm to about 1000 nm, e.g., about 200 nm to about 750 nm. This can result in a reduction of the pitch P1 of the unit cells in the semiconductor device 100. In some cases, the pitch P1 may be in the range of approximately 50 nm to approximately 4000 nm, for example, approximately 200 nm to approximately 2000 nm, or for example, approximately 400 nm to approximately 1500 nm.

[0049] Figure 3 depicts two adjacent exemplary unit cells in a semiconductor device 100 according to an exemplary embodiment of the present disclosure. The power semiconductor device 100 in Figure 3 is a silicon carbide-based trench-gate MOSFET. Figure 3 is intended to represent a structure for identification and illustrative purposes and not to represent the structure to a physical scale. The semiconductor device 100 in Figure 3 is similar to the semiconductor device in Figure 1, except that the semiconductor device includes an additional field shielding region 127 below the gate trench 120. In the example in Figure 3, the semiconductor device 100 includes stacked field shielding regions 125, 127. More specifically, the first field shielding region 125 is stacked with the second shielding region 127 below the gate trench 120. In some examples, the additional shielding regions may be stacked until the electric field is reduced to a target level. In some examples, the shielding regions 125 and / or 127 and / or well region 110 may be connected to a source metallization 142.

[0050] Figure 4 depicts a cross-sectional view of an exemplary unit cell of a semiconductor device 150 according to an exemplary embodiment of the present disclosure. The power semiconductor device 100 in Figure 4 is a silicon carbide-based trench-gate MOSFET. Figure 4 is intended to represent structures for identification and illustrative purposes and is not intended to represent structures to a physical scale. The semiconductor device 150 in Figure 4 is similar to the semiconductor device 100 in Figure 1, except that the semiconductor device 150 has a thicker gate dielectric layer 122 within the gate trench 120 between the gate structure 130 and the drift region 106. In some examples, the gate dielectric layer 122 in the example of Figure 4 may have a thickness T2. The thickness T2 may be in the range of about 500 angstroms to about 2500 angstroms, e.g., about 750 angstroms to about 2000 angstroms, e.g., about 1000 angstroms to about 1750 angstroms.

[0051] Figure 5 depicts a cross-sectional view of an exemplary unit cell of a semiconductor device 160 according to an exemplary embodiment of the present disclosure. The power semiconductor device 100 in Figure 5 is a silicon carbide-based trench gate IGBT. Figure 5 is intended to represent a structure for identification and illustrative purposes and is not intended to represent the structure to a physical scale. The semiconductor device 160 is similar to the semiconductor device 100 in Figure 4, except that the semiconductor device 160 is an IGBT. The semiconductor device 160 includes a moderately doped n-type silicon carbide field stop layer 162. The substrate may also be a highly doped p-type silicon carbide emitter layer 164.

[0052] Figure 6 illustrates a flowchart of an exemplary method 200 for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 6 depicts exemplary process steps for illustrative and illustrative purposes. Using the disclosures provided herein, a person skilled in the art will understand that process steps of any method described herein may be adapted, modified, with the addition, omission, and / or rearrangement of steps not shown without departing from the scope of the disclosure.

[0053] In 202, Method 200 may include forming a wide-bandgap semiconductor structure (e.g., a silicon carbide semiconductor structure) on a substrate (e.g., a silicon carbide substrate). For example, as shown in Figure 7, the Method may include forming a wide-bandgap semiconductor structure 104 on a substrate 102. The wide-bandgap semiconductor structure 104 may be formed using, for example, epitaxial growth. As shown, the silicon carbide semiconductor structure 104 may include a low-doped (n-) silicon carbide drift region 106 on the substrate 102. The low-doped silicon carbide drift region 106 may be formed on the substrate 102 by, for example, epitaxial growth. The wide-bandgap semiconductor structure 104 may include a medium-doped p-type silicon carbide well region 108 on the drift region 106. The medium-doped p-type well region 108 may be formed by, for example, epitaxial growth. The wide-bandgap semiconductor structure 104 may include a highly doped n-type silicon carbide layer 110 on the well region 108. The highly doped n-type silicon carbide layer 110 may be formed, for example, by using ion implantation, at least partially.

[0054] In 204, method 200 may include forming a gate trench within a wide-bandgap semiconductor structure. For example, as shown in Figure 8, the method may include forming a gate trench 120 within a wide-bandgap semiconductor structure 104. The gate trench 120 may extend through a highly doped n-type silicon carbide layer 110, a well region 108, into a drift region 106. In some examples, an electric field shielding region 125 may be formed beneath the gate trench 120, for example, by ion implantation.

[0055] In 205, the method may include forming an embedded gate structure within a gate trench. The embedded gate structure may be a multilayer gate structure. For example, the embedded gate structure may include a gate polysilicon layer and a gate silicide layer on the gate polysilicon layer.

[0056] More specifically, in some examples, method 200 may include forming a gate dielectric layer in the gate trench in 206. For example, as shown in Figure 9, the method may include forming a gate dielectric layer 122 on the bottom and side walls of the gate trench 120. The gate dielectric layer 122 may be an oxide and may be formed using an oxidation process or a suitable deposition process. In some examples, the gate dielectric layer 122 may be SiO2, SiN, Al2O3, MgO x MgN x ZnO, SiN x SiO x It may include one or more of the following. The portion of the gate dielectric layer 122 may be etched off after deposition to form the structure of the gate dielectric layer 122 as shown in Figure 9.

[0057] In 208, Method 200 may include forming a gate polysilicon layer on a gate dielectric layer. For example, as shown in Figure 10, the Method may include forming a first gate layer 132 (e.g., a gate polysilicon layer) of the gate structure on a gate dielectric layer 122. The gate polysilicon layer may be formed using a suitable deposition process. In some examples, the gate polysilicon layer may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, an atomic layer deposition (ALD) process, or other suitable deposition process. A portion of the gate polysilicon layer may be etched off after deposition to form the structure shown in Figure 10.

[0058] In 210, Method 200 may include forming a spacer layer within a gate trench. For example, as shown in Figure 11, the Method may include depositing a spacer material for a spacer layer 124 within a gate trench 120. The spacer material may extend from the gate trench 120 and be at least partially on the upper surface of the wide-bandgap semiconductor structure 104. The spacer material may be formed using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other suitable deposition process. The spacer material may include a dielectric material such as silicon dioxide, silicon nitride, or other suitable dielectric material. For example, in some examples, the spacer material may be, for example, SiO2, Si3N4, Al2O3, MgO x MgN x ZnO, SiN x SiO x It could be one or more of the following.

[0059] As shown in Figure 12, the method may include etching holes into the spacer material to form a spacer layer 124 within the gate trench. At least a portion of the spacer material may remain on the upper surface of the wide-bandgap semiconductor structure 104. This may help mask at least a portion of the wide-bandgap semiconductor structure 104 during future gate formation steps (e.g., formation of the gate silicide layer), thereby reducing the formation of silicides, for example, on the wide-bandgap semiconductor structure 104 during future process steps. Any suitable etching process may be used to etch holes into the spacer material, such as a wet etching process or a plasma-based dry etching process.

[0060] Referring to Figure 6, part 212, Method 200 may include forming a gate silicide layer on a gate polysilicon layer. For example, as shown in Figure 13, the Method may include forming a second gate layer 134 (e.g., a gate silicide layer) in a hole in the spacer layer 124. The second gate layer 134 (e.g., a gate silicide layer) may be entirely within the gate trench 120. In some examples, the second gate layer 134 (e.g., a gate silicide layer) may be made of tantalum silicide Ta y S ix or tungsten silicide W y Si x This includes, where x is in the range of about 2.0 to about 3.0. The second gate layer 134 (e.g., gate silicide layer) can be formed using any suitable process for forming silicide on the first gate layer 132 (e.g., polysilicon layer). For example, one or more metal deposition steps (e.g., tantalum deposition and / or tungsten deposition) and annealing steps can be performed to form the second gate layer (e.g., gate silicide layer).

[0061] In 214, Method 200 may include forming a dielectric layer within a gate trench. For example, as shown in Figure 14, the Method may include forming a dielectric material for a dielectric layer 126 within a gate trench 120. The dielectric material may extend from the gate trench 120. The dielectric material may be formed using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other suitable deposition process. In some examples, the dielectric layer may be a silicate glass such as borosilicate glass or borophosphosilicate glass.

[0062] As shown in Figure 15, forming a dielectric layer within a gate trench may include planarizing the dielectric layer 126 so that its upper surface is coplanar with the upper surface of the wide-bandgap semiconductor structure 104. For example, the method may include etching the dielectric layer 126 and / or the spacer layer 124 so that its upper surface and the spacer layer 124 are coplanar with the upper surface of the semiconductor structure 104. Planarizing the dielectric layer 126 and / or the spacer layer 124 may be performed using a wet etching process and / or a plasma-based dry etching process.

[0063] As shown in Figure 6-216, the method may include forming a silicide layer on a wide-bandgap semiconductor structure. The silicide layer can facilitate ohmic contact between the metallization layer (e.g., source metallization layer) and the wide-bandgap semiconductor structure 104. The silicide layer may be, for example, nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, titanium aluminum aluminum aluminum aluminum aluminum silicide, or titanium tungsten silicide. The silicide layer may be formed using any suitable process for forming silicide on the wide-bandgap semiconductor structure 104. For example, one or more metal deposition steps and annealing steps may be implemented to form the silicide layer. Figure 16 depicts a silicide layer 112 formed on the wide-bandgap semiconductor structure 104.

[0064] In 218, the method may include forming a metallization layer on a silicide layer. The metallization layer may include a flat surface that is in direct contact with the dielectric layer and the wide-bandgap semiconductor structure within the gate trench. For example, as shown in Figure 16, the method may include forming a metallization layer 142 (e.g., a source metallization layer) such that the flat surface of the metallization layer 142 is in direct contact with the dielectric layer 126 and the wide-bandgap semiconductor structure 104.

[0065] The metallization layer 142 may contain a metal suitable for forming ohmic contact with the wide-bandgap semiconductor structure 104. For example, the metallization layer 142 may contain titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), nickel silide (NiSi) x ), Titanium Silicide (TiSi x The metallization layer 142 may contain one or more of the following: titanium nitride (TiN), tungsten silicon nitride (WSiN), platinum (Pt), etc. The metallization layer 142 may be formed using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other suitable deposition process.

[0066] Exemplary aspects of this disclosure are described below. Any of the following features or examples may be used in combination with any of the embodiments or features provided in this disclosure. One exemplary embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a wide-bandgap semiconductor structure. The wide-bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench within the wide-bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes an embedded gate structure within the gate trench. The embedded gate structure includes a gate polysilicon layer and a gate silicide layer.

[0067] In some examples, the upper surface of the gate silicide layer is below the upper surface of the wide-bandgap semiconductor structure. In some examples, the embedded gate structure is covered within the gate trench.

[0068] In some examples, the gate silicide layer is Ta y Six or W y Si x It includes the following. In some examples, x is in the range of approximately 2.0 to approximately 3.0. In some examples, the gate polysilicon layer has a different width than the gate silicide layer. In some examples, the gate polysilicon layer is located between the gate silicide layer and the bottom surface of the gate trench. In some examples, the gate silicide layer is closer to the top surface of the wide bandgap semiconductor structure than the gate polysilicon layer.

[0069] In some examples, the semiconductor device includes a dielectric layer within a gate trench on a buried gate structure. In some examples, the semiconductor device includes a metallization layer on a wide-bandgap semiconductor structure. The metallization layer has a flat surface in contact with the wide-bandgap semiconductor structure and the dielectric layer. In some examples, the dielectric layer is arranged to electrically insulate the buried gate structure from the metallization layer. In some examples, the dielectric layer has an upper surface that is coplanar with the upper surface of the semiconductor structure. In some examples, the dielectric layer is silicate glass.

[0070] In some examples, the semiconductor device includes a spacer layer within the gate trench, the spacer layer being located between at least a portion of the embedded gate structure and the sidewall of the gate trench. In some examples, the spacer layer comprises silicon dioxide or silicon nitride. In some examples, the spacer layer is located between at least a portion of the dielectric layer on the embedded gate structure and the sidewall of the gate trench.

[0071] In some examples, semiconductor devices include a gate dielectric layer between the embedded gate structure and the drift region. In some examples, the gate dielectric layer has a thickness between the embedded gate structure and the bottom surface of the embedded gate structure, and this thickness is in the range of about 250 angstroms to about 2500 angstroms.

[0072] In some examples, the semiconductor structure comprises a second silicide layer on the upper surface of the wide-bandgap semiconductor structure. In some examples, the second silicide layer is made of a different material from the gate silicide layer. In some examples, the second silicide layer includes nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, titanium aluminum aluminum aluminum aluminum aluminum aluminum silicide, or titanium tungsten silicide.

[0073] In some examples, the wide-bandgap semiconductor structure further includes a shielding region beneath the gate trench, and this shielding region has a second conductivity type. In some examples, wide-bandgap semiconductor structures contain silicon carbide.

[0074] In some examples, the semiconductor device is a MOSFET. In some examples, the semiconductor device is an insulated-gate bipolar transistor (IGBT).

[0075] Another exemplary embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a wide-bandgap semiconductor structure. The wide-bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench within the wide-bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a gate structure within the gate trench. The semiconductor device includes a dielectric layer on the gate structure within the gate trench. The semiconductor device includes a spacer layer between the dielectric layer and the sidewall of the gate trench within the gate trench. The semiconductor device includes a gate dielectric layer between the gate structure and the drift region within the gate trench.

[0076] In some examples, the top surface of the gate structure is below the top surface of the wide-bandgap semiconductor structure. In some examples, the gate structure is covered within a gate trench.

[0077] In some examples, the semiconductor device includes a metallization layer. The metallization layer has a flat surface that is in direct contact with the top surface of the wide-bandgap semiconductor structure and the dielectric layer. In some examples, the dielectric layer is positioned to electrically insulate the gate structure from the metallization layer.

[0078] In some examples, the wide-bandgap semiconductor structure includes a silicide layer in contact with the metallization layer. In some examples, the silicide layer includes nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, titanium aluminum silicide, nickel titanium aluminum silicide, or titanium tungsten silicide.

[0079] In some examples, the gate structure has a first gate layer and a second gate layer on the first gate layer. The first gate layer is made of a different material from the second gate layer. In some examples, the first gate layer contains polysilicon and the second gate layer contains silicide. In some examples, the silicide is Ta y S ix or W y Si x In some examples, x is in the range of approximately 2.0 to approximately 3.0.

[0080] In some examples, the first gate layer has a different width than the second gate layer. In some examples, the first gate layer is located between the second gate layer and the bottom surface of the gate trench. In some examples, the second gate layer is closer to the top surface of the wide-bandgap semiconductor structure than the first gate layer.

[0081] In some examples, the dielectric layer has an upper surface that is coplanar with the upper surface of the wide-bandgap semiconductor structure. In some examples, the dielectric layer is made of a different material from the spacer layer. In some examples, the dielectric layer is silicate glass.

[0082] In some examples, the spacer layer contains silicon dioxide or silicon nitride. In some examples, the gate dielectric layer has a thickness between the gate structure and the bottom surface of the gate structure. This thickness is in the range of approximately 250 angstroms to approximately 2500 angstroms.

[0083] In some examples, the wide-bandgap semiconductor structure further includes a shielding region beneath the gate trench, and the shielding region has a second conductivity type. In some examples, wide-bandgap semiconductor structures contain silicon carbide.

[0084] In some examples, the semiconductor device is a MOSFET. In some examples, the semiconductor device is an insulated-gate bipolar transistor (IGBT).

[0085] Another exemplary embodiment of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a gate trench within a wide-bandgap semiconductor structure. The method includes forming an embedded gate structure within the gate trench. The embedded gate structure includes a gate polysilicon layer and a gate silicide layer. The method includes forming a dielectric layer on the embedded gate structure within the gate trench.

[0086] In some examples, a wide-bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. Forming a gate trench involves forming a gate trench that extends through the well region into the drift region.

[0087] In some examples, forming an embedded gate structure includes forming a gate dielectric layer in a gate trench, forming a gate polysilicon layer on the gate dielectric layer, forming a spacer layer in the gate trench, and forming a gate silicide layer on the gate polysilicon layer.

[0088] In some examples, the gate silicide layer is Ta y S ix or W y Si x It comprises the following. In some examples, x is in the range of about 2.0 to about 3.0. In some examples, the gate dielectric layer has a thickness in the range of about 250 angstroms to about 2500 angstroms.

[0089] In some examples, the method includes forming a second silicide layer on a wide-bandgap semiconductor structure and forming a metallization layer on the second silicide layer.

[0090] In some examples, forming a metallization layer involves forming the metallization layer such that it is in direct contact with the dielectric layer. In some examples, forming a dielectric layer involves planarizing the dielectric layer with the top surface of the wide-bandgap semiconductor structure.

[0091] In some examples, the dielectric layer covers the embedded gate structure within the gate trench. In some examples, the semiconductor device is a MOSFET.

[0092] In some examples, the semiconductor device is an insulated-gate bipolar transistor (IGBT). Although the subject matter has been described in detail with respect to certain exemplary embodiments, it will be understood that modifications, variations, and equivalents to such embodiments can be readily generated. Therefore, the scope of this disclosure is illustrative rather than restrictive, and this disclosure does not preclude such modifications, variations, and / or additional inclusions to the subject matter that would be readily apparent to those skilled in the art.

Claims

1. It is a semiconductor device, A wide-bandgap semiconductor structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, A gate trench in the wide bandgap semiconductor structure, wherein the gate trench extends through the well region to the drift region, An embedded gate structure in the gate trench, wherein the embedded gate structure comprises a gate polysilicon layer and a gate silicide layer. A semiconductor device equipped with these features.

2. A semiconductor device according to claim 1, The upper surface of the gate silicide layer is located below the upper surface of the wide-bandgap semiconductor structure in the semiconductor device.

3. A semiconductor device according to claim 1, wherein the embedded gate structure is covered within the gate trench.

4. A semiconductor device according to claim 1, The gate silicide layer is Ta ｙ S ｉｘ or W ｙ Si ｘ A semiconductor device equipped with these features.

5. A semiconductor device according to claim 1, x is a semiconductor device in the range of approximately 2.0 to approximately 3.

0.

6. A semiconductor device according to claim 1, A semiconductor device in which the gate polysilicon layer has a width different from the width of the gate silicide layer.

7. A semiconductor device according to claim 1, The gate polysilicon layer is a semiconductor device located between the gate silicide layer and the bottom surface of the gate trench.

8. A semiconductor device according to claim 1, The gate silicide layer is closer to the upper surface of the wide-bandgap semiconductor structure than the gate polysilicon layer in the semiconductor device.

9. A semiconductor device according to claim 1, further, A semiconductor device comprising a dielectric layer within the gate trench on the embedded gate structure.

10. The semiconductor device according to claim 9, further, A semiconductor device comprising a metallization layer on the wide-bandgap semiconductor structure, wherein the metallization layer has a flat surface in contact with the wide-bandgap semiconductor structure and the dielectric layer.

11. A semiconductor device according to claim 10, A semiconductor device in which the dielectric layer is arranged to electrically insulate the embedded gate structure from the metallization layer.

12. A semiconductor device according to claim 9, A semiconductor device wherein the dielectric layer has an upper surface that is coplanar with the upper surface of the semiconductor structure.

13. A semiconductor device according to claim 9, The dielectric layer is silicate glass, in this semiconductor device.

14. A semiconductor device according to claim 1, further, A semiconductor device comprising a spacer layer in the gate trench, wherein the spacer layer is located between at least a portion of the embedded gate structure and the side wall of the gate trench.

15. A semiconductor device according to claim 14, The spacer layer comprises silicon dioxide or silicon nitride in the semiconductor device.

16. A semiconductor device according to claim 14, The spacer layer is located between at least a portion of the dielectric layer on the embedded gate structure and the side wall of the gate trench in the semiconductor device.

17. A semiconductor device according to claim 1, further, A semiconductor device comprising a gate dielectric layer between the embedded gate structure and the drift region.

18. A semiconductor device according to claim 17, A semiconductor device in which the gate dielectric layer has a thickness between the embedded gate structure and the bottom surface of the embedded gate structure, and the thickness is in the range of about 250 angstroms to about 2500 angstroms.

19. A semiconductor device according to claim 1, The semiconductor structure is a semiconductor device comprising a second silicide layer on the upper surface of the wide-bandgap semiconductor structure.

20. A semiconductor device according to claim 19, A semiconductor device in which the second silicide layer is made of a different material from the gate silicide layer.

21. A semiconductor device according to claim 20, The semiconductor device wherein the second silicide layer contains nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, aluminum titanium silicide, nickel titanium aluminum silicide, or titanium tungsten silicide.

22. A semiconductor device according to claim 1, The wide-bandgap semiconductor structure further comprises a shielding region below the gate trench, the shielding region having the second conductivity type, in the semiconductor device.

23. A semiconductor device according to claim 1, The aforementioned wide-bandgap semiconductor structure is a semiconductor device containing silicon carbide.

24. A semiconductor device according to claim 1, The aforementioned semiconductor device is a MOSFET.

25. A semiconductor device according to claim 1, The semiconductor device is an insulated-gate bipolar transistor (IGBT).

26. It is a semiconductor device, A wide-bandgap semiconductor structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, A gate trench in the wide bandgap semiconductor structure, wherein the gate trench extends through the well region to the drift region, The gate structure within the gate trench, The dielectric layer in the gate trench and on the gate structure, A spacer layer located within the gate trench and between the dielectric layer and the side wall of the gate trench, The gate dielectric layer located within the gate trench and between the gate structure and the drift region A semiconductor device equipped with these features.

27. A semiconductor device according to claim 26, The upper surface of the gate structure is located below the upper surface of the wide-bandgap semiconductor structure, forming a semiconductor device.

28. A semiconductor device according to claim 26, The gate structure is covered within the gate trench of the semiconductor device.

29. A semiconductor device according to claim 26, further, Equipped with a metallization layer, A semiconductor device in which the metallization layer has a flat surface that is in direct contact with the upper surface of the wide-bandgap semiconductor structure and the dielectric layer.

30. A semiconductor device according to claim 29, A semiconductor device in which the dielectric layer is arranged to electrically insulate the gate structure from the metallization layer.

31. A semiconductor device according to claim 29, The wide-bandgap semiconductor structure is a semiconductor device comprising a silicide layer in contact with the metallization layer.

32. A semiconductor device according to claim 31, A semiconductor device in which the silicide layer contains nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, aluminum titanium silicide, nickel titanium aluminum silicide, or titanium tungsten silicide.

33. A semiconductor device according to claim 26, The gate structure comprises a first gate layer and a second gate layer on the first gate layer. A semiconductor device in which the first gate layer is made of a different material from the second gate layer.

34. A semiconductor device according to claim 33, The first gate layer contains polysilicon, The semiconductor device wherein the second gate layer contains a silicide.

35. A semiconductor device according to claim 34, The silicide is Ta ｙ S ｉｘ or W ｙ Si ｘ A semiconductor device.

36. A semiconductor device according to claim 35, x is a semiconductor device in the range of approximately 2.0 to approximately 3.

0.

37. A semiconductor device according to claim 33, A semiconductor device in which the first gate layer has a width different from the width of the second gate layer.

38. A semiconductor device according to claim 33, The first gate layer is a semiconductor device located between the second gate layer and the bottom surface of the gate trench.

39. A semiconductor device according to claim 33, The second gate layer is closer to the upper surface of the wide-bandgap semiconductor structure than the first gate layer in the semiconductor device.

40. A semiconductor device according to claim 26, The dielectric layer has an upper surface that is coplanar with the upper surface of the wide-bandgap semiconductor structure, in a semiconductor device.

41. A semiconductor device according to claim 26, A semiconductor device in which the dielectric layer is made of a different material than the spacer layer.

42. A semiconductor device according to claim 26, The dielectric layer is silicate glass, in this semiconductor device.

43. A semiconductor device according to claim 26, The spacer layer comprises silicon dioxide or silicon nitride in the semiconductor device.

44. A semiconductor device according to claim 26, The gate dielectric layer has a thickness between the gate structure and the bottom surface of the gate structure. A semiconductor device having a thickness in the range of approximately 250 angstroms to approximately 2500 angstroms.

45. A semiconductor device according to claim 26, The wide-bandgap semiconductor structure further includes a shielding region below the gate trench, The shielding region is a semiconductor device having the second conductivity type.

46. A semiconductor device according to claim 26, The aforementioned wide-bandgap semiconductor structure is a semiconductor device containing silicon carbide.

47. A semiconductor device according to claim 26, The aforementioned semiconductor device is a MOSFET.

48. A semiconductor device according to claim 26, The semiconductor device is an insulated-gate bipolar transistor (IGBT).

49. A method for manufacturing semiconductor devices, The aforementioned method, Forming gate trenches within a wide-bandgap semiconductor structure, The method involves forming an embedded gate structure within the gate trench, wherein the embedded gate structure includes a gate polysilicon layer and a gate silicide layer. Forming a dielectric layer in the gate trench and on the embedded gate structure A method that includes [the following features].

50. The method according to claim 49, The wide-bandgap semiconductor structure comprises a drift region of a first conductivity type and a well region of a second conductivity type. A method comprising forming the gate trench, wherein the gate trench extends through the well region into the drift region.

51. The method according to claim 49, Forming the aforementioned embedded gate structure means Forming a gate dielectric layer within the gate trench, Forming the gate polysilicon layer on the gate dielectric layer, Forming a spacer layer within the gate trench, Forming the gate silicide layer on the gate polysilicon layer A method that includes [something].

52. The method according to claim 51, The gate silicide layer comprises Ta ｙ S ｉｘ or W ｙ Si ｘ The method comprising the above components.

53. The method according to claim 52, A method in which x is within the range of approximately 2.0 to approximately 3.

0.

54. The method according to claim 51, The gate dielectric layer has a thickness in the range of about 250 angstroms to about 2500 angstroms.

55. The method according to claim 49, The aforementioned method, Forming a second silicide layer on the aforementioned wide-bandgap semiconductor structure, Forming a metallization layer on the second silicide layer A method that includes [something].

56. The method according to claim 55, A method for forming the metallization layer, comprising forming the metallization layer such that the metallization layer is in direct contact with the dielectric layer.

57. The method according to claim 49, A method for forming the dielectric layer, comprising planarizing the dielectric layer with the upper surface of the wide-bandgap semiconductor structure.

58. The method according to claim 49, A method wherein the dielectric layer covers the embedded gate structure within the gate trench.

59. The method according to claim 49, The semiconductor device is a MOSFET, according to the method.

60. The method according to claim 49, The semiconductor device is an insulated-gate bipolar transistor (IGBT), in this method.

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