Real-time on-chip traffic monitoring in automotive network devices

Abstract

A network device (18) for use in an automotive network (20) includes a semiconductor die, a network device circuit, and an on-chip traffic monitor (76). The network device circuit is located on the die and is configured to forward traffic for the automotive network. The on-chip traffic monitor is located on the die and is configured to monitor traffic passing through the network device circuit from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect performance degradation in the network device circuit by analyzing the monitored traffic.

Description

Technical Field

[0001] Cross-Reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 535,159 filed on August 29, 2023, and U.S. Provisional Patent Application No. 63 / 656,375 filed on June 5, 2024, the disclosures of which are incorporated herein by reference.

[0002] Field of the Disclosure The present disclosure relates generally to network communications, and more particularly to methods and systems for traffic monitoring in network devices.

[0003] Background Communication networks are sometimes used in mission-critical applications, and are therefore required to meet high reliability standards. A typical example is an automotive network used for communication between sensors, electronic control units (ECUs) and other units in a vehicle. Since network reliability in a vehicle is directly related to driver safety, components of automotive networks are required to be highly reliable. For example, a network device may be required to satisfy a specified Fault Tolerant Time Interval (FTTI), which is the maximum allowable time from the occurrence of a fault to transition to a safe state.

[0004] The above description is presented as a general overview of related art in the field, and should not be construed as an admission that any information contained therein is prior art to the present patent application.

[0005] Summary of the Invention One embodiment described herein provides a network device for use in automotive networks. The network device includes a semiconductor die, a network device circuit, and an on-chip traffic monitor. The network device circuit is located on the die and is configured to forward traffic for an automotive network. The on-chip traffic monitor is located on the die and is configured to monitor traffic passing through the network device circuit from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect performance degradation in the network device circuit by analyzing the monitored traffic.

[0006] In some embodiments, the on-chip traffic monitor is configured to select traffic flows from within the traffic and to detect performance degradation in the selected traffic flows.

[0007] In some embodiments, the network device circuit includes (i) a plurality of port circuits located on the die and configured to transmit and receive packets over an automotive network; (ii) a switch fabric located on the die and configured to forward packets between each port circuit; and (iii) an interconnect circuit located on the die and configured to connect the switch fabric to a host via a peripheral bus. An on-chip traffic monitor may be connected to the interconnect circuit.

[0008] In one exemplary embodiment, the on-chip traffic monitor is configured to detect performance degradation by identifying traffic flows associated with a given bus function of a peripheral bus in the traffic and analyzing the identified traffic flows separately from one or more other traffic flows.

[0009] In another embodiment, the interconnect circuit includes a plurality of direct memory access (DMA) engines, and the on-chip traffic monitor is configured to detect performance degradation by identifying in the traffic traffic a traffic flow associated with a given DMA engine among the plurality of DMA engines and analyzing the identified traffic flow separately from one or more other traffic flows.

[0010] In yet another embodiment, the on-chip traffic monitor is configured to detect performance degradation by identifying traffic flows associated with one of the following in the traffic: (i) virtual circuits, (ii) one port circuit among multiple port circuits, (iii) time-sensitive network (TSN) traffic, (i) a defined memory region in the host's memory, and (v) message-signal-interrupt (MSI) traffic, and by analyzing the identified traffic flows separately from one or more other traffic flows.

[0011] In yet another embodiment, the on-chip traffic monitor includes one or more hardware counters, and the on-chip traffic monitor is configured to assign one of the hardware counters to measure the traffic throughput of a selected traffic flow within the traffic. In one exemplary embodiment, the on-chip traffic monitor is configured to measure traffic throughput by using the hardware counters to count the amount of traffic of a selected traffic flow over a defined measurement period.

[0012] In the disclosed embodiments, the on-chip traffic monitor is configured to notify the host in response to the detection of performance degradation. In one embodiment, the on-chip traffic monitor is configured to notify the host of performance degradation within 100 microseconds of the occurrence of performance degradation. In an exemplary embodiment, the on-chip traffic monitor is configured to detect performance degradation by analyzing one or more of the following in the monitored traffic: latency, changes in intrapacket spacing, dropped packets, data corruption, and traffic throughput.

[0013] An additional method for monitoring traffic in network devices of an automotive network is provided according to embodiments described herein. The method includes forwarding traffic for an automotive network using network device circuitry located on a semiconductor die. Traffic passing through the network device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network is monitored using an on-chip traffic monitor located on the semiconductor die. Performance degradation in the network device circuitry is detected by analyzing the monitored traffic using the on-chip traffic monitor.

[0014] This disclosure will be better understood from the following detailed description of its embodiments in conjunction with the drawings. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic block diagram illustrating an automotive communication system, including an automotive network switch having an on-chip traffic monitor, according to one embodiment described herein. [Figure 2] This flowchart schematically illustrates a method for on-chip traffic monitoring in the network switch shown in Figure 1, according to one embodiment described herein.

[0016] Detailed description of the embodiment Network devices used in automotive networks are typically required to detect and address faults within very short timeframes, usually on the order of 10ms to 100ms.

[0017] The embodiments described herein provide improved techniques for detecting performance degradation in network devices. In the context of this specification, the term “performance degradation” includes intermittent faults, permanent failures, and minor or significant degradations in performance metrics of a network device or its components. An exemplary example of performance degradation is a reduction in the bandwidth of data transmitted through a particular switch port. Such performance degradation may be problematic in itself or may indicate an impending failure. Performance degradation can optionally be appropriately defined, for example, as a performance deviation of a defined magnitude from a defined baseline performance.

[0018] The disclosed technology significantly reduces the time required for fault detection and correction by detecting performance degradation before it develops into a failure. The embodiments described herein refer, as an example, primarily to Ethernet switches in automotive networks. However, the disclosed technology is generally applicable to other suitable network devices, network types, and applications.

[0019] In some embodiments, the automotive network device includes a switch implemented on a system-on-a-chip (SoC). The switch communicates with a host via a peripheral bus, such as Peripheral Component Interconnect Express (PCIe). The SoC includes network device circuitry arranged on a semiconductor die. The network device circuitry may include, for example, a number of port circuits ("ports") for sending and receiving packets over the automotive network, a switch fabric for forwarding packets between each port circuit, and interconnection circuits connecting the switch fabric to a host via a PCIe bus.

[0020] In some embodiments, the network device further includes an on-chip traffic monitor located on the die of the switch SoC. The on-chip traffic monitor is configured to monitor traffic passing through the network device circuitry from a source in the automotive network to a destination in the automotive network, and to detect performance degradation in the network device circuitry by analyzing the monitored traffic. In various embodiments, the on-chip traffic monitor is located at an intermediate position between a data source in the automotive network, such as a camera, distance sensor, temperature sensor, audio sensor, or other suitable sensor, and a destination in the automotive network, such as a vehicle CPU or storage device.

[0021] In one exemplary implementation, the on-chip traffic monitor is hardware-implemented and connected to the SoC's interconnect circuitry. In monitoring traffic, the on-chip traffic monitor can detect performance degradation in selected traffic flows of interest at a fine granularity. For example, in some embodiments, the on-chip traffic monitor can be configured to monitor selected virtual channels (VCs), PCIe bus functions (physical functions (PFs) and / or virtual functions (VFs)), the SoC's direct memory access (DMA) engine, Ethernet ports, memory regions in host memory, interrupt events, and traffic flows associated with time-sensitive network (TSN) traffic flows. Each traffic flow is typically analyzed separately, independently of other traffic flows.

[0022] Such fine granularity allows network devices to detect even slight performance degradations with high sensitivity and reliability, and initiate appropriate response actions. Furthermore, the disclosed technology analyzes traffic at intermediate nodes (network devices) rather than at end nodes (e.g., traffic destinations). Analyzing traffic at intermediate nodes is often more efficient than analyzing it at end nodes because traffic at end nodes can be affected by multiple degradations that are difficult to distinguish. Identifying degradations at intermediate nodes can be faster because detection is closer to the system element where the degradation occurs. Detection speed can be critical in automotive networks because it can have a direct impact on safety.

[0023] Figure 1 is a schematic block diagram showing an automotive communication system 10 including one or more automotive network switches 18 according to one embodiment described herein. In this example, the switches 18 are part of an Ethernet network 20 installed in a vehicle. However, generally speaking, the switches 18 may be used in other suitable network environments. The disclosed technology can also be implemented in other types of network devices, such as routers.

[0024] In one embodiment, the vehicle includes a plurality of electronic subsystems 12 of various types. Some of the subsystems 12 include various sensors, such as video cameras, speed sensors, accelerometers, audio sensors, infrared sensors, radar sensors, lidar sensors, ultrasonic sensors, rangefinders, or other proximity sensors, and / or any other suitable type of sensor. Other subsystems 28 include, for example, advanced driver-assistance systems (ADAS) and / or in-vehicle infotainment (IVN) systems. Yet another subsystem 28 includes electronic control units (ECUs) that control vehicle elements, such as the engine, body, steering, etc. Additionally or alternatively, the vehicle may include any other suitable type of electronic subsystem 12.

[0025] In some embodiments, the vehicle is divided into a plurality of zones, and the subsystem 12 in each zone is controlled by a respective "zone ECU" 14. The various zone ECUs 14 communicate with a central computer 16 of the vehicle.

[0026] The electronic subsystem 12, the ECU 14, and the central computer 16 communicate with each other by transmitting and receiving communication packets via the network 20. In this example, the network 20 operates in compliance with one of the IEEE 802.3 Ethernet standards, for example, IEEE 802.3bw-2015 cited above. The network 20 includes a plurality of automotive network switches 18, in this example, Ethernet switches. Communication between each of the switches 18, between the switches 18 and the ECUs 14, and between the ECUs 14 and the subsystems 12 is performed via network links 19. The links 19 may comprise any suitable physical medium depending on the applicable Ethernet standard, for example, twisted pair copper links, optical links, waveguides, etc.

[0027] The lower left part of FIG. 1 shows an internal structure of an exemplary switch 18 in one embodiment. In some embodiments, all switches 18 of the network 20 have the same internal structure. In other embodiments, only a subset of the switches 18, and in some cases only a single switch 18, has this structure.

[0028] In one embodiment, the switch 18 is implemented in a system on chip (SoC). The terms "switch", "SoC", and "switch SoC" are used interchangeably herein. In one embodiment, the switch 18 communicates with a host 28 via a Peripheral Component Interconnect Express (PCIe) bus 32. The switch 18 comprises a semiconductor die on which electronic circuitry (referred to as "network device circuitry") is arranged. Generally speaking, the network device circuitry is configured to perform various packet processing tasks of the switch 18.

[0029] In the example in Figure 1, the network device circuit of switch 18 is: • Multiple Ethernet port circuits 36 (also called "ports" for simplicity) Switch Fabric 40 (i) a media access control (MAC) module 48, (ii) a plurality of direct memory access (DMA) engines 52, and (iii) an interconnection circuit 44 including a routing interconnection matrix 56. Includes.

[0030] The Ethernet port 36, shown at the bottom of the diagram, is configured to communicate via the vehicle's Ethernet network. Among various other tasks, port 36 is configured to perform physical layer (PHY) processing on packets in accordance with the applicable IEEE 802.1 standard. One of the Ethernet ports 36 is designated for communication with the interconnect circuit 44. The switch fabric 40 is configured to forward Ethernet packets between each of the ports 36.

[0031] The interconnection circuit 44 is configured to transfer packets, portions of packets, and other information between the switch fabric 40 and the host 28. In one embodiment, the MAC module 48 is configured to perform MAC layer processing on packets in accordance with the applicable IEEE 802.1 standard. The DMA engines 52 operate in parallel. To transfer packets from the host 28 to the switch fabric 40, one of the DMA engines 52 directly reads packet data from the host 28's memory (via the PCIe bus 32) and transmits the read packet data to the switch fabric 40. To transfer packets from the switch fabric 40 to the host 28, one of the DMA engines 52 receives packet data from the switch fabric 40 and directly writes the packet data to the host 28's memory (via the PCIe bus 72). The routing interconnection matrix 56 routes packets between the DMA engines 52 and the PCIe bus 32.

[0032] In the example shown in Figure 1, switch 18 supports Single Root I / O Virtualization (SR-IOV). In accordance with SR-IOV, host 28 may run various applications implemented as virtual machines (VMs). Applications run on host 28 may include, for example, infotainment applications, advanced driver-assistance systems (ADAS), etc.

[0033] To accommodate various applications and other entities within the host 28, such as a hypervisor, the physical resources of the PCIe bus 32 are divided into multiple PCIe functions (or, more generally, multiple bus functions). A function may include one or more physical functions (PFs) and / or one or more virtual functions (VFs). The host 28 runs one or more PF software (PFSW) drivers 60 and / or one or more VF software (VFSW) drivers 64. A given application or other entity within the host 28, to which a specific PCIe function (PF or VF) is assigned, accesses the PCIe bus 32 by accessing its respective driver (PFSW or VFSW driver).

[0034] In one embodiment, the switch SoC 18 further includes an on-chip traffic monitor 76 (for brevity, also simply referred to herein as the “monitor”). The monitor 76 is located on the same semiconductor die as the network device circuitry of the SoC 18. The on-chip traffic monitor 76 monitors traffic passing through the network device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network (for example, traffic between the electronic subsystem 12 and the central computer 16).

[0035] In this example, monitor 76 is connected to routing and interconnection matrix 56. Monitor 76 detects performance degradation using the techniques described herein by monitoring the traffic flowing through routing and interconnection matrix 56. Performance degradation may include network-level degradation, component-level degradation, or any other type of performance degradation.

[0036] In one embodiment, the on-chip traffic monitor 76 includes monitoring logic 80 and one or more hardware counters 84. The monitoring logic 80 performs various monitoring functions of the monitor 76, including controlling the HW counters 84.

[0037] In a typical operating mode, the monitoring logic 80 can be configured to monitor one or more selected traffic flows from among the traffic passing through the matrix 56. The selected traffic flows may include, for example, flows associated with a selected virtual channel (VC), flows associated with a selected PCIe bus function (PF or VF), flows associated with a specific DMA engine 52, flows associated with a selected Ethernet port 36, flows associated with a selected memory region in the host 28's memory, flows associated with a selected interrupt event, time-sensitive network (TSN) flows, or any other suitable type of flow.

[0038] The monitoring logic 80 assigns a hardware counter 84 to each traffic flow selected for monitoring. A given counter 84 measures the actual bandwidth (throughput) of the corresponding traffic flow by counting the flow's traffic (e.g., in bytes or other appropriate units) over a defined measurement period. At the end of each measurement period, the monitoring logic 80 reads the counter value (indicating the throughput of the traffic flow during the measurement period), resets the counter, and allows the counter to begin counting traffic for the next measurement period. In this way, the monitor 76 obtains a real-time sequence of throughput measurements for the selected traffic flow.

[0039] Such sequences enable rapid and accurate detection and localization of performance degradation. For example, a decrease in throughput associated with a traffic flow linked to a given DMA engine 52 may indicate an imminent failure in that DMA engine. A complete and persistent loss of throughput in a particular traffic flow may indicate an actual failure.

[0040] In some embodiments, the measurement period for each hardware counter 84 can be configured independently of other counters 84. This feature allows the monitoring logic 80 to adapt the measurement period to the characteristics of the traffic flow being monitored. For example, a longer measurement period can be assigned to traffic flows with significantly fluctuating throughput for additional averaging. As another example, a longer measurement period can be assigned to traffic flows characterized by very low throughput to collect sufficient statistics.

[0041] In some embodiments, the switch SoC 18 further includes a safety monitor (SM) 68. Typically, the SM 68 controls an on-chip traffic monitor 76, for example, setting appropriate traffic flows to be monitored in the monitor 76, receiving monitoring results from the monitor 76, and initiating appropriate response actions.

[0042] In an exemplary embodiment, the SM68 reads monitoring results (e.g., counter values) from the monitor 76, compares the monitoring results to a threshold, or evaluates specific criteria with respect to the monitoring results, and notifies the host 28 if the results indicate a performance degradation, and may trigger an appropriate response action. Examples of response actions may include applying a predefined user-defined action to return the switch 18 to a safe state, adjusting the hardware resources of the switch 18, reallocating bandwidth within the switch 18, etc.

[0043] Further aspects of the SM68 are described in U.S. Patent Application No. 17 / 949,231, “Automotive network switch with hardware-implemented safety monitor,” filed on 21 September 2022, which has been assigned to the assignee of this patent application and whose disclosure is incorporated herein by reference.

[0044] In some embodiments, the SoC 18 further includes an interrupt control unit (ICU) 72 configured to issue interrupts to the host 28. Interrupts issued by the ICU 72 typically include message signal interrupts (MSI or MSI-X) transmitted over the PCIe bus 32. In one embodiment, monitoring logic 80 and / or SM68 use the ICU 72 to issue interrupts in response to the detection of performance degradation. Additionally or alternatively, monitoring logic 80 and / or SM68 may notify the host 28 of the detected performance degradation by any other suitable method. In one exemplary embodiment, monitoring logic 80 and / or SM68 notify the host 28 of the performance degradation within tens of microseconds, typically less than 100 μsec (microseconds), of its occurrence.

[0045] The configuration of System 20, Switch 18, and Host 28 shown in Figure 1 is an exemplary configuration drawn simply for clarity. Any other suitable configuration can be used in alternative embodiments. For example, the above description presents a specific "division of labor," or task division, between the on-chip traffic monitor 76 and SM68 and Host 28. Any other suitable task division can be used in alternative embodiments.

[0046] As another example, the measurements performed by the on-chip traffic monitor 76 are by no means limited to throughput measurements or the use of counters. In an alternative embodiment, the on-chip traffic monitor 76 may detect performance degradation by analyzing various characteristics of a given traffic flow, such as latency, changes in intrapacket spacing, dropped packets, data corruption, and traffic throughput exhibited in the monitored traffic flow.

[0047] In various embodiments, the on-chip traffic monitor 76 may detect various types of performance degradation. Non-exclusive examples of degradation include loss of PCIe credits, downgrade of PCIe link speed or bus width, hardware faults, such as loss of read requests for DMA engine access, and many others.

[0048] Various elements of switch 18 may be implemented using dedicated hardware or firmware, for example, using hardwired or programmable logic in application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Additionally or alternatively, some functions of switch 18 may be implemented in software and / or using a combination of hardware and software elements. Elements not essential to understanding the disclosed technology have been omitted from the diagram for clarity.

[0049] In some embodiments, some functions of the switch 18, for example, functions of the host 28, may be implemented in one or more programmable processors, such as one or more central processing units (CPUs) or microcontrollers, which are software-programmed to perform the functions described herein. The software may be downloaded to one of the processors in electronic form, for example, via a network, or alternatively or additionally, provided and / or stored in non-temporary tangible media, such as magnetic, optical, or electronic memory.

[0050] Figure 2 is a schematic flowchart illustrating a method for on-chip traffic monitoring according to one embodiment described herein. The method begins in configuration step 90 by configuring an on-chip traffic monitor 76 to inspect one or more designated traffic flows. The configuration of the monitor 76 may be performed, for example, by a host 28. In one embodiment, the host 28 also specifies the respective measurement period for each traffic flow.

[0051] In the counter assignment process 94, the monitoring logic 80 of the monitor 76 assigns a hardware counter 84 to each traffic flow to be inspected. The monitoring logic also sets an appropriate measurement period for each counter 84.

[0052] In monitoring step 98, the monitoring logic 80 monitors traffic at an intermediate location within the network 20, for example, traffic flowing through the routing and interconnection matrix 56. The traffic typically consists of multiple packets, each packet originating from a specific source within the automotive network and destined for a specific destination within the automotive network. The monitoring logic 80 identifies the traffic of a specified traffic flow within the overall traffic passing through the matrix 56.

[0053] In the measurement step 102, the monitoring logic 80 uses each counter 84 to measure an indicator, such as the actual throughput (actual bandwidth) of each flow. Other appropriate indicators may include, for example, latency, changes in intrapacket spacing, dropped packets, data corruption, etc.

[0054] In one embodiment, to measure the throughput of a given traffic flow, the monitoring logic 80 (i) increments a counter 84 assigned to the flow to count the traffic volume of the flow (e.g., in bytes), and (ii) reads the counter value at the end of each measurement period and resets the counter. As described above, this process generates a sequence of real-time bandwidth readings for each traffic flow, i.e., one reading for each measurement period.

[0055] In the degradation check stage 106, the monitoring logic 80 checks whether the bandwidth reading (and / or other indicators) of any traffic flow indicate a performance degradation. If no performance degradation is observed, the method loops back to the previous stage 98. If a performance degradation is detected, the monitoring logic 80 notifies the host 28 of the detected degradation in the notification stage 110. For example, the logic 80 may issue an interrupt to the host 28 using the ICU 72.

[0056] The method shown in Figure 2 is illustrative and is depicted solely for the purpose of clarifying the concept. In alternative embodiments, any other suitable method can be used.

[0057] While the embodiments described herein primarily focus on detecting performance degradation for safety and reliability, the methods and systems described herein can also be used for other applications. For example, the measurements performed by the on-chip traffic monitor 76 can be used for identifying traffic bottlenecks, optimizing the network, and traffic engineering. As another example, the on-chip traffic monitor 76 may continuously update the maximum and minimum counter values ​​for previous measurement periods to calculate the average value for a particular traffic flow. A host can then use these values ​​to implement bandwidth allocation.

[0058] It should be noted that the embodiments described above are illustrative examples, and the present invention is not limited to those specifically illustrated and described herein. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described above, as well as variations and modifications of those combinations and subcombinations of features that would be conceivable to those skilled in the art by reading the preceding description and that are not disclosed in the prior art. Documents incorporated by reference in this patent application should be considered integral parts of this application, except to the extent that terms are defined in the incorporated document in a manner inconsistent with the definitions expressed or implied herein, only the definitions herein should be considered.

Claims

1. A network device for use in automotive networks, The aforementioned network device Semiconductor die and A network device circuit is disposed on the die and configured to transfer traffic for the automotive network, An on-chip traffic monitor is disposed on the die and is configured to monitor the traffic passing through the network device circuit from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect performance degradation in the network device circuit by analyzing the monitored traffic. Network devices, including those mentioned above.

2. The network device according to claim 1, wherein the on-chip traffic monitor is configured to select a traffic flow from the traffic and to detect the performance degradation in the selected traffic flow.

3. The aforementioned network device circuit A plurality of port circuits arranged on the die and configured to transmit and receive packets via the automotive network, A switch fabric arranged on the die and configured to forward the packets between each of the port circuits, An interconnect circuit disposed on the die and configured to connect the switch fabric to the host via a peripheral bus, Includes, The network device according to claim 1 or 2, wherein the on-chip traffic monitor is connected to the interconnection circuit.

4. The network device according to claim 3, wherein the on-chip traffic monitor is configured to detect the performance degradation by identifying a traffic flow associated with a given bus function of the peripheral bus in the traffic and analyzing the identified traffic flow separately from one or more other traffic flows.

5. The network device according to claim 3, wherein the interconnection circuit includes a plurality of direct memory access (DMA) engines, and the on-chip traffic monitor is configured to detect the performance degradation by identifying a traffic flow associated with a given DMA engine among the plurality of DMA engines in the traffic, and by analyzing the identified traffic flow separately from one or more other traffic flows.

6. The on-chip traffic monitor, In the aforementioned traffic, identify the traffic flow associated with one of the following: (i) a virtual circuit, (ii) one port circuit among multiple port circuits, (iii) time-sensitive network (TSN) traffic, (i) a defined memory area in the host's memory, and (v) message-signal-interrupt (MSI) traffic, and The performance degradation is detected by analyzing the identified traffic flow separately from one or more other traffic flows. A network device according to claim 1 or 2, configured as follows.

7. The network device according to claim 1 or 2, wherein the on-chip traffic monitor includes one or more hardware counters, and the on-chip traffic monitor is configured to assign one of the hardware counters to measure the traffic throughput of a selected traffic flow within the traffic.

8. The network device according to claim 7, wherein the on-chip traffic monitor is configured to measure the traffic throughput by using the hardware counters to count the amount of traffic of the selected traffic flow over a defined measurement period.

9. The network device according to claim 1 or 2, wherein the on-chip traffic monitor is configured to notify the host in response to the detection of the performance degradation.

10. The network device according to claim 9, wherein the on-chip traffic monitor is configured to notify the host of the performance degradation within 100 microseconds of the occurrence of the performance degradation.

11. The network device according to claim 1 or 2, wherein the on-chip traffic monitor is configured to detect the performance degradation by analyzing one or more of the following in the monitored traffic: latency, changes in intrapacket spacing, dropped packets, data corruption, and traffic throughput.

12. A method for monitoring traffic in network devices of an automotive network, The method described above is Using network device circuits arranged on a semiconductor die, the traffic of the automotive network is transferred, The on-chip traffic monitor located on the semiconductor die is used to monitor the traffic passing through the network device circuit from one or more sources in the automotive network to one or more destinations in the automotive network, and the performance degradation in the network device circuit is detected by analyzing the monitored traffic. A method of traffic monitoring, including [specific method / technique].

13. The traffic monitoring method according to claim 12, wherein detecting the performance degradation includes selecting a traffic flow from within the traffic and detecting the performance degradation in the selected traffic flow.

14. The forwarding of the traffic includes (i) transmitting and receiving packets over the automotive network using a plurality of port circuits located on the die, (ii) forwarding the packets between each of the port circuits using a switch fabric located on the die, and (iii) connecting the switch fabric to a host via a peripheral bus using an interconnection circuit located on the die, and The traffic monitoring method according to claim 12 or 13, wherein monitoring the traffic includes monitoring the traffic passing through the interconnection circuit.

15. The traffic monitoring method according to claim 14, wherein detecting the performance degradation includes identifying a traffic flow associated with a given bus function of the peripheral bus in the traffic, and detecting the performance degradation by analyzing the identified traffic flow separately from one or more other traffic flows.

16. The traffic monitoring method according to claim 14, wherein the interconnection circuit includes a plurality of direct memory access (DMA) engines, and detecting the performance degradation includes identifying a traffic flow associated with a given DMA engine among the plurality of DMA engines in the traffic, and detecting the performance degradation by analyzing the identified traffic flow separately from one or more other traffic flows.

17. Detecting the aforementioned performance degradation In the aforementioned traffic, the traffic flow associated with one of the following is identified: (i) a virtual circuit, (ii) one port circuit among multiple port circuits, (iii) time-sensitive network (TSN) traffic, (i) a defined memory area in the host's memory, and (v) message-signal-interrupt (MSI) traffic. The performance degradation is detected by analyzing the identified traffic flow separately from one or more other traffic flows. A method for monitoring traffic according to claim 12 or 13, including the following:

18. The traffic monitoring method according to claim 12 or 13, wherein monitoring the traffic includes assigning one hardware counter from one or more hardware counters to measure the traffic throughput of a selected traffic flow within the traffic.

19. The traffic monitoring method according to claim 18, wherein monitoring the traffic includes measuring the traffic throughput by using the hardware counter to count the amount of traffic of the selected traffic flow over a defined measurement period.

20. The traffic monitoring method according to claim 12 or 13, wherein detecting the performance degradation includes analyzing one or more of the latency, intrapacket spacing, dropped packets, data corruption, and traffic throughput exhibited in the monitored traffic.

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